3 files changed, 39 insertions, 39 deletions

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 26a0a570f92e..e14fe5f569ee 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -748,8 +748,8 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
         }
 
         if (num_encoders != 1)
-                WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
-                     intel_crtc->pipe);
+                WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
+                     pipe_name(intel_crtc->pipe));
 
         BUG_ON(ret == NULL);
         return ret;
@@ -1047,8 +1047,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
                 }
 
         } else {
-                WARN(1, "Invalid encoder type %d for pipe %d\n",
-                     intel_encoder->type, pipe);
+                WARN(1, "Invalid encoder type %d for pipe %c\n",
+                     intel_encoder->type, pipe_name(pipe));
         }
 
         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
@@ -1148,7 +1148,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
                 }
         }
 
-        DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
+        DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
 
         return false;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 462c81a871ab..e472488394ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2101,7 +2101,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         case 1:
                 break;
         default:
-                DRM_ERROR("Can't update plane %d in SAREA\n", plane);
+                DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                 return -EINVAL;
         }
 
@@ -2198,7 +2198,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
         case 2:
                 break;
         default:
-                DRM_ERROR("Can't update plane %d in SAREA\n", plane);
+                DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                 return -EINVAL;
         }
 
@@ -2389,9 +2389,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         }
 
         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
-                DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
-                                intel_crtc->plane,
-                                INTEL_INFO(dev)->num_pipes);
+                DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
+                          plane_name(intel_crtc->plane),
+                          INTEL_INFO(dev)->num_pipes);
                 return -EINVAL;
         }
 
@@ -3299,7 +3299,7 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 found:
         intel_crtc->pch_pll = pll;
         pll->refcount++;
-        DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
+        DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
 prepare: /* separate function? */
         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
 
@@ -3324,7 +3324,7 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
         udelay(500);
         if (wait_for(I915_READ(dslreg) != temp, 5)) {
                 if (wait_for(I915_READ(dslreg) != temp, 5))
-                        DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
+                        DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
         }
 }
 
@@ -5344,11 +5344,11 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
         struct intel_crtc *pipe_B_crtc =
                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
 
-        DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
-                      intel_crtc->pipe, intel_crtc->fdi_lanes);
+        DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
+                      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
         if (intel_crtc->fdi_lanes > 4) {
-                DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
-                              intel_crtc->pipe, intel_crtc->fdi_lanes);
+                DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
+                              pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                 /* Clamp lanes to avoid programming the hw with bogus values. */
                 intel_crtc->fdi_lanes = 4;
 
@@ -5364,8 +5364,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
         case PIPE_B:
                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
                     intel_crtc->fdi_lanes > 2) {
-                        DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
-                                      intel_crtc->pipe, intel_crtc->fdi_lanes);
+                        DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
+                                      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                         /* Clamp lanes to avoid programming the hw with bogus values. */
                         intel_crtc->fdi_lanes = 2;
 
@@ -5381,8 +5381,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
         case PIPE_C:
                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
                         if (intel_crtc->fdi_lanes > 2) {
-                                DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
-                                              intel_crtc->pipe, intel_crtc->fdi_lanes);
+                                DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
+                                              pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
                                 /* Clamp lanes to avoid programming the hw with bogus values. */
                                 intel_crtc->fdi_lanes = 2;
 
@@ -5647,7 +5647,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
         dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
                                      has_reduced_clock ? &fp2 : NULL);
 
-        DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
+        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
         drm_mode_debug_printmodeline(mode);
 
         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
@@ -5656,8 +5656,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
                 if (pll == NULL) {
-                        DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
-                                         pipe);
+                        DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+                                         pipe_name(pipe));
                         return -EINVAL;
                 }
         } else
@@ -5821,7 +5821,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
         /* determine panel color depth */
         dither = intel_crtc->config.dither;
 
-        DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
+        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
         drm_mode_debug_printmodeline(mode);
 
         if (intel_crtc->config.has_dp_encoder)
@@ -9051,8 +9051,8 @@ void intel_modeset_init(struct drm_device *dev)
                 for (j = 0; j < dev_priv->num_plane; j++) {
                         ret = intel_plane_init(dev, i, j);
                         if (ret)
-                                DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
-                                              i, j, ret);
+                                DRM_DEBUG_KMS("pipe %c plane %d init failed: %d\n",
+                                              pipe_name(i), j, ret);
                 }
         }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e34ad9642519..413877d4afea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -113,8 +113,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
         fbc_ctl |= obj->fence_reg;
         I915_WRITE(FBC_CONTROL, fbc_ctl);
 
-        DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
-                      cfb_pitch, crtc->y, intel_crtc->plane);
+        DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
+                      cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 }
 
 static bool i8xx_fbc_enabled(struct drm_device *dev)
@@ -148,7 +148,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
         /* enable it... */
         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 
-        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
+        DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 }
 
 static void g4x_disable_fbc(struct drm_device *dev)
@@ -228,7 +228,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
                 sandybridge_blit_fbc_update(dev);
         }
 
-        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
+        DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 }
 
 static void ironlake_disable_fbc(struct drm_device *dev)
@@ -2146,15 +2146,15 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
                                             &sandybridge_display_wm_info,
                                             latency, &sprite_wm);
         if (!ret) {
-                DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
-                              pipe);
+                DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
+                              pipe_name(pipe));
                 return;
         }
 
         val = I915_READ(reg);
         val &= ~WM0_PIPE_SPRITE_MASK;
         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
-        DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
+        DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
 
 
         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
@@ -2163,8 +2163,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
                                               SNB_READ_WM1_LATENCY() * 500,
                                               &sprite_wm);
         if (!ret) {
-                DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
-                              pipe);
+                DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
+                              pipe_name(pipe));
                 return;
         }
         I915_WRITE(WM1S_LP_ILK, sprite_wm);
@@ -2179,8 +2179,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
                                               SNB_READ_WM2_LATENCY() * 500,
                                               &sprite_wm);
         if (!ret) {
-                DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
-                              pipe);
+                DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
+                              pipe_name(pipe));
                 return;
         }
         I915_WRITE(WM2S_LP_IVB, sprite_wm);
@@ -2191,8 +2191,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
                                               SNB_READ_WM3_LATENCY() * 500,
                                               &sprite_wm);
         if (!ret) {
-                DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
-                              pipe);
+                DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
+                              pipe_name(pipe));
                 return;
         }
         I915_WRITE(WM3S_LP_IVB, sprite_wm);