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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-04-17 10:48:49 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-18 03:55:49 -0400
commit84f44ce795b3da9a08dc2041ecd60550d34c123e (patch)
tree9b762d203116a0e3fad906ba185bcbb70b92e828 /drivers/gpu
parentcfc33bf75bfbf8f95bffe040ee1a5ab1cda8c34c (diff)
drm/i915: Print plane, pipe, port names as alphabetical insted of decimal
Alway use the alphabetical names in debug/error messages for planes, pipes and ports, instead of using decimal numbers occasionally. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c10
-rw-r--r--drivers/gpu/drm/i915/intel_display.c42
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c26
3 files changed, 39 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 26a0a570f92e..e14fe5f569ee 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -748,8 +748,8 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
748 } 748 }
749 749
750 if (num_encoders != 1) 750 if (num_encoders != 1)
751 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders, 751 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
752 intel_crtc->pipe); 752 pipe_name(intel_crtc->pipe));
753 753
754 BUG_ON(ret == NULL); 754 BUG_ON(ret == NULL);
755 return ret; 755 return ret;
@@ -1047,8 +1047,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1047 } 1047 }
1048 1048
1049 } else { 1049 } else {
1050 WARN(1, "Invalid encoder type %d for pipe %d\n", 1050 WARN(1, "Invalid encoder type %d for pipe %c\n",
1051 intel_encoder->type, pipe); 1051 intel_encoder->type, pipe_name(pipe));
1052 } 1052 }
1053 1053
1054 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1054 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
@@ -1148,7 +1148,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1148 } 1148 }
1149 } 1149 }
1150 1150
1151 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); 1151 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1152 1152
1153 return false; 1153 return false;
1154} 1154}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 462c81a871ab..e472488394ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2101,7 +2101,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2101 case 1: 2101 case 1:
2102 break; 2102 break;
2103 default: 2103 default:
2104 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2104 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2105 return -EINVAL; 2105 return -EINVAL;
2106 } 2106 }
2107 2107
@@ -2198,7 +2198,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
2198 case 2: 2198 case 2:
2199 break; 2199 break;
2200 default: 2200 default:
2201 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2201 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2202 return -EINVAL; 2202 return -EINVAL;
2203 } 2203 }
2204 2204
@@ -2389,9 +2389,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2389 } 2389 }
2390 2390
2391 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { 2391 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2392 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", 2392 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2393 intel_crtc->plane, 2393 plane_name(intel_crtc->plane),
2394 INTEL_INFO(dev)->num_pipes); 2394 INTEL_INFO(dev)->num_pipes);
2395 return -EINVAL; 2395 return -EINVAL;
2396 } 2396 }
2397 2397
@@ -3299,7 +3299,7 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
3299found: 3299found:
3300 intel_crtc->pch_pll = pll; 3300 intel_crtc->pch_pll = pll;
3301 pll->refcount++; 3301 pll->refcount++;
3302 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); 3302 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3303prepare: /* separate function? */ 3303prepare: /* separate function? */
3304 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); 3304 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3305 3305
@@ -3324,7 +3324,7 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3324 udelay(500); 3324 udelay(500);
3325 if (wait_for(I915_READ(dslreg) != temp, 5)) { 3325 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3326 if (wait_for(I915_READ(dslreg) != temp, 5)) 3326 if (wait_for(I915_READ(dslreg) != temp, 5))
3327 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 3327 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3328 } 3328 }
3329} 3329}
3330 3330
@@ -5344,11 +5344,11 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5344 struct intel_crtc *pipe_B_crtc = 5344 struct intel_crtc *pipe_B_crtc =
5345 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); 5345 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5346 5346
5347 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", 5347 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5348 intel_crtc->pipe, intel_crtc->fdi_lanes); 5348 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5349 if (intel_crtc->fdi_lanes > 4) { 5349 if (intel_crtc->fdi_lanes > 4) {
5350 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", 5350 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5351 intel_crtc->pipe, intel_crtc->fdi_lanes); 5351 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5352 /* Clamp lanes to avoid programming the hw with bogus values. */ 5352 /* Clamp lanes to avoid programming the hw with bogus values. */
5353 intel_crtc->fdi_lanes = 4; 5353 intel_crtc->fdi_lanes = 4;
5354 5354
@@ -5364,8 +5364,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5364 case PIPE_B: 5364 case PIPE_B:
5365 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && 5365 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5366 intel_crtc->fdi_lanes > 2) { 5366 intel_crtc->fdi_lanes > 2) {
5367 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5367 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5368 intel_crtc->pipe, intel_crtc->fdi_lanes); 5368 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5369 /* Clamp lanes to avoid programming the hw with bogus values. */ 5369 /* Clamp lanes to avoid programming the hw with bogus values. */
5370 intel_crtc->fdi_lanes = 2; 5370 intel_crtc->fdi_lanes = 2;
5371 5371
@@ -5381,8 +5381,8 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5381 case PIPE_C: 5381 case PIPE_C:
5382 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { 5382 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5383 if (intel_crtc->fdi_lanes > 2) { 5383 if (intel_crtc->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5384 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5385 intel_crtc->pipe, intel_crtc->fdi_lanes); 5385 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5386 /* Clamp lanes to avoid programming the hw with bogus values. */ 5386 /* Clamp lanes to avoid programming the hw with bogus values. */
5387 intel_crtc->fdi_lanes = 2; 5387 intel_crtc->fdi_lanes = 2;
5388 5388
@@ -5647,7 +5647,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5647 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock, 5647 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5648 has_reduced_clock ? &fp2 : NULL); 5648 has_reduced_clock ? &fp2 : NULL);
5649 5649
5650 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5650 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5651 drm_mode_debug_printmodeline(mode); 5651 drm_mode_debug_printmodeline(mode);
5652 5652
5653 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5653 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
@@ -5656,8 +5656,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5656 5656
5657 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5657 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5658 if (pll == NULL) { 5658 if (pll == NULL) {
5659 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", 5659 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5660 pipe); 5660 pipe_name(pipe));
5661 return -EINVAL; 5661 return -EINVAL;
5662 } 5662 }
5663 } else 5663 } else
@@ -5821,7 +5821,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5821 /* determine panel color depth */ 5821 /* determine panel color depth */
5822 dither = intel_crtc->config.dither; 5822 dither = intel_crtc->config.dither;
5823 5823
5824 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5824 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5825 drm_mode_debug_printmodeline(mode); 5825 drm_mode_debug_printmodeline(mode);
5826 5826
5827 if (intel_crtc->config.has_dp_encoder) 5827 if (intel_crtc->config.has_dp_encoder)
@@ -9051,8 +9051,8 @@ void intel_modeset_init(struct drm_device *dev)
9051 for (j = 0; j < dev_priv->num_plane; j++) { 9051 for (j = 0; j < dev_priv->num_plane; j++) {
9052 ret = intel_plane_init(dev, i, j); 9052 ret = intel_plane_init(dev, i, j);
9053 if (ret) 9053 if (ret)
9054 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n", 9054 DRM_DEBUG_KMS("pipe %c plane %d init failed: %d\n",
9055 i, j, ret); 9055 pipe_name(i), j, ret);
9056 } 9056 }
9057 } 9057 }
9058 9058
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e34ad9642519..413877d4afea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -113,8 +113,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
113 fbc_ctl |= obj->fence_reg; 113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl); 114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115 115
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, intel_crtc->plane); 117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
118} 118}
119 119
120static bool i8xx_fbc_enabled(struct drm_device *dev) 120static bool i8xx_fbc_enabled(struct drm_device *dev)
@@ -148,7 +148,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
148 /* enable it... */ 148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150 150
151 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
152} 152}
153 153
154static void g4x_disable_fbc(struct drm_device *dev) 154static void g4x_disable_fbc(struct drm_device *dev)
@@ -228,7 +228,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
228 sandybridge_blit_fbc_update(dev); 228 sandybridge_blit_fbc_update(dev);
229 } 229 }
230 230
231 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
232} 232}
233 233
234static void ironlake_disable_fbc(struct drm_device *dev) 234static void ironlake_disable_fbc(struct drm_device *dev)
@@ -2146,15 +2146,15 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2146 &sandybridge_display_wm_info, 2146 &sandybridge_display_wm_info,
2147 latency, &sprite_wm); 2147 latency, &sprite_wm);
2148 if (!ret) { 2148 if (!ret) {
2149 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 2149 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2150 pipe); 2150 pipe_name(pipe));
2151 return; 2151 return;
2152 } 2152 }
2153 2153
2154 val = I915_READ(reg); 2154 val = I915_READ(reg);
2155 val &= ~WM0_PIPE_SPRITE_MASK; 2155 val &= ~WM0_PIPE_SPRITE_MASK;
2156 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 2156 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2157 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 2157 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2158 2158
2159 2159
2160 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2160 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
@@ -2163,8 +2163,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2163 SNB_READ_WM1_LATENCY() * 500, 2163 SNB_READ_WM1_LATENCY() * 500,
2164 &sprite_wm); 2164 &sprite_wm);
2165 if (!ret) { 2165 if (!ret) {
2166 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 2166 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2167 pipe); 2167 pipe_name(pipe));
2168 return; 2168 return;
2169 } 2169 }
2170 I915_WRITE(WM1S_LP_ILK, sprite_wm); 2170 I915_WRITE(WM1S_LP_ILK, sprite_wm);
@@ -2179,8 +2179,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2179 SNB_READ_WM2_LATENCY() * 500, 2179 SNB_READ_WM2_LATENCY() * 500,
2180 &sprite_wm); 2180 &sprite_wm);
2181 if (!ret) { 2181 if (!ret) {
2182 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 2182 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2183 pipe); 2183 pipe_name(pipe));
2184 return; 2184 return;
2185 } 2185 }
2186 I915_WRITE(WM2S_LP_IVB, sprite_wm); 2186 I915_WRITE(WM2S_LP_IVB, sprite_wm);
@@ -2191,8 +2191,8 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2191 SNB_READ_WM3_LATENCY() * 500, 2191 SNB_READ_WM3_LATENCY() * 500,
2192 &sprite_wm); 2192 &sprite_wm);
2193 if (!ret) { 2193 if (!ret) {
2194 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 2194 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2195 pipe); 2195 pipe_name(pipe));
2196 return; 2196 return;
2197 } 2197 }
2198 I915_WRITE(WM3S_LP_IVB, sprite_wm); 2198 I915_WRITE(WM3S_LP_IVB, sprite_wm);