aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h47
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c160
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c157
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c90
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c28
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c53
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c30
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_smc.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c13
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_process.c2
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h32
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c19
-rw-r--r--drivers/gpu/drm/drm_dp_mst_topology.c279
-rw-r--r--drivers/gpu/drm/exynos/exynos_dp_core.c55
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_dsi.c6
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c6
-rw-r--r--drivers/gpu/drm/i2c/adv7511.c48
-rw-r--r--drivers/gpu/drm/i2c/adv7511.h12
-rw-r--r--drivers/gpu/drm/i915/Kconfig1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c33
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c1
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_sa.c5
45 files changed, 764 insertions, 492 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 66f729eaf00b..20c9539abc36 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -25,7 +25,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
25 amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o 25 amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
26 26
27# add asic specific block 27# add asic specific block
28amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \ 28amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
29 ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \ 29 ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
30 amdgpu_amdkfd_gfx_v7.o 30 amdgpu_amdkfd_gfx_v7.o
31 31
@@ -34,6 +34,7 @@ amdgpu-y += \
34 34
35# add GMC block 35# add GMC block
36amdgpu-y += \ 36amdgpu-y += \
37 gmc_v7_0.o \
37 gmc_v8_0.o 38 gmc_v8_0.o
38 39
39# add IH block 40# add IH block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 82edf95b7740..5e7770f9a415 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
87extern int amdgpu_sched_hw_submission; 87extern int amdgpu_sched_hw_submission;
88extern int amdgpu_enable_semaphores; 88extern int amdgpu_enable_semaphores;
89extern int amdgpu_powerplay; 89extern int amdgpu_powerplay;
90extern unsigned amdgpu_pcie_gen_cap;
91extern unsigned amdgpu_pcie_lane_cap;
90 92
91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 93#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 94#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -132,47 +134,6 @@ extern int amdgpu_powerplay;
132#define AMDGPU_RESET_VCE (1 << 13) 134#define AMDGPU_RESET_VCE (1 << 13)
133#define AMDGPU_RESET_VCE1 (1 << 14) 135#define AMDGPU_RESET_VCE1 (1 << 14)
134 136
135/* CG block flags */
136#define AMDGPU_CG_BLOCK_GFX (1 << 0)
137#define AMDGPU_CG_BLOCK_MC (1 << 1)
138#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139#define AMDGPU_CG_BLOCK_UVD (1 << 3)
140#define AMDGPU_CG_BLOCK_VCE (1 << 4)
141#define AMDGPU_CG_BLOCK_HDP (1 << 5)
142#define AMDGPU_CG_BLOCK_BIF (1 << 6)
143
144/* CG flags */
145#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162
163/* PG flags */
164#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169#define AMDGPU_PG_SUPPORT_CP (1 << 5)
170#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
175
176/* GFX current status */ 137/* GFX current status */
177#define AMDGPU_GFX_NORMAL_MODE 0x00000000L 138#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178#define AMDGPU_GFX_SAFE_MODE 0x00000001L 139#define AMDGPU_GFX_SAFE_MODE 0x00000001L
@@ -606,8 +567,6 @@ struct amdgpu_sa_manager {
606 uint32_t align; 567 uint32_t align;
607}; 568};
608 569
609struct amdgpu_sa_bo;
610
611/* sub-allocation buffer */ 570/* sub-allocation buffer */
612struct amdgpu_sa_bo { 571struct amdgpu_sa_bo {
613 struct list_head olist; 572 struct list_head olist;
@@ -2360,6 +2319,8 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2360int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2319int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2361 uint32_t flags); 2320 uint32_t flags);
2362bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2321bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2322bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2323 unsigned long end);
2363bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2324bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2364uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2325uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2365 struct ttm_mem_reg *mem); 2326 struct ttm_mem_reg *mem);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 0e1376317683..362bedc9e507 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -154,7 +154,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
154 .get_fw_version = get_fw_version 154 .get_fw_version = get_fw_version
155}; 155};
156 156
157struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions() 157struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
158{ 158{
159 return (struct kfd2kgd_calls *)&kfd2kgd; 159 return (struct kfd2kgd_calls *)&kfd2kgd;
160} 160}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 79fa5c7de856..04b744d64b57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -115,7 +115,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
115 .get_fw_version = get_fw_version 115 .get_fw_version = get_fw_version
116}; 116};
117 117
118struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions() 118struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
119{ 119{
120 return (struct kfd2kgd_calls *)&kfd2kgd; 120 return (struct kfd2kgd_calls *)&kfd2kgd;
121} 121}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a081dda9fa2f..7a4b101e10c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -795,6 +795,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
795 case CGS_SYSTEM_INFO_PCIE_MLW: 795 case CGS_SYSTEM_INFO_PCIE_MLW:
796 sys_info->value = adev->pm.pcie_mlw_mask; 796 sys_info->value = adev->pm.pcie_mlw_mask;
797 break; 797 break;
798 case CGS_SYSTEM_INFO_CG_FLAGS:
799 sys_info->value = adev->cg_flags;
800 break;
801 case CGS_SYSTEM_INFO_PG_FLAGS:
802 sys_info->value = adev->pg_flags;
803 break;
798 default: 804 default:
799 return -ENODEV; 805 return -ENODEV;
800 } 806 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65531463f88e..51bfc114584e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1795,15 +1795,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1795 } 1795 }
1796 1796
1797 /* post card */ 1797 /* post card */
1798 amdgpu_atom_asic_init(adev->mode_info.atom_context); 1798 if (!amdgpu_card_posted(adev))
1799 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1799 1800
1800 r = amdgpu_resume(adev); 1801 r = amdgpu_resume(adev);
1802 if (r)
1803 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1801 1804
1802 amdgpu_fence_driver_resume(adev); 1805 amdgpu_fence_driver_resume(adev);
1803 1806
1804 r = amdgpu_ib_ring_tests(adev); 1807 if (resume) {
1805 if (r) 1808 r = amdgpu_ib_ring_tests(adev);
1806 DRM_ERROR("ib ring test failed (%d).\n", r); 1809 if (r)
1810 DRM_ERROR("ib ring test failed (%d).\n", r);
1811 }
1807 1812
1808 r = amdgpu_late_init(adev); 1813 r = amdgpu_late_init(adev);
1809 if (r) 1814 if (r)
@@ -1933,80 +1938,97 @@ retry:
1933 return r; 1938 return r;
1934} 1939}
1935 1940
1941#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1942#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1943
1936void amdgpu_get_pcie_info(struct amdgpu_device *adev) 1944void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1937{ 1945{
1938 u32 mask; 1946 u32 mask;
1939 int ret; 1947 int ret;
1940 1948
1941 if (pci_is_root_bus(adev->pdev->bus)) 1949 if (amdgpu_pcie_gen_cap)
1942 return; 1950 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1943 1951
1944 if (amdgpu_pcie_gen2 == 0) 1952 if (amdgpu_pcie_lane_cap)
1945 return; 1953 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1946 1954
1947 if (adev->flags & AMD_IS_APU) 1955 /* covers APUs as well */
1956 if (pci_is_root_bus(adev->pdev->bus)) {
1957 if (adev->pm.pcie_gen_mask == 0)
1958 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1959 if (adev->pm.pcie_mlw_mask == 0)
1960 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1948 return; 1961 return;
1962 }
1949 1963
1950 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1964 if (adev->pm.pcie_gen_mask == 0) {
1951 if (!ret) { 1965 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1952 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | 1966 if (!ret) {
1953 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1967 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1954 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); 1968 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1955 1969 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1956 if (mask & DRM_PCIE_SPEED_25) 1970
1957 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; 1971 if (mask & DRM_PCIE_SPEED_25)
1958 if (mask & DRM_PCIE_SPEED_50) 1972 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1959 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; 1973 if (mask & DRM_PCIE_SPEED_50)
1960 if (mask & DRM_PCIE_SPEED_80) 1974 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1961 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; 1975 if (mask & DRM_PCIE_SPEED_80)
1962 } 1976 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1963 ret = drm_pcie_get_max_link_width(adev->ddev, &mask); 1977 } else {
1964 if (!ret) { 1978 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1965 switch (mask) { 1979 }
1966 case 32: 1980 }
1967 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | 1981 if (adev->pm.pcie_mlw_mask == 0) {
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1982 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1983 if (!ret) {
1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1984 switch (mask) {
1971 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1985 case 32:
1972 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1986 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1974 break; 1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1975 case 16: 1989 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1976 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1990 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1991 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1978 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1979 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1993 break;
1980 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1994 case 16:
1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1995 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1982 break; 1996 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1983 case 12: 1997 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1984 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1998 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1985 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 2000 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2001 break;
1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2002 case 12:
1989 break; 2003 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1990 case 8: 2004 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1991 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 2005 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 2006 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2007 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2008 break;
1995 break; 2009 case 8:
1996 case 4: 2010 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1997 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 2011 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1998 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2012 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2013 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2000 break; 2014 break;
2001 case 2: 2015 case 4:
2002 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2016 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2003 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2017 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2004 break; 2018 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2005 case 1: 2019 break;
2006 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; 2020 case 2:
2007 break; 2021 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2008 default: 2022 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2009 break; 2023 break;
2024 case 1:
2025 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2026 break;
2027 default:
2028 break;
2029 }
2030 } else {
2031 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2010 } 2032 }
2011 } 2033 }
2012} 2034}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b5dbbb573491..9ef1db87cf26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32;
83int amdgpu_sched_hw_submission = 2; 83int amdgpu_sched_hw_submission = 2;
84int amdgpu_enable_semaphores = 0; 84int amdgpu_enable_semaphores = 0;
85int amdgpu_powerplay = -1; 85int amdgpu_powerplay = -1;
86unsigned amdgpu_pcie_gen_cap = 0;
87unsigned amdgpu_pcie_lane_cap = 0;
86 88
87MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 89MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
88module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 90module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
170module_param_named(powerplay, amdgpu_powerplay, int, 0444); 172module_param_named(powerplay, amdgpu_powerplay, int, 0444);
171#endif 173#endif
172 174
175MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
176module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
177
178MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
179module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
180
173static struct pci_device_id pciidlist[] = { 181static struct pci_device_id pciidlist[] = {
174#ifdef CONFIG_DRM_AMDGPU_CIK 182#ifdef CONFIG_DRM_AMDGPU_CIK
175 /* Kaveri */ 183 /* Kaveri */
@@ -256,11 +264,11 @@ static struct pci_device_id pciidlist[] = {
256 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 264 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
257#endif 265#endif
258 /* topaz */ 266 /* topaz */
259 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 267 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 268 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
261 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 269 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
262 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 270 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
263 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 271 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
264 /* tonga */ 272 /* tonga */
265 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 273 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
266 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 274 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index b1969f2b2038..d4e2780c0796 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -142,7 +142,8 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
142 142
143 list_for_each_entry(bo, &node->bos, mn_list) { 143 list_for_each_entry(bo, &node->bos, mn_list) {
144 144
145 if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound) 145 if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start,
146 end))
146 continue; 147 continue;
147 148
148 r = amdgpu_bo_reserve(bo, true); 149 r = amdgpu_bo_reserve(bo, true);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index a2a16acee34d..b8fbbd7699e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -33,6 +33,7 @@
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <drm/drmP.h> 34#include <drm/drmP.h>
35#include <drm/amdgpu_drm.h> 35#include <drm/amdgpu_drm.h>
36#include <drm/drm_cache.h>
36#include "amdgpu.h" 37#include "amdgpu.h"
37#include "amdgpu_trace.h" 38#include "amdgpu_trace.h"
38 39
@@ -261,6 +262,13 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
261 AMDGPU_GEM_DOMAIN_OA); 262 AMDGPU_GEM_DOMAIN_OA);
262 263
263 bo->flags = flags; 264 bo->flags = flags;
265
266 /* For architectures that don't support WC memory,
267 * mask out the WC flag from the BO
268 */
269 if (!drm_arch_can_wc_memory())
270 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
271
264 amdgpu_fill_placement_to_bo(bo, placement); 272 amdgpu_fill_placement_to_bo(bo, placement);
265 /* Kernel allocation are uninterruptible */ 273 /* Kernel allocation are uninterruptible */
266 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 274 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 8b88edb0434b..ca72a2e487b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -354,12 +354,15 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
354 354
355 for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i) 355 for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
356 if (fences[i]) 356 if (fences[i])
357 fences[count++] = fences[i]; 357 fences[count++] = fence_get(fences[i]);
358 358
359 if (count) { 359 if (count) {
360 spin_unlock(&sa_manager->wq.lock); 360 spin_unlock(&sa_manager->wq.lock);
361 t = fence_wait_any_timeout(fences, count, false, 361 t = fence_wait_any_timeout(fences, count, false,
362 MAX_SCHEDULE_TIMEOUT); 362 MAX_SCHEDULE_TIMEOUT);
363 for (i = 0; i < count; ++i)
364 fence_put(fences[i]);
365
363 r = (t > 0) ? 0 : t; 366 r = (t > 0) ? 0 : t;
364 spin_lock(&sa_manager->wq.lock); 367 spin_lock(&sa_manager->wq.lock);
365 } else { 368 } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 8a1752ff3d8e..6442a06d6fdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -783,6 +783,25 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
783 return !!gtt->userptr; 783 return !!gtt->userptr;
784} 784}
785 785
786bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
787 unsigned long end)
788{
789 struct amdgpu_ttm_tt *gtt = (void *)ttm;
790 unsigned long size;
791
792 if (gtt == NULL)
793 return false;
794
795 if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
796 return false;
797
798 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
799 if (gtt->userptr > end || gtt->userptr + size <= start)
800 return false;
801
802 return true;
803}
804
786bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 805bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
787{ 806{
788 struct amdgpu_ttm_tt *gtt = (void *)ttm; 807 struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -808,7 +827,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
808 flags |= AMDGPU_PTE_SNOOPED; 827 flags |= AMDGPU_PTE_SNOOPED;
809 } 828 }
810 829
811 if (adev->asic_type >= CHIP_TOPAZ) 830 if (adev->asic_type >= CHIP_TONGA)
812 flags |= AMDGPU_PTE_EXECUTABLE; 831 flags |= AMDGPU_PTE_EXECUTABLE;
813 832
814 flags |= AMDGPU_PTE_READABLE; 833 flags |= AMDGPU_PTE_READABLE;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 8b4731d4e10e..474ca02b0949 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -31,6 +31,7 @@
31#include "ci_dpm.h" 31#include "ci_dpm.h"
32#include "gfx_v7_0.h" 32#include "gfx_v7_0.h"
33#include "atom.h" 33#include "atom.h"
34#include "amd_pcie.h"
34#include <linux/seq_file.h> 35#include <linux/seq_file.h>
35 36
36#include "smu/smu_7_0_1_d.h" 37#include "smu/smu_7_0_1_d.h"
@@ -5835,18 +5836,16 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5835 u8 frev, crev; 5836 u8 frev, crev;
5836 struct ci_power_info *pi; 5837 struct ci_power_info *pi;
5837 int ret; 5838 int ret;
5838 u32 mask;
5839 5839
5840 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5840 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5841 if (pi == NULL) 5841 if (pi == NULL)
5842 return -ENOMEM; 5842 return -ENOMEM;
5843 adev->pm.dpm.priv = pi; 5843 adev->pm.dpm.priv = pi;
5844 5844
5845 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 5845 pi->sys_pcie_mask =
5846 if (ret) 5846 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5847 pi->sys_pcie_mask = 0; 5847 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5848 else 5848
5849 pi->sys_pcie_mask = mask;
5850 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; 5849 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5851 5850
5852 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1; 5851 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index fd9c9588ef46..155965ed14a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1762,6 +1762,9 @@ static void cik_program_aspm(struct amdgpu_device *adev)
1762 if (amdgpu_aspm == 0) 1762 if (amdgpu_aspm == 0)
1763 return; 1763 return;
1764 1764
1765 if (pci_is_root_bus(adev->pdev->bus))
1766 return;
1767
1765 /* XXX double check APUs */ 1768 /* XXX double check APUs */
1766 if (adev->flags & AMD_IS_APU) 1769 if (adev->flags & AMD_IS_APU)
1767 return; 1770 return;
@@ -2332,72 +2335,72 @@ static int cik_common_early_init(void *handle)
2332 switch (adev->asic_type) { 2335 switch (adev->asic_type) {
2333 case CHIP_BONAIRE: 2336 case CHIP_BONAIRE:
2334 adev->cg_flags = 2337 adev->cg_flags =
2335 AMDGPU_CG_SUPPORT_GFX_MGCG | 2338 AMD_CG_SUPPORT_GFX_MGCG |
2336 AMDGPU_CG_SUPPORT_GFX_MGLS | 2339 AMD_CG_SUPPORT_GFX_MGLS |
2337 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2340 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2338 AMDGPU_CG_SUPPORT_GFX_CGLS | 2341 AMD_CG_SUPPORT_GFX_CGLS |
2339 AMDGPU_CG_SUPPORT_GFX_CGTS | 2342 AMD_CG_SUPPORT_GFX_CGTS |
2340 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2343 AMD_CG_SUPPORT_GFX_CGTS_LS |
2341 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2344 AMD_CG_SUPPORT_GFX_CP_LS |
2342 AMDGPU_CG_SUPPORT_MC_LS | 2345 AMD_CG_SUPPORT_MC_LS |
2343 AMDGPU_CG_SUPPORT_MC_MGCG | 2346 AMD_CG_SUPPORT_MC_MGCG |
2344 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2347 AMD_CG_SUPPORT_SDMA_MGCG |
2345 AMDGPU_CG_SUPPORT_SDMA_LS | 2348 AMD_CG_SUPPORT_SDMA_LS |
2346 AMDGPU_CG_SUPPORT_BIF_LS | 2349 AMD_CG_SUPPORT_BIF_LS |
2347 AMDGPU_CG_SUPPORT_VCE_MGCG | 2350 AMD_CG_SUPPORT_VCE_MGCG |
2348 AMDGPU_CG_SUPPORT_UVD_MGCG | 2351 AMD_CG_SUPPORT_UVD_MGCG |
2349 AMDGPU_CG_SUPPORT_HDP_LS | 2352 AMD_CG_SUPPORT_HDP_LS |
2350 AMDGPU_CG_SUPPORT_HDP_MGCG; 2353 AMD_CG_SUPPORT_HDP_MGCG;
2351 adev->pg_flags = 0; 2354 adev->pg_flags = 0;
2352 adev->external_rev_id = adev->rev_id + 0x14; 2355 adev->external_rev_id = adev->rev_id + 0x14;
2353 break; 2356 break;
2354 case CHIP_HAWAII: 2357 case CHIP_HAWAII:
2355 adev->cg_flags = 2358 adev->cg_flags =
2356 AMDGPU_CG_SUPPORT_GFX_MGCG | 2359 AMD_CG_SUPPORT_GFX_MGCG |
2357 AMDGPU_CG_SUPPORT_GFX_MGLS | 2360 AMD_CG_SUPPORT_GFX_MGLS |
2358 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2361 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2359 AMDGPU_CG_SUPPORT_GFX_CGLS | 2362 AMD_CG_SUPPORT_GFX_CGLS |
2360 AMDGPU_CG_SUPPORT_GFX_CGTS | 2363 AMD_CG_SUPPORT_GFX_CGTS |
2361 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2364 AMD_CG_SUPPORT_GFX_CP_LS |
2362 AMDGPU_CG_SUPPORT_MC_LS | 2365 AMD_CG_SUPPORT_MC_LS |
2363 AMDGPU_CG_SUPPORT_MC_MGCG | 2366 AMD_CG_SUPPORT_MC_MGCG |
2364 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2367 AMD_CG_SUPPORT_SDMA_MGCG |
2365 AMDGPU_CG_SUPPORT_SDMA_LS | 2368 AMD_CG_SUPPORT_SDMA_LS |
2366 AMDGPU_CG_SUPPORT_BIF_LS | 2369 AMD_CG_SUPPORT_BIF_LS |
2367 AMDGPU_CG_SUPPORT_VCE_MGCG | 2370 AMD_CG_SUPPORT_VCE_MGCG |
2368 AMDGPU_CG_SUPPORT_UVD_MGCG | 2371 AMD_CG_SUPPORT_UVD_MGCG |
2369 AMDGPU_CG_SUPPORT_HDP_LS | 2372 AMD_CG_SUPPORT_HDP_LS |
2370 AMDGPU_CG_SUPPORT_HDP_MGCG; 2373 AMD_CG_SUPPORT_HDP_MGCG;
2371 adev->pg_flags = 0; 2374 adev->pg_flags = 0;
2372 adev->external_rev_id = 0x28; 2375 adev->external_rev_id = 0x28;
2373 break; 2376 break;
2374 case CHIP_KAVERI: 2377 case CHIP_KAVERI:
2375 adev->cg_flags = 2378 adev->cg_flags =
2376 AMDGPU_CG_SUPPORT_GFX_MGCG | 2379 AMD_CG_SUPPORT_GFX_MGCG |
2377 AMDGPU_CG_SUPPORT_GFX_MGLS | 2380 AMD_CG_SUPPORT_GFX_MGLS |
2378 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2381 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2379 AMDGPU_CG_SUPPORT_GFX_CGLS | 2382 AMD_CG_SUPPORT_GFX_CGLS |
2380 AMDGPU_CG_SUPPORT_GFX_CGTS | 2383 AMD_CG_SUPPORT_GFX_CGTS |
2381 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2384 AMD_CG_SUPPORT_GFX_CGTS_LS |
2382 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2385 AMD_CG_SUPPORT_GFX_CP_LS |
2383 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2386 AMD_CG_SUPPORT_SDMA_MGCG |
2384 AMDGPU_CG_SUPPORT_SDMA_LS | 2387 AMD_CG_SUPPORT_SDMA_LS |
2385 AMDGPU_CG_SUPPORT_BIF_LS | 2388 AMD_CG_SUPPORT_BIF_LS |
2386 AMDGPU_CG_SUPPORT_VCE_MGCG | 2389 AMD_CG_SUPPORT_VCE_MGCG |
2387 AMDGPU_CG_SUPPORT_UVD_MGCG | 2390 AMD_CG_SUPPORT_UVD_MGCG |
2388 AMDGPU_CG_SUPPORT_HDP_LS | 2391 AMD_CG_SUPPORT_HDP_LS |
2389 AMDGPU_CG_SUPPORT_HDP_MGCG; 2392 AMD_CG_SUPPORT_HDP_MGCG;
2390 adev->pg_flags = 2393 adev->pg_flags =
2391 /*AMDGPU_PG_SUPPORT_GFX_PG | 2394 /*AMD_PG_SUPPORT_GFX_PG |
2392 AMDGPU_PG_SUPPORT_GFX_SMG | 2395 AMD_PG_SUPPORT_GFX_SMG |
2393 AMDGPU_PG_SUPPORT_GFX_DMG |*/ 2396 AMD_PG_SUPPORT_GFX_DMG |*/
2394 AMDGPU_PG_SUPPORT_UVD | 2397 AMD_PG_SUPPORT_UVD |
2395 /*AMDGPU_PG_SUPPORT_VCE | 2398 /*AMD_PG_SUPPORT_VCE |
2396 AMDGPU_PG_SUPPORT_CP | 2399 AMD_PG_SUPPORT_CP |
2397 AMDGPU_PG_SUPPORT_GDS | 2400 AMD_PG_SUPPORT_GDS |
2398 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2401 AMD_PG_SUPPORT_RLC_SMU_HS |
2399 AMDGPU_PG_SUPPORT_ACP | 2402 AMD_PG_SUPPORT_ACP |
2400 AMDGPU_PG_SUPPORT_SAMU |*/ 2403 AMD_PG_SUPPORT_SAMU |*/
2401 0; 2404 0;
2402 if (adev->pdev->device == 0x1312 || 2405 if (adev->pdev->device == 0x1312 ||
2403 adev->pdev->device == 0x1316 || 2406 adev->pdev->device == 0x1316 ||
@@ -2409,29 +2412,29 @@ static int cik_common_early_init(void *handle)
2409 case CHIP_KABINI: 2412 case CHIP_KABINI:
2410 case CHIP_MULLINS: 2413 case CHIP_MULLINS:
2411 adev->cg_flags = 2414 adev->cg_flags =
2412 AMDGPU_CG_SUPPORT_GFX_MGCG | 2415 AMD_CG_SUPPORT_GFX_MGCG |
2413 AMDGPU_CG_SUPPORT_GFX_MGLS | 2416 AMD_CG_SUPPORT_GFX_MGLS |
2414 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2417 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2415 AMDGPU_CG_SUPPORT_GFX_CGLS | 2418 AMD_CG_SUPPORT_GFX_CGLS |
2416 AMDGPU_CG_SUPPORT_GFX_CGTS | 2419 AMD_CG_SUPPORT_GFX_CGTS |
2417 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2420 AMD_CG_SUPPORT_GFX_CGTS_LS |
2418 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2421 AMD_CG_SUPPORT_GFX_CP_LS |
2419 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2422 AMD_CG_SUPPORT_SDMA_MGCG |
2420 AMDGPU_CG_SUPPORT_SDMA_LS | 2423 AMD_CG_SUPPORT_SDMA_LS |
2421 AMDGPU_CG_SUPPORT_BIF_LS | 2424 AMD_CG_SUPPORT_BIF_LS |
2422 AMDGPU_CG_SUPPORT_VCE_MGCG | 2425 AMD_CG_SUPPORT_VCE_MGCG |
2423 AMDGPU_CG_SUPPORT_UVD_MGCG | 2426 AMD_CG_SUPPORT_UVD_MGCG |
2424 AMDGPU_CG_SUPPORT_HDP_LS | 2427 AMD_CG_SUPPORT_HDP_LS |
2425 AMDGPU_CG_SUPPORT_HDP_MGCG; 2428 AMD_CG_SUPPORT_HDP_MGCG;
2426 adev->pg_flags = 2429 adev->pg_flags =
2427 /*AMDGPU_PG_SUPPORT_GFX_PG | 2430 /*AMD_PG_SUPPORT_GFX_PG |
2428 AMDGPU_PG_SUPPORT_GFX_SMG | */ 2431 AMD_PG_SUPPORT_GFX_SMG | */
2429 AMDGPU_PG_SUPPORT_UVD | 2432 AMD_PG_SUPPORT_UVD |
2430 /*AMDGPU_PG_SUPPORT_VCE | 2433 /*AMD_PG_SUPPORT_VCE |
2431 AMDGPU_PG_SUPPORT_CP | 2434 AMD_PG_SUPPORT_CP |
2432 AMDGPU_PG_SUPPORT_GDS | 2435 AMD_PG_SUPPORT_GDS |
2433 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2436 AMD_PG_SUPPORT_RLC_SMU_HS |
2434 AMDGPU_PG_SUPPORT_SAMU |*/ 2437 AMD_PG_SUPPORT_SAMU |*/
2435 0; 2438 0;
2436 if (adev->asic_type == CHIP_KABINI) { 2439 if (adev->asic_type == CHIP_KABINI) {
2437 if (adev->rev_id == 0) 2440 if (adev->rev_id == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 5f712ceddf08..c55ecf0ea845 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -885,7 +885,7 @@ static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
885{ 885{
886 u32 orig, data; 886 u32 orig, data;
887 887
888 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) { 888 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
889 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 889 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
890 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 890 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
891 } else { 891 } else {
@@ -906,7 +906,7 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
906{ 906{
907 u32 orig, data; 907 u32 orig, data;
908 908
909 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) { 909 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
910 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 910 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
911 data |= 0x100; 911 data |= 0x100;
912 if (orig != data) 912 if (orig != data)
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 4dd17f2dd905..9056355309d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -445,13 +445,13 @@ static int cz_dpm_init(struct amdgpu_device *adev)
445 pi->gfx_pg_threshold = 500; 445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true; 446 pi->caps_fps = true;
447 /* uvd */ 447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; 448 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true; 449 pi->caps_uvd_dpm = true;
450 /* vce */ 450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; 451 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true; 452 pi->caps_vce_dpm = true;
453 /* acp */ 453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; 454 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true; 455 pi->caps_acp_dpm = true;
456 456
457 pi->caps_stable_power_state = false; 457 pi->caps_stable_power_state = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 72793f93e2fc..7732059ae30f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4109,7 +4109,7 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
4109 4109
4110 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 4110 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4111 4111
4112 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) { 4112 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4113 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4113 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4114 4114
4115 tmp = gfx_v7_0_halt_rlc(adev); 4115 tmp = gfx_v7_0_halt_rlc(adev);
@@ -4147,9 +4147,9 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
4147{ 4147{
4148 u32 data, orig, tmp = 0; 4148 u32 data, orig, tmp = 0;
4149 4149
4150 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) { 4150 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4151 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) { 4151 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4152 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) { 4152 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4153 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 4153 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
4154 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4154 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4155 if (orig != data) 4155 if (orig != data)
@@ -4176,14 +4176,14 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
4176 4176
4177 gfx_v7_0_update_rlc(adev, tmp); 4177 gfx_v7_0_update_rlc(adev, tmp);
4178 4178
4179 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) { 4179 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
4180 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 4180 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4181 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 4181 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
4182 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 4182 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4183 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 4183 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4184 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 4184 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4185 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) && 4185 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
4186 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS)) 4186 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
4187 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 4187 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4188 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 4188 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
4189 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 4189 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
@@ -4249,7 +4249,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
4249 u32 data, orig; 4249 u32 data, orig;
4250 4250
4251 orig = data = RREG32(mmRLC_PG_CNTL); 4251 orig = data = RREG32(mmRLC_PG_CNTL);
4252 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) 4252 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
4253 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 4253 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4254 else 4254 else
4255 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 4255 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
@@ -4263,7 +4263,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
4263 u32 data, orig; 4263 u32 data, orig;
4264 4264
4265 orig = data = RREG32(mmRLC_PG_CNTL); 4265 orig = data = RREG32(mmRLC_PG_CNTL);
4266 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) 4266 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
4267 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 4267 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4268 else 4268 else
4269 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 4269 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
@@ -4276,7 +4276,7 @@ static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
4276 u32 data, orig; 4276 u32 data, orig;
4277 4277
4278 orig = data = RREG32(mmRLC_PG_CNTL); 4278 orig = data = RREG32(mmRLC_PG_CNTL);
4279 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)) 4279 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
4280 data &= ~0x8000; 4280 data &= ~0x8000;
4281 else 4281 else
4282 data |= 0x8000; 4282 data |= 0x8000;
@@ -4289,7 +4289,7 @@ static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
4289 u32 data, orig; 4289 u32 data, orig;
4290 4290
4291 orig = data = RREG32(mmRLC_PG_CNTL); 4291 orig = data = RREG32(mmRLC_PG_CNTL);
4292 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS)) 4292 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
4293 data &= ~0x2000; 4293 data &= ~0x2000;
4294 else 4294 else
4295 data |= 0x2000; 4295 data |= 0x2000;
@@ -4370,7 +4370,7 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4370{ 4370{
4371 u32 data, orig; 4371 u32 data, orig;
4372 4372
4373 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) { 4373 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
4374 orig = data = RREG32(mmRLC_PG_CNTL); 4374 orig = data = RREG32(mmRLC_PG_CNTL);
4375 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 4375 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4376 if (orig != data) 4376 if (orig != data)
@@ -4442,7 +4442,7 @@ static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4442 u32 data, orig; 4442 u32 data, orig;
4443 4443
4444 orig = data = RREG32(mmRLC_PG_CNTL); 4444 orig = data = RREG32(mmRLC_PG_CNTL);
4445 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)) 4445 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
4446 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4446 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4447 else 4447 else
4448 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4448 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
@@ -4456,7 +4456,7 @@ static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4456 u32 data, orig; 4456 u32 data, orig;
4457 4457
4458 orig = data = RREG32(mmRLC_PG_CNTL); 4458 orig = data = RREG32(mmRLC_PG_CNTL);
4459 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)) 4459 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
4460 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4460 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4461 else 4461 else
4462 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4462 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
@@ -4623,15 +4623,15 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4623 4623
4624static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4624static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4625{ 4625{
4626 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 4626 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4627 AMDGPU_PG_SUPPORT_GFX_SMG | 4627 AMD_PG_SUPPORT_GFX_SMG |
4628 AMDGPU_PG_SUPPORT_GFX_DMG | 4628 AMD_PG_SUPPORT_GFX_DMG |
4629 AMDGPU_PG_SUPPORT_CP | 4629 AMD_PG_SUPPORT_CP |
4630 AMDGPU_PG_SUPPORT_GDS | 4630 AMD_PG_SUPPORT_GDS |
4631 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 4631 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4632 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4632 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4633 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4633 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4634 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 4634 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4635 gfx_v7_0_init_gfx_cgpg(adev); 4635 gfx_v7_0_init_gfx_cgpg(adev);
4636 gfx_v7_0_enable_cp_pg(adev, true); 4636 gfx_v7_0_enable_cp_pg(adev, true);
4637 gfx_v7_0_enable_gds_pg(adev, true); 4637 gfx_v7_0_enable_gds_pg(adev, true);
@@ -4643,14 +4643,14 @@ static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4643 4643
4644static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4644static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4645{ 4645{
4646 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 4646 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4647 AMDGPU_PG_SUPPORT_GFX_SMG | 4647 AMD_PG_SUPPORT_GFX_SMG |
4648 AMDGPU_PG_SUPPORT_GFX_DMG | 4648 AMD_PG_SUPPORT_GFX_DMG |
4649 AMDGPU_PG_SUPPORT_CP | 4649 AMD_PG_SUPPORT_CP |
4650 AMDGPU_PG_SUPPORT_GDS | 4650 AMD_PG_SUPPORT_GDS |
4651 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 4651 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4652 gfx_v7_0_update_gfx_pg(adev, false); 4652 gfx_v7_0_update_gfx_pg(adev, false);
4653 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 4653 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4654 gfx_v7_0_enable_cp_pg(adev, false); 4654 gfx_v7_0_enable_cp_pg(adev, false);
4655 gfx_v7_0_enable_gds_pg(adev, false); 4655 gfx_v7_0_enable_gds_pg(adev, false);
4656 } 4656 }
@@ -4738,6 +4738,22 @@ static int gfx_v7_0_early_init(void *handle)
4738 return 0; 4738 return 0;
4739} 4739}
4740 4740
4741static int gfx_v7_0_late_init(void *handle)
4742{
4743 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4744 int r;
4745
4746 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4747 if (r)
4748 return r;
4749
4750 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4751 if (r)
4752 return r;
4753
4754 return 0;
4755}
4756
4741static int gfx_v7_0_sw_init(void *handle) 4757static int gfx_v7_0_sw_init(void *handle)
4742{ 4758{
4743 struct amdgpu_ring *ring; 4759 struct amdgpu_ring *ring;
@@ -4890,6 +4906,8 @@ static int gfx_v7_0_hw_fini(void *handle)
4890{ 4906{
4891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4907 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4892 4908
4909 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4910 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4893 gfx_v7_0_cp_enable(adev, false); 4911 gfx_v7_0_cp_enable(adev, false);
4894 gfx_v7_0_rlc_stop(adev); 4912 gfx_v7_0_rlc_stop(adev);
4895 gfx_v7_0_fini_pg(adev); 4913 gfx_v7_0_fini_pg(adev);
@@ -5509,14 +5527,14 @@ static int gfx_v7_0_set_powergating_state(void *handle,
5509 if (state == AMD_PG_STATE_GATE) 5527 if (state == AMD_PG_STATE_GATE)
5510 gate = true; 5528 gate = true;
5511 5529
5512 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 5530 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5513 AMDGPU_PG_SUPPORT_GFX_SMG | 5531 AMD_PG_SUPPORT_GFX_SMG |
5514 AMDGPU_PG_SUPPORT_GFX_DMG | 5532 AMD_PG_SUPPORT_GFX_DMG |
5515 AMDGPU_PG_SUPPORT_CP | 5533 AMD_PG_SUPPORT_CP |
5516 AMDGPU_PG_SUPPORT_GDS | 5534 AMD_PG_SUPPORT_GDS |
5517 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 5535 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5518 gfx_v7_0_update_gfx_pg(adev, gate); 5536 gfx_v7_0_update_gfx_pg(adev, gate);
5519 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 5537 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5520 gfx_v7_0_enable_cp_pg(adev, gate); 5538 gfx_v7_0_enable_cp_pg(adev, gate);
5521 gfx_v7_0_enable_gds_pg(adev, gate); 5539 gfx_v7_0_enable_gds_pg(adev, gate);
5522 } 5540 }
@@ -5527,7 +5545,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
5527 5545
5528const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5546const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5529 .early_init = gfx_v7_0_early_init, 5547 .early_init = gfx_v7_0_early_init,
5530 .late_init = NULL, 5548 .late_init = gfx_v7_0_late_init,
5531 .sw_init = gfx_v7_0_sw_init, 5549 .sw_init = gfx_v7_0_sw_init,
5532 .sw_fini = gfx_v7_0_sw_fini, 5550 .sw_fini = gfx_v7_0_sw_fini,
5533 .hw_init = gfx_v7_0_hw_init, 5551 .hw_init = gfx_v7_0_hw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 95c0cdfbd1b3..8f8ec37ecd88 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -111,7 +111,6 @@ MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
111MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); 111MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
112MODULE_FIRMWARE("amdgpu/topaz_me.bin"); 112MODULE_FIRMWARE("amdgpu/topaz_me.bin");
113MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); 113MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
114MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
115MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); 114MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
116 115
117MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); 116MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
@@ -828,7 +827,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
828 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 827 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
829 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 828 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
830 829
831 if (adev->asic_type != CHIP_STONEY) { 830 if ((adev->asic_type != CHIP_STONEY) &&
831 (adev->asic_type != CHIP_TOPAZ)) {
832 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 832 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
833 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 833 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
834 if (!err) { 834 if (!err) {
@@ -3851,10 +3851,16 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3851 if (r) 3851 if (r)
3852 return -EINVAL; 3852 return -EINVAL;
3853 3853
3854 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3854 if (adev->asic_type == CHIP_TOPAZ) {
3855 AMDGPU_UCODE_ID_CP_MEC1); 3855 r = gfx_v8_0_cp_compute_load_microcode(adev);
3856 if (r) 3856 if (r)
3857 return -EINVAL; 3857 return r;
3858 } else {
3859 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3860 AMDGPU_UCODE_ID_CP_MEC1);
3861 if (r)
3862 return -EINVAL;
3863 }
3858 } 3864 }
3859 } 3865 }
3860 3866
@@ -3901,6 +3907,8 @@ static int gfx_v8_0_hw_fini(void *handle)
3901{ 3907{
3902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3908 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3903 3909
3910 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3911 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3904 gfx_v8_0_cp_enable(adev, false); 3912 gfx_v8_0_cp_enable(adev, false);
3905 gfx_v8_0_rlc_stop(adev); 3913 gfx_v8_0_rlc_stop(adev);
3906 gfx_v8_0_cp_compute_fini(adev); 3914 gfx_v8_0_cp_compute_fini(adev);
@@ -4329,6 +4337,14 @@ static int gfx_v8_0_late_init(void *handle)
4329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4330 int r; 4338 int r;
4331 4339
4340 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4341 if (r)
4342 return r;
4343
4344 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4345 if (r)
4346 return r;
4347
4332 /* requires IBs so do in late init after IB pool is initialized */ 4348 /* requires IBs so do in late init after IB pool is initialized */
4333 r = gfx_v8_0_do_edc_gpr_workarounds(adev); 4349 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
4334 if (r) 4350 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 3f956065d069..b8060795b27b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -42,9 +42,39 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
42 42
43MODULE_FIRMWARE("radeon/bonaire_mc.bin"); 43MODULE_FIRMWARE("radeon/bonaire_mc.bin");
44MODULE_FIRMWARE("radeon/hawaii_mc.bin"); 44MODULE_FIRMWARE("radeon/hawaii_mc.bin");
45MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46
47static const u32 golden_settings_iceland_a11[] =
48{
49 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
50 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
53};
54
55static const u32 iceland_mgcg_cgcg_init[] =
56{
57 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
58};
59
60static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
61{
62 switch (adev->asic_type) {
63 case CHIP_TOPAZ:
64 amdgpu_program_register_sequence(adev,
65 iceland_mgcg_cgcg_init,
66 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
67 amdgpu_program_register_sequence(adev,
68 golden_settings_iceland_a11,
69 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
70 break;
71 default:
72 break;
73 }
74}
45 75
46/** 76/**
47 * gmc8_mc_wait_for_idle - wait for MC idle callback. 77 * gmc7_mc_wait_for_idle - wait for MC idle callback.
48 * 78 *
49 * @adev: amdgpu_device pointer 79 * @adev: amdgpu_device pointer
50 * 80 *
@@ -132,13 +162,20 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
132 case CHIP_HAWAII: 162 case CHIP_HAWAII:
133 chip_name = "hawaii"; 163 chip_name = "hawaii";
134 break; 164 break;
165 case CHIP_TOPAZ:
166 chip_name = "topaz";
167 break;
135 case CHIP_KAVERI: 168 case CHIP_KAVERI:
136 case CHIP_KABINI: 169 case CHIP_KABINI:
137 return 0; 170 return 0;
138 default: BUG(); 171 default: BUG();
139 } 172 }
140 173
141 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 174 if (adev->asic_type == CHIP_TOPAZ)
175 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
176 else
177 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
178
142 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 179 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
143 if (err) 180 if (err)
144 goto out; 181 goto out;
@@ -755,7 +792,7 @@ static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
755 792
756 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 793 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
757 orig = data = RREG32(mc_cg_registers[i]); 794 orig = data = RREG32(mc_cg_registers[i]);
758 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 795 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
759 data |= mc_cg_ls_en[i]; 796 data |= mc_cg_ls_en[i];
760 else 797 else
761 data &= ~mc_cg_ls_en[i]; 798 data &= ~mc_cg_ls_en[i];
@@ -772,7 +809,7 @@ static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
772 809
773 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 810 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
774 orig = data = RREG32(mc_cg_registers[i]); 811 orig = data = RREG32(mc_cg_registers[i]);
775 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 812 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
776 data |= mc_cg_en[i]; 813 data |= mc_cg_en[i];
777 else 814 else
778 data &= ~mc_cg_en[i]; 815 data &= ~mc_cg_en[i];
@@ -788,7 +825,7 @@ static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
788 825
789 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 826 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
790 827
791 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 828 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
792 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 829 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
793 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 830 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
794 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 831 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
@@ -811,7 +848,7 @@ static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
811 848
812 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 849 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
813 850
814 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 851 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
815 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 852 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
816 else 853 else
817 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 854 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
@@ -827,7 +864,7 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
827 864
828 orig = data = RREG32(mmHDP_MEM_POWER_LS); 865 orig = data = RREG32(mmHDP_MEM_POWER_LS);
829 866
830 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 867 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
831 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 868 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
832 else 869 else
833 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 870 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
@@ -984,6 +1021,8 @@ static int gmc_v7_0_hw_init(void *handle)
984 int r; 1021 int r;
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
986 1023
1024 gmc_v7_0_init_golden_registers(adev);
1025
987 gmc_v7_0_mc_program(adev); 1026 gmc_v7_0_mc_program(adev);
988 1027
989 if (!(adev->flags & AMD_IS_APU)) { 1028 if (!(adev->flags & AMD_IS_APU)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c0c9a0101eb4..3efd45546241 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -42,9 +42,7 @@
42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44 44
45MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 45MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
48 46
49static const u32 golden_settings_tonga_a11[] = 47static const u32 golden_settings_tonga_a11[] =
50{ 48{
@@ -75,19 +73,6 @@ static const u32 fiji_mgcg_cgcg_init[] =
75 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 73 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
76}; 74};
77 75
78static const u32 golden_settings_iceland_a11[] =
79{
80 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
81 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
84};
85
86static const u32 iceland_mgcg_cgcg_init[] =
87{
88 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
89};
90
91static const u32 cz_mgcg_cgcg_init[] = 76static const u32 cz_mgcg_cgcg_init[] =
92{ 77{
93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
@@ -102,14 +87,6 @@ static const u32 stoney_mgcg_cgcg_init[] =
102static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 87static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
103{ 88{
104 switch (adev->asic_type) { 89 switch (adev->asic_type) {
105 case CHIP_TOPAZ:
106 amdgpu_program_register_sequence(adev,
107 iceland_mgcg_cgcg_init,
108 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
109 amdgpu_program_register_sequence(adev,
110 golden_settings_iceland_a11,
111 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
112 break;
113 case CHIP_FIJI: 90 case CHIP_FIJI:
114 amdgpu_program_register_sequence(adev, 91 amdgpu_program_register_sequence(adev,
115 fiji_mgcg_cgcg_init, 92 fiji_mgcg_cgcg_init,
@@ -229,15 +206,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
229 DRM_DEBUG("\n"); 206 DRM_DEBUG("\n");
230 207
231 switch (adev->asic_type) { 208 switch (adev->asic_type) {
232 case CHIP_TOPAZ:
233 chip_name = "topaz";
234 break;
235 case CHIP_TONGA: 209 case CHIP_TONGA:
236 chip_name = "tonga"; 210 chip_name = "tonga";
237 break; 211 break;
238 case CHIP_FIJI: 212 case CHIP_FIJI:
239 chip_name = "fiji";
240 break;
241 case CHIP_CARRIZO: 213 case CHIP_CARRIZO:
242 case CHIP_STONEY: 214 case CHIP_STONEY:
243 return 0; 215 return 0;
@@ -1007,7 +979,7 @@ static int gmc_v8_0_hw_init(void *handle)
1007 979
1008 gmc_v8_0_mc_program(adev); 980 gmc_v8_0_mc_program(adev);
1009 981
1010 if (!(adev->flags & AMD_IS_APU)) { 982 if (adev->asic_type == CHIP_TONGA) {
1011 r = gmc_v8_0_mc_load_microcode(adev); 983 r = gmc_v8_0_mc_load_microcode(adev);
1012 if (r) { 984 if (r) {
1013 DRM_ERROR("Failed to load MC firmware!\n"); 985 DRM_ERROR("Failed to load MC firmware!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
index 966d4b2ed9da..090486c18249 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
432 case AMDGPU_UCODE_ID_CP_ME: 432 case AMDGPU_UCODE_ID_CP_ME:
433 return UCODE_ID_CP_ME_MASK; 433 return UCODE_ID_CP_ME_MASK;
434 case AMDGPU_UCODE_ID_CP_MEC1: 434 case AMDGPU_UCODE_ID_CP_MEC1:
435 return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; 435 return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
436 case AMDGPU_UCODE_ID_CP_MEC2: 436 case AMDGPU_UCODE_ID_CP_MEC2:
437 return UCODE_ID_CP_MEC_MASK; 437 return UCODE_ID_CP_MEC_MASK;
438 case AMDGPU_UCODE_ID_RLC_G: 438 case AMDGPU_UCODE_ID_RLC_G:
@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
522 return -EINVAL; 522 return -EINVAL;
523 } 523 }
524 524
525 if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
526 &toc->entry[toc->num_entries++])) {
527 DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
528 return -EINVAL;
529 }
530
531 if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0, 525 if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
532 &toc->entry[toc->num_entries++])) { 526 &toc->entry[toc->num_entries++])) {
533 DRM_ERROR("Failed to get firmware entry for SDMA0\n"); 527 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
550 UCODE_ID_CP_ME_MASK | 544 UCODE_ID_CP_ME_MASK |
551 UCODE_ID_CP_PFP_MASK | 545 UCODE_ID_CP_PFP_MASK |
552 UCODE_ID_CP_MEC_MASK | 546 UCODE_ID_CP_MEC_MASK |
553 UCODE_ID_CP_MEC_JT1_MASK | 547 UCODE_ID_CP_MEC_JT1_MASK;
554 UCODE_ID_CP_MEC_JT2_MASK; 548
555 549
556 if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) { 550 if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
557 DRM_ERROR("Fail to request SMU load ucode\n"); 551 DRM_ERROR("Fail to request SMU load ucode\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 7e9154c7f1db..654d76723bc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2859,11 +2859,11 @@ static int kv_dpm_init(struct amdgpu_device *adev)
2859 pi->voltage_drop_t = 0; 2859 pi->voltage_drop_t = 0;
2860 pi->caps_sclk_throttle_low_notification = false; 2860 pi->caps_sclk_throttle_low_notification = false;
2861 pi->caps_fps = false; /* true? */ 2861 pi->caps_fps = false; /* true? */
2862 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; 2862 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2863 pi->caps_uvd_dpm = true; 2863 pi->caps_uvd_dpm = true;
2864 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; 2864 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2865 pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false; 2865 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2866 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; 2866 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2867 pi->caps_stable_p_state = false; 2867 pi->caps_stable_p_state = false;
2868 2868
2869 ret = kv_parse_sys_info_table(adev); 2869 ret = kv_parse_sys_info_table(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 5e9f73af83a8..fbd3767671bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -611,7 +611,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
611{ 611{
612 u32 orig, data; 612 u32 orig, data;
613 613
614 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) { 614 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
615 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 615 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
616 data = 0xfff; 616 data = 0xfff;
617 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 617 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
@@ -830,6 +830,9 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
830 bool gate = false; 830 bool gate = false;
831 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
832 832
833 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
834 return 0;
835
833 if (state == AMD_CG_STATE_GATE) 836 if (state == AMD_CG_STATE_GATE)
834 gate = true; 837 gate = true;
835 838
@@ -848,7 +851,10 @@ static int uvd_v4_2_set_powergating_state(void *handle,
848 * revisit this when there is a cleaner line between 851 * revisit this when there is a cleaner line between
849 * the smc and the hw blocks 852 * the smc and the hw blocks
850 */ 853 */
851 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
855
856 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
857 return 0;
852 858
853 if (state == AMD_PG_STATE_GATE) { 859 if (state == AMD_PG_STATE_GATE) {
854 uvd_v4_2_stop(adev); 860 uvd_v4_2_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 38864f562981..57f1c5bf3bf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -774,6 +774,11 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
774static int uvd_v5_0_set_clockgating_state(void *handle, 774static int uvd_v5_0_set_clockgating_state(void *handle,
775 enum amd_clockgating_state state) 775 enum amd_clockgating_state state)
776{ 776{
777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
778
779 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
780 return 0;
781
777 return 0; 782 return 0;
778} 783}
779 784
@@ -789,6 +794,9 @@ static int uvd_v5_0_set_powergating_state(void *handle,
789 */ 794 */
790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 795 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791 796
797 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
798 return 0;
799
792 if (state == AMD_PG_STATE_GATE) { 800 if (state == AMD_PG_STATE_GATE) {
793 uvd_v5_0_stop(adev); 801 uvd_v5_0_stop(adev);
794 return 0; 802 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 3d5913926436..0b365b7651ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -532,7 +532,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
532 uvd_v6_0_mc_resume(adev); 532 uvd_v6_0_mc_resume(adev);
533 533
534 /* Set dynamic clock gating in S/W control mode */ 534 /* Set dynamic clock gating in S/W control mode */
535 if (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG) { 535 if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
536 if (adev->flags & AMD_IS_APU) 536 if (adev->flags & AMD_IS_APU)
537 cz_set_uvd_clock_gating_branches(adev, false); 537 cz_set_uvd_clock_gating_branches(adev, false);
538 else 538 else
@@ -1000,7 +1000,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1001 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1002 1002
1003 if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) 1003 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1004 return 0; 1004 return 0;
1005 1005
1006 if (enable) { 1006 if (enable) {
@@ -1030,6 +1030,9 @@ static int uvd_v6_0_set_powergating_state(void *handle,
1030 */ 1030 */
1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 1032
1033 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1034 return 0;
1035
1033 if (state == AMD_PG_STATE_GATE) { 1036 if (state == AMD_PG_STATE_GATE) {
1034 uvd_v6_0_stop(adev); 1037 uvd_v6_0_stop(adev);
1035 return 0; 1038 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 52ac7a8f1e58..a822edacfa95 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -373,7 +373,7 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
373{ 373{
374 bool sw_cg = false; 374 bool sw_cg = false;
375 375
376 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) { 376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
377 if (sw_cg) 377 if (sw_cg)
378 vce_v2_0_set_sw_cg(adev, true); 378 vce_v2_0_set_sw_cg(adev, true);
379 else 379 else
@@ -608,6 +608,9 @@ static int vce_v2_0_set_powergating_state(void *handle,
608 */ 608 */
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610 610
611 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
612 return 0;
613
611 if (state == AMD_PG_STATE_GATE) 614 if (state == AMD_PG_STATE_GATE)
612 /* XXX do we need a vce_v2_0_stop()? */ 615 /* XXX do we need a vce_v2_0_stop()? */
613 return 0; 616 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index e99af81e4aec..d662fa9f9091 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -277,7 +277,7 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
277 WREG32_P(mmVCE_STATUS, 0, ~1); 277 WREG32_P(mmVCE_STATUS, 0, ~1);
278 278
279 /* Set Clock-Gating off */ 279 /* Set Clock-Gating off */
280 if (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG) 280 if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
281 vce_v3_0_set_vce_sw_clock_gating(adev, false); 281 vce_v3_0_set_vce_sw_clock_gating(adev, false);
282 282
283 if (r) { 283 if (r) {
@@ -676,7 +676,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
676 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 676 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
677 int i; 677 int i;
678 678
679 if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) 679 if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
680 return 0; 680 return 0;
681 681
682 mutex_lock(&adev->grbm_idx_mutex); 682 mutex_lock(&adev->grbm_idx_mutex);
@@ -728,6 +728,9 @@ static int vce_v3_0_set_powergating_state(void *handle,
728 */ 728 */
729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 729 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
730 730
731 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
732 return 0;
733
731 if (state == AMD_PG_STATE_GATE) 734 if (state == AMD_PG_STATE_GATE)
732 /* XXX do we need a vce_v3_0_stop()? */ 735 /* XXX do we need a vce_v3_0_stop()? */
733 return 0; 736 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 652e76644c31..0d14d108a6c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -61,6 +61,7 @@
61#include "vi.h" 61#include "vi.h"
62#include "vi_dpm.h" 62#include "vi_dpm.h"
63#include "gmc_v8_0.h" 63#include "gmc_v8_0.h"
64#include "gmc_v7_0.h"
64#include "gfx_v8_0.h" 65#include "gfx_v8_0.h"
65#include "sdma_v2_4.h" 66#include "sdma_v2_4.h"
66#include "sdma_v3_0.h" 67#include "sdma_v3_0.h"
@@ -1109,10 +1110,10 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1109 }, 1110 },
1110 { 1111 {
1111 .type = AMD_IP_BLOCK_TYPE_GMC, 1112 .type = AMD_IP_BLOCK_TYPE_GMC,
1112 .major = 8, 1113 .major = 7,
1113 .minor = 0, 1114 .minor = 4,
1114 .rev = 0, 1115 .rev = 0,
1115 .funcs = &gmc_v8_0_ip_funcs, 1116 .funcs = &gmc_v7_0_ip_funcs,
1116 }, 1117 },
1117 { 1118 {
1118 .type = AMD_IP_BLOCK_TYPE_IH, 1119 .type = AMD_IP_BLOCK_TYPE_IH,
@@ -1442,8 +1443,7 @@ static int vi_common_early_init(void *handle)
1442 break; 1443 break;
1443 case CHIP_FIJI: 1444 case CHIP_FIJI:
1444 adev->has_uvd = true; 1445 adev->has_uvd = true;
1445 adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG | 1446 adev->cg_flags = 0;
1446 AMDGPU_CG_SUPPORT_VCE_MGCG;
1447 adev->pg_flags = 0; 1447 adev->pg_flags = 0;
1448 adev->external_rev_id = adev->rev_id + 0x3c; 1448 adev->external_rev_id = adev->rev_id + 0x3c;
1449 break; 1449 break;
@@ -1457,8 +1457,7 @@ static int vi_common_early_init(void *handle)
1457 case CHIP_STONEY: 1457 case CHIP_STONEY:
1458 adev->has_uvd = true; 1458 adev->has_uvd = true;
1459 adev->cg_flags = 0; 1459 adev->cg_flags = 0;
1460 /* Disable UVD pg */ 1460 adev->pg_flags = 0;
1461 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
1462 adev->external_rev_id = adev->rev_id + 0x1; 1461 adev->external_rev_id = adev->rev_id + 0x1;
1463 break; 1462 break;
1464 default: 1463 default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 9be007081b72..a902ae037398 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -194,7 +194,7 @@ static void kfd_process_wq_release(struct work_struct *work)
194 194
195 kfree(p); 195 kfree(p);
196 196
197 kfree((void *)work); 197 kfree(work);
198} 198}
199 199
200static void kfd_process_destroy_delayed(struct rcu_head *rcu) 200static void kfd_process_destroy_delayed(struct rcu_head *rcu)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 1195d06f55bc..dbf7e6413cab 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -85,6 +85,38 @@ enum amd_powergating_state {
85 AMD_PG_STATE_UNGATE, 85 AMD_PG_STATE_UNGATE,
86}; 86};
87 87
88/* CG flags */
89#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
90#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
91#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
92#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
93#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
94#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
95#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
96#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
97#define AMD_CG_SUPPORT_MC_LS (1 << 8)
98#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
99#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
100#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
101#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
102#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
103#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
104#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
105#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
106
107/* PG flags */
108#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
109#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
110#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
111#define AMD_PG_SUPPORT_UVD (1 << 3)
112#define AMD_PG_SUPPORT_VCE (1 << 4)
113#define AMD_PG_SUPPORT_CP (1 << 5)
114#define AMD_PG_SUPPORT_GDS (1 << 6)
115#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
116#define AMD_PG_SUPPORT_SDMA (1 << 8)
117#define AMD_PG_SUPPORT_ACP (1 << 9)
118#define AMD_PG_SUPPORT_SAMU (1 << 10)
119
88enum amd_pm_state_type { 120enum amd_pm_state_type {
89 /* not used for dpm */ 121 /* not used for dpm */
90 POWER_STATE_TYPE_DEFAULT, 122 POWER_STATE_TYPE_DEFAULT,
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 713aec954692..aec38fc3834f 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -109,6 +109,8 @@ enum cgs_system_info_id {
109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
110 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 110 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
111 CGS_SYSTEM_INFO_PCIE_MLW, 111 CGS_SYSTEM_INFO_PCIE_MLW,
112 CGS_SYSTEM_INFO_CG_FLAGS,
113 CGS_SYSTEM_INFO_PG_FLAGS,
112 CGS_SYSTEM_INFO_ID_MAXIMUM, 114 CGS_SYSTEM_INFO_ID_MAXIMUM,
113}; 115};
114 116
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 0874ab42ee95..cf01177ca3b5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -174,6 +174,8 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
174{ 174{
175 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 175 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
176 uint32_t i; 176 uint32_t i;
177 struct cgs_system_info sys_info = {0};
178 int result;
177 179
178 cz_hwmgr->gfx_ramp_step = 256*25/100; 180 cz_hwmgr->gfx_ramp_step = 256*25/100;
179 181
@@ -247,6 +249,22 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 249 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_DisableVoltageIsland); 250 PHM_PlatformCaps_DisableVoltageIsland);
249 251
252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
253 PHM_PlatformCaps_UVDPowerGating);
254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_VCEPowerGating);
256 sys_info.size = sizeof(struct cgs_system_info);
257 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
258 result = cgs_query_system_info(hwmgr->device, &sys_info);
259 if (!result) {
260 if (sys_info.value & AMD_PG_SUPPORT_UVD)
261 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
262 PHM_PlatformCaps_UVDPowerGating);
263 if (sys_info.value & AMD_PG_SUPPORT_VCE)
264 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
265 PHM_PlatformCaps_VCEPowerGating);
266 }
267
250 return 0; 268 return 0;
251} 269}
252 270
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 44a925006479..980d3bf8ea76 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -4451,6 +4451,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4451 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 4451 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 4452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4453 phw_tonga_ulv_parm *ulv; 4453 phw_tonga_ulv_parm *ulv;
4454 struct cgs_system_info sys_info = {0};
4454 4455
4455 PP_ASSERT_WITH_CODE((NULL != hwmgr), 4456 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4456 "Invalid Parameter!", return -1;); 4457 "Invalid Parameter!", return -1;);
@@ -4615,9 +4616,23 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4615 4616
4616 data->vddc_phase_shed_control = 0; 4617 data->vddc_phase_shed_control = 0;
4617 4618
4618 if (0 == result) { 4619 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4619 struct cgs_system_info sys_info = {0}; 4620 PHM_PlatformCaps_UVDPowerGating);
4621 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4622 PHM_PlatformCaps_VCEPowerGating);
4623 sys_info.size = sizeof(struct cgs_system_info);
4624 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4625 result = cgs_query_system_info(hwmgr->device, &sys_info);
4626 if (!result) {
4627 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4628 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4629 PHM_PlatformCaps_UVDPowerGating);
4630 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4631 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4632 PHM_PlatformCaps_VCEPowerGating);
4633 }
4620 4634
4635 if (0 == result) {
4621 data->is_tlu_enabled = 0; 4636 data->is_tlu_enabled = 0;
4622 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 4637 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4623 TONGA_MAX_HARDWARE_POWERLEVELS; 4638 TONGA_MAX_HARDWARE_POWERLEVELS;
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 6ed90a2437e5..8ae13de272c4 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -803,6 +803,18 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)
803 return mstb; 803 return mstb;
804} 804}
805 805
806static void drm_dp_free_mst_port(struct kref *kref);
807
808static void drm_dp_free_mst_branch_device(struct kref *kref)
809{
810 struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref);
811 if (mstb->port_parent) {
812 if (list_empty(&mstb->port_parent->next))
813 kref_put(&mstb->port_parent->kref, drm_dp_free_mst_port);
814 }
815 kfree(mstb);
816}
817
806static void drm_dp_destroy_mst_branch_device(struct kref *kref) 818static void drm_dp_destroy_mst_branch_device(struct kref *kref)
807{ 819{
808 struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref); 820 struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref);
@@ -810,6 +822,15 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref)
810 bool wake_tx = false; 822 bool wake_tx = false;
811 823
812 /* 824 /*
825 * init kref again to be used by ports to remove mst branch when it is
826 * not needed anymore
827 */
828 kref_init(kref);
829
830 if (mstb->port_parent && list_empty(&mstb->port_parent->next))
831 kref_get(&mstb->port_parent->kref);
832
833 /*
813 * destroy all ports - don't need lock 834 * destroy all ports - don't need lock
814 * as there are no more references to the mst branch 835 * as there are no more references to the mst branch
815 * device at this point. 836 * device at this point.
@@ -835,7 +856,8 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref)
835 856
836 if (wake_tx) 857 if (wake_tx)
837 wake_up(&mstb->mgr->tx_waitq); 858 wake_up(&mstb->mgr->tx_waitq);
838 kfree(mstb); 859
860 kref_put(kref, drm_dp_free_mst_branch_device);
839} 861}
840 862
841static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb) 863static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb)
@@ -883,6 +905,7 @@ static void drm_dp_destroy_port(struct kref *kref)
883 * from an EDID retrieval */ 905 * from an EDID retrieval */
884 906
885 mutex_lock(&mgr->destroy_connector_lock); 907 mutex_lock(&mgr->destroy_connector_lock);
908 kref_get(&port->parent->kref);
886 list_add(&port->next, &mgr->destroy_connector_list); 909 list_add(&port->next, &mgr->destroy_connector_list);
887 mutex_unlock(&mgr->destroy_connector_lock); 910 mutex_unlock(&mgr->destroy_connector_lock);
888 schedule_work(&mgr->destroy_connector_work); 911 schedule_work(&mgr->destroy_connector_work);
@@ -1018,18 +1041,27 @@ static bool drm_dp_port_setup_pdt(struct drm_dp_mst_port *port)
1018 return send_link; 1041 return send_link;
1019} 1042}
1020 1043
1021static void drm_dp_check_port_guid(struct drm_dp_mst_branch *mstb, 1044static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
1022 struct drm_dp_mst_port *port)
1023{ 1045{
1024 int ret; 1046 int ret;
1025 if (port->dpcd_rev >= 0x12) { 1047
1026 port->guid_valid = drm_dp_validate_guid(mstb->mgr, port->guid); 1048 memcpy(mstb->guid, guid, 16);
1027 if (!port->guid_valid) { 1049
1028 ret = drm_dp_send_dpcd_write(mstb->mgr, 1050 if (!drm_dp_validate_guid(mstb->mgr, mstb->guid)) {
1029 port, 1051 if (mstb->port_parent) {
1030 DP_GUID, 1052 ret = drm_dp_send_dpcd_write(
1031 16, port->guid); 1053 mstb->mgr,
1032 port->guid_valid = true; 1054 mstb->port_parent,
1055 DP_GUID,
1056 16,
1057 mstb->guid);
1058 } else {
1059
1060 ret = drm_dp_dpcd_write(
1061 mstb->mgr->aux,
1062 DP_GUID,
1063 mstb->guid,
1064 16);
1033 } 1065 }
1034 } 1066 }
1035} 1067}
@@ -1086,7 +1118,6 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
1086 port->dpcd_rev = port_msg->dpcd_revision; 1118 port->dpcd_rev = port_msg->dpcd_revision;
1087 port->num_sdp_streams = port_msg->num_sdp_streams; 1119 port->num_sdp_streams = port_msg->num_sdp_streams;
1088 port->num_sdp_stream_sinks = port_msg->num_sdp_stream_sinks; 1120 port->num_sdp_stream_sinks = port_msg->num_sdp_stream_sinks;
1089 memcpy(port->guid, port_msg->peer_guid, 16);
1090 1121
1091 /* manage mstb port lists with mgr lock - take a reference 1122 /* manage mstb port lists with mgr lock - take a reference
1092 for this list */ 1123 for this list */
@@ -1099,11 +1130,9 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
1099 1130
1100 if (old_ddps != port->ddps) { 1131 if (old_ddps != port->ddps) {
1101 if (port->ddps) { 1132 if (port->ddps) {
1102 drm_dp_check_port_guid(mstb, port);
1103 if (!port->input) 1133 if (!port->input)
1104 drm_dp_send_enum_path_resources(mstb->mgr, mstb, port); 1134 drm_dp_send_enum_path_resources(mstb->mgr, mstb, port);
1105 } else { 1135 } else {
1106 port->guid_valid = false;
1107 port->available_pbn = 0; 1136 port->available_pbn = 0;
1108 } 1137 }
1109 } 1138 }
@@ -1130,13 +1159,11 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
1130 drm_dp_put_port(port); 1159 drm_dp_put_port(port);
1131 goto out; 1160 goto out;
1132 } 1161 }
1133 if (port->port_num >= DP_MST_LOGICAL_PORT_0) { 1162
1134 port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc); 1163 drm_mode_connector_set_tile_property(port->connector);
1135 drm_mode_connector_set_tile_property(port->connector); 1164
1136 }
1137 (*mstb->mgr->cbs->register_connector)(port->connector); 1165 (*mstb->mgr->cbs->register_connector)(port->connector);
1138 } 1166 }
1139
1140out: 1167out:
1141 /* put reference to this port */ 1168 /* put reference to this port */
1142 drm_dp_put_port(port); 1169 drm_dp_put_port(port);
@@ -1161,11 +1188,9 @@ static void drm_dp_update_port(struct drm_dp_mst_branch *mstb,
1161 port->ddps = conn_stat->displayport_device_plug_status; 1188 port->ddps = conn_stat->displayport_device_plug_status;
1162 1189
1163 if (old_ddps != port->ddps) { 1190 if (old_ddps != port->ddps) {
1191 dowork = true;
1164 if (port->ddps) { 1192 if (port->ddps) {
1165 drm_dp_check_port_guid(mstb, port);
1166 dowork = true;
1167 } else { 1193 } else {
1168 port->guid_valid = false;
1169 port->available_pbn = 0; 1194 port->available_pbn = 0;
1170 } 1195 }
1171 } 1196 }
@@ -1222,13 +1247,14 @@ static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper(
1222 struct drm_dp_mst_branch *found_mstb; 1247 struct drm_dp_mst_branch *found_mstb;
1223 struct drm_dp_mst_port *port; 1248 struct drm_dp_mst_port *port;
1224 1249
1250 if (memcmp(mstb->guid, guid, 16) == 0)
1251 return mstb;
1252
1253
1225 list_for_each_entry(port, &mstb->ports, next) { 1254 list_for_each_entry(port, &mstb->ports, next) {
1226 if (!port->mstb) 1255 if (!port->mstb)
1227 continue; 1256 continue;
1228 1257
1229 if (port->guid_valid && memcmp(port->guid, guid, 16) == 0)
1230 return port->mstb;
1231
1232 found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid); 1258 found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid);
1233 1259
1234 if (found_mstb) 1260 if (found_mstb)
@@ -1247,10 +1273,7 @@ static struct drm_dp_mst_branch *drm_dp_get_mst_branch_device_by_guid(
1247 /* find the port by iterating down */ 1273 /* find the port by iterating down */
1248 mutex_lock(&mgr->lock); 1274 mutex_lock(&mgr->lock);
1249 1275
1250 if (mgr->guid_valid && memcmp(mgr->guid, guid, 16) == 0) 1276 mstb = get_mst_branch_device_by_guid_helper(mgr->mst_primary, guid);
1251 mstb = mgr->mst_primary;
1252 else
1253 mstb = get_mst_branch_device_by_guid_helper(mgr->mst_primary, guid);
1254 1277
1255 if (mstb) 1278 if (mstb)
1256 kref_get(&mstb->kref); 1279 kref_get(&mstb->kref);
@@ -1271,8 +1294,13 @@ static void drm_dp_check_and_send_link_address(struct drm_dp_mst_topology_mgr *m
1271 if (port->input) 1294 if (port->input)
1272 continue; 1295 continue;
1273 1296
1274 if (!port->ddps) 1297 if (!port->ddps) {
1298 if (port->cached_edid) {
1299 kfree(port->cached_edid);
1300 port->cached_edid = NULL;
1301 }
1275 continue; 1302 continue;
1303 }
1276 1304
1277 if (!port->available_pbn) 1305 if (!port->available_pbn)
1278 drm_dp_send_enum_path_resources(mgr, mstb, port); 1306 drm_dp_send_enum_path_resources(mgr, mstb, port);
@@ -1283,6 +1311,12 @@ static void drm_dp_check_and_send_link_address(struct drm_dp_mst_topology_mgr *m
1283 drm_dp_check_and_send_link_address(mgr, mstb_child); 1311 drm_dp_check_and_send_link_address(mgr, mstb_child);
1284 drm_dp_put_mst_branch_device(mstb_child); 1312 drm_dp_put_mst_branch_device(mstb_child);
1285 } 1313 }
1314 } else if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
1315 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) {
1316 if (!port->cached_edid) {
1317 port->cached_edid =
1318 drm_get_edid(port->connector, &port->aux.ddc);
1319 }
1286 } 1320 }
1287 } 1321 }
1288} 1322}
@@ -1302,6 +1336,8 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work)
1302 drm_dp_check_and_send_link_address(mgr, mstb); 1336 drm_dp_check_and_send_link_address(mgr, mstb);
1303 drm_dp_put_mst_branch_device(mstb); 1337 drm_dp_put_mst_branch_device(mstb);
1304 } 1338 }
1339
1340 (*mgr->cbs->hotplug)(mgr);
1305} 1341}
1306 1342
1307static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, 1343static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
@@ -1555,10 +1591,12 @@ static void drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr,
1555 txmsg->reply.u.link_addr.ports[i].num_sdp_streams, 1591 txmsg->reply.u.link_addr.ports[i].num_sdp_streams,
1556 txmsg->reply.u.link_addr.ports[i].num_sdp_stream_sinks); 1592 txmsg->reply.u.link_addr.ports[i].num_sdp_stream_sinks);
1557 } 1593 }
1594
1595 drm_dp_check_mstb_guid(mstb, txmsg->reply.u.link_addr.guid);
1596
1558 for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) { 1597 for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) {
1559 drm_dp_add_port(mstb, mgr->dev, &txmsg->reply.u.link_addr.ports[i]); 1598 drm_dp_add_port(mstb, mgr->dev, &txmsg->reply.u.link_addr.ports[i]);
1560 } 1599 }
1561 (*mgr->cbs->hotplug)(mgr);
1562 } 1600 }
1563 } else { 1601 } else {
1564 mstb->link_address_sent = false; 1602 mstb->link_address_sent = false;
@@ -1602,6 +1640,37 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
1602 return 0; 1640 return 0;
1603} 1641}
1604 1642
1643static struct drm_dp_mst_port *drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch *mstb)
1644{
1645 if (!mstb->port_parent)
1646 return NULL;
1647
1648 if (mstb->port_parent->mstb != mstb)
1649 return mstb->port_parent;
1650
1651 return drm_dp_get_last_connected_port_to_mstb(mstb->port_parent->parent);
1652}
1653
1654static struct drm_dp_mst_branch *drm_dp_get_last_connected_port_and_mstb(struct drm_dp_mst_topology_mgr *mgr,
1655 struct drm_dp_mst_branch *mstb,
1656 int *port_num)
1657{
1658 struct drm_dp_mst_branch *rmstb = NULL;
1659 struct drm_dp_mst_port *found_port;
1660 mutex_lock(&mgr->lock);
1661 if (mgr->mst_primary) {
1662 found_port = drm_dp_get_last_connected_port_to_mstb(mstb);
1663
1664 if (found_port) {
1665 rmstb = found_port->parent;
1666 kref_get(&rmstb->kref);
1667 *port_num = found_port->port_num;
1668 }
1669 }
1670 mutex_unlock(&mgr->lock);
1671 return rmstb;
1672}
1673
1605static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr, 1674static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
1606 struct drm_dp_mst_port *port, 1675 struct drm_dp_mst_port *port,
1607 int id, 1676 int id,
@@ -1609,13 +1678,18 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
1609{ 1678{
1610 struct drm_dp_sideband_msg_tx *txmsg; 1679 struct drm_dp_sideband_msg_tx *txmsg;
1611 struct drm_dp_mst_branch *mstb; 1680 struct drm_dp_mst_branch *mstb;
1612 int len, ret; 1681 int len, ret, port_num;
1613 u8 sinks[DRM_DP_MAX_SDP_STREAMS]; 1682 u8 sinks[DRM_DP_MAX_SDP_STREAMS];
1614 int i; 1683 int i;
1615 1684
1685 port_num = port->port_num;
1616 mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent); 1686 mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
1617 if (!mstb) 1687 if (!mstb) {
1618 return -EINVAL; 1688 mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num);
1689
1690 if (!mstb)
1691 return -EINVAL;
1692 }
1619 1693
1620 txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); 1694 txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
1621 if (!txmsg) { 1695 if (!txmsg) {
@@ -1627,7 +1701,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
1627 sinks[i] = i; 1701 sinks[i] = i;
1628 1702
1629 txmsg->dst = mstb; 1703 txmsg->dst = mstb;
1630 len = build_allocate_payload(txmsg, port->port_num, 1704 len = build_allocate_payload(txmsg, port_num,
1631 id, 1705 id,
1632 pbn, port->num_sdp_streams, sinks); 1706 pbn, port->num_sdp_streams, sinks);
1633 1707
@@ -1983,31 +2057,17 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
1983 mgr->mst_primary = mstb; 2057 mgr->mst_primary = mstb;
1984 kref_get(&mgr->mst_primary->kref); 2058 kref_get(&mgr->mst_primary->kref);
1985 2059
1986 {
1987 struct drm_dp_payload reset_pay;
1988 reset_pay.start_slot = 0;
1989 reset_pay.num_slots = 0x3f;
1990 drm_dp_dpcd_write_payload(mgr, 0, &reset_pay);
1991 }
1992
1993 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2060 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
1994 DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); 2061 DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC);
1995 if (ret < 0) { 2062 if (ret < 0) {
1996 goto out_unlock; 2063 goto out_unlock;
1997 } 2064 }
1998 2065
1999 2066 {
2000 /* sort out guid */ 2067 struct drm_dp_payload reset_pay;
2001 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, mgr->guid, 16); 2068 reset_pay.start_slot = 0;
2002 if (ret != 16) { 2069 reset_pay.num_slots = 0x3f;
2003 DRM_DEBUG_KMS("failed to read DP GUID %d\n", ret); 2070 drm_dp_dpcd_write_payload(mgr, 0, &reset_pay);
2004 goto out_unlock;
2005 }
2006
2007 mgr->guid_valid = drm_dp_validate_guid(mgr, mgr->guid);
2008 if (!mgr->guid_valid) {
2009 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, mgr->guid, 16);
2010 mgr->guid_valid = true;
2011 } 2071 }
2012 2072
2013 queue_work(system_long_wq, &mgr->work); 2073 queue_work(system_long_wq, &mgr->work);
@@ -2231,9 +2291,8 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
2231 } 2291 }
2232 2292
2233 drm_dp_update_port(mstb, &msg.u.conn_stat); 2293 drm_dp_update_port(mstb, &msg.u.conn_stat);
2234 DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n", msg.u.conn_stat.port_number, msg.u.conn_stat.legacy_device_plug_status, msg.u.conn_stat.displayport_device_plug_status, msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, msg.u.conn_stat.peer_device_type);
2235 (*mgr->cbs->hotplug)(mgr);
2236 2294
2295 DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n", msg.u.conn_stat.port_number, msg.u.conn_stat.legacy_device_plug_status, msg.u.conn_stat.displayport_device_plug_status, msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, msg.u.conn_stat.peer_device_type);
2237 } else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) { 2296 } else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
2238 drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, msg.req_type, seqno, false); 2297 drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, msg.req_type, seqno, false);
2239 if (!mstb) 2298 if (!mstb)
@@ -2320,10 +2379,6 @@ enum drm_connector_status drm_dp_mst_detect_port(struct drm_connector *connector
2320 2379
2321 case DP_PEER_DEVICE_SST_SINK: 2380 case DP_PEER_DEVICE_SST_SINK:
2322 status = connector_status_connected; 2381 status = connector_status_connected;
2323 /* for logical ports - cache the EDID */
2324 if (port->port_num >= 8 && !port->cached_edid) {
2325 port->cached_edid = drm_get_edid(connector, &port->aux.ddc);
2326 }
2327 break; 2382 break;
2328 case DP_PEER_DEVICE_DP_LEGACY_CONV: 2383 case DP_PEER_DEVICE_DP_LEGACY_CONV:
2329 if (port->ldps) 2384 if (port->ldps)
@@ -2378,10 +2433,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_
2378 2433
2379 if (port->cached_edid) 2434 if (port->cached_edid)
2380 edid = drm_edid_duplicate(port->cached_edid); 2435 edid = drm_edid_duplicate(port->cached_edid);
2381 else { 2436
2382 edid = drm_get_edid(connector, &port->aux.ddc);
2383 drm_mode_connector_set_tile_property(connector);
2384 }
2385 port->has_audio = drm_detect_monitor_audio(edid); 2437 port->has_audio = drm_detect_monitor_audio(edid);
2386 drm_dp_put_port(port); 2438 drm_dp_put_port(port);
2387 return edid; 2439 return edid;
@@ -2446,6 +2498,7 @@ bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp
2446 DRM_DEBUG_KMS("payload: vcpi %d already allocated for pbn %d - requested pbn %d\n", port->vcpi.vcpi, port->vcpi.pbn, pbn); 2498 DRM_DEBUG_KMS("payload: vcpi %d already allocated for pbn %d - requested pbn %d\n", port->vcpi.vcpi, port->vcpi.pbn, pbn);
2447 if (pbn == port->vcpi.pbn) { 2499 if (pbn == port->vcpi.pbn) {
2448 *slots = port->vcpi.num_slots; 2500 *slots = port->vcpi.num_slots;
2501 drm_dp_put_port(port);
2449 return true; 2502 return true;
2450 } 2503 }
2451 } 2504 }
@@ -2605,32 +2658,31 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
2605 */ 2658 */
2606int drm_dp_calc_pbn_mode(int clock, int bpp) 2659int drm_dp_calc_pbn_mode(int clock, int bpp)
2607{ 2660{
2608 fixed20_12 pix_bw; 2661 u64 kbps;
2609 fixed20_12 fbpp; 2662 s64 peak_kbps;
2610 fixed20_12 result; 2663 u32 numerator;
2611 fixed20_12 margin, tmp; 2664 u32 denominator;
2612 u32 res; 2665
2613 2666 kbps = clock * bpp;
2614 pix_bw.full = dfixed_const(clock); 2667
2615 fbpp.full = dfixed_const(bpp); 2668 /*
2616 tmp.full = dfixed_const(8); 2669 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2617 fbpp.full = dfixed_div(fbpp, tmp); 2670 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2618 2671 * common multiplier to render an integer PBN for all link rate/lane
2619 result.full = dfixed_mul(pix_bw, fbpp); 2672 * counts combinations
2620 margin.full = dfixed_const(54); 2673 * calculate
2621 tmp.full = dfixed_const(64); 2674 * peak_kbps *= (1006/1000)
2622 margin.full = dfixed_div(margin, tmp); 2675 * peak_kbps *= (64/54)
2623 result.full = dfixed_div(result, margin); 2676 * peak_kbps *= 8 convert to bytes
2624 2677 */
2625 margin.full = dfixed_const(1006); 2678
2626 tmp.full = dfixed_const(1000); 2679 numerator = 64 * 1006;
2627 margin.full = dfixed_div(margin, tmp); 2680 denominator = 54 * 8 * 1000 * 1000;
2628 result.full = dfixed_mul(result, margin); 2681
2629 2682 kbps *= numerator;
2630 result.full = dfixed_div(result, tmp); 2683 peak_kbps = drm_fixp_from_fraction(kbps, denominator);
2631 result.full = dfixed_ceil(result); 2684
2632 res = dfixed_trunc(result); 2685 return drm_fixp2int_ceil(peak_kbps);
2633 return res;
2634} 2686}
2635EXPORT_SYMBOL(drm_dp_calc_pbn_mode); 2687EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
2636 2688
@@ -2638,11 +2690,23 @@ static int test_calc_pbn_mode(void)
2638{ 2690{
2639 int ret; 2691 int ret;
2640 ret = drm_dp_calc_pbn_mode(154000, 30); 2692 ret = drm_dp_calc_pbn_mode(154000, 30);
2641 if (ret != 689) 2693 if (ret != 689) {
2694 DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2695 154000, 30, 689, ret);
2642 return -EINVAL; 2696 return -EINVAL;
2697 }
2643 ret = drm_dp_calc_pbn_mode(234000, 30); 2698 ret = drm_dp_calc_pbn_mode(234000, 30);
2644 if (ret != 1047) 2699 if (ret != 1047) {
2700 DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2701 234000, 30, 1047, ret);
2645 return -EINVAL; 2702 return -EINVAL;
2703 }
2704 ret = drm_dp_calc_pbn_mode(297000, 24);
2705 if (ret != 1063) {
2706 DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2707 297000, 24, 1063, ret);
2708 return -EINVAL;
2709 }
2646 return 0; 2710 return 0;
2647} 2711}
2648 2712
@@ -2783,6 +2847,13 @@ static void drm_dp_tx_work(struct work_struct *work)
2783 mutex_unlock(&mgr->qlock); 2847 mutex_unlock(&mgr->qlock);
2784} 2848}
2785 2849
2850static void drm_dp_free_mst_port(struct kref *kref)
2851{
2852 struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref);
2853 kref_put(&port->parent->kref, drm_dp_free_mst_branch_device);
2854 kfree(port);
2855}
2856
2786static void drm_dp_destroy_connector_work(struct work_struct *work) 2857static void drm_dp_destroy_connector_work(struct work_struct *work)
2787{ 2858{
2788 struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work); 2859 struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work);
@@ -2803,13 +2874,22 @@ static void drm_dp_destroy_connector_work(struct work_struct *work)
2803 list_del(&port->next); 2874 list_del(&port->next);
2804 mutex_unlock(&mgr->destroy_connector_lock); 2875 mutex_unlock(&mgr->destroy_connector_lock);
2805 2876
2877 kref_init(&port->kref);
2878 INIT_LIST_HEAD(&port->next);
2879
2806 mgr->cbs->destroy_connector(mgr, port->connector); 2880 mgr->cbs->destroy_connector(mgr, port->connector);
2807 2881
2808 drm_dp_port_teardown_pdt(port, port->pdt); 2882 drm_dp_port_teardown_pdt(port, port->pdt);
2809 2883
2810 if (!port->input && port->vcpi.vcpi > 0) 2884 if (!port->input && port->vcpi.vcpi > 0) {
2811 drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); 2885 if (mgr->mst_state) {
2812 kfree(port); 2886 drm_dp_mst_reset_vcpi_slots(mgr, port);
2887 drm_dp_update_payload_part1(mgr);
2888 drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
2889 }
2890 }
2891
2892 kref_put(&port->kref, drm_dp_free_mst_port);
2813 send_hotplug = true; 2893 send_hotplug = true;
2814 } 2894 }
2815 if (send_hotplug) 2895 if (send_hotplug)
@@ -2847,6 +2927,9 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
2847 mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes; 2927 mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
2848 mgr->max_payloads = max_payloads; 2928 mgr->max_payloads = max_payloads;
2849 mgr->conn_base_id = conn_base_id; 2929 mgr->conn_base_id = conn_base_id;
2930 if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 ||
2931 max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8)
2932 return -EINVAL;
2850 mgr->payloads = kcalloc(max_payloads, sizeof(struct drm_dp_payload), GFP_KERNEL); 2933 mgr->payloads = kcalloc(max_payloads, sizeof(struct drm_dp_payload), GFP_KERNEL);
2851 if (!mgr->payloads) 2934 if (!mgr->payloads)
2852 return -ENOMEM; 2935 return -ENOMEM;
@@ -2854,7 +2937,9 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
2854 if (!mgr->proposed_vcpis) 2937 if (!mgr->proposed_vcpis)
2855 return -ENOMEM; 2938 return -ENOMEM;
2856 set_bit(0, &mgr->payload_mask); 2939 set_bit(0, &mgr->payload_mask);
2857 test_calc_pbn_mode(); 2940 if (test_calc_pbn_mode() < 0)
2941 DRM_ERROR("MST PBN self-test failed\n");
2942
2858 return 0; 2943 return 0;
2859} 2944}
2860EXPORT_SYMBOL(drm_dp_mst_topology_mgr_init); 2945EXPORT_SYMBOL(drm_dp_mst_topology_mgr_init);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index b79c316c2ad2..673164b331c8 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1392,7 +1392,7 @@ static const struct component_ops exynos_dp_ops = {
1392static int exynos_dp_probe(struct platform_device *pdev) 1392static int exynos_dp_probe(struct platform_device *pdev)
1393{ 1393{
1394 struct device *dev = &pdev->dev; 1394 struct device *dev = &pdev->dev;
1395 struct device_node *panel_node = NULL, *bridge_node, *endpoint = NULL; 1395 struct device_node *np = NULL, *endpoint = NULL;
1396 struct exynos_dp_device *dp; 1396 struct exynos_dp_device *dp;
1397 int ret; 1397 int ret;
1398 1398
@@ -1404,41 +1404,36 @@ static int exynos_dp_probe(struct platform_device *pdev)
1404 platform_set_drvdata(pdev, dp); 1404 platform_set_drvdata(pdev, dp);
1405 1405
1406 /* This is for the backward compatibility. */ 1406 /* This is for the backward compatibility. */
1407 panel_node = of_parse_phandle(dev->of_node, "panel", 0); 1407 np = of_parse_phandle(dev->of_node, "panel", 0);
1408 if (panel_node) { 1408 if (np) {
1409 dp->panel = of_drm_find_panel(panel_node); 1409 dp->panel = of_drm_find_panel(np);
1410 of_node_put(panel_node); 1410 of_node_put(np);
1411 if (!dp->panel) 1411 if (!dp->panel)
1412 return -EPROBE_DEFER; 1412 return -EPROBE_DEFER;
1413 } else {
1414 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1415 if (endpoint) {
1416 panel_node = of_graph_get_remote_port_parent(endpoint);
1417 if (panel_node) {
1418 dp->panel = of_drm_find_panel(panel_node);
1419 of_node_put(panel_node);
1420 if (!dp->panel)
1421 return -EPROBE_DEFER;
1422 } else {
1423 DRM_ERROR("no port node for panel device.\n");
1424 return -EINVAL;
1425 }
1426 }
1427 }
1428
1429 if (endpoint)
1430 goto out; 1413 goto out;
1414 }
1431 1415
1432 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); 1416 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1433 if (endpoint) { 1417 if (endpoint) {
1434 bridge_node = of_graph_get_remote_port_parent(endpoint); 1418 np = of_graph_get_remote_port_parent(endpoint);
1435 if (bridge_node) { 1419 if (np) {
1436 dp->ptn_bridge = of_drm_find_bridge(bridge_node); 1420 /* The remote port can be either a panel or a bridge */
1437 of_node_put(bridge_node); 1421 dp->panel = of_drm_find_panel(np);
1438 if (!dp->ptn_bridge) 1422 if (!dp->panel) {
1439 return -EPROBE_DEFER; 1423 dp->ptn_bridge = of_drm_find_bridge(np);
1440 } else 1424 if (!dp->ptn_bridge) {
1441 return -EPROBE_DEFER; 1425 of_node_put(np);
1426 return -EPROBE_DEFER;
1427 }
1428 }
1429 of_node_put(np);
1430 } else {
1431 DRM_ERROR("no remote endpoint device node found.\n");
1432 return -EINVAL;
1433 }
1434 } else {
1435 DRM_ERROR("no port endpoint subnode found.\n");
1436 return -EINVAL;
1442 } 1437 }
1443 1438
1444out: 1439out:
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index d84a498ef099..e977a81af2e6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1906,8 +1906,7 @@ static int exynos_dsi_remove(struct platform_device *pdev)
1906 return 0; 1906 return 0;
1907} 1907}
1908 1908
1909#ifdef CONFIG_PM 1909static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1910static int exynos_dsi_suspend(struct device *dev)
1911{ 1910{
1912 struct drm_encoder *encoder = dev_get_drvdata(dev); 1911 struct drm_encoder *encoder = dev_get_drvdata(dev);
1913 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1912 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
@@ -1938,7 +1937,7 @@ static int exynos_dsi_suspend(struct device *dev)
1938 return 0; 1937 return 0;
1939} 1938}
1940 1939
1941static int exynos_dsi_resume(struct device *dev) 1940static int __maybe_unused exynos_dsi_resume(struct device *dev)
1942{ 1941{
1943 struct drm_encoder *encoder = dev_get_drvdata(dev); 1942 struct drm_encoder *encoder = dev_get_drvdata(dev);
1944 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1943 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
@@ -1972,7 +1971,6 @@ err_clk:
1972 1971
1973 return ret; 1972 return ret;
1974} 1973}
1975#endif
1976 1974
1977static const struct dev_pm_ops exynos_dsi_pm_ops = { 1975static const struct dev_pm_ops exynos_dsi_pm_ops = {
1978 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 1976 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index b5fbc1cbf024..0a5a60005f7e 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -1289,8 +1289,7 @@ static int mixer_remove(struct platform_device *pdev)
1289 return 0; 1289 return 0;
1290} 1290}
1291 1291
1292#ifdef CONFIG_PM_SLEEP 1292static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1293static int exynos_mixer_suspend(struct device *dev)
1294{ 1293{
1295 struct mixer_context *ctx = dev_get_drvdata(dev); 1294 struct mixer_context *ctx = dev_get_drvdata(dev);
1296 struct mixer_resources *res = &ctx->mixer_res; 1295 struct mixer_resources *res = &ctx->mixer_res;
@@ -1306,7 +1305,7 @@ static int exynos_mixer_suspend(struct device *dev)
1306 return 0; 1305 return 0;
1307} 1306}
1308 1307
1309static int exynos_mixer_resume(struct device *dev) 1308static int __maybe_unused exynos_mixer_resume(struct device *dev)
1310{ 1309{
1311 struct mixer_context *ctx = dev_get_drvdata(dev); 1310 struct mixer_context *ctx = dev_get_drvdata(dev);
1312 struct mixer_resources *res = &ctx->mixer_res; 1311 struct mixer_resources *res = &ctx->mixer_res;
@@ -1342,7 +1341,6 @@ static int exynos_mixer_resume(struct device *dev)
1342 1341
1343 return 0; 1342 return 0;
1344} 1343}
1345#endif
1346 1344
1347static const struct dev_pm_ops exynos_mixer_pm_ops = { 1345static const struct dev_pm_ops exynos_mixer_pm_ops = {
1348 SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL) 1346 SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL)
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
index 533d1e3d4a99..a02112ba1c3d 100644
--- a/drivers/gpu/drm/i2c/adv7511.c
+++ b/drivers/gpu/drm/i2c/adv7511.c
@@ -136,6 +136,7 @@ static bool adv7511_register_volatile(struct device *dev, unsigned int reg)
136 case ADV7511_REG_BKSV(3): 136 case ADV7511_REG_BKSV(3):
137 case ADV7511_REG_BKSV(4): 137 case ADV7511_REG_BKSV(4):
138 case ADV7511_REG_DDC_STATUS: 138 case ADV7511_REG_DDC_STATUS:
139 case ADV7511_REG_EDID_READ_CTRL:
139 case ADV7511_REG_BSTATUS(0): 140 case ADV7511_REG_BSTATUS(0):
140 case ADV7511_REG_BSTATUS(1): 141 case ADV7511_REG_BSTATUS(1):
141 case ADV7511_REG_CHIP_ID_HIGH: 142 case ADV7511_REG_CHIP_ID_HIGH:
@@ -362,24 +363,31 @@ static void adv7511_power_on(struct adv7511 *adv7511)
362{ 363{
363 adv7511->current_edid_segment = -1; 364 adv7511->current_edid_segment = -1;
364 365
365 regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
366 ADV7511_INT0_EDID_READY);
367 regmap_write(adv7511->regmap, ADV7511_REG_INT(1),
368 ADV7511_INT1_DDC_ERROR);
369 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, 366 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
370 ADV7511_POWER_POWER_DOWN, 0); 367 ADV7511_POWER_POWER_DOWN, 0);
368 if (adv7511->i2c_main->irq) {
369 /*
370 * Documentation says the INT_ENABLE registers are reset in
371 * POWER_DOWN mode. My 7511w preserved the bits, however.
372 * Still, let's be safe and stick to the documentation.
373 */
374 regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
375 ADV7511_INT0_EDID_READY);
376 regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
377 ADV7511_INT1_DDC_ERROR);
378 }
371 379
372 /* 380 /*
373 * Per spec it is allowed to pulse the HDP signal to indicate that the 381 * Per spec it is allowed to pulse the HPD signal to indicate that the
374 * EDID information has changed. Some monitors do this when they wakeup 382 * EDID information has changed. Some monitors do this when they wakeup
375 * from standby or are enabled. When the HDP goes low the adv7511 is 383 * from standby or are enabled. When the HPD goes low the adv7511 is
376 * reset and the outputs are disabled which might cause the monitor to 384 * reset and the outputs are disabled which might cause the monitor to
377 * go to standby again. To avoid this we ignore the HDP pin for the 385 * go to standby again. To avoid this we ignore the HPD pin for the
378 * first few seconds after enabling the output. 386 * first few seconds after enabling the output.
379 */ 387 */
380 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2, 388 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
381 ADV7511_REG_POWER2_HDP_SRC_MASK, 389 ADV7511_REG_POWER2_HPD_SRC_MASK,
382 ADV7511_REG_POWER2_HDP_SRC_NONE); 390 ADV7511_REG_POWER2_HPD_SRC_NONE);
383 391
384 /* 392 /*
385 * Most of the registers are reset during power down or when HPD is low. 393 * Most of the registers are reset during power down or when HPD is low.
@@ -413,9 +421,9 @@ static bool adv7511_hpd(struct adv7511 *adv7511)
413 if (ret < 0) 421 if (ret < 0)
414 return false; 422 return false;
415 423
416 if (irq0 & ADV7511_INT0_HDP) { 424 if (irq0 & ADV7511_INT0_HPD) {
417 regmap_write(adv7511->regmap, ADV7511_REG_INT(0), 425 regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
418 ADV7511_INT0_HDP); 426 ADV7511_INT0_HPD);
419 return true; 427 return true;
420 } 428 }
421 429
@@ -438,7 +446,7 @@ static int adv7511_irq_process(struct adv7511 *adv7511)
438 regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0); 446 regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
439 regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1); 447 regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
440 448
441 if (irq0 & ADV7511_INT0_HDP && adv7511->encoder) 449 if (irq0 & ADV7511_INT0_HPD && adv7511->encoder)
442 drm_helper_hpd_irq_event(adv7511->encoder->dev); 450 drm_helper_hpd_irq_event(adv7511->encoder->dev);
443 451
444 if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) { 452 if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) {
@@ -567,12 +575,14 @@ static int adv7511_get_modes(struct drm_encoder *encoder,
567 575
568 /* Reading the EDID only works if the device is powered */ 576 /* Reading the EDID only works if the device is powered */
569 if (!adv7511->powered) { 577 if (!adv7511->powered) {
570 regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
571 ADV7511_INT0_EDID_READY);
572 regmap_write(adv7511->regmap, ADV7511_REG_INT(1),
573 ADV7511_INT1_DDC_ERROR);
574 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, 578 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
575 ADV7511_POWER_POWER_DOWN, 0); 579 ADV7511_POWER_POWER_DOWN, 0);
580 if (adv7511->i2c_main->irq) {
581 regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
582 ADV7511_INT0_EDID_READY);
583 regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
584 ADV7511_INT1_DDC_ERROR);
585 }
576 adv7511->current_edid_segment = -1; 586 adv7511->current_edid_segment = -1;
577 } 587 }
578 588
@@ -638,10 +648,10 @@ adv7511_encoder_detect(struct drm_encoder *encoder,
638 if (adv7511->status == connector_status_connected) 648 if (adv7511->status == connector_status_connected)
639 status = connector_status_disconnected; 649 status = connector_status_disconnected;
640 } else { 650 } else {
641 /* Renable HDP sensing */ 651 /* Renable HPD sensing */
642 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2, 652 regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
643 ADV7511_REG_POWER2_HDP_SRC_MASK, 653 ADV7511_REG_POWER2_HPD_SRC_MASK,
644 ADV7511_REG_POWER2_HDP_SRC_BOTH); 654 ADV7511_REG_POWER2_HPD_SRC_BOTH);
645 } 655 }
646 656
647 adv7511->status = status; 657 adv7511->status = status;
diff --git a/drivers/gpu/drm/i2c/adv7511.h b/drivers/gpu/drm/i2c/adv7511.h
index 6599ed538426..38515b30cedf 100644
--- a/drivers/gpu/drm/i2c/adv7511.h
+++ b/drivers/gpu/drm/i2c/adv7511.h
@@ -90,7 +90,7 @@
90#define ADV7511_CSC_ENABLE BIT(7) 90#define ADV7511_CSC_ENABLE BIT(7)
91#define ADV7511_CSC_UPDATE_MODE BIT(5) 91#define ADV7511_CSC_UPDATE_MODE BIT(5)
92 92
93#define ADV7511_INT0_HDP BIT(7) 93#define ADV7511_INT0_HPD BIT(7)
94#define ADV7511_INT0_VSYNC BIT(5) 94#define ADV7511_INT0_VSYNC BIT(5)
95#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4) 95#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
96#define ADV7511_INT0_EDID_READY BIT(2) 96#define ADV7511_INT0_EDID_READY BIT(2)
@@ -157,11 +157,11 @@
157#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1) 157#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
158#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0) 158#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
159 159
160#define ADV7511_REG_POWER2_HDP_SRC_MASK 0xc0 160#define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
161#define ADV7511_REG_POWER2_HDP_SRC_BOTH 0x00 161#define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
162#define ADV7511_REG_POWER2_HDP_SRC_HDP 0x40 162#define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
163#define ADV7511_REG_POWER2_HDP_SRC_CEC 0x80 163#define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
164#define ADV7511_REG_POWER2_HDP_SRC_NONE 0xc0 164#define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
165#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4) 165#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
166#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0) 166#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
167 167
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index fcd77b27514d..051eab33e4c7 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -10,7 +10,6 @@ config DRM_I915
10 # the shmem_readpage() which depends upon tmpfs 10 # the shmem_readpage() which depends upon tmpfs
11 select SHMEM 11 select SHMEM
12 select TMPFS 12 select TMPFS
13 select STOP_MACHINE
14 select DRM_KMS_HELPER 13 select DRM_KMS_HELPER
15 select DRM_PANEL 14 select DRM_PANEL
16 select DRM_MIPI_DSI 15 select DRM_MIPI_DSI
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3ac616d7363b..f357058c74d9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -501,7 +501,9 @@ void intel_detect_pch(struct drm_device *dev)
501 WARN_ON(!IS_SKYLAKE(dev) && 501 WARN_ON(!IS_SKYLAKE(dev) &&
502 !IS_KABYLAKE(dev)); 502 !IS_KABYLAKE(dev));
503 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || 503 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
504 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) { 504 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
505 pch->subsystem_vendor == 0x1af4 &&
506 pch->subsystem_device == 0x1100)) {
505 dev_priv->pch_type = intel_virt_detect_pch(dev); 507 dev_priv->pch_type = intel_virt_detect_pch(dev);
506 } else 508 } else
507 continue; 509 continue;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f00828ccc6e..5feb65725c04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2946,7 +2946,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2946 struct i915_vma *vma; 2946 struct i915_vma *vma;
2947 u64 offset; 2947 u64 offset;
2948 2948
2949 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, 2949 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2950 intel_plane->base.state); 2950 intel_plane->base.state);
2951 2951
2952 vma = i915_gem_obj_to_ggtt_view(obj, &view); 2952 vma = i915_gem_obj_to_ggtt_view(obj, &view);
@@ -12075,11 +12075,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
12075 pipe_config->pipe_bpp = connector->base.display_info.bpc*3; 12075 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12076 } 12076 }
12077 12077
12078 /* Clamp bpp to 8 on screens without EDID 1.4 */ 12078 /* Clamp bpp to default limit on screens without EDID 1.4 */
12079 if (connector->base.display_info.bpc == 0 && bpp > 24) { 12079 if (connector->base.display_info.bpc == 0) {
12080 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", 12080 int type = connector->base.connector_type;
12081 bpp); 12081 int clamp_bpp = 24;
12082 pipe_config->pipe_bpp = 24; 12082
12083 /* Fall back to 18 bpp when DP sink capability is unknown. */
12084 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12085 type == DRM_MODE_CONNECTOR_eDP)
12086 clamp_bpp = 18;
12087
12088 if (bpp > clamp_bpp) {
12089 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12090 bpp, clamp_bpp);
12091 pipe_config->pipe_bpp = clamp_bpp;
12092 }
12083 } 12093 }
12084} 12094}
12085 12095
@@ -13883,11 +13893,12 @@ intel_check_primary_plane(struct drm_plane *plane,
13883 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 13893 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13884 bool can_position = false; 13894 bool can_position = false;
13885 13895
13886 /* use scaler when colorkey is not required */ 13896 if (INTEL_INFO(plane->dev)->gen >= 9) {
13887 if (INTEL_INFO(plane->dev)->gen >= 9 && 13897 /* use scaler when colorkey is not required */
13888 state->ckey.flags == I915_SET_COLORKEY_NONE) { 13898 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13889 min_scale = 1; 13899 min_scale = 1;
13890 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); 13900 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13901 }
13891 can_position = true; 13902 can_position = true;
13892 } 13903 }
13893 13904
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa614731d7e..f1fa756c5d5d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1707,6 +1707,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1707 if (flush_domains) { 1707 if (flush_domains) {
1708 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 1708 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1709 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 1709 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1710 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1710 flags |= PIPE_CONTROL_FLUSH_ENABLE; 1711 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1711 } 1712 }
1712 1713
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 339701d7a9a5..40c6aff57256 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
331 if (flush_domains) { 331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
334 flags |= PIPE_CONTROL_FLUSH_ENABLE; 335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
335 } 336 }
336 if (invalidate_domains) { 337 if (invalidate_domains) {
@@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
403 if (flush_domains) { 404 if (flush_domains) {
404 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
405 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
406 flags |= PIPE_CONTROL_FLUSH_ENABLE; 408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
407 } 409 }
408 if (invalidate_domains) { 410 if (invalidate_domains) {
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 84d45633d28c..fb6ad143873f 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -33,6 +33,7 @@
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <drm/drmP.h> 34#include <drm/drmP.h>
35#include <drm/radeon_drm.h> 35#include <drm/radeon_drm.h>
36#include <drm/drm_cache.h>
36#include "radeon.h" 37#include "radeon.h"
37#include "radeon_trace.h" 38#include "radeon_trace.h"
38 39
@@ -245,6 +246,12 @@ int radeon_bo_create(struct radeon_device *rdev,
245 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 246 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
246 "better performance thanks to write-combining\n"); 247 "better performance thanks to write-combining\n");
247 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 248 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
249#else
250 /* For architectures that don't support WC memory,
251 * mask out the WC flag from the BO
252 */
253 if (!drm_arch_can_wc_memory())
254 bo->flags &= ~RADEON_GEM_GTT_WC;
248#endif 255#endif
249 256
250 radeon_ttm_placement_from_domain(bo, domain); 257 radeon_ttm_placement_from_domain(bo, domain);
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index c507896aca45..197b157b73d0 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -349,8 +349,13 @@ int radeon_sa_bo_new(struct radeon_device *rdev,
349 /* see if we can skip over some allocations */ 349 /* see if we can skip over some allocations */
350 } while (radeon_sa_bo_next_hole(sa_manager, fences, tries)); 350 } while (radeon_sa_bo_next_hole(sa_manager, fences, tries));
351 351
352 for (i = 0; i < RADEON_NUM_RINGS; ++i)
353 radeon_fence_ref(fences[i]);
354
352 spin_unlock(&sa_manager->wq.lock); 355 spin_unlock(&sa_manager->wq.lock);
353 r = radeon_fence_wait_any(rdev, fences, false); 356 r = radeon_fence_wait_any(rdev, fences, false);
357 for (i = 0; i < RADEON_NUM_RINGS; ++i)
358 radeon_fence_unref(&fences[i]);
354 spin_lock(&sa_manager->wq.lock); 359 spin_lock(&sa_manager->wq.lock);
355 /* if we have nothing to wait for block */ 360 /* if we have nothing to wait for block */
356 if (r == -ENOENT) { 361 if (r == -ENOENT) {
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 13:23:17 -0400