1 files changed, 91 insertions, 69 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65531463f88e..51bfc114584e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1795,15 +1795,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
        }
        /* post card */
-        amdgpu_atom_asic_init(adev->mode_info.atom_context);
+        if (!amdgpu_card_posted(adev))
+                amdgpu_atom_asic_init(adev->mode_info.atom_context);
        r = amdgpu_resume(adev);
+        if (r)
+                DRM_ERROR("amdgpu_resume failed (%d).\n", r);
        amdgpu_fence_driver_resume(adev);
-        r = amdgpu_ib_ring_tests(adev);
+        if (resume) {
-        if (r)
+                r = amdgpu_ib_ring_tests(adev);
-                DRM_ERROR("ib ring test failed (%d).\n", r);
+                if (r)
+                        DRM_ERROR("ib ring test failed (%d).\n", r);
+        }
        r = amdgpu_late_init(adev);
        if (r)
@@ -1933,80 +1938,97 @@ retry:
        return r;
 }
+#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */
+#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
 {
        u32 mask;
        int ret;
-        if (pci_is_root_bus(adev->pdev->bus))
+        if (amdgpu_pcie_gen_cap)
-                return;
+                adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
-        if (amdgpu_pcie_gen2 == 0)
+        if (amdgpu_pcie_lane_cap)
-                return;
+                adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
-        if (adev->flags & AMD_IS_APU)
+        /* covers APUs as well */
+        if (pci_is_root_bus(adev->pdev->bus)) {
+                if (adev->pm.pcie_gen_mask == 0)
+                        adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
+                if (adev->pm.pcie_mlw_mask == 0)
+                        adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
                return;
+        }
-        ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
+        if (adev->pm.pcie_gen_mask == 0) {
-        if (!ret) {
+                ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-                adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+                if (!ret) {
-                                          CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+                        adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
-                                          CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
+                                                  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+                                                  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-                if (mask & DRM_PCIE_SPEED_25)
-                        adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
+                        if (mask & DRM_PCIE_SPEED_25)
-                if (mask & DRM_PCIE_SPEED_50)
+                                adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
-                        adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
+                        if (mask & DRM_PCIE_SPEED_50)
-                if (mask & DRM_PCIE_SPEED_80)
+                                adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
-                        adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
+                        if (mask & DRM_PCIE_SPEED_80)
-        }
+                                adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
-        ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
+                } else {
-        if (!ret) {
+                        adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
-                switch (mask) {
+                }
-                case 32:
+        }
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
+        if (adev->pm.pcie_mlw_mask == 0) {
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
+                ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+                if (!ret) {
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+                        switch (mask) {
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+                        case 32:
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-                        break;
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-                case 16:
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+                                break;
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                        case 16:
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-                        break;
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-                case 12:
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                                break;
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                        case 12:
-                        break;
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-                case 8:
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                                break;
-                        break;
+                        case 8:
-                case 4:
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                        break;
+                                break;
-                case 2:
+                        case 4:
-                        adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-                                                  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                        break;
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                case 1:
+                                break;
-                        adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
+                        case 2:
-                        break;
+                                adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-                default:
+                                                          CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-                        break;
+                                break;
+                        case 1:
+                                adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
+                                break;
+                        default:
+                                break;
+                        }
+                } else {
+                        adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
                }
        }
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 65531463f88e..51bfc114584e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1795,15 +1795,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1795	}	1795	}
1796		1796
1797	/* post card */	1797	/* post card */
1798	amdgpu_atom_asic_init(adev->mode_info.atom_context);	1798	if (!amdgpu_card_posted(adev))
		1799	amdgpu_atom_asic_init(adev->mode_info.atom_context);
1799		1800
1800	r = amdgpu_resume(adev);	1801	r = amdgpu_resume(adev);
		1802	if (r)
		1803	DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1801		1804
1802	amdgpu_fence_driver_resume(adev);	1805	amdgpu_fence_driver_resume(adev);
1803		1806
1804	r = amdgpu_ib_ring_tests(adev);	1807	if (resume) {
1805	if (r)	1808	r = amdgpu_ib_ring_tests(adev);
1806	DRM_ERROR("ib ring test failed (%d).\n", r);	1809	if (r)
		1810	DRM_ERROR("ib ring test failed (%d).\n", r);
		1811	}
1807		1812
1808	r = amdgpu_late_init(adev);	1813	r = amdgpu_late_init(adev);
1809	if (r)	1814	if (r)
@@ -1933,80 +1938,97 @@ retry:
1933	return r;	1938	return r;
1934	}	1939	}
1935		1940
		1941	#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
		1942	#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
		1943
1936	void amdgpu_get_pcie_info(struct amdgpu_device *adev)	1944	void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1937	{	1945	{
1938	u32 mask;	1946	u32 mask;
1939	int ret;	1947	int ret;
1940		1948
1941	if (pci_is_root_bus(adev->pdev->bus))	1949	if (amdgpu_pcie_gen_cap)
1942	return;	1950	adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1943		1951
1944	if (amdgpu_pcie_gen2 == 0)	1952	if (amdgpu_pcie_lane_cap)
1945	return;	1953	adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1946		1954
1947	if (adev->flags & AMD_IS_APU)	1955	/* covers APUs as well */
		1956	if (pci_is_root_bus(adev->pdev->bus)) {
		1957	if (adev->pm.pcie_gen_mask == 0)
		1958	adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
		1959	if (adev->pm.pcie_mlw_mask == 0)
		1960	adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1948	return;	1961	return;
		1962	}
1949		1963
1950	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);	1964	if (adev->pm.pcie_gen_mask == 0) {
1951	if (!ret) {	1965	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1952	adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \|	1966	if (!ret) {
1953	CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \|	1967	adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \|
1954	CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);	1968	CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \|
1955		1969	CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1956	if (mask & DRM_PCIE_SPEED_25)	1970
1957	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;	1971	if (mask & DRM_PCIE_SPEED_25)
1958	if (mask & DRM_PCIE_SPEED_50)	1972	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1959	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;	1973	if (mask & DRM_PCIE_SPEED_50)
1960	if (mask & DRM_PCIE_SPEED_80)	1974	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1961	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;	1975	if (mask & DRM_PCIE_SPEED_80)
1962	}	1976	adev->pm.pcie_gen_mask \|= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1963	ret = drm_pcie_get_max_link_width(adev->ddev, &mask);	1977	} else {
1964	if (!ret) {	1978	adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1965	switch (mask) {	1979	}
1966	case 32:	1980	}
1967	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 \|	1981	if (adev->pm.pcie_mlw_mask == 0) {
1968	CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 \|	1982	ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1969	CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|	1983	if (!ret) {
1970	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|	1984	switch (mask) {
1971	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|	1985	case 32:
1972	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	1986	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 \|
1973	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	1987	CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 \|
1974	break;	1988	CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|
1975	case 16:	1989	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|
1976	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 \|	1990	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|
1977	CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|	1991	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
1978	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|	1992	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1979	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|	1993	break;
1980	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	1994	case 16:
1981	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	1995	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 \|
1982	break;	1996	CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|
1983	case 12:	1997	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|
1984	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|	1998	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|
1985	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|	1999	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
1986	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|	2000	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1987	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	2001	break;
1988	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	2002	case 12:
1989	break;	2003	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 \|
1990	case 8:	2004	CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|
1991	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|	2005	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|
1992	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|	2006	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
1993	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	2007	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1994	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	2008	break;
1995	break;	2009	case 8:
1996	case 4:	2010	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \|
1997	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|	2011	CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|
1998	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	2012	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
1999	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	2013	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2000	break;	2014	break;
2001	case 2:	2015	case 4:
2002	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|	2016	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \|
2003	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);	2017	CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
2004	break;	2018	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2005	case 1:	2019	break;
2006	adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;	2020	case 2:
2007	break;	2021	adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \|
2008	default:	2022	CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2009	break;	2023	break;
		2024	case 1:
		2025	adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
		2026	break;
		2027	default:
		2028	break;
		2029	}
		2030	} else {
		2031	adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2010	}	2032	}
2011	}	2033	}
2012	}	2034	}