2 files changed, 26 insertions, 2 deletions

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index d8e1fd93908f..40422f6b645e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -107,11 +107,34 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
         .num_lvds = 1,
 };
 
+static const struct rcar_du_device_info rcar_du_r8a7794_info = {
+        .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+                  | RCAR_DU_FEATURE_EXT_CTRL_REGS,
+        .num_crtcs = 2,
+        .routes = {
+                /* R8A7794 has two RGB outputs and one (currently unsupported)
+                 * TCON output.
+                 */
+                [RCAR_DU_OUTPUT_DPAD0] = {
+                        .possible_crtcs = BIT(0),
+                        .encoder_type = DRM_MODE_ENCODER_NONE,
+                        .port = 0,
+                },
+                [RCAR_DU_OUTPUT_DPAD1] = {
+                        .possible_crtcs = BIT(1),
+                        .encoder_type = DRM_MODE_ENCODER_NONE,
+                        .port = 1,
+                },
+        },
+        .num_lvds = 0,
+};
+
 static const struct of_device_id rcar_du_of_table[] = {
         { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
         { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
         { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
         { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
+        { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
         { }
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 7fd39a7d91c8..8e2ffe025153 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -49,9 +49,10 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
         u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
 
         /* The DEFR8 register for the first group also controls RGB output
-         * routing to DPAD0
+         * routing to DPAD0 for DU instances that support it.
          */
-        if (rgrp->index == 0)
+        if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1 &&
+            rgrp->index == 0)
                 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
 
         rcar_du_group_write(rgrp, DEFR8, defr8);