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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2015-07-17 03:44:33 -0400
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2015-10-21 11:52:38 -0400
commit090425c45db3ec438c161f6a5dd05d1824e65dcd (patch)
treeb3f13b29bfa5c55c434679ef3e3819924eea948b /drivers/gpu
parentf1ceb84ae0fba02dcb5aa0ff56b5546767376795 (diff)
drm: rcar-du: Add support for the R8A7794 DU
The R8A7794 DU has a fixed output routing configuration with one RGB output per CRTC and thus lacks the RGB output routing register field. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_drv.c23
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_group.c5
2 files changed, 26 insertions, 2 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index d8e1fd93908f..40422f6b645e 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -107,11 +107,34 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
107 .num_lvds = 1, 107 .num_lvds = 1,
108}; 108};
109 109
110static const struct rcar_du_device_info rcar_du_r8a7794_info = {
111 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
112 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
113 .num_crtcs = 2,
114 .routes = {
115 /* R8A7794 has two RGB outputs and one (currently unsupported)
116 * TCON output.
117 */
118 [RCAR_DU_OUTPUT_DPAD0] = {
119 .possible_crtcs = BIT(0),
120 .encoder_type = DRM_MODE_ENCODER_NONE,
121 .port = 0,
122 },
123 [RCAR_DU_OUTPUT_DPAD1] = {
124 .possible_crtcs = BIT(1),
125 .encoder_type = DRM_MODE_ENCODER_NONE,
126 .port = 1,
127 },
128 },
129 .num_lvds = 0,
130};
131
110static const struct of_device_id rcar_du_of_table[] = { 132static const struct of_device_id rcar_du_of_table[] = {
111 { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, 133 { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
112 { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, 134 { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
113 { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info }, 135 { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
114 { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info }, 136 { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
137 { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
115 { } 138 { }
116}; 139};
117 140
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 7fd39a7d91c8..8e2ffe025153 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -49,9 +49,10 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
49 u32 defr8 = DEFR8_CODE | DEFR8_DEFE8; 49 u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
50 50
51 /* The DEFR8 register for the first group also controls RGB output 51 /* The DEFR8 register for the first group also controls RGB output
52 * routing to DPAD0 52 * routing to DPAD0 for DU instances that support it.
53 */ 53 */
54 if (rgrp->index == 0) 54 if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1 &&
55 rgrp->index == 0)
55 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source); 56 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
56 57
57 rcar_du_group_write(rgrp, DEFR8, defr8); 58 rcar_du_group_write(rgrp, DEFR8, defr8);