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path: root/drivers/gpu/drm/radeon/cik.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r--drivers/gpu/drm/radeon/cik.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 377afa504d2b..89c01fa6dd8e 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
4313 /* init the CE partitions. CE only used for gfx on CIK */ 4313 /* init the CE partitions. CE only used for gfx on CIK */
4314 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 4314 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4315 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 4315 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4316 radeon_ring_write(ring, 0xc000); 4316 radeon_ring_write(ring, 0x8000);
4317 radeon_ring_write(ring, 0xc000); 4317 radeon_ring_write(ring, 0x8000);
4318 4318
4319 /* setup clear context state */ 4319 /* setup clear context state */
4320 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4320 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
@@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
9447 u32 num_heads = 0, lb_size; 9447 u32 num_heads = 0, lb_size;
9448 int i; 9448 int i;
9449 9449
9450 if (!rdev->mode_info.mode_config_initialized)
9451 return;
9452
9450 radeon_update_display_priority(rdev); 9453 radeon_update_display_priority(rdev);
9451 9454
9452 for (i = 0; i < rdev->num_crtc; i++) { 9455 for (i = 0; i < rdev->num_crtc; i++) {