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path: root/drivers/gpu/drm/i915/i915_gem.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bbcd35abf247..f36126383d26 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1544,7 +1544,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1544 1544
1545 /* Access to snoopable pages through the GTT is incoherent. */ 1545 /* Access to snoopable pages through the GTT is incoherent. */
1546 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { 1546 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1547 ret = -EINVAL; 1547 ret = -EFAULT;
1548 goto unlock; 1548 goto unlock;
1549 } 1549 }
1550 1550
@@ -4894,7 +4894,7 @@ i915_gem_load(struct drm_device *dev)
4894 init_waitqueue_head(&dev_priv->gpu_error.reset_queue); 4894 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4895 4895
4896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 4896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4897 if (IS_GEN3(dev)) { 4897 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4898 I915_WRITE(MI_ARB_STATE, 4898 I915_WRITE(MI_ARB_STATE,
4899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 4899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4900 } 4900 }