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-rw-r--r--drivers/gpu/drm/drm_crtc.c7
-rw-r--r--drivers/gpu/drm/drm_plane_helper.c131
-rw-r--r--drivers/gpu/drm/i915/Makefile1
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c6
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c19
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c7
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c83
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h6
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c13
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c145
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h6
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c30
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.h2
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_panel_vbt.c589
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c95
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c21
-rw-r--r--include/drm/drm_plane_helper.h22
21 files changed, 979 insertions, 216 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 239342f554b4..fe94cc10cd35 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2178,6 +2178,13 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
2178 goto out; 2178 goto out;
2179 } 2179 }
2180 2180
2181 /* Check whether this plane is usable on this CRTC */
2182 if (!(plane->possible_crtcs & drm_crtc_mask(crtc))) {
2183 DRM_DEBUG_KMS("Invalid crtc for plane\n");
2184 ret = -EINVAL;
2185 goto out;
2186 }
2187
2181 fb = drm_framebuffer_lookup(dev, plane_req->fb_id); 2188 fb = drm_framebuffer_lookup(dev, plane_req->fb_id);
2182 if (!fb) { 2189 if (!fb) {
2183 DRM_DEBUG_KMS("Unknown framebuffer ID %d\n", 2190 DRM_DEBUG_KMS("Unknown framebuffer ID %d\n",
diff --git a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
index 1b15643b4586..6d133149cc74 100644
--- a/drivers/gpu/drm/drm_plane_helper.c
+++ b/drivers/gpu/drm/drm_plane_helper.c
@@ -25,6 +25,7 @@
25 25
26#include <linux/list.h> 26#include <linux/list.h>
27#include <drm/drmP.h> 27#include <drm/drmP.h>
28#include <drm/drm_plane_helper.h>
28#include <drm/drm_rect.h> 29#include <drm/drm_rect.h>
29#include <drm/drm_plane_helper.h> 30#include <drm/drm_plane_helper.h>
30 31
@@ -74,6 +75,79 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
74} 75}
75 76
76/** 77/**
78 * drm_plane_helper_check_update() - Check plane update for validity
79 * @plane: plane object to update
80 * @crtc: owning CRTC of owning plane
81 * @fb: framebuffer to flip onto plane
82 * @src: source coordinates in 16.16 fixed point
83 * @dest: integer destination coordinates
84 * @clip: integer clipping coordinates
85 * @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
86 * @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
87 * @can_position: is it legal to position the plane such that it
88 * doesn't cover the entire crtc? This will generally
89 * only be false for primary planes.
90 * @can_update_disabled: can the plane be updated while the crtc
91 * is disabled?
92 * @visible: output parameter indicating whether plane is still visible after
93 * clipping
94 *
95 * Checks that a desired plane update is valid. Drivers that provide
96 * their own plane handling rather than helper-provided implementations may
97 * still wish to call this function to avoid duplication of error checking
98 * code.
99 *
100 * RETURNS:
101 * Zero if update appears valid, error code on failure
102 */
103int drm_plane_helper_check_update(struct drm_plane *plane,
104 struct drm_crtc *crtc,
105 struct drm_framebuffer *fb,
106 struct drm_rect *src,
107 struct drm_rect *dest,
108 const struct drm_rect *clip,
109 int min_scale,
110 int max_scale,
111 bool can_position,
112 bool can_update_disabled,
113 bool *visible)
114{
115 int hscale, vscale;
116
117 if (!crtc->enabled && !can_update_disabled) {
118 DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
119 return -EINVAL;
120 }
121
122 /* Check scaling */
123 hscale = drm_rect_calc_hscale(src, dest, min_scale, max_scale);
124 vscale = drm_rect_calc_vscale(src, dest, min_scale, max_scale);
125 if (hscale < 0 || vscale < 0) {
126 DRM_DEBUG_KMS("Invalid scaling of plane\n");
127 return -ERANGE;
128 }
129
130 *visible = drm_rect_clip_scaled(src, dest, clip, hscale, vscale);
131 if (!*visible)
132 /*
133 * Plane isn't visible; some drivers can handle this
134 * so we just return success here. Drivers that can't
135 * (including those that use the primary plane helper's
136 * update function) will return an error from their
137 * update_plane handler.
138 */
139 return 0;
140
141 if (!can_position && !drm_rect_equals(dest, clip)) {
142 DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
143 return -EINVAL;
144 }
145
146 return 0;
147}
148EXPORT_SYMBOL(drm_plane_helper_check_update);
149
150/**
77 * drm_primary_helper_update() - Helper for primary plane update 151 * drm_primary_helper_update() - Helper for primary plane update
78 * @plane: plane object to update 152 * @plane: plane object to update
79 * @crtc: owning CRTC of owning plane 153 * @crtc: owning CRTC of owning plane
@@ -121,57 +195,42 @@ int drm_primary_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
121 .x = src_x >> 16, 195 .x = src_x >> 16,
122 .y = src_y >> 16, 196 .y = src_y >> 16,
123 }; 197 };
198 struct drm_rect src = {
199 .x1 = src_x,
200 .y1 = src_y,
201 .x2 = src_x + src_w,
202 .y2 = src_y + src_h,
203 };
124 struct drm_rect dest = { 204 struct drm_rect dest = {
125 .x1 = crtc_x, 205 .x1 = crtc_x,
126 .y1 = crtc_y, 206 .y1 = crtc_y,
127 .x2 = crtc_x + crtc_w, 207 .x2 = crtc_x + crtc_w,
128 .y2 = crtc_y + crtc_h, 208 .y2 = crtc_y + crtc_h,
129 }; 209 };
130 struct drm_rect clip = { 210 const struct drm_rect clip = {
131 .x2 = crtc->mode.hdisplay, 211 .x2 = crtc->mode.hdisplay,
132 .y2 = crtc->mode.vdisplay, 212 .y2 = crtc->mode.vdisplay,
133 }; 213 };
134 struct drm_connector **connector_list; 214 struct drm_connector **connector_list;
135 int num_connectors, ret; 215 int num_connectors, ret;
216 bool visible;
136 217
137 if (!crtc->enabled) { 218 ret = drm_plane_helper_check_update(plane, crtc, fb,
138 DRM_DEBUG_KMS("Cannot update primary plane of a disabled CRTC.\n"); 219 &src, &dest, &clip,
139 return -EINVAL; 220 DRM_PLANE_HELPER_NO_SCALING,
140 } 221 DRM_PLANE_HELPER_NO_SCALING,
141 222 false, false, &visible);
142 /* Disallow subpixel positioning */
143 if ((src_x | src_y | src_w | src_h) & SUBPIXEL_MASK) {
144 DRM_DEBUG_KMS("Primary plane does not support subpixel positioning\n");
145 return -EINVAL;
146 }
147
148 /* Primary planes are locked to their owning CRTC */
149 if (plane->possible_crtcs != drm_crtc_mask(crtc)) {
150 DRM_DEBUG_KMS("Cannot change primary plane CRTC\n");
151 return -EINVAL;
152 }
153
154 /* Disallow scaling */
155 src_w >>= 16;
156 src_h >>= 16;
157 if (crtc_w != src_w || crtc_h != src_h) {
158 DRM_DEBUG_KMS("Can't scale primary plane\n");
159 return -EINVAL;
160 }
161
162 /* Make sure primary plane covers entire CRTC */
163 drm_rect_intersect(&dest, &clip);
164 if (dest.x1 != 0 || dest.y1 != 0 ||
165 dest.x2 != crtc->mode.hdisplay || dest.y2 != crtc->mode.vdisplay) {
166 DRM_DEBUG_KMS("Primary plane must cover entire CRTC\n");
167 return -EINVAL;
168 }
169
170 /* Framebuffer must be big enough to cover entire plane */
171 ret = drm_crtc_check_viewport(crtc, crtc_x, crtc_y, &crtc->mode, fb);
172 if (ret) 223 if (ret)
173 return ret; 224 return ret;
174 225
226 if (!visible)
227 /*
228 * Primary plane isn't visible. Note that unless a driver
229 * provides their own disable function, this will just
230 * wind up returning -EINVAL to userspace.
231 */
232 return plane->funcs->disable_plane(plane);
233
175 /* Find current connectors for CRTC */ 234 /* Find current connectors for CRTC */
176 num_connectors = get_connectors_for_crtc(crtc, NULL, 0); 235 num_connectors = get_connectors_for_crtc(crtc, NULL, 0);
177 BUG_ON(num_connectors == 0); 236 BUG_ON(num_connectors == 0);
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7b2f3bee3518..cad1683d8bb5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += dvo_ch7017.o \
62 intel_dsi_cmd.o \ 62 intel_dsi_cmd.o \
63 intel_dsi.o \ 63 intel_dsi.o \
64 intel_dsi_pll.o \ 64 intel_dsi_pll.o \
65 intel_dsi_panel_vbt.o \
65 intel_dvo.o \ 66 intel_dvo.o \
66 intel_hdmi.o \ 67 intel_hdmi.o \
67 intel_i2c.o \ 68 intel_i2c.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 169fc2d8c554..601caa88c092 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2353,10 +2353,14 @@ static int i915_display_info(struct seq_file *m, void *unused)
2353 2353
2354 active = cursor_position(dev, crtc->pipe, &x, &y); 2354 active = cursor_position(dev, crtc->pipe, &x, &y);
2355 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n", 2355 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2356 yesno(crtc->cursor_visible), 2356 yesno(crtc->cursor_base),
2357 x, y, crtc->cursor_addr, 2357 x, y, crtc->cursor_addr,
2358 yesno(active)); 2358 yesno(active));
2359 } 2359 }
2360
2361 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2362 yesno(!crtc->cpu_fifo_underrun_disabled),
2363 yesno(!crtc->pch_fifo_underrun_disabled));
2360 } 2364 }
2361 2365
2362 seq_printf(m, "\n"); 2366 seq_printf(m, "\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5b5b82c3f570..651e65e051c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,6 +321,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
321 .has_ddi = 1, 321 .has_ddi = 1,
322 .has_fbc = 1, 322 .has_fbc = 1,
323 GEN_DEFAULT_PIPEOFFSETS, 323 GEN_DEFAULT_PIPEOFFSETS,
324 IVB_CURSOR_OFFSETS,
324}; 325};
325 326
326static const struct intel_device_info intel_broadwell_gt3d_info = { 327static const struct intel_device_info intel_broadwell_gt3d_info = {
@@ -331,6 +332,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = {
331 .has_ddi = 1, 332 .has_ddi = 1,
332 .has_fbc = 1, 333 .has_fbc = 1,
333 GEN_DEFAULT_PIPEOFFSETS, 334 GEN_DEFAULT_PIPEOFFSETS,
335 IVB_CURSOR_OFFSETS,
334}; 336};
335 337
336static const struct intel_device_info intel_broadwell_gt3m_info = { 338static const struct intel_device_info intel_broadwell_gt3m_info = {
@@ -811,17 +813,17 @@ int i915_reset(struct drm_device *dev)
811 } 813 }
812 814
813 /* 815 /*
814 * FIXME: This is horribly race against concurrent pageflip and 816 * FIXME: This races pretty badly against concurrent holders of
815 * vblank wait ioctls since they can observe dev->irqs_disabled 817 * ring interrupts. This is possible since we've started to drop
816 * being false when they shouldn't be able to. 818 * dev->struct_mutex in select places when waiting for the gpu.
817 */ 819 */
818 drm_irq_uninstall(dev);
819 drm_irq_install(dev, dev->pdev->irq);
820 820
821 /* rps/rc6 re-init is necessary to restore state lost after the 821 /*
822 * reset and the re-install of drm irq. Skip for ironlake per 822 * rps/rc6 re-init is necessary to restore state lost after the
823 * reset and the re-install of gt irqs. Skip for ironlake per
823 * previous concerns that it doesn't respond well to some forms 824 * previous concerns that it doesn't respond well to some forms
824 * of re-init after reset. */ 825 * of re-init after reset.
826 */
825 if (INTEL_INFO(dev)->gen > 5) 827 if (INTEL_INFO(dev)->gen > 5)
826 intel_reset_gt_powersave(dev); 828 intel_reset_gt_powersave(dev);
827 829
@@ -1583,6 +1585,7 @@ static int __init i915_init(void)
1583 driver.get_vblank_timestamp = NULL; 1585 driver.get_vblank_timestamp = NULL;
1584#ifndef CONFIG_DRM_I915_UMS 1586#ifndef CONFIG_DRM_I915_UMS
1585 /* Silently fail loading to not upset userspace. */ 1587 /* Silently fail loading to not upset userspace. */
1588 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1586 return 0; 1589 return 0;
1587#endif 1590#endif
1588 } 1591 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e78703e45cf..49414d30e8d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1207,6 +1207,7 @@ struct intel_vbt_data {
1207 unsigned int lvds_use_ssc:1; 1207 unsigned int lvds_use_ssc:1;
1208 unsigned int display_clock_mode:1; 1208 unsigned int display_clock_mode:1;
1209 unsigned int fdi_rx_polarity_inverted:1; 1209 unsigned int fdi_rx_polarity_inverted:1;
1210 unsigned int has_mipi:1;
1210 int lvds_ssc_freq; 1211 int lvds_ssc_freq;
1211 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1212 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1212 1213
@@ -1230,6 +1231,7 @@ struct intel_vbt_data {
1230 1231
1231 /* MIPI DSI */ 1232 /* MIPI DSI */
1232 struct { 1233 struct {
1234 u16 port;
1233 u16 panel_id; 1235 u16 panel_id;
1234 struct mipi_config *config; 1236 struct mipi_config *config;
1235 struct mipi_pps_data *pps; 1237 struct mipi_pps_data *pps;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bbcd35abf247..f36126383d26 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1544,7 +1544,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1544 1544
1545 /* Access to snoopable pages through the GTT is incoherent. */ 1545 /* Access to snoopable pages through the GTT is incoherent. */
1546 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { 1546 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1547 ret = -EINVAL; 1547 ret = -EFAULT;
1548 goto unlock; 1548 goto unlock;
1549 } 1549 }
1550 1550
@@ -4894,7 +4894,7 @@ i915_gem_load(struct drm_device *dev)
4894 init_waitqueue_head(&dev_priv->gpu_error.reset_queue); 4894 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4895 4895
4896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 4896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4897 if (IS_GEN3(dev)) { 4897 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4898 I915_WRITE(MI_ARB_STATE, 4898 I915_WRITE(MI_ARB_STATE,
4899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 4899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4900 } 4900 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 931b906f292a..eec820aec022 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1775,6 +1775,13 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1775 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 1775 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1776 if (bdw_gmch_ctl) 1776 if (bdw_gmch_ctl)
1777 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 1777 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1778
1779#ifdef CONFIG_X86_32
1780 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1781 if (bdw_gmch_ctl > 4)
1782 bdw_gmch_ctl = 4;
1783#endif
1784
1778 return bdw_gmch_ctl << 20; 1785 return bdw_gmch_ctl << 20;
1779} 1786}
1780 1787
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cbf31cbfa084..cf288a95347c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -335,7 +335,8 @@ void i9xx_check_fifo_underruns(struct drm_device *dev)
335} 335}
336 336
337static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 337static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
338 enum pipe pipe, bool enable) 338 enum pipe pipe,
339 bool enable, bool old)
339{ 340{
340 struct drm_i915_private *dev_priv = dev->dev_private; 341 struct drm_i915_private *dev_priv = dev->dev_private;
341 u32 reg = PIPESTAT(pipe); 342 u32 reg = PIPESTAT(pipe);
@@ -347,7 +348,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
347 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
348 POSTING_READ(reg); 349 POSTING_READ(reg);
349 } else { 350 } else {
350 if (pipestat & PIPE_FIFO_UNDERRUN_STATUS) 351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
351 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
352 } 353 }
353} 354}
@@ -366,7 +367,8 @@ static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
366} 367}
367 368
368static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 369static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
369 enum pipe pipe, bool enable) 370 enum pipe pipe,
371 bool enable, bool old)
370{ 372{
371 struct drm_i915_private *dev_priv = dev->dev_private; 373 struct drm_i915_private *dev_priv = dev->dev_private;
372 if (enable) { 374 if (enable) {
@@ -379,7 +381,8 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
379 } else { 381 } else {
380 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
381 383
382 if (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { 384 if (old &&
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
383 DRM_ERROR("uncleared fifo underrun on pipe %c\n", 386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
384 pipe_name(pipe)); 387 pipe_name(pipe));
385 } 388 }
@@ -444,7 +447,7 @@ static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
444 447
445static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 448static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
446 enum transcoder pch_transcoder, 449 enum transcoder pch_transcoder,
447 bool enable) 450 bool enable, bool old)
448{ 451{
449 struct drm_i915_private *dev_priv = dev->dev_private; 452 struct drm_i915_private *dev_priv = dev->dev_private;
450 453
@@ -459,7 +462,8 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
459 } else { 462 } else {
460 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
461 464
462 if (I915_READ(SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { 465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
463 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", 467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
464 transcoder_name(pch_transcoder)); 468 transcoder_name(pch_transcoder));
465 } 469 }
@@ -486,28 +490,23 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
486 struct drm_i915_private *dev_priv = dev->dev_private; 490 struct drm_i915_private *dev_priv = dev->dev_private;
487 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
489 bool ret; 493 bool old;
490 494
491 assert_spin_locked(&dev_priv->irq_lock); 495 assert_spin_locked(&dev_priv->irq_lock);
492 496
493 ret = !intel_crtc->cpu_fifo_underrun_disabled; 497 old = !intel_crtc->cpu_fifo_underrun_disabled;
494
495 if (enable == ret)
496 goto done;
497
498 intel_crtc->cpu_fifo_underrun_disabled = !enable; 498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499 499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable); 501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev)) 502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev)) 504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); 505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev)) 506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508 508
509done: 509 return old;
510 return ret;
511} 510}
512 511
513bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 512bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
@@ -556,7 +555,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; 555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
558 unsigned long flags; 557 unsigned long flags;
559 bool ret; 558 bool old;
560 559
561 /* 560 /*
562 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
@@ -569,21 +568,16 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
569 568
570 spin_lock_irqsave(&dev_priv->irq_lock, flags); 569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
571 570
572 ret = !intel_crtc->pch_fifo_underrun_disabled; 571 old = !intel_crtc->pch_fifo_underrun_disabled;
573
574 if (enable == ret)
575 goto done;
576
577 intel_crtc->pch_fifo_underrun_disabled = !enable; 572 intel_crtc->pch_fifo_underrun_disabled = !enable;
578 573
579 if (HAS_PCH_IBX(dev)) 574 if (HAS_PCH_IBX(dev))
580 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
581 else 576 else
582 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
583 578
584done:
585 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
586 return ret; 580 return old;
587} 581}
588 582
589 583
@@ -2634,10 +2628,6 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
2634 else 2628 else
2635 i915_enable_pipestat(dev_priv, pipe, 2629 i915_enable_pipestat(dev_priv, pipe,
2636 PIPE_VBLANK_INTERRUPT_STATUS); 2630 PIPE_VBLANK_INTERRUPT_STATUS);
2637
2638 /* maintain vblank delivery even in deep C-states */
2639 if (INTEL_INFO(dev)->gen == 3)
2640 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2631 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2642 2632
2643 return 0; 2633 return 0;
@@ -2701,9 +2691,6 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
2701 unsigned long irqflags; 2691 unsigned long irqflags;
2702 2692
2703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2693 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2704 if (INTEL_INFO(dev)->gen == 3)
2705 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2706
2707 i915_disable_pipestat(dev_priv, pipe, 2694 i915_disable_pipestat(dev_priv, pipe,
2708 PIPE_VBLANK_INTERRUPT_STATUS | 2695 PIPE_VBLANK_INTERRUPT_STATUS |
2709 PIPE_START_VBLANK_INTERRUPT_STATUS); 2696 PIPE_START_VBLANK_INTERRUPT_STATUS);
@@ -3117,11 +3104,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
3117 ibx_irq_reset(dev); 3104 ibx_irq_reset(dev);
3118} 3105}
3119 3106
3120static void ironlake_irq_preinstall(struct drm_device *dev)
3121{
3122 ironlake_irq_reset(dev);
3123}
3124
3125static void valleyview_irq_preinstall(struct drm_device *dev) 3107static void valleyview_irq_preinstall(struct drm_device *dev)
3126{ 3108{
3127 struct drm_i915_private *dev_priv = dev->dev_private; 3109 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3151,6 +3133,14 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
3151 POSTING_READ(VLV_IER); 3133 POSTING_READ(VLV_IER);
3152} 3134}
3153 3135
3136static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3137{
3138 GEN8_IRQ_RESET_NDX(GT, 0);
3139 GEN8_IRQ_RESET_NDX(GT, 1);
3140 GEN8_IRQ_RESET_NDX(GT, 2);
3141 GEN8_IRQ_RESET_NDX(GT, 3);
3142}
3143
3154static void gen8_irq_reset(struct drm_device *dev) 3144static void gen8_irq_reset(struct drm_device *dev)
3155{ 3145{
3156 struct drm_i915_private *dev_priv = dev->dev_private; 3146 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3159,10 +3149,7 @@ static void gen8_irq_reset(struct drm_device *dev)
3159 I915_WRITE(GEN8_MASTER_IRQ, 0); 3149 I915_WRITE(GEN8_MASTER_IRQ, 0);
3160 POSTING_READ(GEN8_MASTER_IRQ); 3150 POSTING_READ(GEN8_MASTER_IRQ);
3161 3151
3162 GEN8_IRQ_RESET_NDX(GT, 0); 3152 gen8_gt_irq_reset(dev_priv);
3163 GEN8_IRQ_RESET_NDX(GT, 1);
3164 GEN8_IRQ_RESET_NDX(GT, 2);
3165 GEN8_IRQ_RESET_NDX(GT, 3);
3166 3153
3167 for_each_pipe(pipe) 3154 for_each_pipe(pipe)
3168 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); 3155 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
@@ -3174,11 +3161,6 @@ static void gen8_irq_reset(struct drm_device *dev)
3174 ibx_irq_reset(dev); 3161 ibx_irq_reset(dev);
3175} 3162}
3176 3163
3177static void gen8_irq_preinstall(struct drm_device *dev)
3178{
3179 gen8_irq_reset(dev);
3180}
3181
3182static void cherryview_irq_preinstall(struct drm_device *dev) 3164static void cherryview_irq_preinstall(struct drm_device *dev)
3183{ 3165{
3184 struct drm_i915_private *dev_priv = dev->dev_private; 3166 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3187,10 +3169,7 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
3187 I915_WRITE(GEN8_MASTER_IRQ, 0); 3169 I915_WRITE(GEN8_MASTER_IRQ, 0);
3188 POSTING_READ(GEN8_MASTER_IRQ); 3170 POSTING_READ(GEN8_MASTER_IRQ);
3189 3171
3190 GEN8_IRQ_RESET_NDX(GT, 0); 3172 gen8_gt_irq_reset(dev_priv);
3191 GEN8_IRQ_RESET_NDX(GT, 1);
3192 GEN8_IRQ_RESET_NDX(GT, 2);
3193 GEN8_IRQ_RESET_NDX(GT, 3);
3194 3173
3195 GEN5_IRQ_RESET(GEN8_PCU_); 3174 GEN5_IRQ_RESET(GEN8_PCU_);
3196 3175
@@ -4387,7 +4366,7 @@ void intel_irq_init(struct drm_device *dev)
4387 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4366 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4388 } else if (IS_GEN8(dev)) { 4367 } else if (IS_GEN8(dev)) {
4389 dev->driver->irq_handler = gen8_irq_handler; 4368 dev->driver->irq_handler = gen8_irq_handler;
4390 dev->driver->irq_preinstall = gen8_irq_preinstall; 4369 dev->driver->irq_preinstall = gen8_irq_reset;
4391 dev->driver->irq_postinstall = gen8_irq_postinstall; 4370 dev->driver->irq_postinstall = gen8_irq_postinstall;
4392 dev->driver->irq_uninstall = gen8_irq_uninstall; 4371 dev->driver->irq_uninstall = gen8_irq_uninstall;
4393 dev->driver->enable_vblank = gen8_enable_vblank; 4372 dev->driver->enable_vblank = gen8_enable_vblank;
@@ -4395,7 +4374,7 @@ void intel_irq_init(struct drm_device *dev)
4395 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 4374 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4396 } else if (HAS_PCH_SPLIT(dev)) { 4375 } else if (HAS_PCH_SPLIT(dev)) {
4397 dev->driver->irq_handler = ironlake_irq_handler; 4376 dev->driver->irq_handler = ironlake_irq_handler;
4398 dev->driver->irq_preinstall = ironlake_irq_preinstall; 4377 dev->driver->irq_preinstall = ironlake_irq_reset;
4399 dev->driver->irq_postinstall = ironlake_irq_postinstall; 4378 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4400 dev->driver->irq_uninstall = ironlake_irq_uninstall; 4379 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4401 dev->driver->enable_vblank = ironlake_enable_vblank; 4380 dev->driver->enable_vblank = ironlake_enable_vblank;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5122254e7213..e691b30b2817 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1179,7 +1179,7 @@ enum punit_power_well {
1179#define I915_ERROR_INSTRUCTION (1<<0) 1179#define I915_ERROR_INSTRUCTION (1<<0)
1180#define INSTPM 0x020c0 1180#define INSTPM 0x020c0
1181#define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1181#define INSTPM_SELF_EN (1<<12) /* 915GM only */
1182#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 1182#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1183 will not assert AGPBUSY# and will only 1183 will not assert AGPBUSY# and will only
1184 be delivered when out of C3. */ 1184 be delivered when out of C3. */
1185#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1185#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
@@ -1260,6 +1260,10 @@ enum punit_power_well {
1260#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1260#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1261#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1261#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1262 1262
1263#define MI_STATE 0x020e4 /* gen2 only */
1264#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1265#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1266
1263#define CACHE_MODE_0 0x02120 /* 915+ only */ 1267#define CACHE_MODE_0 0x02120 /* 915+ only */
1264#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1268#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1265#define CM0_IZ_OPT_DISABLE (1<<6) 1269#define CM0_IZ_OPT_DISABLE (1<<6)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6b6509656f16..1ee98f121a00 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -744,6 +744,10 @@ parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
744 int i, panel_id, seq_size; 744 int i, panel_id, seq_size;
745 u16 block_size; 745 u16 block_size;
746 746
747 /* parse MIPI blocks only if LFP type is MIPI */
748 if (!dev_priv->vbt.has_mipi)
749 return;
750
747 /* Initialize this to undefined indicating no generic MIPI support */ 751 /* Initialize this to undefined indicating no generic MIPI support */
748 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; 752 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
749 753
@@ -1059,6 +1063,15 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
1059 /* skip the device block if device type is invalid */ 1063 /* skip the device block if device type is invalid */
1060 continue; 1064 continue;
1061 } 1065 }
1066
1067 if (p_child->common.dvo_port >= DVO_PORT_MIPIA
1068 && p_child->common.dvo_port <= DVO_PORT_MIPID
1069 &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
1070 DRM_DEBUG_KMS("Found MIPI as LFP\n");
1071 dev_priv->vbt.has_mipi = 1;
1072 dev_priv->vbt.dsi.port = p_child->common.dvo_port;
1073 }
1074
1062 child_dev_ptr = dev_priv->vbt.child_dev + count; 1075 child_dev_ptr = dev_priv->vbt.child_dev + count;
1063 count++; 1076 count++;
1064 memcpy((void *)child_dev_ptr, (void *)p_child, 1077 memcpy((void *)child_dev_ptr, (void *)p_child,
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 6009debebaaf..b98667796337 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -743,6 +743,10 @@ int intel_parse_bios(struct drm_device *dev);
743#define DVO_PORT_DPC 8 743#define DVO_PORT_DPC 8
744#define DVO_PORT_DPD 9 744#define DVO_PORT_DPD 9
745#define DVO_PORT_DPA 10 745#define DVO_PORT_DPA 10
746#define DVO_PORT_MIPIA 21
747#define DVO_PORT_MIPIB 22
748#define DVO_PORT_MIPIC 23
749#define DVO_PORT_MIPID 24
746 750
747/* Block 52 contains MIPI Panel info 751/* Block 52 contains MIPI Panel info
748 * 6 such enteries will there. Index into correct 752 * 6 such enteries will there. Index into correct
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7a4c7c98378a..efd3cf50cb0f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1484,14 +1484,6 @@ static void intel_reset_dpio(struct drm_device *dev)
1484 if (!IS_VALLEYVIEW(dev)) 1484 if (!IS_VALLEYVIEW(dev))
1485 return; 1485 return;
1486 1486
1487 /*
1488 * Enable the CRI clock source so we can get at the display and the
1489 * reference clock for VGA hotplug / manual detection.
1490 */
1491 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1492 DPLL_REFA_CLK_ENABLE_VLV |
1493 DPLL_INTEGRATED_CRI_CLK_VLV);
1494
1495 if (IS_CHERRYVIEW(dev)) { 1487 if (IS_CHERRYVIEW(dev)) {
1496 enum dpio_phy phy; 1488 enum dpio_phy phy;
1497 u32 val; 1489 u32 val;
@@ -1516,17 +1508,23 @@ static void intel_reset_dpio(struct drm_device *dev)
1516 1508
1517 } else { 1509 } else {
1518 /* 1510 /*
1519 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1511 * If DPIO has already been reset, e.g. by BIOS, just skip all
1520 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1512 * this.
1521 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522 * b. The other bits such as sfr settings / modesel may all
1523 * be set to 0.
1524 *
1525 * This should only be done on init and resume from S3 with
1526 * both PLLs disabled, or we risk losing DPIO and PLL
1527 * synchronization.
1528 */ 1513 */
1529 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1514 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515 return;
1516
1517 /*
1518 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519 * Need to assert and de-assert PHY SB reset by gating the
1520 * common lane power, then un-gating it.
1521 * Simply ungating isn't enough to reset the PHY enough to get
1522 * ports and lanes running.
1523 */
1524 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525 false);
1526 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527 true);
1530 } 1528 }
1531} 1529}
1532 1530
@@ -7868,29 +7866,33 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7868 struct drm_device *dev = crtc->dev; 7866 struct drm_device *dev = crtc->dev;
7869 struct drm_i915_private *dev_priv = dev->dev_private; 7867 struct drm_i915_private *dev_priv = dev->dev_private;
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871 bool visible = base != 0; 7869 uint32_t cntl;
7872 u32 cntl;
7873 7870
7874 if (intel_crtc->cursor_visible == visible) 7871 if (base != intel_crtc->cursor_base) {
7875 return;
7876
7877 cntl = I915_READ(_CURACNTR);
7878 if (visible) {
7879 /* On these chipsets we can only modify the base whilst 7872 /* On these chipsets we can only modify the base whilst
7880 * the cursor is disabled. 7873 * the cursor is disabled.
7881 */ 7874 */
7875 if (intel_crtc->cursor_cntl) {
7876 I915_WRITE(_CURACNTR, 0);
7877 POSTING_READ(_CURACNTR);
7878 intel_crtc->cursor_cntl = 0;
7879 }
7880
7882 I915_WRITE(_CURABASE, base); 7881 I915_WRITE(_CURABASE, base);
7882 POSTING_READ(_CURABASE);
7883 }
7883 7884
7884 cntl &= ~(CURSOR_FORMAT_MASK); 7885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7885 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 7886 cntl = 0;
7886 cntl |= CURSOR_ENABLE | 7887 if (base)
7888 cntl = (CURSOR_ENABLE |
7887 CURSOR_GAMMA_ENABLE | 7889 CURSOR_GAMMA_ENABLE |
7888 CURSOR_FORMAT_ARGB; 7890 CURSOR_FORMAT_ARGB);
7889 } else 7891 if (intel_crtc->cursor_cntl != cntl) {
7890 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 7892 I915_WRITE(_CURACNTR, cntl);
7891 I915_WRITE(_CURACNTR, cntl); 7893 POSTING_READ(_CURACNTR);
7892 7894 intel_crtc->cursor_cntl = cntl;
7893 intel_crtc->cursor_visible = visible; 7895 }
7894} 7896}
7895 7897
7896static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 7898static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
@@ -7899,16 +7901,12 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7899 struct drm_i915_private *dev_priv = dev->dev_private; 7901 struct drm_i915_private *dev_priv = dev->dev_private;
7900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7901 int pipe = intel_crtc->pipe; 7903 int pipe = intel_crtc->pipe;
7902 bool visible = base != 0; 7904 uint32_t cntl;
7903
7904 if (intel_crtc->cursor_visible != visible) {
7905 int16_t width = intel_crtc->cursor_width;
7906 uint32_t cntl = I915_READ(CURCNTR(pipe));
7907 if (base) {
7908 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7909 cntl |= MCURSOR_GAMMA_ENABLE;
7910 7905
7911 switch (width) { 7906 cntl = 0;
7907 if (base) {
7908 cntl = MCURSOR_GAMMA_ENABLE;
7909 switch (intel_crtc->cursor_width) {
7912 case 64: 7910 case 64:
7913 cntl |= CURSOR_MODE_64_ARGB_AX; 7911 cntl |= CURSOR_MODE_64_ARGB_AX;
7914 break; 7912 break;
@@ -7921,18 +7919,16 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7921 default: 7919 default:
7922 WARN_ON(1); 7920 WARN_ON(1);
7923 return; 7921 return;
7924 }
7925 cntl |= pipe << 28; /* Connect to correct pipe */
7926 } else {
7927 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7928 cntl |= CURSOR_MODE_DISABLE;
7929 } 7922 }
7923 cntl |= pipe << 28; /* Connect to correct pipe */
7924 }
7925 if (intel_crtc->cursor_cntl != cntl) {
7930 I915_WRITE(CURCNTR(pipe), cntl); 7926 I915_WRITE(CURCNTR(pipe), cntl);
7931 7927 POSTING_READ(CURCNTR(pipe));
7932 intel_crtc->cursor_visible = visible; 7928 intel_crtc->cursor_cntl = cntl;
7933 } 7929 }
7930
7934 /* and commit changes on next vblank */ 7931 /* and commit changes on next vblank */
7935 POSTING_READ(CURCNTR(pipe));
7936 I915_WRITE(CURBASE(pipe), base); 7932 I915_WRITE(CURBASE(pipe), base);
7937 POSTING_READ(CURBASE(pipe)); 7933 POSTING_READ(CURBASE(pipe));
7938} 7934}
@@ -7943,15 +7939,12 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7943 struct drm_i915_private *dev_priv = dev->dev_private; 7939 struct drm_i915_private *dev_priv = dev->dev_private;
7944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945 int pipe = intel_crtc->pipe; 7941 int pipe = intel_crtc->pipe;
7946 bool visible = base != 0; 7942 uint32_t cntl;
7947 7943
7948 if (intel_crtc->cursor_visible != visible) { 7944 cntl = 0;
7949 int16_t width = intel_crtc->cursor_width; 7945 if (base) {
7950 uint32_t cntl = I915_READ(CURCNTR(pipe)); 7946 cntl = MCURSOR_GAMMA_ENABLE;
7951 if (base) { 7947 switch (intel_crtc->cursor_width) {
7952 cntl &= ~CURSOR_MODE;
7953 cntl |= MCURSOR_GAMMA_ENABLE;
7954 switch (width) {
7955 case 64: 7948 case 64:
7956 cntl |= CURSOR_MODE_64_ARGB_AX; 7949 cntl |= CURSOR_MODE_64_ARGB_AX;
7957 break; 7950 break;
@@ -7964,21 +7957,18 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7964 default: 7957 default:
7965 WARN_ON(1); 7958 WARN_ON(1);
7966 return; 7959 return;
7967 }
7968 } else {
7969 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7970 cntl |= CURSOR_MODE_DISABLE;
7971 } 7960 }
7972 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 7961 }
7973 cntl |= CURSOR_PIPE_CSC_ENABLE; 7962 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
7974 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; 7963 cntl |= CURSOR_PIPE_CSC_ENABLE;
7975 }
7976 I915_WRITE(CURCNTR(pipe), cntl);
7977 7964
7978 intel_crtc->cursor_visible = visible; 7965 if (intel_crtc->cursor_cntl != cntl) {
7966 I915_WRITE(CURCNTR(pipe), cntl);
7967 POSTING_READ(CURCNTR(pipe));
7968 intel_crtc->cursor_cntl = cntl;
7979 } 7969 }
7970
7980 /* and commit changes on next vblank */ 7971 /* and commit changes on next vblank */
7981 POSTING_READ(CURCNTR(pipe));
7982 I915_WRITE(CURBASE(pipe), base); 7972 I915_WRITE(CURBASE(pipe), base);
7983 POSTING_READ(CURBASE(pipe)); 7973 POSTING_READ(CURBASE(pipe));
7984} 7974}
@@ -7994,7 +7984,6 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7994 int x = intel_crtc->cursor_x; 7984 int x = intel_crtc->cursor_x;
7995 int y = intel_crtc->cursor_y; 7985 int y = intel_crtc->cursor_y;
7996 u32 base = 0, pos = 0; 7986 u32 base = 0, pos = 0;
7997 bool visible;
7998 7987
7999 if (on) 7988 if (on)
8000 base = intel_crtc->cursor_addr; 7989 base = intel_crtc->cursor_addr;
@@ -8023,8 +8012,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8023 } 8012 }
8024 pos |= y << CURSOR_Y_SHIFT; 8013 pos |= y << CURSOR_Y_SHIFT;
8025 8014
8026 visible = base != 0; 8015 if (base == 0 && intel_crtc->cursor_base == 0)
8027 if (!visible && !intel_crtc->cursor_visible)
8028 return; 8016 return;
8029 8017
8030 I915_WRITE(CURPOS(pipe), pos); 8018 I915_WRITE(CURPOS(pipe), pos);
@@ -8035,6 +8023,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8035 i845_update_cursor(crtc, base); 8023 i845_update_cursor(crtc, base);
8036 else 8024 else
8037 i9xx_update_cursor(crtc, base); 8025 i9xx_update_cursor(crtc, base);
8026 intel_crtc->cursor_base = base;
8038} 8027}
8039 8028
8040static int intel_crtc_cursor_set(struct drm_crtc *crtc, 8029static int intel_crtc_cursor_set(struct drm_crtc *crtc,
@@ -10990,6 +10979,9 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
10990 intel_crtc->plane = !pipe; 10979 intel_crtc->plane = !pipe;
10991 } 10980 }
10992 10981
10982 intel_crtc->cursor_base = ~0;
10983 intel_crtc->cursor_cntl = ~0;
10984
10993 init_waitqueue_head(&intel_crtc->vbl_wait); 10985 init_waitqueue_head(&intel_crtc->vbl_wait);
10994 10986
10995 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 10987 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
@@ -11103,7 +11095,7 @@ static void intel_setup_outputs(struct drm_device *dev)
11103 11095
11104 intel_lvds_init(dev); 11096 intel_lvds_init(dev);
11105 11097
11106 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev)) 11098 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11107 intel_crt_init(dev); 11099 intel_crt_init(dev);
11108 11100
11109 if (HAS_DDI(dev)) { 11101 if (HAS_DDI(dev)) {
@@ -11618,9 +11610,6 @@ static struct intel_quirk intel_quirks[] = {
11618 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 11610 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11619 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 11611 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11620 11612
11621 /* 830 needs to leave pipe A & dpll A up */
11622 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11623
11624 /* Lenovo U160 cannot use SSC on LVDS */ 11613 /* Lenovo U160 cannot use SSC on LVDS */
11625 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 11614 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11626 11615
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0de04983501e..bda0ae3d80cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -386,7 +386,8 @@ struct intel_crtc {
386 uint32_t cursor_addr; 386 uint32_t cursor_addr;
387 int16_t cursor_x, cursor_y; 387 int16_t cursor_x, cursor_y;
388 int16_t cursor_width, cursor_height; 388 int16_t cursor_width, cursor_height;
389 bool cursor_visible; 389 uint32_t cursor_cntl;
390 uint32_t cursor_base;
390 391
391 struct intel_plane_config plane_config; 392 struct intel_plane_config plane_config;
392 struct intel_crtc_config config; 393 struct intel_crtc_config config;
@@ -973,7 +974,8 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
973void intel_init_runtime_pm(struct drm_i915_private *dev_priv); 974void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
974void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); 975void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
975void ilk_wm_get_hw_state(struct drm_device *dev); 976void ilk_wm_get_hw_state(struct drm_device *dev);
976 977void __vlv_set_power_well(struct drm_i915_private *dev_priv,
978 enum punit_power_well power_well_id, bool enable);
977 979
978/* intel_sdvo.c */ 980/* intel_sdvo.c */
979bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 981bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2525cdd52343..02f99d768d49 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -35,6 +35,11 @@
35 35
36/* the sub-encoders aka panel drivers */ 36/* the sub-encoders aka panel drivers */
37static const struct intel_dsi_device intel_dsi_devices[] = { 37static const struct intel_dsi_device intel_dsi_devices[] = {
38 {
39 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
40 .name = "vbt-generic-dsi-vid-mode-display",
41 .dev_ops = &vbt_generic_dsi_display_ops,
42 },
38}; 43};
39 44
40static void band_gap_reset(struct drm_i915_private *dev_priv) 45static void band_gap_reset(struct drm_i915_private *dev_priv)
@@ -201,6 +206,19 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder)
201 */ 206 */
202} 207}
203 208
209static void intel_dsi_pre_disable(struct intel_encoder *encoder)
210{
211 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
212
213 DRM_DEBUG_KMS("\n");
214
215 if (is_vid_mode(intel_dsi)) {
216 /* Send Shutdown command to the panel in LP mode */
217 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
218 msleep(10);
219 }
220}
221
204static void intel_dsi_disable(struct intel_encoder *encoder) 222static void intel_dsi_disable(struct intel_encoder *encoder)
205{ 223{
206 struct drm_device *dev = encoder->base.dev; 224 struct drm_device *dev = encoder->base.dev;
@@ -213,10 +231,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
213 DRM_DEBUG_KMS("\n"); 231 DRM_DEBUG_KMS("\n");
214 232
215 if (is_vid_mode(intel_dsi)) { 233 if (is_vid_mode(intel_dsi)) {
216 /* Send Shutdown command to the panel in LP mode */
217 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
218 msleep(10);
219
220 /* de-assert ip_tg_enable signal */ 234 /* de-assert ip_tg_enable signal */
221 temp = I915_READ(MIPI_PORT_CTRL(pipe)); 235 temp = I915_READ(MIPI_PORT_CTRL(pipe));
222 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); 236 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
@@ -288,6 +302,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
288 302
289 DRM_DEBUG_KMS("\n"); 303 DRM_DEBUG_KMS("\n");
290 304
305 intel_dsi_disable(encoder);
306
291 intel_dsi_clear_device_ready(encoder); 307 intel_dsi_clear_device_ready(encoder);
292 308
293 val = I915_READ(DSPCLK_GATE_D); 309 val = I915_READ(DSPCLK_GATE_D);
@@ -655,6 +671,10 @@ bool intel_dsi_init(struct drm_device *dev)
655 671
656 DRM_DEBUG_KMS("\n"); 672 DRM_DEBUG_KMS("\n");
657 673
674 /* There is no detection method for MIPI so rely on VBT */
675 if (!dev_priv->vbt.has_mipi)
676 return false;
677
658 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 678 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
659 if (!intel_dsi) 679 if (!intel_dsi)
660 return false; 680 return false;
@@ -686,7 +706,7 @@ bool intel_dsi_init(struct drm_device *dev)
686 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; 706 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
687 intel_encoder->pre_enable = intel_dsi_pre_enable; 707 intel_encoder->pre_enable = intel_dsi_pre_enable;
688 intel_encoder->enable = intel_dsi_enable_nop; 708 intel_encoder->enable = intel_dsi_enable_nop;
689 intel_encoder->disable = intel_dsi_disable; 709 intel_encoder->disable = intel_dsi_pre_disable;
690 intel_encoder->post_disable = intel_dsi_post_disable; 710 intel_encoder->post_disable = intel_dsi_post_disable;
691 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 711 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
692 intel_encoder->get_config = intel_dsi_get_config; 712 intel_encoder->get_config = intel_dsi_get_config;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e3f4e91c526f..31db33d3e5cc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -133,4 +133,6 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
133extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); 133extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
134extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); 134extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
135 135
136extern struct intel_dsi_dev_ops vbt_generic_dsi_display_ops;
137
136#endif /* _INTEL_DSI_H */ 138#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
new file mode 100644
index 000000000000..21a0d348cedc
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -0,0 +1,589 @@
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27#include <drm/drmP.h>
28#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h>
30#include <drm/i915_drm.h>
31#include <linux/slab.h>
32#include <video/mipi_display.h>
33#include <asm/intel-mid.h>
34#include <video/mipi_display.h>
35#include "i915_drv.h"
36#include "intel_drv.h"
37#include "intel_dsi.h"
38#include "intel_dsi_cmd.h"
39
40#define MIPI_TRANSFER_MODE_SHIFT 0
41#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
42#define MIPI_PORT_SHIFT 3
43
44#define PREPARE_CNT_MAX 0x3F
45#define EXIT_ZERO_CNT_MAX 0x3F
46#define CLK_ZERO_CNT_MAX 0xFF
47#define TRAIL_CNT_MAX 0x1F
48
49#define NS_KHZ_RATIO 1000000
50
51#define GPI0_NC_0_HV_DDI0_HPD 0x4130
52#define GPIO_NC_0_HV_DDI0_PAD 0x4138
53#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
55#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
56#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
57#define GPIO_NC_3_PANEL0_VDDEN 0x4140
58#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
59#define GPIO_NC_4_PANEL0_BLKEN 0x4150
60#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
61#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
62#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
63#define GPIO_NC_6_PCONF0 0x4180
64#define GPIO_NC_6_PAD 0x4188
65#define GPIO_NC_7_PCONF0 0x4190
66#define GPIO_NC_7_PAD 0x4198
67#define GPIO_NC_8_PCONF0 0x4170
68#define GPIO_NC_8_PAD 0x4178
69#define GPIO_NC_9_PCONF0 0x4100
70#define GPIO_NC_9_PAD 0x4108
71#define GPIO_NC_10_PCONF0 0x40E0
72#define GPIO_NC_10_PAD 0x40E8
73#define GPIO_NC_11_PCONF0 0x40F0
74#define GPIO_NC_11_PAD 0x40F8
75
76struct gpio_table {
77 u16 function_reg;
78 u16 pad_reg;
79 u8 init;
80};
81
82static struct gpio_table gtable[] = {
83 { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
84 { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
85 { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
86 { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
87 { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
88 { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
89 { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
90 { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
91 { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
92 { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
93 { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
94 { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
95};
96
97static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
98{
99 u8 type, byte, mode, vc, port;
100 u16 len;
101
102 byte = *data++;
103 mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
104 vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
105 port = (byte >> MIPI_PORT_SHIFT) & 0x3;
106
107 /* LP or HS mode */
108 intel_dsi->hs = mode;
109
110 /* get packet type and increment the pointer */
111 type = *data++;
112
113 len = *((u16 *) data);
114 data += 2;
115
116 switch (type) {
117 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
118 dsi_vc_generic_write_0(intel_dsi, vc);
119 break;
120 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
121 dsi_vc_generic_write_1(intel_dsi, vc, *data);
122 break;
123 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
124 dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1));
125 break;
126 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
127 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
128 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
129 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
130 break;
131 case MIPI_DSI_GENERIC_LONG_WRITE:
132 dsi_vc_generic_write(intel_dsi, vc, data, len);
133 break;
134 case MIPI_DSI_DCS_SHORT_WRITE:
135 dsi_vc_dcs_write_0(intel_dsi, vc, *data);
136 break;
137 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
138 dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1));
139 break;
140 case MIPI_DSI_DCS_READ:
141 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
142 break;
143 case MIPI_DSI_DCS_LONG_WRITE:
144 dsi_vc_dcs_write(intel_dsi, vc, data, len);
145 break;
146 };
147
148 data += len;
149
150 return data;
151}
152
153static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
154{
155 u32 delay = *((u32 *) data);
156
157 usleep_range(delay, delay + 10);
158 data += 4;
159
160 return data;
161}
162
163static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
164{
165 u8 gpio, action;
166 u16 function, pad;
167 u32 val;
168 struct drm_device *dev = intel_dsi->base.base.dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170
171 gpio = *data++;
172
173 /* pull up/down */
174 action = *data++;
175
176 function = gtable[gpio].function_reg;
177 pad = gtable[gpio].pad_reg;
178
179 mutex_lock(&dev_priv->dpio_lock);
180 if (!gtable[gpio].init) {
181 /* program the function */
182 /* FIXME: remove constant below */
183 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
184 gtable[gpio].init = 1;
185 }
186
187 val = 0x4 | action;
188
189 /* pull up/down */
190 vlv_gpio_nc_write(dev_priv, pad, val);
191 mutex_unlock(&dev_priv->dpio_lock);
192
193 return data;
194}
195
196typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
197static const fn_mipi_elem_exec exec_elem[] = {
198 NULL, /* reserved */
199 mipi_exec_send_packet,
200 mipi_exec_delay,
201 mipi_exec_gpio,
202 NULL, /* status read; later */
203};
204
205/*
206 * MIPI Sequence from VBT #53 parsing logic
207 * We have already separated each seqence during bios parsing
208 * Following is generic execution function for any sequence
209 */
210
211static const char * const seq_name[] = {
212 "UNDEFINED",
213 "MIPI_SEQ_ASSERT_RESET",
214 "MIPI_SEQ_INIT_OTP",
215 "MIPI_SEQ_DISPLAY_ON",
216 "MIPI_SEQ_DISPLAY_OFF",
217 "MIPI_SEQ_DEASSERT_RESET"
218};
219
220static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
221{
222 u8 *data = sequence;
223 fn_mipi_elem_exec mipi_elem_exec;
224 int index;
225
226 if (!sequence)
227 return;
228
229 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
230
231 /* go to the first element of the sequence */
232 data++;
233
234 /* parse each byte till we reach end of sequence byte - 0x00 */
235 while (1) {
236 index = *data;
237 mipi_elem_exec = exec_elem[index];
238 if (!mipi_elem_exec) {
239 DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
240 return;
241 }
242
243 /* goto element payload */
244 data++;
245
246 /* execute the element specific rotines */
247 data = mipi_elem_exec(intel_dsi, data);
248
249 /*
250 * After processing the element, data should point to
251 * next element or end of sequence
252 * check if have we reached end of sequence
253 */
254 if (*data == 0x00)
255 break;
256 }
257}
258
259static bool generic_init(struct intel_dsi_device *dsi)
260{
261 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
262 struct drm_device *dev = intel_dsi->base.base.dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
265 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
266 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
267 u32 bits_per_pixel = 24;
268 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
269 u32 ui_num, ui_den;
270 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
271 u32 ths_prepare_ns, tclk_trail_ns;
272 u32 tclk_prepare_clkzero, ths_prepare_hszero;
273 u32 lp_to_hs_switch, hs_to_lp_switch;
274
275 DRM_DEBUG_KMS("\n");
276
277 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
278 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
279 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
280 intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
281
282 if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
283 bits_per_pixel = 18;
284 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
285 bits_per_pixel = 16;
286
287 bitrate = (mode->clock * bits_per_pixel) / intel_dsi->lane_count;
288
289 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
290 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
291 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
292 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
293 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
294 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
295 intel_dsi->init_count = mipi_config->master_init_timer;
296 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
297 intel_dsi->video_frmt_cfg_bits = mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
298
299 switch (intel_dsi->escape_clk_div) {
300 case 0:
301 tlpx_ns = 50;
302 break;
303 case 1:
304 tlpx_ns = 100;
305 break;
306
307 case 2:
308 tlpx_ns = 200;
309 break;
310 default:
311 tlpx_ns = 50;
312 break;
313 }
314
315 switch (intel_dsi->lane_count) {
316 case 1:
317 case 2:
318 extra_byte_count = 2;
319 break;
320 case 3:
321 extra_byte_count = 4;
322 break;
323 case 4:
324 default:
325 extra_byte_count = 3;
326 break;
327 }
328
329 /*
330 * ui(s) = 1/f [f in hz]
331 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
332 */
333
334 /* in Kbps */
335 ui_num = NS_KHZ_RATIO;
336 ui_den = bitrate;
337
338 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
339 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
340
341 /*
342 * B060
343 * LP byte clock = TLPX/ (8UI)
344 */
345 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
346
347 /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
348 *
349 * Since txddrclkhs_i is 2xUI, all the count values programmed in
350 * DPHY param register are divided by 2
351 *
352 * prepare count
353 */
354 ths_prepare_ns = max(mipi_config->ths_prepare, mipi_config->tclk_prepare);
355 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
356
357 /* exit zero count */
358 exit_zero_cnt = DIV_ROUND_UP(
359 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
360 ui_num * 2
361 );
362
363 /*
364 * Exit zero is unified val ths_zero and ths_exit
365 * minimum value for ths_exit = 110ns
366 * min (exit_zero_cnt * 2) = 110/UI
367 * exit_zero_cnt = 55/UI
368 */
369 if (exit_zero_cnt < (55 * ui_den / ui_num))
370 if ((55 * ui_den) % ui_num)
371 exit_zero_cnt += 1;
372
373 /* clk zero count */
374 clk_zero_cnt = DIV_ROUND_UP(
375 (tclk_prepare_clkzero - ths_prepare_ns)
376 * ui_den, 2 * ui_num);
377
378 /* trail count */
379 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
380 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
381
382 if (prepare_cnt > PREPARE_CNT_MAX ||
383 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
384 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
385 trail_cnt > TRAIL_CNT_MAX)
386 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
387
388 if (prepare_cnt > PREPARE_CNT_MAX)
389 prepare_cnt = PREPARE_CNT_MAX;
390
391 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
392 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
393
394 if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
395 clk_zero_cnt = CLK_ZERO_CNT_MAX;
396
397 if (trail_cnt > TRAIL_CNT_MAX)
398 trail_cnt = TRAIL_CNT_MAX;
399
400 /* B080 */
401 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
402 clk_zero_cnt << 8 | prepare_cnt;
403
404 /*
405 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
406 * + 10UI + Extra Byte Count
407 *
408 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
409 * Extra Byte Count is calculated according to number of lanes.
410 * High Low Switch Count is the Max of LP to HS and
411 * HS to LP switch count
412 *
413 */
414 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
415
416 /* B044 */
417 /* FIXME:
418 * The comment above does not match with the code */
419 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
420 exit_zero_cnt * 2 + 10, 8);
421
422 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
423
424 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
425 intel_dsi->hs_to_lp_count += extra_byte_count;
426
427 /* B088 */
428 /* LP -> HS for clock lanes
429 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
430 * extra byte count
431 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
432 * 2(in UI) + extra byte count
433 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
434 * 8 + extra byte count
435 */
436 intel_dsi->clk_lp_to_hs_count =
437 DIV_ROUND_UP(
438 4 * tlpx_ui + prepare_cnt * 2 +
439 clk_zero_cnt * 2,
440 8);
441
442 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
443
444 /* HS->LP for Clock Lanes
445 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
446 * Extra byte count
447 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
448 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
449 * Extra byte count
450 */
451 intel_dsi->clk_hs_to_lp_count =
452 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
453 8);
454 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
455
456 DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
457 DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
458 "disabled" : "enabled");
459 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
460 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
461 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
462 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
463 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
464 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
465 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
466 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
467 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
468 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
469 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
470 DRM_DEBUG_KMS("BTA %s\n",
471 intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
472 "disabled" : "enabled");
473
474 /* delays in VBT are in unit of 100us, so need to convert
475 * here in ms
476 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
477 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
478 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
479 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
480 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
481 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
482
483 return true;
484}
485
486static int generic_mode_valid(struct intel_dsi_device *dsi,
487 struct drm_display_mode *mode)
488{
489 return MODE_OK;
490}
491
492static bool generic_mode_fixup(struct intel_dsi_device *dsi,
493 const struct drm_display_mode *mode,
494 struct drm_display_mode *adjusted_mode) {
495 return true;
496}
497
498static void generic_panel_reset(struct intel_dsi_device *dsi)
499{
500 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
501 struct drm_device *dev = intel_dsi->base.base.dev;
502 struct drm_i915_private *dev_priv = dev->dev_private;
503
504 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
505
506 generic_exec_sequence(intel_dsi, sequence);
507}
508
509static void generic_disable_panel_power(struct intel_dsi_device *dsi)
510{
511 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
512 struct drm_device *dev = intel_dsi->base.base.dev;
513 struct drm_i915_private *dev_priv = dev->dev_private;
514
515 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
516
517 generic_exec_sequence(intel_dsi, sequence);
518}
519
520static void generic_send_otp_cmds(struct intel_dsi_device *dsi)
521{
522 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
523 struct drm_device *dev = intel_dsi->base.base.dev;
524 struct drm_i915_private *dev_priv = dev->dev_private;
525
526 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
527
528 generic_exec_sequence(intel_dsi, sequence);
529}
530
531static void generic_enable(struct intel_dsi_device *dsi)
532{
533 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
534 struct drm_device *dev = intel_dsi->base.base.dev;
535 struct drm_i915_private *dev_priv = dev->dev_private;
536
537 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
538
539 generic_exec_sequence(intel_dsi, sequence);
540}
541
542static void generic_disable(struct intel_dsi_device *dsi)
543{
544 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
545 struct drm_device *dev = intel_dsi->base.base.dev;
546 struct drm_i915_private *dev_priv = dev->dev_private;
547
548 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
549
550 generic_exec_sequence(intel_dsi, sequence);
551}
552
553static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi)
554{
555 return connector_status_connected;
556}
557
558static bool generic_get_hw_state(struct intel_dsi_device *dev)
559{
560 return true;
561}
562
563static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
564{
565 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
566 struct drm_device *dev = intel_dsi->base.base.dev;
567 struct drm_i915_private *dev_priv = dev->dev_private;
568
569 dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED;
570 return dev_priv->vbt.lfp_lvds_vbt_mode;
571}
572
573static void generic_destroy(struct intel_dsi_device *dsi) { }
574
575/* Callbacks. We might not need them all. */
576struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
577 .init = generic_init,
578 .mode_valid = generic_mode_valid,
579 .mode_fixup = generic_mode_fixup,
580 .panel_reset = generic_panel_reset,
581 .disable_panel_power = generic_disable_panel_power,
582 .send_otp_cmds = generic_send_otp_cmds,
583 .enable = generic_enable,
584 .disable = generic_disable,
585 .detect = generic_detect,
586 .get_hw_state = generic_get_hw_state,
587 .get_modes = generic_get_modes,
588 .destroy = generic_destroy,
589};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 906d06f73e51..d1e53abec1b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5388,8 +5388,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
5388 I915_WRITE(GEN6_UCGCTL2, 5388 I915_WRITE(GEN6_UCGCTL2,
5389 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 5389 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5390 5390
5391 /* WaDisableL3Bank2xClockGate:vlv */ 5391 /* WaDisableL3Bank2xClockGate:vlv
5392 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 5392 * Disabling L3 clock gating- MMIO 940c[25] = 1
5393 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5394 I915_WRITE(GEN7_UCGCTL4,
5395 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5393 5396
5394 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 5397 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5395 5398
@@ -5541,6 +5544,12 @@ static void gen3_init_clock_gating(struct drm_device *dev)
5541 5544
5542 /* IIR "flip pending" means done if this bit is set */ 5545 /* IIR "flip pending" means done if this bit is set */
5543 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 5546 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5547
5548 /* interrupts should cause a wake up from C3 */
5549 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5550
5551 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5552 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5544} 5553}
5545 5554
5546static void i85x_init_clock_gating(struct drm_device *dev) 5555static void i85x_init_clock_gating(struct drm_device *dev)
@@ -5548,6 +5557,10 @@ static void i85x_init_clock_gating(struct drm_device *dev)
5548 struct drm_i915_private *dev_priv = dev->dev_private; 5557 struct drm_i915_private *dev_priv = dev->dev_private;
5549 5558
5550 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 5559 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5560
5561 /* interrupts should cause a wake up from C3 */
5562 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5563 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5551} 5564}
5552 5565
5553static void i830_init_clock_gating(struct drm_device *dev) 5566static void i830_init_clock_gating(struct drm_device *dev)
@@ -5599,10 +5612,25 @@ bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5599 enum intel_display_power_domain domain) 5612 enum intel_display_power_domain domain)
5600{ 5613{
5601 struct i915_power_domains *power_domains; 5614 struct i915_power_domains *power_domains;
5615 struct i915_power_well *power_well;
5616 bool is_enabled;
5617 int i;
5618
5619 if (dev_priv->pm.suspended)
5620 return false;
5602 5621
5603 power_domains = &dev_priv->power_domains; 5622 power_domains = &dev_priv->power_domains;
5623 is_enabled = true;
5624 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5625 if (power_well->always_on)
5626 continue;
5604 5627
5605 return power_domains->domain_use_count[domain]; 5628 if (!power_well->count) {
5629 is_enabled = false;
5630 break;
5631 }
5632 }
5633 return is_enabled;
5606} 5634}
5607 5635
5608bool intel_display_power_enabled(struct drm_i915_private *dev_priv, 5636bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
@@ -5745,13 +5773,34 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5745 return true; 5773 return true;
5746} 5774}
5747 5775
5748static void vlv_set_power_well(struct drm_i915_private *dev_priv, 5776void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5749 struct i915_power_well *power_well, bool enable) 5777 enum punit_power_well power_well_id, bool enable)
5750{ 5778{
5751 enum punit_power_well power_well_id = power_well->data; 5779 struct drm_device *dev = dev_priv->dev;
5752 u32 mask; 5780 u32 mask;
5753 u32 state; 5781 u32 state;
5754 u32 ctrl; 5782 u32 ctrl;
5783 enum pipe pipe;
5784
5785 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5786 if (enable) {
5787 /*
5788 * Enable the CRI clock source so we can get at the
5789 * display and the reference clock for VGA
5790 * hotplug / manual detection.
5791 */
5792 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5793 DPLL_REFA_CLK_ENABLE_VLV |
5794 DPLL_INTEGRATED_CRI_CLK_VLV);
5795 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5796 } else {
5797 for_each_pipe(pipe)
5798 assert_pll_disabled(dev_priv, pipe);
5799 /* Assert common reset */
5800 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5801 ~DPIO_CMNRST);
5802 }
5803 }
5755 5804
5756 mask = PUNIT_PWRGT_MASK(power_well_id); 5805 mask = PUNIT_PWRGT_MASK(power_well_id);
5757 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 5806 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
@@ -5779,6 +5828,28 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5779 5828
5780out: 5829out:
5781 mutex_unlock(&dev_priv->rps.hw_lock); 5830 mutex_unlock(&dev_priv->rps.hw_lock);
5831
5832 /*
5833 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
5834 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
5835 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
5836 * b. The other bits such as sfr settings / modesel may all
5837 * be set to 0.
5838 *
5839 * This should only be done on init and resume from S3 with
5840 * both PLLs disabled, or we risk losing DPIO and PLL
5841 * synchronization.
5842 */
5843 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
5844 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
5845}
5846
5847static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5848 struct i915_power_well *power_well, bool enable)
5849{
5850 enum punit_power_well power_well_id = power_well->data;
5851
5852 __vlv_set_power_well(dev_priv, power_well_id, enable);
5782} 5853}
5783 5854
5784static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 5855static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -6114,12 +6185,6 @@ static struct i915_power_well vlv_power_wells[] = {
6114 .ops = &vlv_display_power_well_ops, 6185 .ops = &vlv_display_power_well_ops,
6115 }, 6186 },
6116 { 6187 {
6117 .name = "dpio-common",
6118 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6119 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6120 .ops = &vlv_dpio_power_well_ops,
6121 },
6122 {
6123 .name = "dpio-tx-b-01", 6188 .name = "dpio-tx-b-01",
6124 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 6189 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6125 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 6190 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
@@ -6155,6 +6220,12 @@ static struct i915_power_well vlv_power_wells[] = {
6155 .ops = &vlv_dpio_power_well_ops, 6220 .ops = &vlv_dpio_power_well_ops,
6156 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 6221 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6157 }, 6222 },
6223 {
6224 .name = "dpio-common",
6225 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6226 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6227 .ops = &vlv_dpio_power_well_ops,
6228 },
6158}; 6229};
6159 6230
6160#define set_power_wells(power_domains, __power_wells) ({ \ 6231#define set_power_wells(power_domains, __power_wells) ({ \
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3379722d0e6d..279488addf3f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1494,7 +1494,7 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1494 return; 1494 return;
1495 1495
1496 intel_stop_ring_buffer(ring); 1496 intel_stop_ring_buffer(ring);
1497 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1497 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1498 1498
1499 iounmap(ringbuf->virtual_start); 1499 iounmap(ringbuf->virtual_start);
1500 1500
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2f5d5d3f0043..79cba593df0d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -393,26 +393,8 @@ void intel_uncore_early_sanitize(struct drm_device *dev)
393 393
394void intel_uncore_sanitize(struct drm_device *dev) 394void intel_uncore_sanitize(struct drm_device *dev)
395{ 395{
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 u32 reg_val;
398
399 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 396 /* BIOS often leaves RC6 enabled, but disable it for hw init */
400 intel_disable_gt_powersave(dev); 397 intel_disable_gt_powersave(dev);
401
402 /* Turn off power gate, require especially for the BIOS less system */
403 if (IS_VALLEYVIEW(dev)) {
404
405 mutex_lock(&dev_priv->rps.hw_lock);
406 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
407
408 if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) |
409 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) |
410 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D)))
411 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
412
413 mutex_unlock(&dev_priv->rps.hw_lock);
414
415 }
416} 398}
417 399
418/* 400/*
@@ -967,6 +949,9 @@ static int i965_do_reset(struct drm_device *dev)
967{ 949{
968 int ret; 950 int ret;
969 951
952 /* FIXME: i965g/gm need a display save/restore for gpu reset. */
953 return -ENODEV;
954
970 /* 955 /*
971 * Set the domains we want to reset (GRDOM/bits 2 and 3) as 956 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
972 * well as the reset bit (GR/bit 0). Setting the GR bit 957 * well as the reset bit (GR/bit 0). Setting the GR bit
diff --git a/include/drm/drm_plane_helper.h b/include/drm/drm_plane_helper.h
index c5e7ab9503c8..52e6870534b2 100644
--- a/include/drm/drm_plane_helper.h
+++ b/include/drm/drm_plane_helper.h
@@ -24,6 +24,17 @@
24#ifndef DRM_PLANE_HELPER_H 24#ifndef DRM_PLANE_HELPER_H
25#define DRM_PLANE_HELPER_H 25#define DRM_PLANE_HELPER_H
26 26
27#include <drm/drm_rect.h>
28
29/*
30 * Drivers that don't allow primary plane scaling may pass this macro in place
31 * of the min/max scale parameters of the update checker function.
32 *
33 * Due to src being in 16.16 fixed point and dest being in integer pixels,
34 * 1<<16 represents no scaling.
35 */
36#define DRM_PLANE_HELPER_NO_SCALING (1<<16)
37
27/** 38/**
28 * DOC: plane helpers 39 * DOC: plane helpers
29 * 40 *
@@ -31,6 +42,17 @@
31 * planes. 42 * planes.
32 */ 43 */
33 44
45extern int drm_plane_helper_check_update(struct drm_plane *plane,
46 struct drm_crtc *crtc,
47 struct drm_framebuffer *fb,
48 struct drm_rect *src,
49 struct drm_rect *dest,
50 const struct drm_rect *clip,
51 int min_scale,
52 int max_scale,
53 bool can_position,
54 bool can_update_disabled,
55 bool *visible);
34extern int drm_primary_helper_update(struct drm_plane *plane, 56extern int drm_primary_helper_update(struct drm_plane *plane,
35 struct drm_crtc *crtc, 57 struct drm_crtc *crtc,
36 struct drm_framebuffer *fb, 58 struct drm_framebuffer *fb,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-05 07:38:11 -0500