diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index a7c1c584a191..a5b96eac3033 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |||
| @@ -173,6 +173,7 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) | |||
| 173 | ARRAY_SIZE(polaris11_golden_settings_a11)); | 173 | ARRAY_SIZE(polaris11_golden_settings_a11)); |
| 174 | break; | 174 | break; |
| 175 | case CHIP_POLARIS10: | 175 | case CHIP_POLARIS10: |
| 176 | case CHIP_VEGAM: | ||
| 176 | amdgpu_device_program_register_sequence(adev, | 177 | amdgpu_device_program_register_sequence(adev, |
| 177 | polaris10_golden_settings_a11, | 178 | polaris10_golden_settings_a11, |
| 178 | ARRAY_SIZE(polaris10_golden_settings_a11)); | 179 | ARRAY_SIZE(polaris10_golden_settings_a11)); |
| @@ -473,6 +474,7 @@ static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) | |||
| 473 | num_crtc = 2; | 474 | num_crtc = 2; |
| 474 | break; | 475 | break; |
| 475 | case CHIP_POLARIS10: | 476 | case CHIP_POLARIS10: |
| 477 | case CHIP_VEGAM: | ||
| 476 | num_crtc = 6; | 478 | num_crtc = 6; |
| 477 | break; | 479 | break; |
| 478 | case CHIP_POLARIS11: | 480 | case CHIP_POLARIS11: |
| @@ -1445,6 +1447,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) | |||
| 1445 | adev->mode_info.audio.num_pins = 7; | 1447 | adev->mode_info.audio.num_pins = 7; |
| 1446 | break; | 1448 | break; |
| 1447 | case CHIP_POLARIS10: | 1449 | case CHIP_POLARIS10: |
| 1450 | case CHIP_VEGAM: | ||
| 1448 | adev->mode_info.audio.num_pins = 8; | 1451 | adev->mode_info.audio.num_pins = 8; |
| 1449 | break; | 1452 | break; |
| 1450 | case CHIP_POLARIS11: | 1453 | case CHIP_POLARIS11: |
| @@ -1862,7 +1865,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, | |||
| 1862 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | 1865 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 1863 | struct drm_device *dev = crtc->dev; | 1866 | struct drm_device *dev = crtc->dev; |
| 1864 | struct amdgpu_device *adev = dev->dev_private; | 1867 | struct amdgpu_device *adev = dev->dev_private; |
| 1865 | struct amdgpu_framebuffer *amdgpu_fb; | ||
| 1866 | struct drm_framebuffer *target_fb; | 1868 | struct drm_framebuffer *target_fb; |
| 1867 | struct drm_gem_object *obj; | 1869 | struct drm_gem_object *obj; |
| 1868 | struct amdgpu_bo *abo; | 1870 | struct amdgpu_bo *abo; |
| @@ -1881,18 +1883,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, | |||
| 1881 | return 0; | 1883 | return 0; |
| 1882 | } | 1884 | } |
| 1883 | 1885 | ||
| 1884 | if (atomic) { | 1886 | if (atomic) |
| 1885 | amdgpu_fb = to_amdgpu_framebuffer(fb); | ||
| 1886 | target_fb = fb; | 1887 | target_fb = fb; |
| 1887 | } else { | 1888 | else |
| 1888 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | ||
| 1889 | target_fb = crtc->primary->fb; | 1889 | target_fb = crtc->primary->fb; |
| 1890 | } | ||
| 1891 | 1890 | ||
| 1892 | /* If atomic, assume fb object is pinned & idle & fenced and | 1891 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1893 | * just update base pointers | 1892 | * just update base pointers |
| 1894 | */ | 1893 | */ |
| 1895 | obj = amdgpu_fb->obj; | 1894 | obj = target_fb->obj[0]; |
| 1896 | abo = gem_to_amdgpu_bo(obj); | 1895 | abo = gem_to_amdgpu_bo(obj); |
| 1897 | r = amdgpu_bo_reserve(abo, false); | 1896 | r = amdgpu_bo_reserve(abo, false); |
| 1898 | if (unlikely(r != 0)) | 1897 | if (unlikely(r != 0)) |
| @@ -2082,8 +2081,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, | |||
| 2082 | WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); | 2081 | WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); |
| 2083 | 2082 | ||
| 2084 | if (!atomic && fb && fb != crtc->primary->fb) { | 2083 | if (!atomic && fb && fb != crtc->primary->fb) { |
| 2085 | amdgpu_fb = to_amdgpu_framebuffer(fb); | 2084 | abo = gem_to_amdgpu_bo(fb->obj[0]); |
| 2086 | abo = gem_to_amdgpu_bo(amdgpu_fb->obj); | ||
| 2087 | r = amdgpu_bo_reserve(abo, true); | 2085 | r = amdgpu_bo_reserve(abo, true); |
| 2088 | if (unlikely(r != 0)) | 2086 | if (unlikely(r != 0)) |
| 2089 | return r; | 2087 | return r; |
| @@ -2253,7 +2251,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) | |||
| 2253 | 2251 | ||
| 2254 | if ((adev->asic_type == CHIP_POLARIS10) || | 2252 | if ((adev->asic_type == CHIP_POLARIS10) || |
| 2255 | (adev->asic_type == CHIP_POLARIS11) || | 2253 | (adev->asic_type == CHIP_POLARIS11) || |
| 2256 | (adev->asic_type == CHIP_POLARIS12)) { | 2254 | (adev->asic_type == CHIP_POLARIS12) || |
| 2255 | (adev->asic_type == CHIP_VEGAM)) { | ||
| 2257 | struct amdgpu_encoder *amdgpu_encoder = | 2256 | struct amdgpu_encoder *amdgpu_encoder = |
| 2258 | to_amdgpu_encoder(amdgpu_crtc->encoder); | 2257 | to_amdgpu_encoder(amdgpu_crtc->encoder); |
| 2259 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | 2258 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| @@ -2601,11 +2600,9 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) | |||
| 2601 | dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | 2600 | dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 2602 | if (crtc->primary->fb) { | 2601 | if (crtc->primary->fb) { |
| 2603 | int r; | 2602 | int r; |
| 2604 | struct amdgpu_framebuffer *amdgpu_fb; | ||
| 2605 | struct amdgpu_bo *abo; | 2603 | struct amdgpu_bo *abo; |
| 2606 | 2604 | ||
| 2607 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | 2605 | abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); |
| 2608 | abo = gem_to_amdgpu_bo(amdgpu_fb->obj); | ||
| 2609 | r = amdgpu_bo_reserve(abo, true); | 2606 | r = amdgpu_bo_reserve(abo, true); |
| 2610 | if (unlikely(r)) | 2607 | if (unlikely(r)) |
| 2611 | DRM_ERROR("failed to reserve abo before unpin\n"); | 2608 | DRM_ERROR("failed to reserve abo before unpin\n"); |
| @@ -2673,7 +2670,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, | |||
| 2673 | 2670 | ||
| 2674 | if ((adev->asic_type == CHIP_POLARIS10) || | 2671 | if ((adev->asic_type == CHIP_POLARIS10) || |
| 2675 | (adev->asic_type == CHIP_POLARIS11) || | 2672 | (adev->asic_type == CHIP_POLARIS11) || |
| 2676 | (adev->asic_type == CHIP_POLARIS12)) { | 2673 | (adev->asic_type == CHIP_POLARIS12) || |
| 2674 | (adev->asic_type == CHIP_VEGAM)) { | ||
| 2677 | struct amdgpu_encoder *amdgpu_encoder = | 2675 | struct amdgpu_encoder *amdgpu_encoder = |
| 2678 | to_amdgpu_encoder(amdgpu_crtc->encoder); | 2676 | to_amdgpu_encoder(amdgpu_crtc->encoder); |
| 2679 | int encoder_mode = | 2677 | int encoder_mode = |
| @@ -2830,6 +2828,7 @@ static int dce_v11_0_early_init(void *handle) | |||
| 2830 | adev->mode_info.num_dig = 9; | 2828 | adev->mode_info.num_dig = 9; |
| 2831 | break; | 2829 | break; |
| 2832 | case CHIP_POLARIS10: | 2830 | case CHIP_POLARIS10: |
| 2831 | case CHIP_VEGAM: | ||
| 2833 | adev->mode_info.num_hpd = 6; | 2832 | adev->mode_info.num_hpd = 6; |
| 2834 | adev->mode_info.num_dig = 6; | 2833 | adev->mode_info.num_dig = 6; |
| 2835 | break; | 2834 | break; |
| @@ -2949,7 +2948,8 @@ static int dce_v11_0_hw_init(void *handle) | |||
| 2949 | amdgpu_atombios_encoder_init_dig(adev); | 2948 | amdgpu_atombios_encoder_init_dig(adev); |
| 2950 | if ((adev->asic_type == CHIP_POLARIS10) || | 2949 | if ((adev->asic_type == CHIP_POLARIS10) || |
| 2951 | (adev->asic_type == CHIP_POLARIS11) || | 2950 | (adev->asic_type == CHIP_POLARIS11) || |
| 2952 | (adev->asic_type == CHIP_POLARIS12)) { | 2951 | (adev->asic_type == CHIP_POLARIS12) || |
| 2952 | (adev->asic_type == CHIP_VEGAM)) { | ||
| 2953 | amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, | 2953 | amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, |
| 2954 | DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); | 2954 | DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); |
| 2955 | amdgpu_atombios_crtc_set_dce_clock(adev, 0, | 2955 | amdgpu_atombios_crtc_set_dce_clock(adev, 0, |
