Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This starts to support NVIDIA volta hardware with nouveau, and adds
  amdgpu support for the GPU in the Kabylake-G (the intel + radeon
  single package chip), along with some initial Intel icelake enabling.

  Summary:

  New Drivers:
   - v3d - driver for broadcom V3D V3.x+ hardware
   - xen-front - XEN PV display frontend

  core:
   - handle zpos normalization in the core
   - stop looking at legacy pointers in atomic paths
   - improved scheduler documentation
   - improved aspect ratio validation
   - aspect ratio support for 64:27 and 256:135
   - drop unused control node code.

  i915:
   - Icelake (ICL) enabling
   - GuC/HuC refactoring
   - PSR/PSR2 enabling and fixes
   - DPLL management refactoring
   - DP MST fixes
   - NV12 enabling
   - HDCP improvements
   - GEM/Execlist/reset improvements
   - GVT improvements
   - stolen memory first 4k fix

  amdgpu:
   - Vega 20 support
   - VEGAM support (Kabylake-G)
   - preOS scanout buffer reservation
   - power management gfxoff support for raven
   - SR-IOV fixes
   - Vega10 power profiles and clock voltage control
   - scatter/gather display support on CZ/ST

  amdkfd:
   - GFX9 dGPU support
   - userptr memory mapping

  nouveau:
   - major refactoring for Volta GV100 support

  tda998x:
   - HDMI i2c CEC support

  etnaviv:
   - removed unused logging code
   - license text cleanups
   - MMU handling improvements
   - timeout fence fix for 50 days uptime

  tegra:
   - IOMMU support in gr2d/gr3d drivers
   - zpos support

  vc4:
   - syncobj support
   - CTM, plane alpha and async cursor support

  analogix_dp:
   - HPD and aux chan fixes

  sun4i:
   - MIPI DSI support

  tilcdc:
   - clock divider fixes for OMAP-l138 LCDK board

  rcar-du:
   - R8A77965 support
   - dma-buf fences fixes
   - hardware indexed crtc/du group handling
   - generic zplane property support

  atmel-hclcdc:
   - generic zplane property support

  mediatek:
   - use generic video mode function

  exynos:
   - S5PV210 FIMD variant support
   - IPP v2 framework
   - more HW overlays support"

* tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits)
  drm/amdgpu: fix 32-bit build warning
  drm/exynos: fimc: signedness bug in fimc_setup_clocks()
  drm/exynos: scaler: fix static checker warning
  drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC
  drm/amd/display: Remove use of division operator for long longs
  drm/amdgpu: Update GFX info structure to match what vega20 used
  drm/amdgpu/pp: remove duplicate assignment
  drm/sched: add rcu_barrier after entity fini
  drm/amdgpu: move VM BOs on LRU again
  drm/amdgpu: consistenly use VM moved flag
  drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
  drm/amdgpu: further optimize amdgpu_vm_handle_moved
  drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
  drm/amdgpu: rework VM state machine lock handling v2
  drm/amdgpu: Add runtime VCN PG support
  drm/amdgpu: Enable VCN static PG by default on RV
  drm/amdgpu: Add VCN static PG support on RV
  drm/amdgpu: Enable VCN CG by default on RV
  drm/amdgpu: Add static CG control for VCN on RV
  drm/exynos: Fix default value for zpos plane property
  ...

1 files changed, 15 insertions, 15 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a7c1c584a191..a5b96eac3033 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -173,6 +173,7 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
                                                         ARRAY_SIZE(polaris11_golden_settings_a11));
                 break;
         case CHIP_POLARIS10:
+        case CHIP_VEGAM:
                 amdgpu_device_program_register_sequence(adev,
                                                         polaris10_golden_settings_a11,
                                                         ARRAY_SIZE(polaris10_golden_settings_a11));
@@ -473,6 +474,7 @@ static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
                 num_crtc = 2;
                 break;
         case CHIP_POLARIS10:
+        case CHIP_VEGAM:
                 num_crtc = 6;
                 break;
         case CHIP_POLARIS11:
@@ -1445,6 +1447,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
                 adev->mode_info.audio.num_pins = 7;
                 break;
         case CHIP_POLARIS10:
+        case CHIP_VEGAM:
                 adev->mode_info.audio.num_pins = 8;
                 break;
         case CHIP_POLARIS11:
@@ -1862,7 +1865,6 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct drm_device *dev = crtc->dev;
         struct amdgpu_device *adev = dev->dev_private;
-        struct amdgpu_framebuffer *amdgpu_fb;
         struct drm_framebuffer *target_fb;
         struct drm_gem_object *obj;
         struct amdgpu_bo *abo;
@@ -1881,18 +1883,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
                 return 0;
         }
 
-        if (atomic) {
-                amdgpu_fb = to_amdgpu_framebuffer(fb);
+        if (atomic)
                 target_fb = fb;
-        } else {
-                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
+        else
                 target_fb = crtc->primary->fb;
-        }
 
         /* If atomic, assume fb object is pinned & idle & fenced and
          * just update base pointers
          */
-        obj = amdgpu_fb->obj;
+        obj = target_fb->obj[0];
         abo = gem_to_amdgpu_bo(obj);
         r = amdgpu_bo_reserve(abo, false);
         if (unlikely(r != 0))
@@ -2082,8 +2081,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
 
         if (!atomic && fb && fb != crtc->primary->fb) {
-                amdgpu_fb = to_amdgpu_framebuffer(fb);
-                abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
+                abo = gem_to_amdgpu_bo(fb->obj[0]);
                 r = amdgpu_bo_reserve(abo, true);
                 if (unlikely(r != 0))
                         return r;
@@ -2253,7 +2251,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
 
         if ((adev->asic_type == CHIP_POLARIS10) ||
             (adev->asic_type == CHIP_POLARIS11) ||
-            (adev->asic_type == CHIP_POLARIS12)) {
+            (adev->asic_type == CHIP_POLARIS12) ||
+            (adev->asic_type == CHIP_VEGAM)) {
                 struct amdgpu_encoder *amdgpu_encoder =
                         to_amdgpu_encoder(amdgpu_crtc->encoder);
                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2601,11 +2600,9 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
         if (crtc->primary->fb) {
                 int r;
-                struct amdgpu_framebuffer *amdgpu_fb;
                 struct amdgpu_bo *abo;
 
-                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
-                abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
+                abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
                 r = amdgpu_bo_reserve(abo, true);
                 if (unlikely(r))
                         DRM_ERROR("failed to reserve abo before unpin\n");
@@ -2673,7 +2670,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
 
         if ((adev->asic_type == CHIP_POLARIS10) ||
             (adev->asic_type == CHIP_POLARIS11) ||
-            (adev->asic_type == CHIP_POLARIS12)) {
+            (adev->asic_type == CHIP_POLARIS12) ||
+            (adev->asic_type == CHIP_VEGAM)) {
                 struct amdgpu_encoder *amdgpu_encoder =
                         to_amdgpu_encoder(amdgpu_crtc->encoder);
                 int encoder_mode =
@@ -2830,6 +2828,7 @@ static int dce_v11_0_early_init(void *handle)
                 adev->mode_info.num_dig = 9;
                 break;
         case CHIP_POLARIS10:
+        case CHIP_VEGAM:
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 6;
                 break;
@@ -2949,7 +2948,8 @@ static int dce_v11_0_hw_init(void *handle)
         amdgpu_atombios_encoder_init_dig(adev);
         if ((adev->asic_type == CHIP_POLARIS10) ||
             (adev->asic_type == CHIP_POLARIS11) ||
-            (adev->asic_type == CHIP_POLARIS12)) {
+            (adev->asic_type == CHIP_POLARIS12) ||
+            (adev->asic_type == CHIP_VEGAM)) {
                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,