1 files changed, 51 insertions, 58 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index f55f72a37ca8..7b33867036e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -277,6 +277,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
         case CHIP_PITCAIRN:
         case CHIP_VERDE:
         case CHIP_OLAND:
+        case CHIP_HAINAN:
                 return AMDGPU_FW_LOAD_DIRECT;
 #endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
@@ -296,19 +297,15 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
         case CHIP_POLARIS11:
         case CHIP_POLARIS12:
         case CHIP_VEGAM:
-                if (!load_type)
-                        return AMDGPU_FW_LOAD_DIRECT;
-                else
-                        return AMDGPU_FW_LOAD_SMU;
+                return AMDGPU_FW_LOAD_SMU;
         case CHIP_VEGA10:
         case CHIP_RAVEN:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 if (!load_type)
                         return AMDGPU_FW_LOAD_DIRECT;
                 else
                         return AMDGPU_FW_LOAD_PSP;
-        case CHIP_VEGA20:
-                return AMDGPU_FW_LOAD_DIRECT;
         default:
                 DRM_ERROR("Unknown firmware load type\n");
         }
@@ -322,6 +319,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 {
         const struct common_firmware_header *header = NULL;
         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
+        const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 
         if (NULL == ucode->fw)
                 return 0;
@@ -333,8 +331,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                 return 0;
 
         header = (const struct common_firmware_header *)ucode->fw->data;
-
         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+        dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 
         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
             (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
@@ -343,7 +341,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
              ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
-             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
+             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
+                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 
                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
@@ -365,6 +365,20 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                                               le32_to_cpu(header->ucode_array_offset_bytes) +
                                               le32_to_cpu(cp_hdr->jt_offset) * 4),
                        ucode->ucode_size);
+        } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
+                ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+                                le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+                memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                              le32_to_cpu(header->ucode_array_offset_bytes)),
+                       ucode->ucode_size);
+        } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
+                ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+                memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                              le32_to_cpu(header->ucode_array_offset_bytes) +
+                                              le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
+                       ucode->ucode_size);
         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
                 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
                 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
@@ -406,32 +420,41 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
         return 0;
 }
 
-int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
 {
-        uint64_t fw_offset = 0;
-        int i, err;
-        struct amdgpu_firmware_info *ucode = NULL;
-        const struct common_firmware_header *header = NULL;
-
-        if (!adev->firmware.fw_size) {
-                dev_warn(adev->dev, "No ip firmware need to load\n");
-                return 0;
-        }
-
-        if (!adev->in_gpu_reset) {
-                err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
-                                        amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
-                                        &adev->firmware.fw_buf,
-                                        &adev->firmware.fw_buf_mc,
-                                        &adev->firmware.fw_buf_ptr);
-                if (err) {
+        if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+                amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+                        amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+                        &adev->firmware.fw_buf,
+                        &adev->firmware.fw_buf_mc,
+                        &adev->firmware.fw_buf_ptr);
+                if (!adev->firmware.fw_buf) {
                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
-                        goto failed;
+                        return -ENOMEM;
+                } else if (amdgpu_sriov_vf(adev)) {
+                        memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
                 }
         }
+        return 0;
+}
 
-        memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+        if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+                amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+                &adev->firmware.fw_buf_mc,
+                &adev->firmware.fw_buf_ptr);
+}
+
+int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
+{
+        uint64_t fw_offset = 0;
+        int i;
+        struct amdgpu_firmware_info *ucode = NULL;
 
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
+        if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
+                return 0;
         /*
          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
          * ucode info here
@@ -448,7 +471,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
         for (i = 0; i < adev->firmware.max_ucodes; i++) {
                 ucode = &adev->firmware.ucode[i];
                 if (ucode->fw) {
-                        header = (const struct common_firmware_header *)ucode->fw->data;
                         amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
                                                     adev->firmware.fw_buf_ptr + fw_offset);
                         if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
@@ -463,33 +485,4 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
                 }
         }
         return 0;
-
-failed:
-        if (err)
-                adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
-        return err;
-}