Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This is going to rebuild more than drm as it adds a new helper to
  list.h for doing bulk updates. Seemed like a reasonable addition to
  me.

  Otherwise the usual merge window stuff lots of i915 and amdgpu, not so
  much nouveau, and piles of everything else.

  Core:
   - Adds a new list.h helper for doing bulk list updates for TTM.
   - Don't leak fb address in smem_start to userspace (comes with EXPORT
     workaround for people using mali out of tree hacks)
   - udmabuf device to turn memfd regions into dma-buf
   - Per-plane blend mode property
   - ref/unref replacements with get/put
   - fbdev conflicting framebuffers code cleaned up
   - host-endian format variants
   - panel orientation quirk for Acer One 10

  bridge:
   - TI SN65DSI86 chip support

  vkms:
   - GEM support.
   - Cursor support

  amdgpu:
   - Merge amdkfd and amdgpu into one module
   - CEC over DP AUX support
   - Picasso APU support + VCN dynamic powergating
   - Raven2 APU support
   - Vega20 enablement + kfd support
   - ACP powergating improvements
   - ABGR/XBGR display support
   - VCN jpeg support
   - xGMI support
   - DC i2c/aux cleanup
   - Ycbcr 4:2:0 support
   - GPUVM improvements
   - Powerplay and powerplay endian fixes
   - Display underflow fixes

  vmwgfx:
   - Move vmwgfx specific TTM code to vmwgfx
   - Split out vmwgfx buffer/resource validation code
   - Atomic operation rework

  bochs:
   - use more helpers
   - format/byteorder improvements

  qxl:
   - use more helpers

  i915:
   - GGTT coherency getparam
   - Turn off resource streamer API
   - More Icelake enablement + DMC firmware
   - Full PPGTT for Ivybridge, Haswell and Valleyview
   - DDB distribution based on resolution
   - Limited range DP display support

  nouveau:
   - CEC over DP AUX support
   - Initial HDMI 2.0 support

  virtio-gpu:
   - vmap support for PRIME objects

  tegra:
   - Initial Tegra194 support
   - DMA/IOMMU integration fixes

  msm:
   - a6xx perf improvements + clock prefix
   - GPU preemption optimisations
   - a6xx devfreq support
   - cursor support

  rockchip:
   - PX30 support
   - rgb output interface support

  mediatek:
   - HDMI output support on mt2701 and mt7623

  rcar-du:
   - Interlaced modes on Gen3
   - LVDS on R8A77980
   - D3 and E3 SoC support

  hisilicon:
   - misc fixes

  mxsfb:
   - runtime pm support

  sun4i:
   - R40 TCON support
   - Allwinner A64 support
   - R40 HDMI support

  omapdrm:
   - Driver rework changing display pipeline ordering to use common code
   - DMM memory barrier and irq fixes
   - Errata workarounds

  exynos:
   - out-bridge support for LVDS bridge driver
   - Samsung 16x16 tiled format support
   - Plane alpha and pixel blend mode support

  tilcdc:
   - suspend/resume update

  mali-dp:
   - misc updates"

* tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits)
  firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.
  drm/i915/icl: Fix signal_levels
  drm/i915/icl: Fix DDI/TC port clk_off bits
  drm/i915/icl: create function to identify combophy port
  drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
  drm/i915: Large page offsets for pread/pwrite
  drm/i915/selftests: Disable shrinker across mmap-exhaustion
  drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode
  drm/i915: Fix intel_dp_mst_best_encoder()
  drm/i915: Skip vcpi allocation for MSTB ports that are gone
  drm/i915: Don't unset intel_connector->mst_port
  drm/i915: Only reset seqno if actually idle
  drm/i915: Use the correct crtc when sanitizing plane mapping
  drm/i915: Restore vblank interrupts earlier
  drm/i915: Check fb stride against plane max stride
  drm/amdgpu/vcn:Fix uninitialized symbol error
  drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003)
  drm/amd/amdgpu: Fix debugfs error handling
  drm/amdgpu: Update gc_9_0 golden settings.
  drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields
  ...

1 files changed, 51 insertions, 58 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index f55f72a37ca8..7b33867036e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -277,6 +277,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
         case CHIP_PITCAIRN:
         case CHIP_VERDE:
         case CHIP_OLAND:
+        case CHIP_HAINAN:
                 return AMDGPU_FW_LOAD_DIRECT;
 #endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
@@ -296,19 +297,15 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
         case CHIP_POLARIS11:
         case CHIP_POLARIS12:
         case CHIP_VEGAM:
-                if (!load_type)
-                        return AMDGPU_FW_LOAD_DIRECT;
-                else
-                        return AMDGPU_FW_LOAD_SMU;
+                return AMDGPU_FW_LOAD_SMU;
         case CHIP_VEGA10:
         case CHIP_RAVEN:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 if (!load_type)
                         return AMDGPU_FW_LOAD_DIRECT;
                 else
                         return AMDGPU_FW_LOAD_PSP;
-        case CHIP_VEGA20:
-                return AMDGPU_FW_LOAD_DIRECT;
         default:
                 DRM_ERROR("Unknown firmware load type\n");
         }
@@ -322,6 +319,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
 {
         const struct common_firmware_header *header = NULL;
         const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
+        const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
 
         if (NULL == ucode->fw)
                 return 0;
@@ -333,8 +331,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                 return 0;
 
         header = (const struct common_firmware_header *)ucode->fw->data;
-
         cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+        dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
 
         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
             (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
@@ -343,7 +341,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
              ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
              ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
-             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
+             ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
+                 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
                 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 
                 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
@@ -365,6 +365,20 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                                               le32_to_cpu(header->ucode_array_offset_bytes) +
                                               le32_to_cpu(cp_hdr->jt_offset) * 4),
                        ucode->ucode_size);
+        } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
+                ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+                                le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+                memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                              le32_to_cpu(header->ucode_array_offset_bytes)),
+                       ucode->ucode_size);
+        } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
+                ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+                memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+                                              le32_to_cpu(header->ucode_array_offset_bytes) +
+                                              le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
+                       ucode->ucode_size);
         } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
                 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
                 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
@@ -406,32 +420,41 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
         return 0;
 }
 
-int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
 {
-        uint64_t fw_offset = 0;
-        int i, err;
-        struct amdgpu_firmware_info *ucode = NULL;
-        const struct common_firmware_header *header = NULL;
-
-        if (!adev->firmware.fw_size) {
-                dev_warn(adev->dev, "No ip firmware need to load\n");
-                return 0;
-        }
-
-        if (!adev->in_gpu_reset) {
-                err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
-                                        amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
-                                        &adev->firmware.fw_buf,
-                                        &adev->firmware.fw_buf_mc,
-                                        &adev->firmware.fw_buf_ptr);
-                if (err) {
+        if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+                amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+                        amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+                        &adev->firmware.fw_buf,
+                        &adev->firmware.fw_buf_mc,
+                        &adev->firmware.fw_buf_ptr);
+                if (!adev->firmware.fw_buf) {
                         dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
-                        goto failed;
+                        return -ENOMEM;
+                } else if (amdgpu_sriov_vf(adev)) {
+                        memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
                 }
         }
+        return 0;
+}
 
-        memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+        if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+                amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
+                &adev->firmware.fw_buf_mc,
+                &adev->firmware.fw_buf_ptr);
+}
+
+int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
+{
+        uint64_t fw_offset = 0;
+        int i;
+        struct amdgpu_firmware_info *ucode = NULL;
 
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
+        if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
+                return 0;
         /*
          * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
          * ucode info here
@@ -448,7 +471,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
         for (i = 0; i < adev->firmware.max_ucodes; i++) {