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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c239
1 files changed, 66 insertions, 173 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 06373d44b3da..8af67f649660 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -24,46 +24,21 @@
24#include <drm/drmP.h> 24#include <drm/drmP.h>
25#include "amdgpu.h" 25#include "amdgpu.h"
26#include "amdgpu_ih.h" 26#include "amdgpu_ih.h"
27#include "amdgpu_amdkfd.h"
28
29/**
30 * amdgpu_ih_ring_alloc - allocate memory for the IH ring
31 *
32 * @adev: amdgpu_device pointer
33 *
34 * Allocate a ring buffer for the interrupt controller.
35 * Returns 0 for success, errors for failure.
36 */
37static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
38{
39 int r;
40
41 /* Allocate ring buffer */
42 if (adev->irq.ih.ring_obj == NULL) {
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
44 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
45 &adev->irq.ih.ring_obj,
46 &adev->irq.ih.gpu_addr,
47 (void **)&adev->irq.ih.ring);
48 if (r) {
49 DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
50 return r;
51 }
52 }
53 return 0;
54}
55 27
56/** 28/**
57 * amdgpu_ih_ring_init - initialize the IH state 29 * amdgpu_ih_ring_init - initialize the IH state
58 * 30 *
59 * @adev: amdgpu_device pointer 31 * @adev: amdgpu_device pointer
32 * @ih: ih ring to initialize
33 * @ring_size: ring size to allocate
34 * @use_bus_addr: true when we can use dma_alloc_coherent
60 * 35 *
61 * Initializes the IH state and allocates a buffer 36 * Initializes the IH state and allocates a buffer
62 * for the IH ring buffer. 37 * for the IH ring buffer.
63 * Returns 0 for success, errors for failure. 38 * Returns 0 for success, errors for failure.
64 */ 39 */
65int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, 40int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
66 bool use_bus_addr) 41 unsigned ring_size, bool use_bus_addr)
67{ 42{
68 u32 rb_bufsz; 43 u32 rb_bufsz;
69 int r; 44 int r;
@@ -71,70 +46,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
71 /* Align ring size */ 46 /* Align ring size */
72 rb_bufsz = order_base_2(ring_size / 4); 47 rb_bufsz = order_base_2(ring_size / 4);
73 ring_size = (1 << rb_bufsz) * 4; 48 ring_size = (1 << rb_bufsz) * 4;
74 adev->irq.ih.ring_size = ring_size; 49 ih->ring_size = ring_size;
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; 50 ih->ptr_mask = ih->ring_size - 1;
76 adev->irq.ih.rptr = 0; 51 ih->rptr = 0;
77 adev->irq.ih.use_bus_addr = use_bus_addr; 52 ih->use_bus_addr = use_bus_addr;
78 53
79 if (adev->irq.ih.use_bus_addr) { 54 if (use_bus_addr) {
80 if (!adev->irq.ih.ring) { 55 if (ih->ring)
81 /* add 8 bytes for the rptr/wptr shadows and 56 return 0;
82 * add them to the end of the ring allocation. 57
83 */ 58 /* add 8 bytes for the rptr/wptr shadows and
84 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev, 59 * add them to the end of the ring allocation.
85 adev->irq.ih.ring_size + 8, 60 */
86 &adev->irq.ih.rb_dma_addr); 61 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
87 if (adev->irq.ih.ring == NULL) 62 &ih->rb_dma_addr, GFP_KERNEL);
88 return -ENOMEM; 63 if (ih->ring == NULL)
89 memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8); 64 return -ENOMEM;
90 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; 65
91 adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1; 66 memset((void *)ih->ring, 0, ih->ring_size + 8);
92 } 67 ih->wptr_offs = (ih->ring_size / 4) + 0;
93 return 0; 68 ih->rptr_offs = (ih->ring_size / 4) + 1;
94 } else { 69 } else {
95 r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs); 70 r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
71 if (r)
72 return r;
73
74 r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
96 if (r) { 75 if (r) {
97 dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r); 76 amdgpu_device_wb_free(adev, ih->wptr_offs);
98 return r; 77 return r;
99 } 78 }
100 79
101 r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs); 80 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
81 AMDGPU_GEM_DOMAIN_GTT,
82 &ih->ring_obj, &ih->gpu_addr,
83 (void **)&ih->ring);
102 if (r) { 84 if (r) {
103 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); 85 amdgpu_device_wb_free(adev, ih->rptr_offs);
104 dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r); 86 amdgpu_device_wb_free(adev, ih->wptr_offs);
105 return r; 87 return r;
106 } 88 }
107
108 return amdgpu_ih_ring_alloc(adev);
109 } 89 }
90 return 0;
110} 91}
111 92
112/** 93/**
113 * amdgpu_ih_ring_fini - tear down the IH state 94 * amdgpu_ih_ring_fini - tear down the IH state
114 * 95 *
115 * @adev: amdgpu_device pointer 96 * @adev: amdgpu_device pointer
97 * @ih: ih ring to tear down
116 * 98 *
117 * Tears down the IH state and frees buffer 99 * Tears down the IH state and frees buffer
118 * used for the IH ring buffer. 100 * used for the IH ring buffer.
119 */ 101 */
120void amdgpu_ih_ring_fini(struct amdgpu_device *adev) 102void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
121{ 103{
122 if (adev->irq.ih.use_bus_addr) { 104 if (ih->use_bus_addr) {
123 if (adev->irq.ih.ring) { 105 if (!ih->ring)
124 /* add 8 bytes for the rptr/wptr shadows and 106 return;
125 * add them to the end of the ring allocation. 107
126 */ 108 /* add 8 bytes for the rptr/wptr shadows and
127 pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8, 109 * add them to the end of the ring allocation.
128 (void *)adev->irq.ih.ring, 110 */
129 adev->irq.ih.rb_dma_addr); 111 dma_free_coherent(adev->dev, ih->ring_size + 8,
130 adev->irq.ih.ring = NULL; 112 (void *)ih->ring, ih->rb_dma_addr);
131 } 113 ih->ring = NULL;
132 } else { 114 } else {
133 amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj, 115 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
134 &adev->irq.ih.gpu_addr, 116 (void **)&ih->ring);
135 (void **)&adev->irq.ih.ring); 117 amdgpu_device_wb_free(adev, ih->wptr_offs);
136 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); 118 amdgpu_device_wb_free(adev, ih->rptr_offs);
137 amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
138 } 119 }