Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie: "This is going to rebuild more than drm as it adds a new helper to list.h for doing bulk updates. Seemed like a reasonable addition to me. Otherwise the usual merge window stuff lots of i915 and amdgpu, not so much nouveau, and piles of everything else. Core: - Adds a new list.h helper for doing bulk list updates for TTM. - Don't leak fb address in smem_start to userspace (comes with EXPORT workaround for people using mali out of tree hacks) - udmabuf device to turn memfd regions into dma-buf - Per-plane blend mode property - ref/unref replacements with get/put - fbdev conflicting framebuffers code cleaned up - host-endian format variants - panel orientation quirk for Acer One 10 bridge: - TI SN65DSI86 chip support vkms: - GEM support. - Cursor support amdgpu: - Merge amdkfd and amdgpu into one module - CEC over DP AUX support - Picasso APU support + VCN dynamic powergating - Raven2 APU support - Vega20 enablement + kfd support - ACP powergating improvements - ABGR/XBGR display support - VCN jpeg support - xGMI support - DC i2c/aux cleanup - Ycbcr 4:2:0 support - GPUVM improvements - Powerplay and powerplay endian fixes - Display underflow fixes vmwgfx: - Move vmwgfx specific TTM code to vmwgfx - Split out vmwgfx buffer/resource validation code - Atomic operation rework bochs: - use more helpers - format/byteorder improvements qxl: - use more helpers i915: - GGTT coherency getparam - Turn off resource streamer API - More Icelake enablement + DMC firmware - Full PPGTT for Ivybridge, Haswell and Valleyview - DDB distribution based on resolution - Limited range DP display support nouveau: - CEC over DP AUX support - Initial HDMI 2.0 support virtio-gpu: - vmap support for PRIME objects tegra: - Initial Tegra194 support - DMA/IOMMU integration fixes msm: - a6xx perf improvements + clock prefix - GPU preemption optimisations - a6xx devfreq support - cursor support rockchip: - PX30 support - rgb output interface support mediatek: - HDMI output support on mt2701 and mt7623 rcar-du: - Interlaced modes on Gen3 - LVDS on R8A77980 - D3 and E3 SoC support hisilicon: - misc fixes mxsfb: - runtime pm support sun4i: - R40 TCON support - Allwinner A64 support - R40 HDMI support omapdrm: - Driver rework changing display pipeline ordering to use common code - DMM memory barrier and irq fixes - Errata workarounds exynos: - out-bridge support for LVDS bridge driver - Samsung 16x16 tiled format support - Plane alpha and pixel blend mode support tilcdc: - suspend/resume update mali-dp: - misc updates" * tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits) firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake. drm/i915/icl: Fix signal_levels drm/i915/icl: Fix DDI/TC port clk_off bits drm/i915/icl: create function to identify combophy port drm/i915/gen9+: Fix initial readout for Y tiled framebuffers drm/i915: Large page offsets for pread/pwrite drm/i915/selftests: Disable shrinker across mmap-exhaustion drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode drm/i915: Fix intel_dp_mst_best_encoder() drm/i915: Skip vcpi allocation for MSTB ports that are gone drm/i915: Don't unset intel_connector->mst_port drm/i915: Only reset seqno if actually idle drm/i915: Use the correct crtc when sanitizing plane mapping drm/i915: Restore vblank interrupts earlier drm/i915: Check fb stride against plane max stride drm/amdgpu/vcn:Fix uninitialized symbol error drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003) drm/amd/amdgpu: Fix debugfs error handling drm/amdgpu: Update gc_9_0 golden settings. drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2018-10-28 20:49:53 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2018-10-28 20:49:53 -0400
commit: 53b3b6bbfde6aae8d1ededc86ad4e0e1e00eb5f8 (patch)
tree: b29473f21270aefd113b298c9402be8b4b3c91b4 /drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
parent: 746bb4ed6d626f3f9e431a7f9b20504538e62ded (diff)
parent: f2bfc71aee75feff33ca659322b72ffeed5a243d (diff)
1 files changed, 66 insertions, 173 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 06373d44b3da..8af67f649660 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -24,46 +24,21 @@
 #include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_ih.h"
-#include "amdgpu_amdkfd.h"
-/**
- * amdgpu_ih_ring_alloc - allocate memory for the IH ring
- *
- * @adev: amdgpu_device pointer
- *
- * Allocate a ring buffer for the interrupt controller.
- * Returns 0 for success, errors for failure.
- */
-static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
-{
-        int r;
-        /* Allocate ring buffer */
-        if (adev->irq.ih.ring_obj == NULL) {
-                r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
-                                            PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
-                                            &adev->irq.ih.ring_obj,
-                                            &adev->irq.ih.gpu_addr,
-                                            (void **)&adev->irq.ih.ring);
-                if (r) {
-                        DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
-                        return r;
-                }
-        }
-        return 0;
-}
 /**
 * amdgpu_ih_ring_init - initialize the IH state
 *
 * @adev: amdgpu_device pointer
+ * @ih: ih ring to initialize
+ * @ring_size: ring size to allocate
+ * @use_bus_addr: true when we can use dma_alloc_coherent
 *
 * Initializes the IH state and allocates a buffer
 * for the IH ring buffer.
 * Returns 0 for success, errors for failure.
 */
-int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
+int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
-                        bool use_bus_addr)
+                        unsigned ring_size, bool use_bus_addr)
 {
        u32 rb_bufsz;
        int r;
@@ -71,70 +46,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
        /* Align ring size */
        rb_bufsz = order_base_2(ring_size / 4);
        ring_size = (1 << rb_bufsz) * 4;
-        adev->irq.ih.ring_size = ring_size;
+        ih->ring_size = ring_size;
-        adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
+        ih->ptr_mask = ih->ring_size - 1;
-        adev->irq.ih.rptr = 0;
+        ih->rptr = 0;
-        adev->irq.ih.use_bus_addr = use_bus_addr;
+        ih->use_bus_addr = use_bus_addr;
-        if (adev->irq.ih.use_bus_addr) {
+        if (use_bus_addr) {
-                if (!adev->irq.ih.ring) {
+                if (ih->ring)
-                        /* add 8 bytes for the rptr/wptr shadows and
+                        return 0;
-                         * add them to the end of the ring allocation.
-                         */
+                /* add 8 bytes for the rptr/wptr shadows and
-                        adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
+                 * add them to the end of the ring allocation.
-                                                                 adev->irq.ih.ring_size + 8,
+                 */
-                                                                 &adev->irq.ih.rb_dma_addr);
+                ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
-                        if (adev->irq.ih.ring == NULL)
+                                              &ih->rb_dma_addr, GFP_KERNEL);
-                                return -ENOMEM;
+                if (ih->ring == NULL)
-                        memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
+                        return -ENOMEM;
-                        adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
-                        adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
+                memset((void *)ih->ring, 0, ih->ring_size + 8);
-                }
+                ih->wptr_offs = (ih->ring_size / 4) + 0;
-                return 0;
+                ih->rptr_offs = (ih->ring_size / 4) + 1;
        } else {
-                r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
+                r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
+                if (r)
+                        return r;
+                r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
                if (r) {
-                        dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
+                        amdgpu_device_wb_free(adev, ih->wptr_offs);
                        return r;
                }
-                r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
+                r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
+                                            AMDGPU_GEM_DOMAIN_GTT,
+                                            &ih->ring_obj, &ih->gpu_addr,
+                                            (void **)&ih->ring);
                if (r) {
-                        amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
+                        amdgpu_device_wb_free(adev, ih->rptr_offs);
-                        dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
+                        amdgpu_device_wb_free(adev, ih->wptr_offs);
                        return r;
                }
-                return amdgpu_ih_ring_alloc(adev);
        }
+        return 0;
 }
 /**
 * amdgpu_ih_ring_fini - tear down the IH state
 *
 * @adev: amdgpu_device pointer
+ * @ih: ih ring to tear down
 *
 * Tears down the IH state and frees buffer
 * used for the IH ring buffer.
 */
-void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
+void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 {
-        if (adev->irq.ih.use_bus_addr) {
+        if (ih->use_bus_addr) {
-                if (adev->irq.ih.ring) {
+                if (!ih->ring)
-                        /* add 8 bytes for the rptr/wptr shadows and
+                        return;
-                         * add them to the end of the ring allocation.
-                         */
+                /* add 8 bytes for the rptr/wptr shadows and
-                        pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
+                 * add them to the end of the ring allocation.
author	Linus Torvalds <torvalds@linux-foundation.org>	2018-10-28 20:49:53 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2018-10-28 20:49:53 -0400
commit	53b3b6bbfde6aae8d1ededc86ad4e0e1e00eb5f8 (patch)
tree	b29473f21270aefd113b298c9402be8b4b3c91b4 /drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
parent	746bb4ed6d626f3f9e431a7f9b20504538e62ded (diff)
parent	f2bfc71aee75feff33ca659322b72ffeed5a243d (diff)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 06373d44b3da..8af67f649660 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -24,46 +24,21 @@
24	#include <drm/drmP.h>	24	#include <drm/drmP.h>
25	#include "amdgpu.h"	25	#include "amdgpu.h"
26	#include "amdgpu_ih.h"	26	#include "amdgpu_ih.h"
27	#include "amdgpu_amdkfd.h"
28
29	/**
30	* amdgpu_ih_ring_alloc - allocate memory for the IH ring
31	*
32	* @adev: amdgpu_device pointer
33	*
34	* Allocate a ring buffer for the interrupt controller.
35	* Returns 0 for success, errors for failure.
36	*/
37	static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
38	{
39	int r;
40
41	/* Allocate ring buffer */
42	if (adev->irq.ih.ring_obj == NULL) {
43	r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
44	PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
45	&adev->irq.ih.ring_obj,
46	&adev->irq.ih.gpu_addr,
47	(void **)&adev->irq.ih.ring);
48	if (r) {
49	DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
50	return r;
51	}
52	}
53	return 0;
54	}
55		27
56	/**	28	/**
57	* amdgpu_ih_ring_init - initialize the IH state	29	* amdgpu_ih_ring_init - initialize the IH state
58	*	30	*
59	* @adev: amdgpu_device pointer	31	* @adev: amdgpu_device pointer
		32	* @ih: ih ring to initialize
		33	* @ring_size: ring size to allocate
		34	* @use_bus_addr: true when we can use dma_alloc_coherent
60	*	35	*
61	* Initializes the IH state and allocates a buffer	36	* Initializes the IH state and allocates a buffer
62	* for the IH ring buffer.	37	* for the IH ring buffer.
63	* Returns 0 for success, errors for failure.	38	* Returns 0 for success, errors for failure.
64	*/	39	*/
65	int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,	40	int amdgpu_ih_ring_init(struct amdgpu_device adev, struct amdgpu_ih_ring ih,
66	bool use_bus_addr)	41	unsigned ring_size, bool use_bus_addr)
67	{	42	{
68	u32 rb_bufsz;	43	u32 rb_bufsz;
69	int r;	44	int r;
@@ -71,70 +46,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
71	/* Align ring size */	46	/* Align ring size */
72	rb_bufsz = order_base_2(ring_size / 4);	47	rb_bufsz = order_base_2(ring_size / 4);
73	ring_size = (1 << rb_bufsz) * 4;	48	ring_size = (1 << rb_bufsz) * 4;
74	adev->irq.ih.ring_size = ring_size;	49	ih->ring_size = ring_size;
75	adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;	50	ih->ptr_mask = ih->ring_size - 1;
76	adev->irq.ih.rptr = 0;	51	ih->rptr = 0;
77	adev->irq.ih.use_bus_addr = use_bus_addr;	52	ih->use_bus_addr = use_bus_addr;
78		53
79	if (adev->irq.ih.use_bus_addr) {	54	if (use_bus_addr) {
80	if (!adev->irq.ih.ring) {	55	if (ih->ring)
81	/* add 8 bytes for the rptr/wptr shadows and	56	return 0;
82	* add them to the end of the ring allocation.	57
83	*/	58	/* add 8 bytes for the rptr/wptr shadows and
84	adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,	59	* add them to the end of the ring allocation.
85	adev->irq.ih.ring_size + 8,	60	*/
86	&adev->irq.ih.rb_dma_addr);	61	ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
87	if (adev->irq.ih.ring == NULL)	62	&ih->rb_dma_addr, GFP_KERNEL);
88	return -ENOMEM;	63	if (ih->ring == NULL)
89	memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);	64	return -ENOMEM;
90	adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;	65
91	adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;	66	memset((void *)ih->ring, 0, ih->ring_size + 8);
92	}	67	ih->wptr_offs = (ih->ring_size / 4) + 0;
93	return 0;	68	ih->rptr_offs = (ih->ring_size / 4) + 1;
94	} else {	69	} else {
95	r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);	70	r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
		71	if (r)
		72	return r;
		73
		74	r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
96	if (r) {	75	if (r) {
97	dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);	76	amdgpu_device_wb_free(adev, ih->wptr_offs);
98	return r;	77	return r;
99	}	78	}
100		79
101	r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);	80	r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
		81	AMDGPU_GEM_DOMAIN_GTT,
		82	&ih->ring_obj, &ih->gpu_addr,
		83	(void **)&ih->ring);
102	if (r) {	84	if (r) {
103	amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);	85	amdgpu_device_wb_free(adev, ih->rptr_offs);
104	dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);	86	amdgpu_device_wb_free(adev, ih->wptr_offs);
105	return r;	87	return r;
106	}	88	}
107
108	return amdgpu_ih_ring_alloc(adev);
109	}	89	}
		90	return 0;
110	}	91	}
111		92
112	/**	93	/**
113	* amdgpu_ih_ring_fini - tear down the IH state	94	* amdgpu_ih_ring_fini - tear down the IH state
114	*	95	*
115	* @adev: amdgpu_device pointer	96	* @adev: amdgpu_device pointer
		97	* @ih: ih ring to tear down
116	*	98	*
117	* Tears down the IH state and frees buffer	99	* Tears down the IH state and frees buffer
118	* used for the IH ring buffer.	100	* used for the IH ring buffer.
119	*/	101	*/
120	void amdgpu_ih_ring_fini(struct amdgpu_device *adev)	102	void amdgpu_ih_ring_fini(struct amdgpu_device adev, struct amdgpu_ih_ring ih)
121	{	103	{
122	if (adev->irq.ih.use_bus_addr) {	104	if (ih->use_bus_addr) {
123	if (adev->irq.ih.ring) {	105	if (!ih->ring)
124	/* add 8 bytes for the rptr/wptr shadows and	106	return;
125	* add them to the end of the ring allocation.	107
126	*/	108	/* add 8 bytes for the rptr/wptr shadows and
127	pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,	109	* add them to the end of the ring allocation.