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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c64
1 files changed, 34 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 83dda05325b8..831c2bfd2072 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1042,14 +1042,6 @@ static bool amdgpu_check_pot_argument(int arg)
1042 1042
1043static void amdgpu_get_block_size(struct amdgpu_device *adev) 1043static void amdgpu_get_block_size(struct amdgpu_device *adev)
1044{ 1044{
1045 /* from AI, asic starts to support multiple level VMPT */
1046 if (adev->asic_type >= CHIP_VEGA10) {
1047 if (amdgpu_vm_block_size != 9)
1048 dev_warn(adev->dev,
1049 "Multi-VMPT limits block size to one page!\n");
1050 amdgpu_vm_block_size = 9;
1051 return;
1052 }
1053 /* defines number of bits in page table versus page directory, 1045 /* defines number of bits in page table versus page directory,
1054 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1046 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1055 * page table and the remaining bits are in the page directory */ 1047 * page table and the remaining bits are in the page directory */
@@ -1079,6 +1071,36 @@ static void amdgpu_get_block_size(struct amdgpu_device *adev)
1079 } 1071 }
1080} 1072}
1081 1073
1074static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1075{
1076 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1077 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1078 amdgpu_vm_size);
1079 goto def_value;
1080 }
1081
1082 if (amdgpu_vm_size < 1) {
1083 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1084 amdgpu_vm_size);
1085 goto def_value;
1086 }
1087
1088 /*
1089 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1090 */
1091 if (amdgpu_vm_size > 1024) {
1092 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1093 amdgpu_vm_size);
1094 goto def_value;
1095 }
1096
1097 return;
1098
1099def_value:
1100 amdgpu_vm_size = 8;
1101 dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
1102}
1103
1082/** 1104/**
1083 * amdgpu_check_arguments - validate module params 1105 * amdgpu_check_arguments - validate module params
1084 * 1106 *
@@ -1108,26 +1130,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
1108 } 1130 }
1109 } 1131 }
1110 1132
1111 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { 1133 amdgpu_check_vm_size(adev);
1112 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1113 amdgpu_vm_size);
1114 amdgpu_vm_size = 8;
1115 }
1116
1117 if (amdgpu_vm_size < 1) {
1118 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1119 amdgpu_vm_size);
1120 amdgpu_vm_size = 8;
1121 }
1122
1123 /*
1124 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1125 */
1126 if (amdgpu_vm_size > 1024) {
1127 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1128 amdgpu_vm_size);
1129 amdgpu_vm_size = 8;
1130 }
1131 1134
1132 amdgpu_get_block_size(adev); 1135 amdgpu_get_block_size(adev);
1133 1136
@@ -2249,9 +2252,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2249 } 2252 }
2250 2253
2251 r = amdgpu_resume(adev); 2254 r = amdgpu_resume(adev);
2252 if (r) 2255 if (r) {
2253 DRM_ERROR("amdgpu_resume failed (%d).\n", r); 2256 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2254 2257 return r;
2258 }
2255 amdgpu_fence_driver_resume(adev); 2259 amdgpu_fence_driver_resume(adev);
2256 2260
2257 if (resume) { 2261 if (resume) {