diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 262 |
1 files changed, 176 insertions, 86 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index df6965761046..f9b54236102d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | |||
| @@ -27,6 +27,30 @@ | |||
| 27 | #include "amdgpu.h" | 27 | #include "amdgpu.h" |
| 28 | #include "amdgpu_sched.h" | 28 | #include "amdgpu_sched.h" |
| 29 | 29 | ||
| 30 | #define to_amdgpu_ctx_entity(e) \ | ||
| 31 | container_of((e), struct amdgpu_ctx_entity, entity) | ||
| 32 | |||
| 33 | const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { | ||
| 34 | [AMDGPU_HW_IP_GFX] = 1, | ||
| 35 | [AMDGPU_HW_IP_COMPUTE] = 4, | ||
| 36 | [AMDGPU_HW_IP_DMA] = 2, | ||
| 37 | [AMDGPU_HW_IP_UVD] = 1, | ||
| 38 | [AMDGPU_HW_IP_VCE] = 1, | ||
| 39 | [AMDGPU_HW_IP_UVD_ENC] = 1, | ||
| 40 | [AMDGPU_HW_IP_VCN_DEC] = 1, | ||
| 41 | [AMDGPU_HW_IP_VCN_ENC] = 1, | ||
| 42 | }; | ||
| 43 | |||
| 44 | static int amdgput_ctx_total_num_entities(void) | ||
| 45 | { | ||
| 46 | unsigned i, num_entities = 0; | ||
| 47 | |||
| 48 | for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) | ||
| 49 | num_entities += amdgpu_ctx_num_entities[i]; | ||
| 50 | |||
| 51 | return num_entities; | ||
| 52 | } | ||
| 53 | |||
| 30 | static int amdgpu_ctx_priority_permit(struct drm_file *filp, | 54 | static int amdgpu_ctx_priority_permit(struct drm_file *filp, |
| 31 | enum drm_sched_priority priority) | 55 | enum drm_sched_priority priority) |
| 32 | { | 56 | { |
| @@ -48,6 +72,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, | |||
| 48 | struct drm_file *filp, | 72 | struct drm_file *filp, |
| 49 | struct amdgpu_ctx *ctx) | 73 | struct amdgpu_ctx *ctx) |
| 50 | { | 74 | { |
| 75 | unsigned num_entities = amdgput_ctx_total_num_entities(); | ||
| 51 | unsigned i, j; | 76 | unsigned i, j; |
| 52 | int r; | 77 | int r; |
| 53 | 78 | ||
| @@ -60,19 +85,33 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, | |||
| 60 | 85 | ||
| 61 | memset(ctx, 0, sizeof(*ctx)); | 86 | memset(ctx, 0, sizeof(*ctx)); |
| 62 | ctx->adev = adev; | 87 | ctx->adev = adev; |
| 63 | kref_init(&ctx->refcount); | 88 | |
| 64 | spin_lock_init(&ctx->ring_lock); | 89 | ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities, |
| 65 | ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, | ||
| 66 | sizeof(struct dma_fence*), GFP_KERNEL); | 90 | sizeof(struct dma_fence*), GFP_KERNEL); |
| 67 | if (!ctx->fences) | 91 | if (!ctx->fences) |
| 68 | return -ENOMEM; | 92 | return -ENOMEM; |
| 69 | 93 | ||
| 70 | mutex_init(&ctx->lock); | 94 | ctx->entities[0] = kcalloc(num_entities, |
| 95 | sizeof(struct amdgpu_ctx_entity), | ||
| 96 | GFP_KERNEL); | ||
| 97 | if (!ctx->entities[0]) { | ||
| 98 | r = -ENOMEM; | ||
| 99 | goto error_free_fences; | ||
| 100 | } | ||
| 71 | 101 | ||
| 72 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | 102 | for (i = 0; i < num_entities; ++i) { |
| 73 | ctx->rings[i].sequence = 1; | 103 | struct amdgpu_ctx_entity *entity = &ctx->entities[0][i]; |
| 74 | ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; | 104 | |
| 105 | entity->sequence = 1; | ||
| 106 | entity->fences = &ctx->fences[amdgpu_sched_jobs * i]; | ||
| 75 | } | 107 | } |
| 108 | for (i = 1; i < AMDGPU_HW_IP_NUM; ++i) | ||
| 109 | ctx->entities[i] = ctx->entities[i - 1] + | ||
| 110 | amdgpu_ctx_num_entities[i - 1]; | ||
| 111 | |||
| 112 | kref_init(&ctx->refcount); | ||
| 113 | spin_lock_init(&ctx->ring_lock); | ||
| 114 | mutex_init(&ctx->lock); | ||
| 76 | 115 | ||
| 77 | ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); | 116 | ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); |
| 78 | ctx->reset_counter_query = ctx->reset_counter; | 117 | ctx->reset_counter_query = ctx->reset_counter; |
| @@ -80,31 +119,70 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, | |||
| 80 | ctx->init_priority = priority; | 119 | ctx->init_priority = priority; |
| 81 | ctx->override_priority = DRM_SCHED_PRIORITY_UNSET; | 120 | ctx->override_priority = DRM_SCHED_PRIORITY_UNSET; |
| 82 | 121 | ||
| 83 | /* create context entity for each ring */ | 122 | for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { |
| 84 | for (i = 0; i < adev->num_rings; i++) { | 123 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; |
| 85 | struct amdgpu_ring *ring = adev->rings[i]; | 124 | struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS]; |
| 86 | struct drm_sched_rq *rq; | 125 | unsigned num_rings; |
| 126 | |||
| 127 | switch (i) { | ||
| 128 | case AMDGPU_HW_IP_GFX: | ||
| 129 | rings[0] = &adev->gfx.gfx_ring[0]; | ||
| 130 | num_rings = 1; | ||
| 131 | break; | ||
| 132 | case AMDGPU_HW_IP_COMPUTE: | ||
| 133 | for (j = 0; j < adev->gfx.num_compute_rings; ++j) | ||
| 134 | rings[j] = &adev->gfx.compute_ring[j]; | ||
| 135 | num_rings = adev->gfx.num_compute_rings; | ||
| 136 | break; | ||
| 137 | case AMDGPU_HW_IP_DMA: | ||
| 138 | for (j = 0; j < adev->sdma.num_instances; ++j) | ||
| 139 | rings[j] = &adev->sdma.instance[j].ring; | ||
| 140 | num_rings = adev->sdma.num_instances; | ||
| 141 | break; | ||
| 142 | case AMDGPU_HW_IP_UVD: | ||
| 143 | rings[0] = &adev->uvd.inst[0].ring; | ||
| 144 | num_rings = 1; | ||
| 145 | break; | ||
| 146 | case AMDGPU_HW_IP_VCE: | ||
| 147 | rings[0] = &adev->vce.ring[0]; | ||
| 148 | num_rings = 1; | ||
| 149 | break; | ||
| 150 | case AMDGPU_HW_IP_UVD_ENC: | ||
| 151 | rings[0] = &adev->uvd.inst[0].ring_enc[0]; | ||
| 152 | num_rings = 1; | ||
| 153 | break; | ||
| 154 | case AMDGPU_HW_IP_VCN_DEC: | ||
| 155 | rings[0] = &adev->vcn.ring_dec; | ||
| 156 | num_rings = 1; | ||
| 157 | break; | ||
| 158 | case AMDGPU_HW_IP_VCN_ENC: | ||
| 159 | rings[0] = &adev->vcn.ring_enc[0]; | ||
| 160 | num_rings = 1; | ||
| 161 | break; | ||
| 162 | case AMDGPU_HW_IP_VCN_JPEG: | ||
| 163 | rings[0] = &adev->vcn.ring_jpeg; | ||
| 164 | num_rings = 1; | ||
| 165 | break; | ||
| 166 | } | ||
| 87 | 167 | ||
| 88 | rq = &ring->sched.sched_rq[priority]; | 168 | for (j = 0; j < num_rings; ++j) |
| 169 | rqs[j] = &rings[j]->sched.sched_rq[priority]; | ||
| 89 | 170 | ||
| 90 | if (ring == &adev->gfx.kiq.ring) | 171 | for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) |
| 91 | continue; | 172 | r = drm_sched_entity_init(&ctx->entities[i][j].entity, |
| 92 | 173 | rqs, num_rings, &ctx->guilty); | |
| 93 | r = drm_sched_entity_init(&ctx->rings[i].entity, | ||
| 94 | &rq, 1, &ctx->guilty); | ||
| 95 | if (r) | 174 | if (r) |
| 96 | goto failed; | 175 | goto error_cleanup_entities; |
| 97 | } | 176 | } |
| 98 | 177 | ||
| 99 | r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr); | ||
| 100 | if (r) | ||
| 101 | goto failed; | ||
| 102 | |||
| 103 | return 0; | 178 | return 0; |
| 104 | 179 | ||
| 105 | failed: | 180 | error_cleanup_entities: |
| 106 | for (j = 0; j < i; j++) | 181 | for (i = 0; i < num_entities; ++i) |
| 107 | drm_sched_entity_destroy(&ctx->rings[j].entity); | 182 | drm_sched_entity_destroy(&ctx->entities[0][i].entity); |
| 183 | kfree(ctx->entities[0]); | ||
| 184 | |||
| 185 | error_free_fences: | ||
| 108 | kfree(ctx->fences); | 186 | kfree(ctx->fences); |
| 109 | ctx->fences = NULL; | 187 | ctx->fences = NULL; |
| 110 | return r; | 188 | return r; |
| @@ -113,25 +191,47 @@ failed: | |||
| 113 | static void amdgpu_ctx_fini(struct kref *ref) | 191 | static void amdgpu_ctx_fini(struct kref *ref) |
| 114 | { | 192 | { |
| 115 | struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); | 193 | struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); |
| 194 | unsigned num_entities = amdgput_ctx_total_num_entities(); | ||
| 116 | struct amdgpu_device *adev = ctx->adev; | 195 | struct amdgpu_device *adev = ctx->adev; |
| 117 | unsigned i, j; | 196 | unsigned i, j; |
| 118 | 197 | ||
| 119 | if (!adev) | 198 | if (!adev) |
| 120 | return; | 199 | return; |
| 121 | 200 | ||
| 122 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | ||
