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-rw-r--r--arch/x86/include/asm/pgtable-3level.h7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index a564084c6141..f8b1ad2c3828 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -2,6 +2,8 @@
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H 2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H 3#define _ASM_X86_PGTABLE_3LEVEL_H
4 4
5#include <asm/atomic64_32.h>
6
5/* 7/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page 8 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs. 9 * tables on PPro+ CPUs.
@@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
150{ 152{
151 pte_t res; 153 pte_t res;
152 154
153 /* xchg acts as a barrier before the setting of the high bits */ 155 res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
154 res.pte_low = xchg(&ptep->pte_low, 0);
155 res.pte_high = ptep->pte_high;
156 ptep->pte_high = 0;
157 156
158 return res; 157 return res;
159} 158}