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authorJason Gunthorpe <jgg@mellanox.com>2018-09-05 18:21:22 -0400
committerJason Gunthorpe <jgg@mellanox.com>2018-09-05 18:21:22 -0400
commit2c910cb75e1fe6de52d95c8e32caedd1629a33a5 (patch)
tree94a0eea6f8cde689d11e7583ddd0a930b8785ab4 /arch/x86/include/asm/pgtable-3level.h
parent627212c9d49ba2759b699450f5d8f45f73e062fa (diff)
parentb53b1c08a23eb1091982daacb2122f90a7094a77 (diff)
Merge branch 'uverbs_dev_cleanups' into rdma.git for-next
For dependencies, branch based on rdma.git 'for-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/ Pull 'uverbs_dev_cleanups' from Leon Romanovsky: ==================== Reuse the char device code interfaces to simplify ib_uverbs_device creation and destruction. As part of this series, we are sending fix to cleanup path, which was discovered during internal review, The fix definitely can go to -rc, but it means that this series will be dependent on rdma-rc. ==================== * branch 'uverbs_dev_cleanups': RDMA/uverbs: Use device.groups to initialize device attributes RDMA/uverbs: Use cdev_device_add() instead of cdev_add() RDMA/core: Depend on device_add() to add device attributes RDMA/uverbs: Fix error cleanup path of ib_uverbs_add_one() Resolved conflict in ib_device_unregister_sysfs() Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Diffstat (limited to 'arch/x86/include/asm/pgtable-3level.h')
-rw-r--r--arch/x86/include/asm/pgtable-3level.h7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index a564084c6141..f8b1ad2c3828 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -2,6 +2,8 @@
2#ifndef _ASM_X86_PGTABLE_3LEVEL_H 2#ifndef _ASM_X86_PGTABLE_3LEVEL_H
3#define _ASM_X86_PGTABLE_3LEVEL_H 3#define _ASM_X86_PGTABLE_3LEVEL_H
4 4
5#include <asm/atomic64_32.h>
6
5/* 7/*
6 * Intel Physical Address Extension (PAE) Mode - three-level page 8 * Intel Physical Address Extension (PAE) Mode - three-level page
7 * tables on PPro+ CPUs. 9 * tables on PPro+ CPUs.
@@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
150{ 152{
151 pte_t res; 153 pte_t res;
152 154
153 /* xchg acts as a barrier before the setting of the high bits */ 155 res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
154 res.pte_low = xchg(&ptep->pte_low, 0);
155 res.pte_high = ptep->pte_high;
156 ptep->pte_high = 0;
157 156
158 return res; 157 return res;
159} 158}