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-rw-r--r--arch/powerpc/mm/hash_native_64.c36
1 files changed, 22 insertions, 14 deletions
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index f8a871a72985..88ce7d212320 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -55,7 +55,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
55 * We need 14 to 65 bits of va for a tlibe of 4K page 55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already. 56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can 57 * And top two bits are already ignored because we can
58 * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT 58 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
59 * of 12. 59 * of 12.
60 */ 60 */
61 va = vpn << VPN_SHIFT; 61 va = vpn << VPN_SHIFT;
@@ -64,7 +64,8 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
64 * Older versions of the architecture (2.02 and earler) require the 64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits. 65 * masking of the top 16 bits.
66 */ 66 */
67 va &= ~(0xffffULL << 48); 67 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
68 va &= ~(0xffffULL << 48);
68 69
69 switch (psize) { 70 switch (psize) {
70 case MMU_PAGE_4K: 71 case MMU_PAGE_4K:
@@ -113,7 +114,8 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
113 * Older versions of the architecture (2.02 and earler) require the 114 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits. 115 * masking of the top 16 bits.
115 */ 116 */
116 va &= ~(0xffffULL << 48); 117 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
118 va &= ~(0xffffULL << 48);
117 119
118 switch (psize) { 120 switch (psize) {
119 case MMU_PAGE_4K: 121 case MMU_PAGE_4K:
@@ -605,7 +607,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
605 * crashdump and all bets are off anyway. 607 * crashdump and all bets are off anyway.
606 * 608 *
607 * TODO: add batching support when enabled. remember, no dynamic memory here, 609 * TODO: add batching support when enabled. remember, no dynamic memory here,
608 * athough there is the control page available... 610 * although there is the control page available...
609 */ 611 */
610static void native_hpte_clear(void) 612static void native_hpte_clear(void)
611{ 613{
@@ -723,23 +725,29 @@ static void native_flush_hash_range(unsigned long number, int local)
723 local_irq_restore(flags); 725 local_irq_restore(flags);
724} 726}
725 727
726static int native_update_partition_table(u64 patb1) 728static int native_register_proc_table(unsigned long base, unsigned long page_size,
729 unsigned long table_size)
727{ 730{
731 unsigned long patb1 = base << 25; /* VSID */
732
733 patb1 |= (page_size << 5); /* sllp */
734 patb1 |= table_size;
735
728 partition_tb->patb1 = cpu_to_be64(patb1); 736 partition_tb->patb1 = cpu_to_be64(patb1);
729 return 0; 737 return 0;
730} 738}
731 739
732void __init hpte_init_native(void) 740void __init hpte_init_native(void)
733{ 741{
734 ppc_md.hpte_invalidate = native_hpte_invalidate; 742 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
735 ppc_md.hpte_updatepp = native_hpte_updatepp; 743 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
736 ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; 744 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
737 ppc_md.hpte_insert = native_hpte_insert; 745 mmu_hash_ops.hpte_insert = native_hpte_insert;
738 ppc_md.hpte_remove = native_hpte_remove; 746 mmu_hash_ops.hpte_remove = native_hpte_remove;
739 ppc_md.hpte_clear_all = native_hpte_clear; 747 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
740 ppc_md.flush_hash_range = native_flush_hash_range; 748 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
741 ppc_md.hugepage_invalidate = native_hugepage_invalidate; 749 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
742 750
743 if (cpu_has_feature(CPU_FTR_ARCH_300)) 751 if (cpu_has_feature(CPU_FTR_ARCH_300))
744 ppc_md.update_partition_table = native_update_partition_table; 752 ppc_md.register_process_table = native_register_proc_table;
745} 753}