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-rw-r--r--arch/mips/mti-malta/malta-dt.c15
-rw-r--r--arch/mips/mti-malta/malta-dtshim.c187
-rw-r--r--arch/mips/mti-malta/malta-init.c17
-rw-r--r--arch/mips/mti-malta/malta-int.c111
-rw-r--r--arch/mips/mti-malta/malta-platform.c73
-rw-r--r--arch/mips/mti-malta/malta-reset.c21
-rw-r--r--arch/mips/mti-malta/malta-setup.c10
7 files changed, 198 insertions, 236 deletions
diff --git a/arch/mips/mti-malta/malta-dt.c b/arch/mips/mti-malta/malta-dt.c
index 47a22889285f..4822943100f3 100644
--- a/arch/mips/mti-malta/malta-dt.c
+++ b/arch/mips/mti-malta/malta-dt.c
@@ -17,18 +17,3 @@ void __init device_tree_init(void)
17{ 17{
18 unflatten_and_copy_device_tree(); 18 unflatten_and_copy_device_tree();
19} 19}
20
21static const struct of_device_id bus_ids[] __initconst = {
22 { .compatible = "simple-bus", },
23 { .compatible = "isa", },
24 {},
25};
26
27static int __init publish_devices(void)
28{
29 if (!of_have_populated_dt())
30 return 0;
31
32 return of_platform_bus_probe(NULL, bus_ids, NULL);
33}
34device_initcall(publish_devices);
diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta/malta-dtshim.c
index 151f4882ec8a..c398582c316f 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -13,18 +13,66 @@
13#include <linux/libfdt.h> 13#include <linux/libfdt.h>
14#include <linux/of_fdt.h> 14#include <linux/of_fdt.h>
15#include <linux/sizes.h> 15#include <linux/sizes.h>
16#include <asm/addrspace.h>
16#include <asm/bootinfo.h> 17#include <asm/bootinfo.h>
17#include <asm/fw/fw.h> 18#include <asm/fw/fw.h>
19#include <asm/mips-boards/generic.h>
20#include <asm/mips-boards/malta.h>
21#include <asm/mips-cm.h>
18#include <asm/page.h> 22#include <asm/page.h>
19 23
24#define ROCIT_REG_BASE 0x1f403000
25#define ROCIT_CONFIG_GEN1 (ROCIT_REG_BASE + 0x04)
26#define ROCIT_CONFIG_GEN1_MEMMAP_SHIFT 8
27#define ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
28
20static unsigned char fdt_buf[16 << 10] __initdata; 29static unsigned char fdt_buf[16 << 10] __initdata;
21 30
22/* determined physical memory size, not overridden by command line args */ 31/* determined physical memory size, not overridden by command line args */
23extern unsigned long physical_memsize; 32extern unsigned long physical_memsize;
24 33
25#define MAX_MEM_ARRAY_ENTRIES 1 34enum mem_map {
35 MEM_MAP_V1 = 0,
36 MEM_MAP_V2,
37};
38
39#define MAX_MEM_ARRAY_ENTRIES 2
26 40
27static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size) 41static __init int malta_scon(void)
42{
43 int scon = MIPS_REVISION_SCONID;
44
45 if (scon != MIPS_REVISION_SCON_OTHER)
46 return scon;
47
48 switch (MIPS_REVISION_CORID) {
49 case MIPS_REVISION_CORID_QED_RM5261:
50 case MIPS_REVISION_CORID_CORE_LV:
51 case MIPS_REVISION_CORID_CORE_FPGA:
52 case MIPS_REVISION_CORID_CORE_FPGAR2:
53 return MIPS_REVISION_SCON_GT64120;
54
55 case MIPS_REVISION_CORID_CORE_EMUL_BON:
56 case MIPS_REVISION_CORID_BONITO64:
57 case MIPS_REVISION_CORID_CORE_20K:
58 return MIPS_REVISION_SCON_BONITO;
59
60 case MIPS_REVISION_CORID_CORE_MSC:
61 case MIPS_REVISION_CORID_CORE_FPGA2:
62 case MIPS_REVISION_CORID_CORE_24K:
63 return MIPS_REVISION_SCON_SOCIT;
64
65 case MIPS_REVISION_CORID_CORE_FPGA3:
66 case MIPS_REVISION_CORID_CORE_FPGA4:
67 case MIPS_REVISION_CORID_CORE_FPGA5:
68 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
69 default:
70 return MIPS_REVISION_SCON_ROCIT;
71 }
72}
73
74static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size,
75 enum mem_map map)
28{ 76{
29 unsigned long size_preio; 77 unsigned long size_preio;
30 unsigned entries; 78 unsigned entries;
@@ -39,11 +87,47 @@ static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
39 * DDR but limits it to 2GB. 87 * DDR but limits it to 2GB.
40 */ 88 */
41 mem_array[1] = cpu_to_be32(size); 89 mem_array[1] = cpu_to_be32(size);
90 goto done;
91 }
92
93 size_preio = min_t(unsigned long, size, SZ_256M);
94 mem_array[1] = cpu_to_be32(size_preio);
95 size -= size_preio;
96 if (!size)
97 goto done;
98
99 if (map == MEM_MAP_V2) {
100 /*
101 * We have a flat 32 bit physical memory map with DDR filling
102 * all 4GB of the memory map, apart from the I/O region which
103 * obscures 256MB from 0x10000000-0x1fffffff.
104 *
105 * Therefore we discard the 256MB behind the I/O region.
106 */
107 if (size <= SZ_256M)
108 goto done;
109 size -= SZ_256M;
110
111 /* Make use of the memory following the I/O region */
112 entries++;
113 mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_512M);
114 mem_array[3] = cpu_to_be32(size);
42 } else { 115 } else {
43 size_preio = min_t(unsigned long, size, SZ_256M); 116 /*
44 mem_array[1] = cpu_to_be32(size_preio); 117 * We have a 32 bit physical memory map with a 2GB DDR region
118 * aliased in the upper & lower halves of it. The I/O region
119 * obscures 256MB from 0x10000000-0x1fffffff in the low alias
120 * but the DDR it obscures is accessible via the high alias.
121 *
122 * Simply access everything beyond the lowest 256MB of DDR using
123 * the high alias.
124 */
125 entries++;
126 mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_2G + SZ_256M);
127 mem_array[3] = cpu_to_be32(size);
45 } 128 }
46 129
130done:
47 BUG_ON(entries > MAX_MEM_ARRAY_ENTRIES); 131 BUG_ON(entries > MAX_MEM_ARRAY_ENTRIES);
48 return entries; 132 return entries;
49} 133}
@@ -54,6 +138,8 @@ static void __init append_memory(void *fdt, int root_off)
54 unsigned long memsize; 138 unsigned long memsize;
55 unsigned mem_entries; 139 unsigned mem_entries;
56 int i, err, mem_off; 140 int i, err, mem_off;
141 enum mem_map mem_map;
142 u32 config;
57 char *var, param_name[10], *var_names[] = { 143 char *var, param_name[10], *var_names[] = {
58 "ememsize", "memsize", 144 "ememsize", "memsize",
59 }; 145 };
@@ -106,6 +192,20 @@ static void __init append_memory(void *fdt, int root_off)
106 /* if the user says there's more RAM than we thought, believe them */ 192 /* if the user says there's more RAM than we thought, believe them */
107 physical_memsize = max_t(unsigned long, physical_memsize, memsize); 193 physical_memsize = max_t(unsigned long, physical_memsize, memsize);
108 194
195 /* detect the memory map in use */
196 if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
197 /* ROCit has a register indicating the memory map in use */
198 config = readl((void __iomem *)CKSEG1ADDR(ROCIT_CONFIG_GEN1));
199 mem_map = config & ROCIT_CONFIG_GEN1_MEMMAP_MASK;
200 mem_map >>= ROCIT_CONFIG_GEN1_MEMMAP_SHIFT;
201 } else {
202 /* if not using ROCit, presume the v1 memory map */
203 mem_map = MEM_MAP_V1;
204 }
205 if (mem_map > MEM_MAP_V2)
206 panic("Unsupported physical memory map v%u detected",
207 (unsigned int)mem_map);
208
109 /* append memory to the DT */ 209 /* append memory to the DT */
110 mem_off = fdt_add_subnode(fdt, root_off, "memory"); 210 mem_off = fdt_add_subnode(fdt, root_off, "memory");
111 if (mem_off < 0) 211 if (mem_off < 0)
@@ -115,19 +215,93 @@ static void __init append_memory(void *fdt, int root_off)
115 if (err) 215 if (err)
116 panic("Unable to set memory node device_type: %d", err); 216 panic("Unable to set memory node device_type: %d", err);
117 217
118 mem_entries = gen_fdt_mem_array(mem_array, physical_memsize); 218 mem_entries = gen_fdt_mem_array(mem_array, physical_memsize, mem_map);
119 err = fdt_setprop(fdt, mem_off, "reg", mem_array, 219 err = fdt_setprop(fdt, mem_off, "reg", mem_array,
120 mem_entries * 2 * sizeof(mem_array[0])); 220 mem_entries * 2 * sizeof(mem_array[0]));
121 if (err) 221 if (err)
122 panic("Unable to set memory regs property: %d", err); 222 panic("Unable to set memory regs property: %d", err);
123 223
124 mem_entries = gen_fdt_mem_array(mem_array, memsize); 224 mem_entries = gen_fdt_mem_array(mem_array, memsize, mem_map);
125 err = fdt_setprop(fdt, mem_off, "linux,usable-memory", mem_array, 225 err = fdt_setprop(fdt, mem_off, "linux,usable-memory", mem_array,
126 mem_entries * 2 * sizeof(mem_array[0])); 226 mem_entries * 2 * sizeof(mem_array[0]));
127 if (err) 227 if (err)
128 panic("Unable to set linux,usable-memory property: %d", err); 228 panic("Unable to set linux,usable-memory property: %d", err);
129} 229}
130 230
231static void __init remove_gic(void *fdt)
232{
233 int err, gic_off, i8259_off, cpu_off;
234 void __iomem *biu_base;
235 uint32_t cpu_phandle, sc_cfg;
236
237 /* if we have a CM which reports a GIC is present, leave the DT alone */
238 err = mips_cm_probe();
239 if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
240 return;
241
242 if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
243 /*
244 * On systems using the RocIT system controller a GIC may be
245 * present without a CM. Detect whether that is the case.
246 */
247 biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
248 MSC01_BIU_ADDRSPACE_SZ);
249 sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
250 if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) {
251 /* enable the GIC at the system controller level */
252 sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF);
253 __raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
254 return;
255 }
256 }
257
258 gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
259 if (gic_off < 0) {
260 pr_warn("malta-dtshim: unable to find DT GIC node: %d\n",
261 gic_off);
262 return;
263 }
264
265 err = fdt_nop_node(fdt, gic_off);
266 if (err)
267 pr_warn("malta-dtshim: unable to nop GIC node\n");
268
269 i8259_off = fdt_node_offset_by_compatible(fdt, -1, "intel,i8259");
270 if (i8259_off < 0) {
271 pr_warn("malta-dtshim: unable to find DT i8259 node: %d\n",
272 i8259_off);
273 return;
274 }
275
276 cpu_off = fdt_node_offset_by_compatible(fdt, -1,
277 "mti,cpu-interrupt-controller");
278 if (cpu_off < 0) {
279 pr_warn("malta-dtshim: unable to find CPU intc node: %d\n",
280 cpu_off);
281 return;
282 }
283
284 cpu_phandle = fdt_get_phandle(fdt, cpu_off);
285 if (!cpu_phandle) {
286 pr_warn("malta-dtshim: unable to get CPU intc phandle\n");
287 return;
288 }
289
290 err = fdt_setprop_u32(fdt, i8259_off, "interrupt-parent", cpu_phandle);
291 if (err) {
292 pr_warn("malta-dtshim: unable to set i8259 interrupt-parent: %d\n",
293 err);
294 return;
295 }
296
297 err = fdt_setprop_u32(fdt, i8259_off, "interrupts", 2);
298 if (err) {
299 pr_warn("malta-dtshim: unable to set i8259 interrupts: %d\n",
300 err);
301 return;
302 }
303}
304
131void __init *malta_dt_shim(void *fdt) 305void __init *malta_dt_shim(void *fdt)
132{ 306{
133 int root_off, len, err; 307 int root_off, len, err;
@@ -153,6 +327,7 @@ void __init *malta_dt_shim(void *fdt)
153 return fdt; 327 return fdt;
154 328
155 append_memory(fdt_buf, root_off); 329 append_memory(fdt_buf, root_off);
330 remove_gic(fdt_buf);
156 331
157 err = fdt_pack(fdt_buf); 332 err = fdt_pack(fdt_buf);
158 if (err) 333 if (err)
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index dc2c5214809d..0f3b881a3190 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/string.h> 15#include <linux/string.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/pci_regs.h>
17#include <linux/serial_core.h> 18#include <linux/serial_core.h>
18 19
19#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
@@ -242,23 +243,19 @@ mips_pci_controller:
242 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 243 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
243 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 244 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
244#endif 245#endif
245#ifndef CONFIG_EVA 246
246 /* Fix up target memory mapping. */
247 MSC_READ(MSC01_PCI_BAR0, mask);
248 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
249#else
250 /* 247 /*
251 * Setup the Malta max (2GB) memory for PCI DMA in host bridge 248 * Setup the Malta max (2GB) memory for PCI DMA in host bridge
252 * in transparent addressing mode, starting from 0x80000000. 249 * in transparent addressing mode.
253 */ 250 */
254 mask = PHYS_OFFSET | (1<<3); 251 mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
255 MSC_WRITE(MSC01_PCI_BAR0, mask); 252 MSC_WRITE(MSC01_PCI_BAR0, mask);
256
257 mask = PHYS_OFFSET;
258 MSC_WRITE(MSC01_PCI_HEAD4, mask); 253 MSC_WRITE(MSC01_PCI_HEAD4, mask);
254
255 mask &= MSC01_PCI_BAR0_SIZE_MSK;
259 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); 256 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
260 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); 257 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
261#endif 258
262 /* Don't handle target retries indefinitely. */ 259 /* Don't handle target retries indefinitely. */
263 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 260 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
264 MSC01_PCI_CFG_MAXRTRY_MSK) 261 MSC01_PCI_CFG_MAXRTRY_MSK)
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index c6a6c7afddab..cb675ec6f283 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -14,11 +14,13 @@
14 */ 14 */
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/irqchip.h>
17#include <linux/sched.h> 18#include <linux/sched.h>
18#include <linux/smp.h> 19#include <linux/smp.h>
19#include <linux/interrupt.h> 20#include <linux/interrupt.h>
20#include <linux/io.h> 21#include <linux/io.h>
21#include <linux/irqchip/mips-gic.h> 22#include <linux/irqchip/mips-gic.h>
23#include <linux/of_irq.h>
22#include <linux/kernel_stat.h> 24#include <linux/kernel_stat.h>
23#include <linux/kernel.h> 25#include <linux/kernel.h>
24#include <linux/random.h> 26#include <linux/random.h>
@@ -37,10 +39,6 @@
37#include <asm/setup.h> 39#include <asm/setup.h>
38#include <asm/rtlx.h> 40#include <asm/rtlx.h>
39 41
40static void __iomem *_msc01_biu_base;
41
42static DEFINE_RAW_SPINLOCK(mips_irq_lock);
43
44static inline int mips_pcibios_iack(void) 42static inline int mips_pcibios_iack(void)
45{ 43{
46 int irq; 44 int irq;
@@ -85,49 +83,6 @@ static inline int mips_pcibios_iack(void)
85 return irq; 83 return irq;
86} 84}
87 85
88static inline int get_int(void)
89{
90 unsigned long flags;
91 int irq;
92 raw_spin_lock_irqsave(&mips_irq_lock, flags);
93
94 irq = mips_pcibios_iack();
95
96 /*
97 * The only way we can decide if an interrupt is spurious
98 * is by checking the 8259 registers. This needs a spinlock
99 * on an SMP system, so leave it up to the generic code...
100 */
101
102 raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
103
104 return irq;
105}
106
107static void malta_hw0_irqdispatch(void)
108{
109 int irq;
110
111 irq = get_int();
112 if (irq < 0) {
113 /* interrupt has already been cleared */
114 return;
115 }
116
117 do_IRQ(MALTA_INT_BASE + irq);
118
119#ifdef CONFIG_MIPS_VPE_APSP_API_MT
120 if (aprp_hook)
121 aprp_hook();
122#endif
123}
124
125static irqreturn_t i8259_handler(int irq, void *dev_id)
126{
127 malta_hw0_irqdispatch();
128 return IRQ_HANDLED;
129}
130
131static void corehi_irqdispatch(void) 86static void corehi_irqdispatch(void)
132{ 87{
133 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 88 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
@@ -240,12 +195,6 @@ static struct irqaction irq_call = {
240}; 195};
241#endif /* CONFIG_MIPS_MT_SMP */ 196#endif /* CONFIG_MIPS_MT_SMP */
242 197
243static struct irqaction i8259irq = {
244 .handler = i8259_handler,
245 .name = "XT-PIC cascade",
246 .flags = IRQF_NO_THREAD,
247};
248
249static struct irqaction corehi_irqaction = { 198static struct irqaction corehi_irqaction = {
250 .handler = corehi_handler, 199 .handler = corehi_handler,
251 .name = "CoreHi", 200 .name = "CoreHi",
@@ -281,28 +230,10 @@ void __init arch_init_ipiirq(int irq, struct irqaction *action)
281 230
282void __init arch_init_irq(void) 231void __init arch_init_irq(void)
283{ 232{
284 int corehi_irq, i8259_irq; 233 int corehi_irq;
285
286 init_i8259_irqs();
287 234
288 if (!cpu_has_veic) 235 i8259_set_poll(mips_pcibios_iack);
289 mips_cpu_irq_init(); 236 irqchip_init();
290
291 if (mips_cm_present()) {
292 write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
293 gic_present = 1;
294 } else {
295 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
296 _msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
297 MSC01_BIU_ADDRSPACE_SZ);
298 gic_present =
299 (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
300 MSC01_SC_CFG_GICPRES_MSK) >>
301 MSC01_SC_CFG_GICPRES_SHF;
302 }
303 }
304 if (gic_present)
305 pr_debug("GIC present\n");
306 237
307 switch (mips_revision_sconid) { 238 switch (mips_revision_sconid) {
308 case MIPS_REVISION_SCON_SOCIT: 239 case MIPS_REVISION_SCON_SOCIT:
@@ -330,18 +261,6 @@ void __init arch_init_irq(void)
330 } 261 }
331 262
332 if (gic_present) { 263 if (gic_present) {
333 int i;
334
335 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
336 MIPS_GIC_IRQ_BASE);
337 if (!mips_cm_present()) {
338 /* Enable the GIC */
339 i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
340 __raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
341 _msc01_biu_base + MSC01_SC_CFG_OFS);
342 pr_debug("GIC Enabled\n");
343 }
344 i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
345 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 264 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
346 } else { 265 } else {
347#if defined(CONFIG_MIPS_MT_SMP) 266#if defined(CONFIG_MIPS_MT_SMP)
@@ -361,33 +280,13 @@ void __init arch_init_irq(void)
361 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 280 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
362#endif 281#endif
363 if (cpu_has_veic) { 282 if (cpu_has_veic) {
364 set_vi_handler(MSC01E_INT_I8259A,
365 malta_hw0_irqdispatch);
366 set_vi_handler(MSC01E_INT_COREHI, 283 set_vi_handler(MSC01E_INT_COREHI,
367 corehi_irqdispatch); 284 corehi_irqdispatch);
368 i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
369 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; 285 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
370 } else { 286 } else {
371 i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
372 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 287 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
373 } 288 }
374 } 289 }
375 290
376 setup_irq(i8259_irq, &i8259irq);
377 setup_irq(corehi_irq, &corehi_irqaction); 291 setup_irq(corehi_irq, &corehi_irqaction);
378} 292}
379
380void malta_be_init(void)
381{
382 /* Could change CM error mask register. */
383}
384
385int malta_be_handler(struct pt_regs *regs, int is_fixup)
386{
387 /* This duplicates the handling in do_be which seems wrong */
388 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
389
390 mips_cm_error_report();
391
392 return retval;
393}
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index e1dd1c1d3fde..516e1233d771 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -23,14 +23,10 @@
23 */ 23 */
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/serial_8250.h> 25#include <linux/serial_8250.h>
26#include <linux/mc146818rtc.h>
27#include <linux/module.h> 26#include <linux/module.h>
28#include <linux/irq.h> 27#include <linux/irq.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mtd/physmap.h>
31#include <linux/platform_device.h> 28#include <linux/platform_device.h>
32#include <asm/mips-boards/maltaint.h> 29#include <asm/mips-boards/maltaint.h>
33#include <mtd/mtd-abi.h>
34 30
35#define SMC_PORT(base, int) \ 31#define SMC_PORT(base, int) \
36{ \ 32{ \
@@ -68,80 +64,13 @@ static struct platform_device malta_uart8250_device = {
68 }, 64 },
69}; 65};
70 66
71struct resource malta_rtc_resources[] = {
72 {
73 .start = RTC_PORT(0),
74 .end = RTC_PORT(7),
75 .flags = IORESOURCE_IO,
76 }, {
77 .start = RTC_IRQ,
78 .end = RTC_IRQ,
79 .flags = IORESOURCE_IRQ,
80 }
81};
82
83static struct platform_device malta_rtc_device = {
84 .name = "rtc_cmos",
85 .id = -1,
86 .resource = malta_rtc_resources,
87 .num_resources = ARRAY_SIZE(malta_rtc_resources),
88};
89
90static struct mtd_partition malta_mtd_partitions[] = {
91 {
92 .name = "YAMON",
93 .offset = 0x0,
94 .size = 0x100000,
95 .mask_flags = MTD_WRITEABLE
96 }, {
97 .name = "User FS",
98 .offset = 0x100000,
99 .size = 0x2e0000
100 }, {
101 .name = "Board Config",
102 .offset = 0x3e0000,
103 .size = 0x020000,
104 .mask_flags = MTD_WRITEABLE
105 }
106};
107
108static struct physmap_flash_data malta_flash_data = {
109 .width = 4,
110 .nr_parts = ARRAY_SIZE(malta_mtd_partitions),
111 .parts = malta_mtd_partitions
112};
113
114static struct resource malta_flash_resource = {
115 .start = 0x1e000000,
116 .end = 0x1e3fffff,
117 .flags = IORESOURCE_MEM
118};
119
120static struct platform_device malta_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &malta_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &malta_flash_resource,
128};
129
130static struct platform_device *malta_devices[] __initdata = { 67static struct platform_device *malta_devices[] __initdata = {
131 &malta_uart8250_device, 68 &malta_uart8250_device,
132 &malta_rtc_device,
133 &malta_flash_device,
134}; 69};
135 70
136static int __init malta_add_devices(void) 71static int __init malta_add_devices(void)
137{ 72{
138 int err; 73 return platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
139
140 err = platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
141 if (err)
142 return err;
143
144 return 0;
145} 74}
146 75
147device_initcall(malta_add_devices); 76device_initcall(malta_add_devices);
diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c
index 2fd2cc2c5034..dd6f62ad4417 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -8,38 +8,21 @@
8 */ 8 */
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/pm.h> 10#include <linux/pm.h>
11#include <linux/reboot.h>
11 12
12#include <asm/reboot.h> 13#include <asm/reboot.h>
13#include <asm/mach-malta/malta-pm.h> 14#include <asm/mach-malta/malta-pm.h>
14 15
15#define SOFTRES_REG 0x1f000500
16#define GORESET 0x42
17
18static void mips_machine_restart(char *command)
19{
20 unsigned int __iomem *softres_reg =
21 ioremap(SOFTRES_REG, sizeof(unsigned int));
22
23 __raw_writel(GORESET, softres_reg);
24}
25
26static void mips_machine_halt(void)
27{
28 while (true);
29}
30
31static void mips_machine_power_off(void) 16static void mips_machine_power_off(void)
32{ 17{
33 mips_pm_suspend(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF); 18 mips_pm_suspend(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF);
34 19
35 pr_info("Failed to power down, resetting\n"); 20 pr_info("Failed to power down, resetting\n");
36 mips_machine_restart(NULL); 21 machine_restart(NULL);
37} 22}
38 23
39static int __init mips_reboot_setup(void) 24static int __init mips_reboot_setup(void)
40{ 25{
41 _machine_restart = mips_machine_restart;
42 _machine_halt = mips_machine_halt;
43 pm_power_off = mips_machine_power_off; 26 pm_power_off = mips_machine_power_off;
44 27
45 return 0; 28 return 0;
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 7e7364b0501e..a01d5debfcaf 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -42,9 +42,6 @@
42#define ROCIT_CONFIG_GEN0 0x1f403000 42#define ROCIT_CONFIG_GEN0 0x1f403000
43#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7) 43#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
44 44
45extern void malta_be_init(void);
46extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
47
48static struct resource standard_io_resources[] = { 45static struct resource standard_io_resources[] = {
49 { 46 {
50 .name = "dma1", 47 .name = "dma1",
@@ -154,12 +151,12 @@ static void __init plat_setup_iocoherency(void)
154 * coherency instead. 151 * coherency instead.
155 */ 152 */
156 if (plat_enable_iocoherency()) { 153 if (plat_enable_iocoherency()) {
157 if (coherentio == 0) 154 if (coherentio == IO_COHERENCE_DISABLED)
158 pr_info("Hardware DMA cache coherency disabled\n"); 155 pr_info("Hardware DMA cache coherency disabled\n");
159 else 156 else
160 pr_info("Hardware DMA cache coherency enabled\n"); 157 pr_info("Hardware DMA cache coherency enabled\n");
161 } else { 158 } else {
162 if (coherentio == 1) 159 if (coherentio == IO_COHERENCE_ENABLED)
163 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); 160 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
164 else 161 else
165 pr_info("Software DMA cache coherency enabled\n"); 162 pr_info("Software DMA cache coherency enabled\n");
@@ -301,7 +298,4 @@ void __init plat_mem_setup(void)
301#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 298#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
302 screen_info_setup(); 299 screen_info_setup();
303#endif 300#endif
304
305 board_be_init = malta_be_init;
306 board_be_handler = malta_be_handler;
307} 301}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 09:40:20 -0500