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-rw-r--r--arch/mips/include/asm/cacheops.h106
1 files changed, 64 insertions, 42 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 06b9bc7ea14b..c3212ff26723 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -12,54 +12,76 @@
12#define __ASM_CACHEOPS_H 12#define __ASM_CACHEOPS_H
13 13
14/* 14/*
15 * Most cache ops are split into a 2 bit field identifying the cache, and a 3
16 * bit field identifying the cache operation.
17 */
18#define CacheOp_Cache 0x03
19#define CacheOp_Op 0x1c
20
21#define Cache_I 0x00
22#define Cache_D 0x01
23#define Cache_T 0x02
24#define Cache_S 0x03
25
26#define Index_Writeback_Inv 0x00
27#define Index_Load_Tag 0x04
28#define Index_Store_Tag 0x08
29#define Hit_Invalidate 0x10
30#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
31#define Hit_Writeback 0x18
32
33/*
15 * Cache Operations available on all MIPS processors with R4000-style caches 34 * Cache Operations available on all MIPS processors with R4000-style caches
16 */ 35 */
17#define Index_Invalidate_I 0x00 36#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
18#define Index_Writeback_Inv_D 0x01 37#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
19#define Index_Load_Tag_I 0x04 38#define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
20#define Index_Load_Tag_D 0x05 39#define Index_Load_Tag_D (Cache_D | Index_Load_Tag)
21#define Index_Store_Tag_I 0x08 40#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
22#define Index_Store_Tag_D 0x09 41#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
23#define Hit_Invalidate_I 0x10 42#define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
24#define Hit_Invalidate_D 0x11 43#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
25#define Hit_Writeback_Inv_D 0x15 44#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
26 45
27/* 46/*
28 * R4000-specific cacheops 47 * R4000-specific cacheops
29 */ 48 */
30#define Create_Dirty_Excl_D 0x0d 49#define Create_Dirty_Excl_D (Cache_D | 0x0c)
31#define Fill 0x14 50#define Fill (Cache_I | 0x14)
32#define Hit_Writeback_I 0x18 51#define Hit_Writeback_I (Cache_I | Hit_Writeback)
33#define Hit_Writeback_D 0x19 52#define Hit_Writeback_D (Cache_D | Hit_Writeback)
34 53
35/* 54/*
36 * R4000SC and R4400SC-specific cacheops 55 * R4000SC and R4400SC-specific cacheops
37 */ 56 */
38#define Index_Invalidate_SI 0x02 57#define Cache_SI 0x02
39#define Index_Writeback_Inv_SD 0x03 58#define Cache_SD 0x03
40#define Index_Load_Tag_SI 0x06 59
41#define Index_Load_Tag_SD 0x07 60#define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv)
42#define Index_Store_Tag_SI 0x0A 61#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv)
43#define Index_Store_Tag_SD 0x0B 62#define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag)
44#define Create_Dirty_Excl_SD 0x0f 63#define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag)
45#define Hit_Invalidate_SI 0x12 64#define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag)
46#define Hit_Invalidate_SD 0x13 65#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag)
47#define Hit_Writeback_Inv_SD 0x17 66#define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
48#define Hit_Writeback_SD 0x1b 67#define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate)
49#define Hit_Set_Virtual_SI 0x1e 68#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate)
50#define Hit_Set_Virtual_SD 0x1f 69#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv)
70#define Hit_Writeback_SD (Cache_SD | Hit_Writeback)
71#define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
72#define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
51 73
52/* 74/*
53 * R5000-specific cacheops 75 * R5000-specific cacheops
54 */ 76 */
55#define R5K_Page_Invalidate_S 0x17 77#define R5K_Page_Invalidate_S (Cache_S | 0x14)
56 78
57/* 79/*
58 * RM7000-specific cacheops 80 * RM7000-specific cacheops
59 */ 81 */
60#define Page_Invalidate_T 0x16 82#define Page_Invalidate_T (Cache_T | 0x14)
61#define Index_Store_Tag_T 0x0a 83#define Index_Store_Tag_T (Cache_T | Index_Store_Tag)
62#define Index_Load_Tag_T 0x06 84#define Index_Load_Tag_T (Cache_T | Index_Load_Tag)
63 85
64/* 86/*
65 * R10000-specific cacheops 87 * R10000-specific cacheops
@@ -67,22 +89,22 @@
67 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 89 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
68 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 90 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
69 */ 91 */
70#define Index_Writeback_Inv_S 0x03 92#define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
71#define Index_Load_Tag_S 0x07 93#define Index_Load_Tag_S (Cache_S | Index_Load_Tag)
72#define Index_Store_Tag_S 0x0B 94#define Index_Store_Tag_S (Cache_S | Index_Store_Tag)
73#define Hit_Invalidate_S 0x13 95#define Hit_Invalidate_S (Cache_S | Hit_Invalidate)
74#define Cache_Barrier 0x14 96#define Cache_Barrier 0x14
75#define Hit_Writeback_Inv_S 0x17 97#define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
76#define Index_Load_Data_I 0x18 98#define Index_Load_Data_I (Cache_I | 0x18)
77#define Index_Load_Data_D 0x19 99#define Index_Load_Data_D (Cache_D | 0x18)
78#define Index_Load_Data_S 0x1b 100#define Index_Load_Data_S (Cache_S | 0x18)
79#define Index_Store_Data_I 0x1c 101#define Index_Store_Data_I (Cache_I | 0x1c)
80#define Index_Store_Data_D 0x1d 102#define Index_Store_Data_D (Cache_D | 0x1c)
81#define Index_Store_Data_S 0x1f 103#define Index_Store_Data_S (Cache_S | 0x1c)
82 104
83/* 105/*
84 * Loongson2-specific cacheops 106 * Loongson2-specific cacheops
85 */ 107 */
86#define Hit_Invalidate_I_Loongson2 0x00 108#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
87 109
88#endif /* __ASM_CACHEOPS_H */ 110#endif /* __ASM_CACHEOPS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 13:57:43 -0400