Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.

  The executive summary:

   - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
   - Avoid useless rebuilds for zboot.
   - jz4780: Add NEMC, BCH and NAND device tree nodes
   - Initial support for the MicroChip's DT platform.  As all the device
     drivers are missing this is still of limited use.
   - Some Loongson3 cleanups.
   - The unavoidable whitespace polishing.
   - Reduce clock skew when synchronizing the CPU cycle counters on CPU
     startup.
   - Add MIPS R6 fixes.
   - Lots of cleanups across arch/mips as fallout from KVM.
   - Lots of minor fixes and changes for IEEE 754-2008 support to the
     FPU emulator / fp-assist software.
   - Minor Ralink, BCM47xx and bcm963xx platform support improvments.
   - Support SMP on BCM63168"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
  MIPS: zboot: Add support for serial debug using the PROM
  MIPS: zboot: Avoid useless rebuilds
  MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
  MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
  MIPS: bcm963xx: Update bcm_tag field image_sequence
  MIPS: bcm963xx: Move extended flash address to bcm_tag header file
  MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
  MIPS: bcm63xx: nvram: Use nvram structure definition from header file
  MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
  MAINTAINERS: Add KVM for MIPS entry
  MIPS: KVM: Add missing newline to kvm_err()
  MIPS: Move KVM specific opcodes into asm/inst.h
  MIPS: KVM: Use cacheops.h definitions
  MIPS: Break down cacheops.h definitions
  MIPS: Use EXCCODE_ constants with set_except_vector()
  MIPS: Update trap codes
  MIPS: Move Cause.ExcCode trap codes to mipsregs.h
  MIPS: KVM: Make kvm_mips_{init,exit}() static
  MIPS: KVM: Refactor added offsetof()s
  MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
  ...

1 files changed, 64 insertions, 42 deletions

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 06b9bc7ea14b..c3212ff26723 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -12,54 +12,76 @@
 #define __ASM_CACHEOPS_H
 
 /*
+ * Most cache ops are split into a 2 bit field identifying the cache, and a 3
+ * bit field identifying the cache operation.
+ */
+#define CacheOp_Cache                   0x03
+#define CacheOp_Op                      0x1c
+
+#define Cache_I                         0x00
+#define Cache_D                         0x01
+#define Cache_T                         0x02
+#define Cache_S                         0x03
+
+#define Index_Writeback_Inv             0x00
+#define Index_Load_Tag                  0x04
+#define Index_Store_Tag                 0x08
+#define Hit_Invalidate                  0x10
+#define Hit_Writeback_Inv               0x14    /* not with Cache_I though */
+#define Hit_Writeback                   0x18
+
+/*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
-#define Index_Invalidate_I              0x00
-#define Index_Writeback_Inv_D           0x01
-#define Index_Load_Tag_I                0x04
-#define Index_Load_Tag_D                0x05
-#define Index_Store_Tag_I               0x08
-#define Index_Store_Tag_D               0x09
-#define Hit_Invalidate_I                0x10
-#define Hit_Invalidate_D                0x11
-#define Hit_Writeback_Inv_D             0x15
+#define Index_Invalidate_I              (Cache_I | Index_Writeback_Inv)
+#define Index_Writeback_Inv_D           (Cache_D | Index_Writeback_Inv)
+#define Index_Load_Tag_I                (Cache_I | Index_Load_Tag)
+#define Index_Load_Tag_D                (Cache_D | Index_Load_Tag)
+#define Index_Store_Tag_I               (Cache_I | Index_Store_Tag)
+#define Index_Store_Tag_D               (Cache_D | Index_Store_Tag)
+#define Hit_Invalidate_I                (Cache_I | Hit_Invalidate)
+#define Hit_Invalidate_D                (Cache_D | Hit_Invalidate)
+#define Hit_Writeback_Inv_D             (Cache_D | Hit_Writeback_Inv)
 
 /*
  * R4000-specific cacheops
  */
-#define Create_Dirty_Excl_D             0x0d
-#define Fill                            0x14
-#define Hit_Writeback_I                 0x18
-#define Hit_Writeback_D                 0x19
+#define Create_Dirty_Excl_D             (Cache_D | 0x0c)
+#define Fill                            (Cache_I | 0x14)
+#define Hit_Writeback_I                 (Cache_I | Hit_Writeback)
+#define Hit_Writeback_D                 (Cache_D | Hit_Writeback)
 
 /*
  * R4000SC and R4400SC-specific cacheops
  */
-#define Index_Invalidate_SI             0x02
-#define Index_Writeback_Inv_SD          0x03
-#define Index_Load_Tag_SI               0x06
-#define Index_Load_Tag_SD               0x07
-#define Index_Store_Tag_SI              0x0A
-#define Index_Store_Tag_SD              0x0B
-#define Create_Dirty_Excl_SD            0x0f
-#define Hit_Invalidate_SI               0x12
-#define Hit_Invalidate_SD               0x13
-#define Hit_Writeback_Inv_SD            0x17
-#define Hit_Writeback_SD                0x1b
-#define Hit_Set_Virtual_SI              0x1e
-#define Hit_Set_Virtual_SD              0x1f
+#define Cache_SI                        0x02
+#define Cache_SD                        0x03
+
+#define Index_Invalidate_SI             (Cache_SI | Index_Writeback_Inv)
+#define Index_Writeback_Inv_SD          (Cache_SD | Index_Writeback_Inv)
+#define Index_Load_Tag_SI               (Cache_SI | Index_Load_Tag)
+#define Index_Load_Tag_SD               (Cache_SD | Index_Load_Tag)
+#define Index_Store_Tag_SI              (Cache_SI | Index_Store_Tag)
+#define Index_Store_Tag_SD              (Cache_SD | Index_Store_Tag)
+#define Create_Dirty_Excl_SD            (Cache_SD | 0x0c)
+#define Hit_Invalidate_SI               (Cache_SI | Hit_Invalidate)
+#define Hit_Invalidate_SD               (Cache_SD | Hit_Invalidate)
+#define Hit_Writeback_Inv_SD            (Cache_SD | Hit_Writeback_Inv)
+#define Hit_Writeback_SD                (Cache_SD | Hit_Writeback)
+#define Hit_Set_Virtual_SI              (Cache_SI | 0x1c)
+#define Hit_Set_Virtual_SD              (Cache_SD | 0x1c)
 
 /*
  * R5000-specific cacheops
  */
-#define R5K_Page_Invalidate_S           0x17
+#define R5K_Page_Invalidate_S           (Cache_S | 0x14)
 
 /*
  * RM7000-specific cacheops
  */
-#define Page_Invalidate_T               0x16
-#define Index_Store_Tag_T               0x0a
-#define Index_Load_Tag_T                0x06
+#define Page_Invalidate_T               (Cache_T | 0x14)
+#define Index_Store_Tag_T               (Cache_T | Index_Store_Tag)
+#define Index_Load_Tag_T                (Cache_T | Index_Load_Tag)
 
 /*
  * R10000-specific cacheops
@@ -67,22 +89,22 @@
  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  */
-#define Index_Writeback_Inv_S           0x03
-#define Index_Load_Tag_S                0x07
-#define Index_Store_Tag_S               0x0B
-#define Hit_Invalidate_S                0x13
+#define Index_Writeback_Inv_S           (Cache_S | Index_Writeback_Inv)
+#define Index_Load_Tag_S                (Cache_S | Index_Load_Tag)
+#define Index_Store_Tag_S               (Cache_S | Index_Store_Tag)
+#define Hit_Invalidate_S                (Cache_S | Hit_Invalidate)
 #define Cache_Barrier                   0x14
-#define Hit_Writeback_Inv_S             0x17
-#define Index_Load_Data_I               0x18
-#define Index_Load_Data_D               0x19
-#define Index_Load_Data_S               0x1b
-#define Index_Store_Data_I              0x1c
-#define Index_Store_Data_D              0x1d
-#define Index_Store_Data_S              0x1f
+#define Hit_Writeback_Inv_S             (Cache_S | Hit_Writeback_Inv)
+#define Index_Load_Data_I               (Cache_I | 0x18)
+#define Index_Load_Data_D               (Cache_D | 0x18)
+#define Index_Load_Data_S               (Cache_S | 0x18)
+#define Index_Store_Data_I              (Cache_I | 0x1c)
+#define Index_Store_Data_D              (Cache_D | 0x1c)
+#define Index_Store_Data_S              (Cache_S | 0x1c)
 
 /*
  * Loongson2-specific cacheops
  */
-#define Hit_Invalidate_I_Loongson2      0x00
+#define Hit_Invalidate_I_Loongson2      (Cache_I | 0x00)
 
 #endif  /* __ASM_CACHEOPS_H */