diff options
| -rw-r--r-- | drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 720721196b12..e2f2c04355b9 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | |||
| @@ -129,6 +129,7 @@ | |||
| 129 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | 129 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) |
| 130 | #define CMD_HDR_PIR_OFF 8 | 130 | #define CMD_HDR_PIR_OFF 8 |
| 131 | #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) | 131 | #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) |
| 132 | #define SERDES_CFG (PORT_BASE + 0x1c) | ||
| 132 | #define SL_CFG (PORT_BASE + 0x84) | 133 | #define SL_CFG (PORT_BASE + 0x84) |
| 133 | #define AIP_LIMIT (PORT_BASE + 0x90) | 134 | #define AIP_LIMIT (PORT_BASE + 0x90) |
| 134 | #define SL_CONTROL (PORT_BASE + 0x94) | 135 | #define SL_CONTROL (PORT_BASE + 0x94) |
| @@ -525,6 +526,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) | |||
| 525 | } | 526 | } |
| 526 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, | 527 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, |
| 527 | prog_phy_link_rate); | 528 | prog_phy_link_rate); |
| 529 | hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); | ||
| 528 | hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); | 530 | hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); |
| 529 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); | 531 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); |
| 530 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); | 532 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); |
