scsi: hisi_sas: Change SERDES_CFG init value to increase reliability of HiLink

With default value of register SERDES_CFG, the link is not stable for some
special disks when running IO. According to HW guys' suggestion, need to
make the bit10~19 value of register SERDES_CFG the max value to increase
the reliability of the HiLink.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Reviewed-by: Yupeng Zhou <zhouyupeng1@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 720721196b12..e2f2c04355b9 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -129,6 +129,7 @@
 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 #define CMD_HDR_PIR_OFF                 8
 #define CMD_HDR_PIR_MSK                 (0x1 << CMD_HDR_PIR_OFF)
+#define SERDES_CFG                      (PORT_BASE + 0x1c)
 #define SL_CFG                          (PORT_BASE + 0x84)
 #define AIP_LIMIT                       (PORT_BASE + 0x90)
 #define SL_CONTROL                      (PORT_BASE + 0x94)
@@ -525,6 +526,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
                 }
                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
                         prog_phy_link_rate);
+                hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
                 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);