aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/i915/gvt/vgpu.c4
-rw-r--r--drivers/gpu/drm/i915/i915_cmd_parser.c2
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c16
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c18
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h29
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c14
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_fence_reg.c10
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c6
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c7
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c18
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c24
-rw-r--r--drivers/gpu/drm/i915/i915_perf.c4
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c12
-rw-r--r--drivers/gpu/drm/i915/intel_atomic.c2
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c2
-rw-r--r--drivers/gpu/drm/i915/intel_cdclk.c10
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c6
-rw-r--r--drivers/gpu/drm/i915/intel_device_info.c14
-rw-r--r--drivers/gpu/drm/i915/intel_display.c74
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c24
-rw-r--r--drivers/gpu/drm/i915/intel_engine_cs.c4
-rw-r--r--drivers/gpu/drm/i915/intel_fbc.c22
-rw-r--r--drivers/gpu/drm/i915/intel_fifo_underrun.c6
-rw-r--r--drivers/gpu/drm/i915/intel_guc_fw.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hangcheck.c2
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c4
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c4
-rw-r--r--drivers/gpu/drm/i915/intel_mocs.c2
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c10
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c8
-rw-r--r--drivers/gpu/drm/i915/intel_pipe_crc.c8
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c58
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c4
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c28
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h4
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c4
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c6
-rw-r--r--drivers/gpu/drm/i915/intel_uc.c2
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c18
-rw-r--r--drivers/gpu/drm/i915/intel_wopcm.c4
-rw-r--r--drivers/gpu/drm/i915/intel_workarounds.c4
44 files changed, 249 insertions, 261 deletions
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..e1c860f80eb0 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
148 gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, 148 gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
149 high_avail / vgpu_types[i].high_mm); 149 high_avail / vgpu_types[i].high_mm);
150 150
151 if (IS_GEN8(gvt->dev_priv)) 151 if (IS_GEN(gvt->dev_priv, 8))
152 sprintf(gvt->types[i].name, "GVTg_V4_%s", 152 sprintf(gvt->types[i].name, "GVTg_V4_%s",
153 vgpu_types[i].name); 153 vgpu_types[i].name);
154 else if (IS_GEN9(gvt->dev_priv)) 154 else if (IS_GEN(gvt->dev_priv, 9))
155 sprintf(gvt->types[i].name, "GVTg_V5_%s", 155 sprintf(gvt->types[i].name, "GVTg_V5_%s",
156 vgpu_types[i].name); 156 vgpu_types[i].name);
157 157
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..33e8eed64423 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
865 int cmd_table_count; 865 int cmd_table_count;
866 int ret; 866 int ret;
867 867
868 if (!IS_GEN7(engine->i915)) 868 if (!IS_GEN(engine->i915, 7))
869 return; 869 return;
870 870
871 switch (engine->id) { 871 switch (engine->id) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 40a61ef9aac1..2b52c91113b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1070,7 +1070,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1070 1070
1071 intel_runtime_pm_get(dev_priv); 1071 intel_runtime_pm_get(dev_priv);
1072 1072
1073 if (IS_GEN5(dev_priv)) { 1073 if (IS_GEN(dev_priv, 5)) {
1074 u16 rgvswctl = I915_READ16(MEMSWCTL); 1074 u16 rgvswctl = I915_READ16(MEMSWCTL);
1075 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 1075 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1076 1076
@@ -1791,7 +1791,7 @@ static int i915_emon_status(struct seq_file *m, void *unused)
1791 unsigned long temp, chipset, gfx; 1791 unsigned long temp, chipset, gfx;
1792 int ret; 1792 int ret;
1793 1793
1794 if (!IS_GEN5(dev_priv)) 1794 if (!IS_GEN(dev_priv, 5))
1795 return -ENODEV; 1795 return -ENODEV;
1796 1796
1797 intel_runtime_pm_get(dev_priv); 1797 intel_runtime_pm_get(dev_priv);
@@ -2040,7 +2040,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
2040 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 2040 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2041 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 2041 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2042 2042
2043 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { 2043 if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
2044 seq_printf(m, "DDC = 0x%08x\n", 2044 seq_printf(m, "DDC = 0x%08x\n",
2045 I915_READ(DCC)); 2045 I915_READ(DCC));
2046 seq_printf(m, "DDC2 = 0x%08x\n", 2046 seq_printf(m, "DDC2 = 0x%08x\n",
@@ -2125,12 +2125,12 @@ static void gen6_ppgtt_info(struct seq_file *m,
2125 struct intel_engine_cs *engine; 2125 struct intel_engine_cs *engine;
2126 enum intel_engine_id id; 2126 enum intel_engine_id id;
2127 2127
2128 if (IS_GEN6(dev_priv)) 2128 if (IS_GEN(dev_priv, 6))
2129 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 2129 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2130 2130
2131 for_each_engine(engine, dev_priv, id) { 2131 for_each_engine(engine, dev_priv, id) {
2132 seq_printf(m, "%s\n", engine->name); 2132 seq_printf(m, "%s\n", engine->name);
2133 if (IS_GEN7(dev_priv)) 2133 if (IS_GEN(dev_priv, 7))
2134 seq_printf(m, "GFX_MODE: 0x%08x\n", 2134 seq_printf(m, "GFX_MODE: 0x%08x\n",
2135 I915_READ(RING_MODE_GEN7(engine))); 2135 I915_READ(RING_MODE_GEN7(engine)));
2136 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", 2136 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
@@ -4274,7 +4274,7 @@ i915_cache_sharing_get(void *data, u64 *val)
4274 struct drm_i915_private *dev_priv = data; 4274 struct drm_i915_private *dev_priv = data;
4275 u32 snpcr; 4275 u32 snpcr;
4276 4276
4277 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 4277 if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
4278 return -ENODEV; 4278 return -ENODEV;
4279 4279
4280 intel_runtime_pm_get(dev_priv); 4280 intel_runtime_pm_get(dev_priv);
@@ -4294,7 +4294,7 @@ i915_cache_sharing_set(void *data, u64 val)
4294 struct drm_i915_private *dev_priv = data; 4294 struct drm_i915_private *dev_priv = data;
4295 u32 snpcr; 4295 u32 snpcr;
4296 4296
4297 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 4297 if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
4298 return -ENODEV; 4298 return -ENODEV;
4299 4299
4300 if (val > 3) 4300 if (val > 3)
@@ -4551,7 +4551,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
4551 cherryview_sseu_device_status(dev_priv, &sseu); 4551 cherryview_sseu_device_status(dev_priv, &sseu);
4552 } else if (IS_BROADWELL(dev_priv)) { 4552 } else if (IS_BROADWELL(dev_priv)) {
4553 broadwell_sseu_device_status(dev_priv, &sseu); 4553 broadwell_sseu_device_status(dev_priv, &sseu);
4554 } else if (IS_GEN9(dev_priv)) { 4554 } else if (IS_GEN(dev_priv, 9)) {
4555 gen9_sseu_device_status(dev_priv, &sseu); 4555 gen9_sseu_device_status(dev_priv, &sseu);
4556 } else if (INTEL_GEN(dev_priv) >= 10) { 4556 } else if (INTEL_GEN(dev_priv) >= 10) {
4557 gen10_sseu_device_status(dev_priv, &sseu); 4557 gen10_sseu_device_status(dev_priv, &sseu);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b310a897a4ad..77c0f97fe77c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -132,15 +132,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
132 switch (id) { 132 switch (id) {
133 case INTEL_PCH_IBX_DEVICE_ID_TYPE: 133 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
134 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 134 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
135 WARN_ON(!IS_GEN5(dev_priv)); 135 WARN_ON(!IS_GEN(dev_priv, 5));
136 return PCH_IBX; 136 return PCH_IBX;
137 case INTEL_PCH_CPT_DEVICE_ID_TYPE: 137 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
138 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 138 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
139 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); 139 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
140 return PCH_CPT; 140 return PCH_CPT;
141 case INTEL_PCH_PPT_DEVICE_ID_TYPE: 141 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
142 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 142 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
143 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); 143 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
144 /* PantherPoint is CPT compatible */ 144 /* PantherPoint is CPT compatible */
145 return PCH_CPT; 145 return PCH_CPT;
146 case INTEL_PCH_LPT_DEVICE_ID_TYPE: 146 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
@@ -217,9 +217,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
217 * make an educated guess as to which PCH is really there. 217 * make an educated guess as to which PCH is really there.
218 */ 218 */
219 219
220 if (IS_GEN5(dev_priv)) 220 if (IS_GEN(dev_priv, 5))
221 id = INTEL_PCH_IBX_DEVICE_ID_TYPE; 221 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
222 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 222 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
223 id = INTEL_PCH_CPT_DEVICE_ID_TYPE; 223 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
224 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) 224 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
225 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; 225 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
@@ -966,7 +966,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv)
966 int mmio_bar; 966 int mmio_bar;
967 int mmio_size; 967 int mmio_size;
968 968
969 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; 969 mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
970 /* 970 /*
971 * Before gen4, the registers and the GTT are behind different BARs. 971 * Before gen4, the registers and the GTT are behind different BARs.
972 * However, from gen4 onwards, the registers and the GTT are shared 972 * However, from gen4 onwards, the registers and the GTT are shared
@@ -1341,7 +1341,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
1341 /* Need to calculate bandwidth only for Gen9 */ 1341 /* Need to calculate bandwidth only for Gen9 */
1342 if (IS_BROXTON(dev_priv)) 1342 if (IS_BROXTON(dev_priv))
1343 ret = bxt_get_dram_info(dev_priv); 1343 ret = bxt_get_dram_info(dev_priv);
1344 else if (IS_GEN9(dev_priv)) 1344 else if (IS_GEN(dev_priv, 9))
1345 ret = skl_get_dram_info(dev_priv); 1345 ret = skl_get_dram_info(dev_priv);
1346 else 1346 else
1347 ret = skl_dram_get_channels_info(dev_priv); 1347 ret = skl_dram_get_channels_info(dev_priv);
@@ -1436,7 +1436,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1436 pci_set_master(pdev); 1436 pci_set_master(pdev);
1437 1437
1438 /* overlay on gen2 is broken and can't address above 1G */ 1438 /* overlay on gen2 is broken and can't address above 1G */
1439 if (IS_GEN2(dev_priv)) { 1439 if (IS_GEN(dev_priv, 2)) {
1440 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); 1440 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1441 if (ret) { 1441 if (ret) {
1442 DRM_ERROR("failed to set DMA mask\n"); 1442 DRM_ERROR("failed to set DMA mask\n");
@@ -1574,7 +1574,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
1574 acpi_video_register(); 1574 acpi_video_register();
1575 } 1575 }
1576 1576
1577 if (IS_GEN5(dev_priv)) 1577 if (IS_GEN(dev_priv, 5))
1578 intel_gpu_ips_init(dev_priv); 1578 intel_gpu_ips_init(dev_priv);
1579 1579
1580 intel_audio_init(dev_priv); 1580 intel_audio_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 031738d48aad..c34198f51b13 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2214,6 +2214,10 @@ intel_info(const struct drm_i915_private *dev_priv)
2214#define IS_GEN_RANGE(dev_priv, s, e) \ 2214#define IS_GEN_RANGE(dev_priv, s, e) \
2215 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) 2215 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2216 2216
2217#define IS_GEN(dev_priv, n) \
2218 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2219 (dev_priv)->info.gen == (n))
2220
2217/* 2221/*
2218 * Return true if revision is in range [since,until] inclusive. 2222 * Return true if revision is in range [since,until] inclusive.
2219 * 2223 *
@@ -2365,26 +2369,9 @@ intel_info(const struct drm_i915_private *dev_priv)
2365#define IS_ICL_REVID(p, since, until) \ 2369#define IS_ICL_REVID(p, since, until) \
2366 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 2370 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2367 2371
2368/*
2369 * The genX designation typically refers to the render engine, so render
2370 * capability related checks should use IS_GEN, while display and other checks
2371 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2372 * chips, etc.).
2373 */
2374#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2375#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2376#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2377#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2378#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2379#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2380#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2381#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2382#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2383#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2384
2385#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 2372#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2386#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) 2373#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2387#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) 2374#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2388 2375
2389#define ENGINE_MASK(id) BIT(id) 2376#define ENGINE_MASK(id) BIT(id)
2390#define RENDER_RING ENGINE_MASK(RCS) 2377#define RENDER_RING ENGINE_MASK(RCS)
@@ -2405,7 +2392,7 @@ intel_info(const struct drm_i915_private *dev_priv)
2405#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) 2392#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2406#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) 2393#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2407 2394
2408#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) 2395#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN(dev_priv, 7)
2409 2396
2410#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) 2397#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2411#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) 2398#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
@@ -2457,7 +2444,7 @@ intel_info(const struct drm_i915_private *dev_priv)
2457/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2444/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2458 * rows, which changed the alignment requirements and fence programming. 2445 * rows, which changed the alignment requirements and fence programming.
2459 */ 2446 */
2460#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ 2447#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2461 !(IS_I915G(dev_priv) || \ 2448 !(IS_I915G(dev_priv) || \
2462 IS_I915GM(dev_priv))) 2449 IS_I915GM(dev_priv)))
2463#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv) 2450#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d36a9755ad91..39ee67e01bb7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5226,15 +5226,15 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
5226 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | 5226 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
5227 DISP_TILE_SURFACE_SWIZZLING); 5227 DISP_TILE_SURFACE_SWIZZLING);
5228 5228
5229 if (IS_GEN5(dev_priv)) 5229 if (IS_GEN(dev_priv, 5))
5230 return; 5230 return;
5231 5231
5232 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); 5232 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
5233 if (IS_GEN6(dev_priv)) 5233 if (IS_GEN(dev_priv, 6))
5234 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); 5234 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
5235 else if (IS_GEN7(dev_priv)) 5235 else if (IS_GEN(dev_priv, 7))
5236 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); 5236 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
5237 else if (IS_GEN8(dev_priv)) 5237 else if (IS_GEN(dev_priv, 8))
5238 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); 5238 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
5239 else 5239 else
5240 BUG(); 5240 BUG();
@@ -5256,10 +5256,10 @@ static void init_unused_rings(struct drm_i915_private *dev_priv)
5256 init_unused_ring(dev_priv, SRB1_BASE); 5256 init_unused_ring(dev_priv, SRB1_BASE);
5257 init_unused_ring(dev_priv, SRB2_BASE); 5257 init_unused_ring(dev_priv, SRB2_BASE);
5258 init_unused_ring(dev_priv, SRB3_BASE); 5258 init_unused_ring(dev_priv, SRB3_BASE);
5259 } else if (IS_GEN2(dev_priv)) { 5259 } else if (IS_GEN(dev_priv, 2)) {
5260 init_unused_ring(dev_priv, SRB0_BASE); 5260 init_unused_ring(dev_priv, SRB0_BASE);
5261 init_unused_ring(dev_priv, SRB1_BASE); 5261 init_unused_ring(dev_priv, SRB1_BASE);
5262 } else if (IS_GEN3(dev_priv)) { 5262 } else if (IS_GEN(dev_priv, 3)) {
5263 init_unused_ring(dev_priv, PRB1_BASE); 5263 init_unused_ring(dev_priv, PRB1_BASE);
5264 init_unused_ring(dev_priv, PRB2_BASE); 5264 init_unused_ring(dev_priv, PRB2_BASE);
5265 } 5265 }
@@ -5583,7 +5583,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
5583 } 5583 }
5584 5584
5585 ret = i915_gem_init_scratch(dev_priv, 5585 ret = i915_gem_init_scratch(dev_priv,
5586 IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE); 5586 IS_GEN(dev_priv, 2) ? SZ_256K : PAGE_SIZE);
5587 if (ret) { 5587 if (ret) {
5588 GEM_BUG_ON(ret == -EIO); 5588 GEM_BUG_ON(ret == -EIO);
5589 goto err_ggtt; 5589 goto err_ggtt;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 371c07087095..014152e2bc68 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -311,7 +311,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
311 address_mode = INTEL_LEGACY_64B_CONTEXT; 311 address_mode = INTEL_LEGACY_64B_CONTEXT;
312 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; 312 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
313 313
314 if (IS_GEN8(i915)) 314 if (IS_GEN(i915, 8))
315 desc |= GEN8_CTX_L3LLC_COHERENT; 315 desc |= GEN8_CTX_L3LLC_COHERENT;
316 316
317 /* TODO: WaDisableLiteRestore when we start using semaphore 317 /* TODO: WaDisableLiteRestore when we start using semaphore
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1a1c04db6c80..844bd5ad87bc 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1380,7 +1380,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
1380 * batchbuffers. 1380 * batchbuffers.
1381 */ 1381 */
1382 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && 1382 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1383 IS_GEN6(eb->i915)) { 1383 IS_GEN(eb->i915, 6)) {
1384 err = i915_vma_bind(target, target->obj->cache_level, 1384 err = i915_vma_bind(target, target->obj->cache_level,
1385 PIN_GLOBAL); 1385 PIN_GLOBAL);
1386 if (WARN_ONCE(err, 1386 if (WARN_ONCE(err,
@@ -1893,7 +1893,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
1893 u32 *cs; 1893 u32 *cs;
1894 int i; 1894 int i;
1895 1895
1896 if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) { 1896 if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS) {
1897 DRM_DEBUG("sol reset is gen7/rcs only\n"); 1897 DRM_DEBUG("sol reset is gen7/rcs only\n");
1898 return -EINVAL; 1898 return -EINVAL;
1899 } 1899 }
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d548ac05ccd7..24df2e2a8fc1 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -193,9 +193,9 @@ static void fence_write(struct drm_i915_fence_reg *fence,
193 * and explicitly managed for internal users. 193 * and explicitly managed for internal users.
194 */ 194 */
195 195
196 if (IS_GEN2(fence->i915)) 196 if (IS_GEN(fence->i915, 2))
197 i830_write_fence_reg(fence, vma); 197 i830_write_fence_reg(fence, vma);
198 else if (IS_GEN3(fence->i915)) 198 else if (IS_GEN(fence->i915, 3))
199 i915_write_fence_reg(fence, vma); 199 i915_write_fence_reg(fence, vma);
200 else 200 else
201 i965_write_fence_reg(fence, vma); 201 i965_write_fence_reg(fence, vma);
@@ -596,13 +596,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
596 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 596 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
597 } 597 }
598 } 598 }
599 } else if (IS_GEN5(dev_priv)) { 599 } else if (IS_GEN(dev_priv, 5)) {
600 /* On Ironlake whatever DRAM config, GPU always do 600 /* On Ironlake whatever DRAM config, GPU always do
601 * same swizzling setup. 601 * same swizzling setup.
602 */ 602 */
603 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 603 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
604 swizzle_y = I915_BIT_6_SWIZZLE_9; 604 swizzle_y = I915_BIT_6_SWIZZLE_9;
605 } else if (IS_GEN2(dev_priv)) { 605 } else if (IS_GEN(dev_priv, 2)) {
606 /* As far as we know, the 865 doesn't have these bit 6 606 /* As far as we know, the 865 doesn't have these bit 6
607 * swizzling issues. 607 * swizzling issues.
608 */ 608 */
@@ -647,7 +647,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
647 } 647 }
648 648
649 /* check for L-shaped memory aka modified enhanced addressing */ 649 /* check for L-shaped memory aka modified enhanced addressing */
650 if (IS_GEN4(dev_priv) && 650 if (IS_GEN(dev_priv, 4) &&
651 !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { 651 !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
652 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 652 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
653 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 653 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 62bde517d383..6e31745f6156 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2193,9 +2193,9 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
2193{ 2193{
2194 gtt_write_workarounds(dev_priv); 2194 gtt_write_workarounds(dev_priv);
2195 2195
2196 if (IS_GEN6(dev_priv)) 2196 if (IS_GEN(dev_priv, 6))
2197 gen6_ppgtt_enable(dev_priv); 2197 gen6_ppgtt_enable(dev_priv);
2198 else if (IS_GEN7(dev_priv)) 2198 else if (IS_GEN(dev_priv, 7))
2199 gen7_ppgtt_enable(dev_priv); 2199 gen7_ppgtt_enable(dev_priv);
2200 2200
2201 return 0; 2201 return 0;
@@ -2277,7 +2277,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
2277 /* Query intel_iommu to see if we need the workaround. Presumably that 2277 /* Query intel_iommu to see if we need the workaround. Presumably that
2278 * was loaded first. 2278 * was loaded first.
2279 */ 2279 */
2280 return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); 2280 return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
2281} 2281}
2282 2282
2283static void gen6_check_faults(struct drm_i915_private *dev_priv) 2283static void gen6_check_faults(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f29a7ff7c362..2f756a97689a 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -102,7 +102,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
102 resource_size_t ggtt_start; 102 resource_size_t ggtt_start;
103 103
104 ggtt_start = I915_READ(PGTBL_CTL); 104 ggtt_start = I915_READ(PGTBL_CTL);
105 if (IS_GEN4(dev_priv)) 105 if (IS_GEN(dev_priv, 4))
106 ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | 106 ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
107 (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; 107 (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
108 else 108 else
@@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
156 * GEN3 firmware likes to smash pci bridges into the stolen 156 * GEN3 firmware likes to smash pci bridges into the stolen
157 * range. Apparently this works. 157 * range. Apparently this works.
158 */ 158 */
159 if (r == NULL && !IS_GEN3(dev_priv)) { 159 if (r == NULL && !IS_GEN(dev_priv, 3)) {
160 DRM_ERROR("conflict detected with stolen region: %pR\n", 160 DRM_ERROR("conflict detected with stolen region: %pR\n",
161 dsm); 161 dsm);
162 162
@@ -194,7 +194,8 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
194 * Whether ILK really reuses the ELK register for this is unclear. 194 * Whether ILK really reuses the ELK register for this is unclear.
195 * Let's see if we catch anyone with this supposedly enabled on ILK. 195 * Let's see if we catch anyone with this supposedly enabled on ILK.
196 */ 196 */
197 WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val); 197 WARN(IS_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n",
198 reg_val);
198 199
199 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) 200 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
200 return; 201 return;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index d9dc9df523b5..39319ff1679c 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -87,7 +87,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
87 } 87 }
88 88
89 /* Previous chips need a power-of-two fence region when tiling */ 89 /* Previous chips need a power-of-two fence region when tiling */
90 if (IS_GEN3(i915)) 90 if (IS_GEN(i915, 3))
91 ggtt_size = 1024*1024; 91 ggtt_size = 1024*1024;
92 else 92 else
93 ggtt_size = 512*1024; 93 ggtt_size = 512*1024;
@@ -162,7 +162,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
162 return false; 162 return false;
163 } 163 }
164 164
165 if (IS_GEN2(i915) || 165 if (IS_GEN(i915, 2) ||
166 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) 166 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
167 tile_width = 128; 167 tile_width = 128;
168 else 168 else
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3f9ce403c755..4477631d2636 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -735,7 +735,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
735 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 735 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
736 } 736 }
737 737
738 if (IS_GEN7(m->i915)) 738 if (IS_GEN(m->i915, 7))
739 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 739 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
740 740
741 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 741 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
@@ -1314,7 +1314,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
1314 if (!HWS_NEEDS_PHYSICAL(dev_priv)) { 1314 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1315 i915_reg_t mmio; 1315 i915_reg_t mmio;
1316 1316
1317 if (IS_GEN7(dev_priv)) { 1317 if (IS_GEN(dev_priv, 7)) {
1318 switch (engine->id) { 1318 switch (engine->id) {
1319 default: 1319 default:
1320 case RCS: 1320 case RCS:
@@ -1330,7 +1330,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
1330 mmio = VEBOX_HWS_PGA_GEN7; 1330 mmio = VEBOX_HWS_PGA_GEN7;
1331 break; 1331 break;
1332 } 1332 }
1333 } else if (IS_GEN6(engine->i915)) { 1333 } else if (IS_GEN(engine->i915, 6)) {
1334 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1334 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1335 } else { 1335 } else {
1336 /* XXX: gen8 returns to sanity */ 1336 /* XXX: gen8 returns to sanity */
@@ -1352,10 +1352,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
1352 1352
1353 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 1353 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1354 1354
1355 if (IS_GEN6(dev_priv)) 1355 if (IS_GEN(dev_priv, 6))
1356 ee->vm_info.pp_dir_base = 1356 ee->vm_info.pp_dir_base =
1357 I915_READ(RING_PP_DIR_BASE_READ(engine)); 1357 I915_READ(RING_PP_DIR_BASE_READ(engine));
1358 else if (IS_GEN7(dev_priv)) 1358 else if (IS_GEN(dev_priv, 7))
1359 ee->vm_info.pp_dir_base = 1359 ee->vm_info.pp_dir_base =
1360 I915_READ(RING_PP_DIR_BASE(engine)); 1360 I915_READ(RING_PP_DIR_BASE(engine));
1361 else if (INTEL_GEN(dev_priv) >= 8) 1361 else if (INTEL_GEN(dev_priv) >= 8)
@@ -1725,7 +1725,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
1725 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1725 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1726 } 1726 }
1727 1727
1728 if (IS_GEN7(dev_priv)) 1728 if (IS_GEN(dev_priv, 7))
1729 error->err_int = I915_READ(GEN7_ERR_INT); 1729 error->err_int = I915_READ(GEN7_ERR_INT);
1730 1730
1731 if (INTEL_GEN(dev_priv) >= 8) { 1731 if (INTEL_GEN(dev_priv) >= 8) {
@@ -1733,7 +1733,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
1733 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1733 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1734 } 1734 }
1735 1735
1736 if (IS_GEN6(dev_priv)) { 1736 if (IS_GEN(dev_priv, 6)) {
1737 error->forcewake = I915_READ_FW(FORCEWAKE); 1737 error->forcewake = I915_READ_FW(FORCEWAKE);
1738 error->gab_ctl = I915_READ(GAB_CTL); 1738 error->gab_ctl = I915_READ(GAB_CTL);
1739 error->gfx_mode = I915_READ(GFX_MODE); 1739 error->gfx_mode = I915_READ(GFX_MODE);
@@ -1753,7 +1753,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
1753 error->ccid = I915_READ(CCID); 1753 error->ccid = I915_READ(CCID);
1754 1754
1755 /* 3: Feature specific registers */ 1755 /* 3: Feature specific registers */
1756 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 1756 if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
1757 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1757 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1758 error->gac_eco = I915_READ(GAC_ECO_BITS); 1758 error->gac_eco = I915_READ(GAC_ECO_BITS);
1759 } 1759 }
@@ -1777,7 +1777,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
1777 error->ier = I915_READ(DEIER); 1777 error->ier = I915_READ(DEIER);
1778 error->gtier[0] = I915_READ(GTIER); 1778 error->gtier[0] = I915_READ(GTIER);
1779 error->ngtier = 1; 1779 error->ngtier = 1;
1780 } else if (IS_GEN2(dev_priv)) { 1780 } else if (IS_GEN(dev_priv, 2)) {
1781 error->ier = I915_READ16(IER); 1781 error->ier = I915_READ16(IER);
1782 } else if (!IS_VALLEYVIEW(dev_priv)) { 1782 } else if (!IS_VALLEYVIEW(dev_priv)) {
1783 error->ier = I915_READ(IER); 1783 error->ier = I915_READ(IER);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..e2dac9b5f4ce 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -950,7 +950,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
950 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 950 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
951 vtotal /= 2; 951 vtotal /= 2;
952 952
953 if (IS_GEN2(dev_priv)) 953 if (IS_GEN(dev_priv, 2))
954 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 954 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
955 else 955 else
956 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 956 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
@@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1030 if (stime) 1030 if (stime)
1031 *stime = ktime_get(); 1031 *stime = ktime_get();
1032 1032
1033 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { 1033 if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1034 /* No obvious pixelcount register. Only query vertical 1034 /* No obvious pixelcount register. Only query vertical
1035 * scanout position from Display scan line register. 1035 * scanout position from Display scan line register.
1036 */ 1036 */
@@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1090 else 1090 else
1091 position += vtotal - vbl_end; 1091 position += vtotal - vbl_end;
1092 1092
1093 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { 1093 if (IS_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
1094 *vpos = position; 1094 *vpos = position;
1095 *hpos = 0; 1095 *hpos = 0;
1096 } else { 1096 } else {
@@ -2547,7 +2547,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2547 I915_WRITE(SDEIIR, pch_iir); 2547 I915_WRITE(SDEIIR, pch_iir);
2548 } 2548 }
2549 2549
2550 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) 2550 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2551 ironlake_rps_change_irq_handler(dev_priv); 2551 ironlake_rps_change_irq_handler(dev_priv);
2552} 2552}
2553 2553
@@ -3243,7 +3243,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv)
3243{ 3243{
3244 u32 eir; 3244 u32 eir;
3245 3245
3246 if (!IS_GEN2(dev_priv)) 3246 if (!IS_GEN(dev_priv, 2))
3247 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); 3247 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
3248 3248
3249 if (INTEL_GEN(dev_priv) < 4) 3249 if (INTEL_GEN(dev_priv) < 4)
@@ -3586,11 +3586,11 @@ static void ironlake_irq_reset(struct drm_device *dev)
3586{ 3586{
3587 struct drm_i915_private *dev_priv = to_i915(dev); 3587 struct drm_i915_private *dev_priv = to_i915(dev);
3588 3588
3589 if (IS_GEN5(dev_priv)) 3589 if (IS_GEN(dev_priv, 5))
3590 I915_WRITE(HWSTAM, 0xffffffff); 3590 I915_WRITE(HWSTAM, 0xffffffff);
3591 3591
3592 GEN3_IRQ_RESET(DE); 3592 GEN3_IRQ_RESET(DE);
3593 if (IS_GEN7(dev_priv)) 3593 if (IS_GEN(dev_priv, 7))
3594 I915_WRITE(GEN7_ERR_INT, 0xffffffff); 3594 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3595 3595
3596 if (IS_HASWELL(dev_priv)) { 3596 if (IS_HASWELL(dev_priv)) {
@@ -4045,7 +4045,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
4045 } 4045 }
4046 4046
4047 gt_irqs |= GT_RENDER_USER_INTERRUPT; 4047 gt_irqs |= GT_RENDER_USER_INTERRUPT;
4048 if (IS_GEN5(dev_priv)) { 4048 if (IS_GEN(dev_priv, 5)) {
4049 gt_irqs |= ILK_BSD_USER_INTERRUPT; 4049 gt_irqs |= ILK_BSD_USER_INTERRUPT;
4050 } else { 4050 } else {
4051 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 4051 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
@@ -4836,7 +4836,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4836 if (INTEL_GEN(dev_priv) >= 8) 4836 if (INTEL_GEN(dev_priv) >= 8)
4837 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 4837 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4838 4838
4839 if (IS_GEN2(dev_priv)) { 4839 if (IS_GEN(dev_priv, 2)) {
4840 /* Gen2 doesn't have a hardware frame counter */ 4840 /* Gen2 doesn't have a hardware frame counter */
4841 dev->max_vblank_count = 0; 4841 dev->max_vblank_count = 0;
4842 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { 4842 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
@@ -4852,7 +4852,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4852 * Gen2 doesn't have a hardware frame counter and so depends on 4852 * Gen2 doesn't have a hardware frame counter and so depends on
4853 * vblank interrupts to produce sane vblank seuquence numbers. 4853 * vblank interrupts to produce sane vblank seuquence numbers.
4854 */ 4854 */
4855 if (!IS_GEN2(dev_priv)) 4855 if (!IS_GEN(dev_priv, 2))
4856 dev->vblank_disable_immediate = true; 4856 dev->vblank_disable_immediate = true;
4857 4857
4858 /* Most platforms treat the display irq block as an always-on 4858 /* Most platforms treat the display irq block as an always-on
@@ -4924,14 +4924,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4924 dev->driver->disable_vblank = ironlake_disable_vblank; 4924 dev->driver->disable_vblank = ironlake_disable_vblank;
4925 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; 4925 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4926 } else { 4926 } else {
4927 if (IS_GEN2(dev_priv)) { 4927 if (IS_GEN(dev_priv, 2)) {
4928 dev->driver->irq_preinstall = i8xx_irq_reset; 4928 dev->driver->irq_preinstall = i8xx_irq_reset;
4929 dev->driver->irq_postinstall = i8xx_irq_postinstall; 4929 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4930 dev->driver->irq_handler = i8xx_irq_handler; 4930 dev->driver->irq_handler = i8xx_irq_handler;
4931 dev->driver->irq_uninstall = i8xx_irq_reset; 4931 dev->driver->irq_uninstall = i8xx_irq_reset;
4932 dev->driver->enable_vblank = i8xx_enable_vblank; 4932 dev->driver->enable_vblank = i8xx_enable_vblank;
4933 dev->driver->disable_vblank = i8xx_disable_vblank; 4933 dev->driver->disable_vblank = i8xx_disable_vblank;
4934 } else if (IS_GEN3(dev_priv)) { 4934 } else if (IS_GEN(dev_priv, 3)) {
4935 dev->driver->irq_preinstall = i915_irq_reset; 4935 dev->driver->irq_preinstall = i915_irq_reset;
4936 dev->driver->irq_postinstall = i915_irq_postinstall; 4936 dev->driver->irq_postinstall = i915_irq_postinstall;
4937 dev->driver->irq_uninstall = i915_irq_reset; 4937 dev->driver->irq_uninstall = i915_irq_reset;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ad0095be435d..6c7992320443 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3415,7 +3415,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
3415 dev_priv->perf.oa.ops.read = gen8_oa_read; 3415 dev_priv->perf.oa.ops.read = gen8_oa_read;
3416 dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; 3416 dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
3417 3417
3418 if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) { 3418 if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) {
3419 dev_priv->perf.oa.ops.is_valid_b_counter_reg = 3419 dev_priv->perf.oa.ops.is_valid_b_counter_reg =
3420 gen7_is_valid_b_counter_addr; 3420 gen7_is_valid_b_counter_addr;
3421 dev_priv->perf.oa.ops.is_valid_mux_reg = 3421 dev_priv->perf.oa.ops.is_valid_mux_reg =
@@ -3431,7 +3431,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
3431 dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; 3431 dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
3432 dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; 3432 dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
3433 3433
3434 if (IS_GEN8(dev_priv)) { 3434 if (IS_GEN(dev_priv, 8)) {
3435 dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; 3435 dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
3436 dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; 3436 dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
3437 3437
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8f3aa4dc0c98..f40ba5e429e0 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -65,7 +65,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
65 65
66 i915_save_display(dev_priv); 66 i915_save_display(dev_priv);
67 67
68 if (IS_GEN4(dev_priv)) 68 if (IS_GEN(dev_priv, 4))
69 pci_read_config_word(pdev, GCDGMBUS, 69 pci_read_config_word(pdev, GCDGMBUS,
70 &dev_priv->regfile.saveGCDGMBUS); 70 &dev_priv->regfile.saveGCDGMBUS);
71 71
@@ -77,14 +77,14 @@ int i915_save_state(struct drm_i915_private *dev_priv)
77 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 77 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
78 78
79 /* Scratch space */ 79 /* Scratch space */
80 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { 80 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
81 for (i = 0; i < 7; i++) { 81 for (i = 0; i < 7; i++) {
82 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); 82 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
83 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 83 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
84 } 84 }
85 for (i = 0; i < 3; i++) 85 for (i = 0; i < 3; i++)
86 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); 86 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
87 } else if (IS_GEN2(dev_priv)) { 87 } else if (IS_GEN(dev_priv, 2)) {
88 for (i = 0; i < 7; i++) 88 for (i = 0; i < 7; i++)
89 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 89 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
90 } else if (HAS_GMCH_DISPLAY(dev_priv)) { 90 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
@@ -108,7 +108,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
108 108
109 mutex_lock(&dev_priv->drm.struct_mutex); 109 mutex_lock(&dev_priv->drm.struct_mutex);
110 110
111 if (IS_GEN4(dev_priv)) 111 if (IS_GEN(dev_priv, 4))
112 pci_write_config_word(pdev, GCDGMBUS, 112 pci_write_config_word(pdev, GCDGMBUS,
113 dev_priv->regfile.saveGCDGMBUS); 113 dev_priv->regfile.saveGCDGMBUS);
114 i915_restore_display(dev_priv); 114 i915_restore_display(dev_priv);
@@ -122,14 +122,14 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
122 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); 122 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
123 123
124 /* Scratch space */ 124 /* Scratch space */
125 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { 125 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
126 for (i = 0; i < 7; i++) { 126 for (i = 0; i < 7; i++) {
127 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); 127 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
128 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 128 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
129 } 129 }
130 for (i = 0; i < 3; i++) 130 for (i = 0; i < 3; i++)
131 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); 131 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
132 } else if (IS_GEN2(dev_priv)) { 132 } else if (IS_GEN(dev_priv, 2)) {
133 for (i = 0; i < 7; i++) 133 for (i = 0; i < 7; i++)
134 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 134 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
135 } else if (HAS_GMCH_DISPLAY(dev_priv)) { 135 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 8cb02f28d30c..fdfc7425e644 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -233,7 +233,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
233 if (plane_state && plane_state->base.fb && 233 if (plane_state && plane_state->base.fb &&
234 plane_state->base.fb->format->is_yuv && 234 plane_state->base.fb->format->is_yuv &&
235 plane_state->base.fb->format->num_planes > 1) { 235 plane_state->base.fb->format->num_planes > 1) {
236 if (IS_GEN9(dev_priv) && 236 if (IS_GEN(dev_priv, 9) &&
237 !IS_GEMINILAKE(dev_priv)) { 237 !IS_GEMINILAKE(dev_priv)) {
238 mode = SKL_PS_SCALER_MODE_NV12; 238 mode = SKL_PS_SCALER_MODE_NV12;
239 } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) { 239 } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index ae55a6865d5c..0571aa2846a7 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
758 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 758 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
759 u32 tmp; 759 u32 tmp;
760 760
761 if (!IS_GEN9(dev_priv)) 761 if (!IS_GEN(dev_priv, 9))
762 return; 762 return;
763 763
764 i915_audio_component_get_power(kdev); 764 i915_audio_component_get_power(kdev);
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 25e3aba9cded..2021e484a287 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2140{ 2140{
2141 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2141 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2142 return DIV_ROUND_UP(pixel_rate, 2); 2142 return DIV_ROUND_UP(pixel_rate, 2);
2143 else if (IS_GEN9(dev_priv) || 2143 else if (IS_GEN(dev_priv, 9) ||
2144 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2144 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2145 return pixel_rate; 2145 return pixel_rate;
2146 else if (IS_CHERRYVIEW(dev_priv)) 2146 else if (IS_CHERRYVIEW(dev_priv))
@@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2176 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { 2176 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2177 /* Display WA #1145: glk,cnl */ 2177 /* Display WA #1145: glk,cnl */
2178 min_cdclk = max(316800, min_cdclk); 2178 min_cdclk = max(316800, min_cdclk);
2179 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { 2179 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2180 /* Display WA #1144: skl,bxt */ 2180 /* Display WA #1144: skl,bxt */
2181 min_cdclk = max(432000, min_cdclk); 2181 min_cdclk = max(432000, min_cdclk);
2182 } 2182 }
@@ -2537,7 +2537,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2537 2537
2538 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2538 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2539 return 2 * max_cdclk_freq; 2539 return 2 * max_cdclk_freq;
2540 else if (IS_GEN9(dev_priv) || 2540 else if (IS_GEN(dev_priv, 9) ||
2541 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2541 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2542 return max_cdclk_freq; 2542 return max_cdclk_freq;
2543 else if (IS_CHERRYVIEW(dev_priv)) 2543 else if (IS_CHERRYVIEW(dev_priv))
@@ -2785,9 +2785,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2785 dev_priv->display.get_cdclk = hsw_get_cdclk; 2785 dev_priv->display.get_cdclk = hsw_get_cdclk;
2786 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 2786 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2787 dev_priv->display.get_cdclk = vlv_get_cdclk; 2787 dev_priv->display.get_cdclk = vlv_get_cdclk;
2788 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 2788 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2789 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 2789 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2790 else if (IS_GEN5(dev_priv)) 2790 else if (IS_GEN(dev_priv, 5))
2791 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; 2791 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2792 else if (IS_GM45(dev_priv)) 2792 else if (IS_GM45(dev_priv))
2793 dev_priv->display.get_cdclk = gm45_get_cdclk; 2793 dev_priv->display.get_cdclk = gm45_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 68f2fb89ece3..bf4fd739b68c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
322 * DAC limit supposedly 355 MHz. 322 * DAC limit supposedly 355 MHz.
323 */ 323 */
324 max_clock = 270000; 324 max_clock = 270000;
325 else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) 325 else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4))
326 max_clock = 400000; 326 max_clock = 400000;
327 else 327 else
328 max_clock = 350000; 328 max_clock = 350000;
@@ -666,7 +666,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
666 /* Set the border color to purple. */ 666 /* Set the border color to purple. */
667 I915_WRITE(bclrpat_reg, 0x500050); 667 I915_WRITE(bclrpat_reg, 0x500050);
668 668
669 if (!IS_GEN2(dev_priv)) { 669 if (!IS_GEN(dev_priv, 2)) {
670 uint32_t pipeconf = I915_READ(pipeconf_reg); 670 uint32_t pipeconf = I915_READ(pipeconf_reg);
671 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 671 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
672 POSTING_READ(pipeconf_reg); 672 POSTING_READ(pipeconf_reg);
@@ -981,7 +981,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
981 else 981 else
982 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 982 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
983 983
984 if (IS_GEN2(dev_priv)) 984 if (IS_GEN(dev_priv, 2))
985 connector->interlace_allowed = 0; 985 connector->interlace_allowed = 0;
986 else 986 else
987 connector->interlace_allowed = 1; 987 connector->interlace_allowed = 1;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index bd5c4d62c635..8627b9a6bff4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -748,7 +748,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
748 if (INTEL_GEN(dev_priv) >= 10) { 748 if (INTEL_GEN(dev_priv) >= 10) {
749 for_each_pipe(dev_priv, pipe) 749 for_each_pipe(dev_priv, pipe)
750 info->num_scalers[pipe] = 2; 750 info->num_scalers[pipe] = 2;
751 } else if (IS_GEN9(dev_priv)) { 751 } else if (IS_GEN(dev_priv, 9)) {
752 info->num_scalers[PIPE_A] = 2; 752 info->num_scalers[PIPE_A] = 2;
753 info->num_scalers[PIPE_B] = 2; 753 info->num_scalers[PIPE_B] = 2;
754 info->num_scalers[PIPE_C] = 1; 754 info->num_scalers[PIPE_C] = 1;
@@ -756,10 +756,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
756 756
757 BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); 757 BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
758 758
759 if (IS_GEN11(dev_priv)) 759 if (IS_GEN(dev_priv, 11))
760 for_each_pipe(dev_priv, pipe) 760 for_each_pipe(dev_priv, pipe)
761 info->num_sprites[pipe] = 6; 761 info->num_sprites[pipe] = 6;
762 else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) 762 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
763 for_each_pipe(dev_priv, pipe) 763 for_each_pipe(dev_priv, pipe)
764 info->num_sprites[pipe] = 3; 764 info->num_sprites[pipe] = 3;
765 else if (IS_BROXTON(dev_priv)) { 765 else if (IS_BROXTON(dev_priv)) {
@@ -787,7 +787,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
787 DRM_INFO("Display disabled (module parameter)\n"); 787 DRM_INFO("Display disabled (module parameter)\n");
788 info->num_pipes = 0; 788 info->num_pipes = 0;
789 } else if (HAS_DISPLAY(dev_priv) && 789 } else if (HAS_DISPLAY(dev_priv) &&
790 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && 790 (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) &&
791 HAS_PCH_SPLIT(dev_priv)) { 791 HAS_PCH_SPLIT(dev_priv)) {
792 u32 fuse_strap = I915_READ(FUSE_STRAP); 792 u32 fuse_strap = I915_READ(FUSE_STRAP);
793 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 793 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
@@ -851,14 +851,14 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
851 cherryview_sseu_info_init(dev_priv); 851 cherryview_sseu_info_init(dev_priv);
852 else if (IS_BROADWELL(dev_priv)) 852 else if (IS_BROADWELL(dev_priv))
853 broadwell_sseu_info_init(dev_priv); 853 broadwell_sseu_info_init(dev_priv);
854 else if (IS_GEN9(dev_priv)) 854 else if (IS_GEN(dev_priv, 9))
855 gen9_sseu_info_init(dev_priv); 855 gen9_sseu_info_init(dev_priv);
856 else if (IS_GEN10(dev_priv)) 856 else if (IS_GEN(dev_priv, 10))
857 gen10_sseu_info_init(dev_priv); 857 gen10_sseu_info_init(dev_priv);
858 else if (INTEL_GEN(dev_priv) >= 11) 858 else if (INTEL_GEN(dev_priv) >= 11)
859 gen11_sseu_info_init(dev_priv); 859 gen11_sseu_info_init(dev_priv);
860 860
861 if (IS_GEN6(dev_priv) && intel_vtd_active()) { 861 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
862 DRM_INFO("Disabling ppGTT for VT-d support\n"); 862 DRM_INFO("Disabling ppGTT for VT-d support\n");
863 info->ppgtt = INTEL_PPGTT_NONE; 863 info->ppgtt = INTEL_PPGTT_NONE;
864 } 864 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 13e5650b6f31..b9e8a9898983 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -984,7 +984,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
984 u32 line1, line2; 984 u32 line1, line2;
985 u32 line_mask; 985 u32 line_mask;
986 986
987 if (IS_GEN2(dev_priv)) 987 if (IS_GEN(dev_priv, 2))
988 line_mask = DSL_LINEMASK_GEN2; 988 line_mask = DSL_LINEMASK_GEN2;
989 else 989 else
990 line_mask = DSL_LINEMASK_GEN3; 990 line_mask = DSL_LINEMASK_GEN3;
@@ -1110,7 +1110,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110 u32 val; 1110 u32 val;
1111 1111
1112 /* ILK FDI PLL is always enabled */ 1112 /* ILK FDI PLL is always enabled */
1113 if (IS_GEN5(dev_priv)) 1113 if (IS_GEN(dev_priv, 5))
1114 return; 1114 return;
1115 1115
1116 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1116 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -1850,7 +1850,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1850 1850
1851static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) 1851static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1852{ 1852{
1853 return IS_GEN2(dev_priv) ? 2048 : 4096; 1853 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1854} 1854}
1855 1855
1856static unsigned int 1856static unsigned int
@@ -1863,7 +1863,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1863 case DRM_FORMAT_MOD_LINEAR: 1863 case DRM_FORMAT_MOD_LINEAR:
1864 return cpp; 1864 return cpp;
1865 case I915_FORMAT_MOD_X_TILED: 1865 case I915_FORMAT_MOD_X_TILED:
1866 if (IS_GEN2(dev_priv)) 1866 if (IS_GEN(dev_priv, 2))
1867 return 128; 1867 return 128;
1868 else 1868 else
1869 return 512; 1869 return 512;
@@ -1872,7 +1872,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1872 return 128; 1872 return 128;
1873 /* fall through */ 1873 /* fall through */
1874 case I915_FORMAT_MOD_Y_TILED: 1874 case I915_FORMAT_MOD_Y_TILED:
1875 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) 1875 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1876 return 128; 1876 return 128;
1877 else 1877 else
1878 return 512; 1878 return 512;
@@ -3193,8 +3193,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3193 3193
3194 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; 3194 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3195 3195
3196 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || 3196 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3197 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 3197 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3198 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 3198 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3199 3199
3200 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 3200 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -4120,7 +4120,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
4120 temp = I915_READ(reg); 4120 temp = I915_READ(reg);
4121 temp &= ~FDI_LINK_TRAIN_NONE; 4121 temp &= ~FDI_LINK_TRAIN_NONE;
4122 temp |= FDI_LINK_TRAIN_PATTERN_2; 4122 temp |= FDI_LINK_TRAIN_PATTERN_2;
4123 if (IS_GEN6(dev_priv)) { 4123 if (IS_GEN(dev_priv, 6)) {
4124 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 4124 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4125 /* SNB-B */ 4125 /* SNB-B */
4126 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 4126 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -4919,10 +4919,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4919 /* range checks */ 4919 /* range checks */
4920 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || 4920 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4921 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || 4921 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4922 (IS_GEN11(dev_priv) && 4922 (IS_GEN(dev_priv, 11) &&
4923 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || 4923 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4924 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || 4924 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4925 (!IS_GEN11(dev_priv) && 4925 (!IS_GEN(dev_priv, 11) &&
4926 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || 4926 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4927 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { 4927 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4928 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " 4928 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
@@ -5213,7 +5213,7 @@ intel_post_enable_primary(struct drm_crtc *crtc,
5213 * FIXME: Need to fix the logic to work when we turn off all planes 5213 * FIXME: Need to fix the logic to work when we turn off all planes
5214 * but leave the pipe running. 5214 * but leave the pipe running.
5215 */ 5215 */
5216 if (IS_GEN2(dev_priv)) 5216 if (IS_GEN(dev_priv, 2))
5217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 5217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5218 5218
5219 /* Underruns don't always raise interrupts, so check manually. */ 5219 /* Underruns don't always raise interrupts, so check manually. */
@@ -5234,7 +5234,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5234 * Gen2 reports pipe underruns whenever all planes are disabled. 5234 * Gen2 reports pipe underruns whenever all planes are disabled.
5235 * So disable underrun reporting before all the planes get disabled. 5235 * So disable underrun reporting before all the planes get disabled.
5236 */ 5236 */
5237 if (IS_GEN2(dev_priv)) 5237 if (IS_GEN(dev_priv, 2))
5238 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 5238 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5239 5239
5240 hsw_disable_ips(to_intel_crtc_state(crtc->state)); 5240 hsw_disable_ips(to_intel_crtc_state(crtc->state));
@@ -5292,7 +5292,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5292 return false; 5292 return false;
5293 5293
5294 /* WA Display #0827: Gen9:all */ 5294 /* WA Display #0827: Gen9:all */
5295 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) 5295 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5296 return true; 5296 return true;
5297 5297
5298 return false; 5298 return false;
@@ -5365,7 +5365,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5365 * Gen2 reports pipe underruns whenever all planes are disabled. 5365 * Gen2 reports pipe underruns whenever all planes are disabled.
5366 * So disable underrun reporting before all the planes get disabled. 5366 * So disable underrun reporting before all the planes get disabled.
5367 */ 5367 */
5368 if (IS_GEN2(dev_priv) && old_primary_state->visible && 5368 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5369 (modeset || !new_primary_state->base.visible)) 5369 (modeset || !new_primary_state->base.visible))
5370 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 5370 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5371 } 5371 }
@@ -6184,7 +6184,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6184 6184
6185 intel_crtc->active = true; 6185 intel_crtc->active = true;
6186 6186
6187 if (!IS_GEN2(dev_priv)) 6187 if (!IS_GEN(dev_priv, 2))
6188 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 6188 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6189 6189
6190 intel_encoders_pre_enable(crtc, pipe_config, old_state); 6190 intel_encoders_pre_enable(crtc, pipe_config, old_state);
@@ -6236,7 +6236,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6236 * On gen2 planes are double buffered but the pipe isn't, so we must 6236 * On gen2 planes are double buffered but the pipe isn't, so we must
6237 * wait for planes to fully turn off before disabling the pipe. 6237 * wait for planes to fully turn off before disabling the pipe.
6238 */ 6238 */
6239 if (IS_GEN2(dev_priv)) 6239 if (IS_GEN(dev_priv, 2))
6240 intel_wait_for_vblank(dev_priv, pipe); 6240 intel_wait_for_vblank(dev_priv, pipe);
6241 6241
6242 intel_encoders_disable(crtc, old_crtc_state, old_state); 6242 intel_encoders_disable(crtc, old_crtc_state, old_state);
@@ -6261,7 +6261,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6261 6261
6262 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); 6262 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6263 6263
6264 if (!IS_GEN2(dev_priv)) 6264 if (!IS_GEN(dev_priv, 2))
6265 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 6265 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6266 6266
6267 if (!dev_priv->display.initial_watermarks) 6267 if (!dev_priv->display.initial_watermarks)
@@ -6868,7 +6868,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
6868 * Strictly speaking some registers are available before 6868 * Strictly speaking some registers are available before
6869 * gen7, but we only support DRRS on gen7+ 6869 * gen7, but we only support DRRS on gen7+
6870 */ 6870 */
6871 return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); 6871 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
6872} 6872}
6873 6873
6874static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, 6874static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -9005,7 +9005,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9005 /* We currently do not free assignements of panel fitters on 9005 /* We currently do not free assignements of panel fitters on
9006 * ivb/hsw (since we don't use the higher upscaling modes which 9006 * ivb/hsw (since we don't use the higher upscaling modes which
9007 * differentiates them) so just WARN about this case for now. */ 9007 * differentiates them) so just WARN about this case for now. */
9008 if (IS_GEN7(dev_priv)) { 9008 if (IS_GEN(dev_priv, 7)) {
9009 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != 9009 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9010 PF_PIPE_SEL_IVB(crtc->pipe)); 9010 PF_PIPE_SEL_IVB(crtc->pipe));
9011 } 9011 }
@@ -9995,7 +9995,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 9995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9996 u32 cntl = 0; 9996 u32 cntl = 0;
9997 9997
9998 if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 9998 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
9999 cntl |= MCURSOR_TRICKLE_FEED_DISABLE; 9999 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10000 10000
10001 if (INTEL_GEN(dev_priv) <= 10) { 10001 if (INTEL_GEN(dev_priv) <= 10) {
@@ -10468,7 +10468,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
10468 return dev_priv->vbt.lvds_ssc_freq; 10468 return dev_priv->vbt.lvds_ssc_freq;
10469 else if (HAS_PCH_SPLIT(dev_priv)) 10469 else if (HAS_PCH_SPLIT(dev_priv))
10470 return 120000; 10470 return 120000;
10471 else if (!IS_GEN2(dev_priv)) 10471 else if (!IS_GEN(dev_priv, 2))
10472 return 96000; 10472 return 96000;
10473 else 10473 else
10474 return 48000; 10474 return 48000;
@@ -10501,7 +10501,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10501 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 10501 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10502 } 10502 }
10503 10503
10504 if (!IS_GEN2(dev_priv)) { 10504 if (!IS_GEN(dev_priv, 2)) {
10505 if (IS_PINEVIEW(dev_priv)) 10505 if (IS_PINEVIEW(dev_priv))
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 10507 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -10815,7 +10815,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
10815 * the w/a on all three platforms. 10815 * the w/a on all three platforms.
10816 */ 10816 */
10817 if (plane->id == PLANE_SPRITE0 && 10817 if (plane->id == PLANE_SPRITE0 &&
10818 (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) || 10818 (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6) ||
10819 IS_IVYBRIDGE(dev_priv)) && 10819 IS_IVYBRIDGE(dev_priv)) &&
10820 (turn_on || (!needs_scaling(old_plane_state) && 10820 (turn_on || (!needs_scaling(old_plane_state) &&
10821 needs_scaling(to_intel_plane_state(plane_state))))) 10821 needs_scaling(to_intel_plane_state(plane_state)))))
@@ -12373,7 +12373,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12373 * However if queried just before the start of vblank we'll get an 12373 * However if queried just before the start of vblank we'll get an
12374 * answer that's slightly in the future. 12374 * answer that's slightly in the future.
12375 */ 12375 */
12376 if (IS_GEN2(dev_priv)) { 12376 if (IS_GEN(dev_priv, 2)) {
12377 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 12377 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12378 int vtotal; 12378 int vtotal;
12379 12379
@@ -13573,7 +13573,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13573{ 13573{
13574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 13574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13575 13575
13576 if (!IS_GEN2(dev_priv)) 13576 if (!IS_GEN(dev_priv, 2))
13577 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 13577 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13578 13578
13579 if (crtc_state->has_pch_encoder) { 13579 if (crtc_state->has_pch_encoder) {
@@ -14180,7 +14180,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
14180 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 14180 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14181 return false; 14181 return false;
14182 14182
14183 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) 14183 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14184 return false; 14184 return false;
14185 14185
14186 return true; 14186 return true;
@@ -14392,7 +14392,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14392 } 14392 }
14393 14393
14394 vlv_dsi_init(dev_priv); 14394 vlv_dsi_init(dev_priv);
14395 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { 14395 } else if (!IS_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) {
14396 bool found = false; 14396 bool found = false;
14397 14397
14398 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { 14398 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
@@ -14426,7 +14426,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14426 14426
14427 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) 14427 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14428 intel_dp_init(dev_priv, DP_D, PORT_D); 14428 intel_dp_init(dev_priv, DP_D, PORT_D);
14429 } else if (IS_GEN2(dev_priv)) 14429 } else if (IS_GEN(dev_priv, 2))
14430 intel_dvo_init(dev_priv); 14430 intel_dvo_init(dev_priv);
14431 14431
14432 if (SUPPORTS_TV(dev_priv)) 14432 if (SUPPORTS_TV(dev_priv))
@@ -14624,7 +14624,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14624 * require the entire fb to accommodate that to avoid 14624 * require the entire fb to accommodate that to avoid
14625 * potential runtime errors at plane configuration time. 14625 * potential runtime errors at plane configuration time.
14626 */ 14626 */
14627 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && 14627 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
14628 is_ccs_modifier(fb->modifier)) 14628 is_ccs_modifier(fb->modifier))
14629 stride_alignment *= 4; 14629 stride_alignment *= 4;
14630 14630
@@ -14829,7 +14829,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14829 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; 14829 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14830 dev_priv->display.crtc_enable = i9xx_crtc_enable; 14830 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14831 dev_priv->display.crtc_disable = i9xx_crtc_disable; 14831 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14832 } else if (!IS_GEN2(dev_priv)) { 14832 } else if (!IS_GEN(dev_priv, 2)) {
14833 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 14833 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14834 dev_priv->display.get_initial_plane_config = 14834 dev_priv->display.get_initial_plane_config =
14835 i9xx_get_initial_plane_config; 14835 i9xx_get_initial_plane_config;
@@ -14845,9 +14845,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14845 dev_priv->display.crtc_disable = i9xx_crtc_disable; 14845 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14846 } 14846 }
14847 14847
14848 if (IS_GEN5(dev_priv)) { 14848 if (IS_GEN(dev_priv, 5)) {
14849 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 14849 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14850 } else if (IS_GEN6(dev_priv)) { 14850 } else if (IS_GEN(dev_priv, 6)) {
14851 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 14851 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14852 } else if (IS_IVYBRIDGE(dev_priv)) { 14852 } else if (IS_IVYBRIDGE(dev_priv)) {
14853 /* FIXME: detect B0+ stepping and use auto training */ 14853 /* FIXME: detect B0+ stepping and use auto training */
@@ -14979,12 +14979,12 @@ fail:
14979 14979
14980static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) 14980static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14981{ 14981{
14982 if (IS_GEN5(dev_priv)) { 14982 if (IS_GEN(dev_priv, 5)) {
14983 u32 fdi_pll_clk = 14983 u32 fdi_pll_clk =
14984 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; 14984 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14985 14985
14986 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; 14986 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14987 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 14987 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
14988 dev_priv->fdi_pll_freq = 270000; 14988 dev_priv->fdi_pll_freq = 270000;
14989 } else { 14989 } else {
14990 return; 14990 return;
@@ -15100,10 +15100,10 @@ int intel_modeset_init(struct drm_device *dev)
15100 } 15100 }
15101 15101
15102 /* maximum framebuffer dimensions */ 15102 /* maximum framebuffer dimensions */
15103 if (IS_GEN2(dev_priv)) { 15103 if (IS_GEN(dev_priv, 2)) {
15104 dev->mode_config.max_width = 2048; 15104 dev->mode_config.max_width = 2048;
15105 dev->mode_config.max_height = 2048; 15105 dev->mode_config.max_height = 2048;
15106 } else if (IS_GEN3(dev_priv)) { 15106 } else if (IS_GEN(dev_priv, 3)) {
15107 dev->mode_config.max_width = 4096; 15107 dev->mode_config.max_width = 4096;
15108 dev->mode_config.max_height = 4096; 15108 dev->mode_config.max_height = 4096;
15109 } else { 15109 } else {
@@ -15114,7 +15114,7 @@ int intel_modeset_init(struct drm_device *dev)
15114 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { 15114 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15115 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; 15115 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15116 dev->mode_config.cursor_height = 1023; 15116 dev->mode_config.cursor_height = 1023;
15117 } else if (IS_GEN2(dev_priv)) { 15117 } else if (IS_GEN(dev_priv, 2)) {
15118 dev->mode_config.cursor_width = 64; 15118 dev->mode_config.cursor_width = 64;
15119 dev->mode_config.cursor_height = 64; 15119 dev->mode_config.cursor_height = 64;
15120 } else { 15120 } else {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e94faa0a42eb..b3138abd3321 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -344,7 +344,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
344 if (INTEL_GEN(dev_priv) >= 10) { 344 if (INTEL_GEN(dev_priv) >= 10) {
345 source_rates = cnl_rates; 345 source_rates = cnl_rates;
346 size = ARRAY_SIZE(cnl_rates); 346 size = ARRAY_SIZE(cnl_rates);
347 if (IS_GEN10(dev_priv)) 347 if (IS_GEN(dev_priv, 10))
348 max_rate = cnl_max_source_rate(intel_dp); 348 max_rate = cnl_max_source_rate(intel_dp);
349 else 349 else
350 max_rate = icl_max_source_rate(intel_dp); 350 max_rate = icl_max_source_rate(intel_dp);
@@ -1128,7 +1128,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1128 to_i915(intel_dig_port->base.base.dev); 1128 to_i915(intel_dig_port->base.base.dev);
1129 uint32_t precharge, timeout; 1129 uint32_t precharge, timeout;
1130 1130
1131 if (IS_GEN6(dev_priv)) 1131 if (IS_GEN(dev_priv, 6))
1132 precharge = 3; 1132 precharge = 3;
1133 else 1133 else
1134 precharge = 5; 1134 precharge = 5;
@@ -2585,7 +2585,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
2585 2585
2586 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2586 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2587 pp = ironlake_get_pp_control(intel_dp); 2587 pp = ironlake_get_pp_control(intel_dp);
2588 if (IS_GEN5(dev_priv)) { 2588 if (IS_GEN(dev_priv, 5)) {
2589 /* ILK workaround: disable reset around power sequence */ 2589 /* ILK workaround: disable reset around power sequence */
2590 pp &= ~PANEL_POWER_RESET; 2590 pp &= ~PANEL_POWER_RESET;
2591 I915_WRITE(pp_ctrl_reg, pp); 2591 I915_WRITE(pp_ctrl_reg, pp);
@@ -2593,7 +2593,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
2593 } 2593 }
2594 2594
2595 pp |= PANEL_POWER_ON; 2595 pp |= PANEL_POWER_ON;
2596 if (!IS_GEN5(dev_priv)) 2596 if (!IS_GEN(dev_priv, 5))
2597 pp |= PANEL_POWER_RESET; 2597 pp |= PANEL_POWER_RESET;
2598 2598
2599 I915_WRITE(pp_ctrl_reg, pp); 2599 I915_WRITE(pp_ctrl_reg, pp);
@@ -2602,7 +2602,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
2602 wait_panel_on(intel_dp); 2602 wait_panel_on(intel_dp);
2603 intel_dp->last_power_on = jiffies; 2603 intel_dp->last_power_on = jiffies;
2604 2604
2605 if (IS_GEN5(dev_priv)) { 2605 if (IS_GEN(dev_priv, 5)) {
2606 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2606 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2607 I915_WRITE(pp_ctrl_reg, pp); 2607 I915_WRITE(pp_ctrl_reg, pp);
2608 POSTING_READ(pp_ctrl_reg); 2608 POSTING_READ(pp_ctrl_reg);
@@ -2831,7 +2831,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2831 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2831 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2832 * 2. Program DP PLL enable 2832 * 2. Program DP PLL enable
2833 */ 2833 */
2834 if (IS_GEN5(dev_priv)) 2834 if (IS_GEN(dev_priv, 5))
2835 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 2835 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2836 2836
2837 intel_dp->DP |= DP_PLL_ENABLE; 2837 intel_dp->DP |= DP_PLL_ENABLE;
@@ -3849,7 +3849,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3849 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 3849 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3850 signal_levels = ivb_cpu_edp_signal_levels(train_set); 3850 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3851 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3851 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3852 } else if (IS_GEN6(dev_priv) && port == PORT_A) { 3852 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3853 signal_levels = snb_cpu_edp_signal_levels(train_set); 3853 signal_levels = snb_cpu_edp_signal_levels(train_set);
3854 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3854 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3855 } else { 3855 } else {
@@ -5271,17 +5271,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
5271 5271
5272 if (INTEL_GEN(dev_priv) >= 11) 5272 if (INTEL_GEN(dev_priv) >= 11)
5273 return icl_digital_port_connected(encoder); 5273 return icl_digital_port_connected(encoder);
5274 else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) 5274 else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5275 return spt_digital_port_connected(encoder); 5275 return spt_digital_port_connected(encoder);
5276 else if (IS_GEN9_LP(dev_priv)) 5276 else if (IS_GEN9_LP(dev_priv))
5277 return bxt_digital_port_connected(encoder); 5277 return bxt_digital_port_connected(encoder);
5278 else if (IS_GEN8(dev_priv)) 5278 else if (IS_GEN(dev_priv, 8))
5279 return bdw_digital_port_connected(encoder); 5279 return bdw_digital_port_connected(encoder);
5280 else if (IS_GEN7(dev_priv)) 5280 else if (IS_GEN(dev_priv, 7))
5281 return ivb_digital_port_connected(encoder); 5281 return ivb_digital_port_connected(encoder);
5282 else if (IS_GEN6(dev_priv)) 5282 else if (IS_GEN(dev_priv, 6))
5283 return snb_digital_port_connected(encoder); 5283 return snb_digital_port_connected(encoder);
5284 else if (IS_GEN5(dev_priv)) 5284 else if (IS_GEN(dev_priv, 5))
5285 return ilk_digital_port_connected(encoder); 5285 return ilk_digital_port_connected(encoder);
5286 5286
5287 MISSING_CASE(INTEL_GEN(dev_priv)); 5287 MISSING_CASE(INTEL_GEN(dev_priv));
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index fe5e87b6e1af..8ff794db7881 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
438 * the semaphore value, then when the seqno moves backwards all 438 * the semaphore value, then when the seqno moves backwards all
439 * future waits will complete instantly (causing rendering corruption). 439 * future waits will complete instantly (causing rendering corruption).
440 */ 440 */
441 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 441 if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
442 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); 442 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
443 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); 443 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
444 if (HAS_VEBOX(dev_priv)) 444 if (HAS_VEBOX(dev_priv))
@@ -774,7 +774,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
774 u32 slice = fls(sseu->slice_mask); 774 u32 slice = fls(sseu->slice_mask);
775 u32 subslice = fls(sseu->subslice_mask[slice]); 775 u32 subslice = fls(sseu->subslice_mask[slice]);
776 776
777 if (IS_GEN10(dev_priv)) 777 if (IS_GEN(dev_priv, 10))
778 mcr_s_ss_select = GEN8_MCR_SLICE(slice) | 778 mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
779 GEN8_MCR_SUBSLICE(subslice); 779 GEN8_MCR_SUBSLICE(subslice);
780 else if (INTEL_GEN(dev_priv) >= 11) 780 else if (INTEL_GEN(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index b57e31fc0f1e..1d3ff026d1bc 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
84 int lines; 84 int lines;
85 85
86 intel_fbc_get_plane_source_size(cache, NULL, &lines); 86 intel_fbc_get_plane_source_size(cache, NULL, &lines);
87 if (IS_GEN7(dev_priv)) 87 if (IS_GEN(dev_priv, 7))
88 lines = min(lines, 2048); 88 lines = min(lines, 2048);
89 else if (INTEL_GEN(dev_priv) >= 8) 89 else if (INTEL_GEN(dev_priv) >= 8)
90 lines = min(lines, 2560); 90 lines = min(lines, 2560);
@@ -127,7 +127,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
127 cfb_pitch = params->fb.stride; 127 cfb_pitch = params->fb.stride;
128 128
129 /* FBC_CTL wants 32B or 64B units */ 129 /* FBC_CTL wants 32B or 64B units */
130 if (IS_GEN2(dev_priv)) 130 if (IS_GEN(dev_priv, 2))
131 cfb_pitch = (cfb_pitch / 32) - 1; 131 cfb_pitch = (cfb_pitch / 32) - 1;
132 else 132 else
133 cfb_pitch = (cfb_pitch / 64) - 1; 133 cfb_pitch = (cfb_pitch / 64) - 1;
@@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
136 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 136 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
137 I915_WRITE(FBC_TAG(i), 0); 137 I915_WRITE(FBC_TAG(i), 0);
138 138
139 if (IS_GEN4(dev_priv)) { 139 if (IS_GEN(dev_priv, 4)) {
140 u32 fbc_ctl2; 140 u32 fbc_ctl2;
141 141
142 /* Set it up... */ 142 /* Set it up... */
@@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
233 233
234 if (params->flags & PLANE_HAS_FENCE) { 234 if (params->flags & PLANE_HAS_FENCE) {
235 dpfc_ctl |= DPFC_CTL_FENCE_EN; 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev_priv)) 236 if (IS_GEN(dev_priv, 5))
237 dpfc_ctl |= params->vma->fence->id; 237 dpfc_ctl |= params->vma->fence->id;
238 if (IS_GEN6(dev_priv)) { 238 if (IS_GEN(dev_priv, 6)) {
239 I915_WRITE(SNB_DPFC_CTL_SA, 239 I915_WRITE(SNB_DPFC_CTL_SA,
240 SNB_CPU_FENCE_ENABLE | 240 SNB_CPU_FENCE_ENABLE |
241 params->vma->fence->id); 241 params->vma->fence->id);
@@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
243 params->crtc.fence_y_offset); 243 params->crtc.fence_y_offset);
244 } 244 }
245 } else { 245 } else {
246 if (IS_GEN6(dev_priv)) { 246 if (IS_GEN(dev_priv, 6)) {
247 I915_WRITE(SNB_DPFC_CTL_SA, 0); 247 I915_WRITE(SNB_DPFC_CTL_SA, 0);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); 248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
249 } 249 }
@@ -282,7 +282,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
282 int threshold = dev_priv->fbc.threshold; 282 int threshold = dev_priv->fbc.threshold;
283 283
284 /* Display WA #0529: skl, kbl, bxt. */ 284 /* Display WA #0529: skl, kbl, bxt. */
285 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { 285 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
286 u32 val = I915_READ(CHICKEN_MISC_4); 286 u32 val = I915_READ(CHICKEN_MISC_4);
287 287
288 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); 288 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
@@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
581 if (stride < 512) 581 if (stride < 512)
582 return false; 582 return false;
583 583
584 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) 584 if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
585 return stride == 4096 || stride == 8192; 585 return stride == 4096 || stride == 8192;
586 586
587 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) 587 if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
588 return false; 588 return false;
589 589
590 if (stride > 16384) 590 if (stride > 16384)
@@ -603,7 +603,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
603 case DRM_FORMAT_XRGB1555: 603 case DRM_FORMAT_XRGB1555:
604 case DRM_FORMAT_RGB565: 604 case DRM_FORMAT_RGB565:
605 /* 16bpp not supported on gen2 */ 605 /* 16bpp not supported on gen2 */
606 if (IS_GEN2(dev_priv)) 606 if (IS_GEN(dev_priv, 2))
607 return false; 607 return false;
608 /* WaFbcOnly1to1Ratio:ctg */ 608 /* WaFbcOnly1to1Ratio:ctg */
609 if (IS_G4X(dev_priv)) 609 if (IS_G4X(dev_priv))
@@ -842,7 +842,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
842 842
843 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); 843 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
844 844
845 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) 845 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
846 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, 846 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
847 32 * fbc->threshold) * 8; 847 32 * fbc->threshold) * 8;
848} 848}
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 77c123cc8817..ff2743ccbece 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -260,9 +260,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
260 260
261 if (HAS_GMCH_DISPLAY(dev_priv)) 261 if (HAS_GMCH_DISPLAY(dev_priv))
262 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 262 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
263 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 263 else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
264 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 264 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
265 else if (IS_GEN7(dev_priv)) 265 else if (IS_GEN(dev_priv, 7))
266 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); 266 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
267 else if (INTEL_GEN(dev_priv) >= 8) 267 else if (INTEL_GEN(dev_priv) >= 8)
268 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 268 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
@@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
423 423
424 if (HAS_GMCH_DISPLAY(dev_priv)) 424 if (HAS_GMCH_DISPLAY(dev_priv))
425 i9xx_check_fifo_underruns(crtc); 425 i9xx_check_fifo_underruns(crtc);
426 else if (IS_GEN7(dev_priv)) 426 else if (IS_GEN(dev_priv, 7))
427 ivybridge_check_fifo_underruns(crtc); 427 ivybridge_check_fifo_underruns(crtc);
428 } 428 }
429 429
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index a67144ee5ceb..4b437e05e2cd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -115,7 +115,7 @@ static void guc_prepare_xfer(struct intel_guc *guc)
115 else 115 else
116 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); 116 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
117 117
118 if (IS_GEN9(dev_priv)) { 118 if (IS_GEN(dev_priv, 9)) {
119 /* DOP Clock Gating Enable for GuC clocks */ 119 /* DOP Clock Gating Enable for GuC clocks */
120 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | 120 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
121 I915_READ(GEN7_MISCCPCTL))); 121 I915_READ(GEN7_MISCCPCTL)));
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 41921a843d42..495fa145f37f 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -236,7 +236,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
236 if (ha != ENGINE_DEAD) 236 if (ha != ENGINE_DEAD)
237 return ha; 237 return ha;
238 238
239 if (IS_GEN2(dev_priv)) 239 if (IS_GEN(dev_priv, 2))
240 return ENGINE_DEAD; 240 return ENGINE_DEAD;
241 241
242 /* Is the chip hanging on a WAIT_FOR_EVENT? 242 /* Is the chip hanging on a WAIT_FOR_EVENT?
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ae7e5b288ed5..f16fb30da64f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1990,7 +1990,7 @@ static int gen8_emit_flush_render(struct i915_request *request,
1990 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 1990 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1991 * pipe control. 1991 * pipe control.
1992 */ 1992 */
1993 if (IS_GEN9(request->i915)) 1993 if (IS_GEN(request->i915, 9))
1994 vf_flush_wa = true; 1994 vf_flush_wa = true;
1995 1995
1996 /* WaForGAMHang:kbl */ 1996 /* WaForGAMHang:kbl */
@@ -2341,7 +2341,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
2341 * subslices are enabled, or a count between one and four on the first 2341 * subslices are enabled, or a count between one and four on the first
2342 * slice. 2342 * slice.
2343 */ 2343 */
2344 if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) { 2344 if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) {
2345 GEM_BUG_ON(subslices & 1); 2345 GEM_BUG_ON(subslices & 1);
2346 2346
2347 subslice_pg = false; 2347 subslice_pg = false;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index e6c5d985ea0a..b85e195f7c8a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
279 * special lvds dither control bit on pch-split platforms, dithering is 279 * special lvds dither control bit on pch-split platforms, dithering is
280 * only controlled through the PIPECONF reg. 280 * only controlled through the PIPECONF reg.
281 */ 281 */
282 if (IS_GEN4(dev_priv)) { 282 if (IS_GEN(dev_priv, 4)) {
283 /* 283 /*
284 * Bspec wording suggests that LVDS port dithering only exists 284 * Bspec wording suggests that LVDS port dithering only exists
285 * for 18bpp panels. 285 * for 18bpp panels.
@@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
919 intel_encoder->cloneable = 0; 919 intel_encoder->cloneable = 0;
920 if (HAS_PCH_SPLIT(dev_priv)) 920 if (HAS_PCH_SPLIT(dev_priv))
921 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 921 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
922 else if (IS_GEN4(dev_priv)) 922 else if (IS_GEN(dev_priv, 4))
923 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 923 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
924 else 924 else
925 intel_encoder->crtc_mask = (1 << 1); 925 intel_encoder->crtc_mask = (1 << 1);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871a8c9a..e976c5ce5479 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -193,7 +193,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
193 } 193 }
194 194
195 /* WaDisableSkipCaching:skl,bxt,kbl,glk */ 195 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
196 if (IS_GEN9(dev_priv)) { 196 if (IS_GEN(dev_priv, 9)) {
197 int i; 197 int i;
198 198
199 for (i = 0; i < table->size; i++) 199 for (i = 0; i < table->size; i++)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 20ea7c99d13a..c153be043078 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -541,7 +541,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt
541{ 541{
542 u32 sw; 542 u32 sw;
543 543
544 if (IS_GEN2(dev_priv)) 544 if (IS_GEN(dev_priv, 2))
545 sw = ALIGN((offset & 31) + width, 32); 545 sw = ALIGN((offset & 31) + width, 32);
546 else 546 else
547 sw = ALIGN((offset & 63) + width, 64); 547 sw = ALIGN((offset & 63) + width, 64);
@@ -778,7 +778,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
778 u32 oconfig; 778 u32 oconfig;
779 779
780 oconfig = OCONF_CC_OUT_8BIT; 780 oconfig = OCONF_CC_OUT_8BIT;
781 if (IS_GEN4(dev_priv)) 781 if (IS_GEN(dev_priv, 4))
782 oconfig |= OCONF_CSC_MODE_BT709; 782 oconfig |= OCONF_CSC_MODE_BT709;
783 oconfig |= pipe == 0 ? 783 oconfig |= pipe == 0 ?
784 OCONF_PIPE_A : OCONF_PIPE_B; 784 OCONF_PIPE_A : OCONF_PIPE_B;
@@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
1012 1012
1013 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1013 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1014 return -EINVAL; 1014 return -EINVAL;
1015 if (IS_GEN4(dev_priv) && rec->stride_Y < 512) 1015 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
1016 return -EINVAL; 1016 return -EINVAL;
1017 1017
1018 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1018 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
@@ -1246,7 +1246,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1246 attrs->contrast = overlay->contrast; 1246 attrs->contrast = overlay->contrast;
1247 attrs->saturation = overlay->saturation; 1247 attrs->saturation = overlay->saturation;
1248 1248
1249 if (!IS_GEN2(dev_priv)) { 1249 if (!IS_GEN(dev_priv, 2)) {
1250 attrs->gamma0 = I915_READ(OGAMC0); 1250 attrs->gamma0 = I915_READ(OGAMC0);
1251 attrs->gamma1 = I915_READ(OGAMC1); 1251 attrs->gamma1 = I915_READ(OGAMC1);
1252 attrs->gamma2 = I915_READ(OGAMC2); 1252 attrs->gamma2 = I915_READ(OGAMC2);
@@ -1270,7 +1270,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1270 update_reg_attrs(overlay, overlay->regs); 1270 update_reg_attrs(overlay, overlay->regs);
1271 1271
1272 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1272 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1273 if (IS_GEN2(dev_priv)) 1273 if (IS_GEN(dev_priv, 2))
1274 goto out_unlock; 1274 goto out_unlock;
1275 1275
1276 if (overlay->active) { 1276 if (overlay->active) {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e6cd7b55c018..ee3e0842d542 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32
563 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); 563 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc);
564 } 564 }
565 565
566 if (IS_GEN4(dev_priv)) { 566 if (IS_GEN(dev_priv, 4)) {
567 mask = BACKLIGHT_DUTY_CYCLE_MASK; 567 mask = BACKLIGHT_DUTY_CYCLE_MASK;
568 } else { 568 } else {
569 level <<= 1; 569 level <<= 1;
@@ -929,7 +929,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
929 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 929 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
930 * that has backlight. 930 * that has backlight.
931 */ 931 */
932 if (IS_GEN2(dev_priv)) 932 if (IS_GEN(dev_priv, 2))
933 I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); 933 I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
934} 934}
935 935
@@ -1557,7 +1557,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
1557 1557
1558 ctl = I915_READ(BLC_PWM_CTL); 1558 ctl = I915_READ(BLC_PWM_CTL);
1559 1559
1560 if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) 1560 if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1561 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; 1561 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
1562 1562
1563 if (IS_PINEVIEW(dev_priv)) 1563 if (IS_PINEVIEW(dev_priv))
@@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
1886 panel->backlight.get = vlv_get_backlight; 1886 panel->backlight.get = vlv_get_backlight;
1887 panel->backlight.hz_to_pwm = vlv_hz_to_pwm; 1887 panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
1888 } 1888 }
1889 } else if (IS_GEN4(dev_priv)) { 1889 } else if (IS_GEN(dev_priv, 4)) {
1890 panel->backlight.setup = i965_setup_backlight; 1890 panel->backlight.setup = i965_setup_backlight;
1891 panel->backlight.enable = i965_enable_backlight; 1891 panel->backlight.enable = i965_enable_backlight;
1892 panel->backlight.disable = i965_disable_backlight; 1892 panel->backlight.disable = i965_disable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index f3c9010e332a..9e870caf8104 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -427,13 +427,13 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
427 enum intel_pipe_crc_source *source, u32 *val, 427 enum intel_pipe_crc_source *source, u32 *val,
428 bool set_wa) 428 bool set_wa)
429{ 429{
430 if (IS_GEN2(dev_priv)) 430 if (IS_GEN(dev_priv, 2))
431 return i8xx_pipe_crc_ctl_reg(source, val); 431 return i8xx_pipe_crc_ctl_reg(source, val);
432 else if (INTEL_GEN(dev_priv) < 5) 432 else if (INTEL_GEN(dev_priv) < 5)
433 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 433 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
434 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 434 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
435 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); 435 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
436 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 436 else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
437 return ilk_pipe_crc_ctl_reg(source, val); 437 return ilk_pipe_crc_ctl_reg(source, val);
438 else 438 else
439 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); 439 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
@@ -544,13 +544,13 @@ static int
544intel_is_valid_crc_source(struct drm_i915_private *dev_priv, 544intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
545 const enum intel_pipe_crc_source source) 545 const enum intel_pipe_crc_source source)
546{ 546{
547 if (IS_GEN2(dev_priv)) 547 if (IS_GEN(dev_priv, 2))
548 return i8xx_crc_source_valid(dev_priv, source); 548 return i8xx_crc_source_valid(dev_priv, source);
549 else if (INTEL_GEN(dev_priv) < 5) 549 else if (INTEL_GEN(dev_priv) < 5)
550 return i9xx_crc_source_valid(dev_priv, source); 550 return i9xx_crc_source_valid(dev_priv, source);
551 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 551 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
552 return vlv_crc_source_valid(dev_priv, source); 552 return vlv_crc_source_valid(dev_priv, source);
553 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 553 else if (IS_GEN(dev_priv, 5) || IS_GEN(dev_priv, 6))
554 return ilk_crc_source_valid(dev_priv, source); 554 return ilk_crc_source_valid(dev_priv, source);
555 else 555 else
556 return ivb_crc_source_valid(dev_priv, source); 556 return ivb_crc_source_valid(dev_priv, source);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6c7c11d2c0e..b11fac679e10 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2271,7 +2271,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2271 2271
2272 if (IS_I945GM(dev_priv)) 2272 if (IS_I945GM(dev_priv))
2273 wm_info = &i945_wm_info; 2273 wm_info = &i945_wm_info;
2274 else if (!IS_GEN2(dev_priv)) 2274 else if (!IS_GEN(dev_priv, 2))
2275 wm_info = &i915_wm_info; 2275 wm_info = &i915_wm_info;
2276 else 2276 else
2277 wm_info = &i830_a_wm_info; 2277 wm_info = &i830_a_wm_info;
@@ -2285,7 +2285,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2285 crtc->base.primary->state->fb; 2285 crtc->base.primary->state->fb;
2286 int cpp; 2286 int cpp;
2287 2287
2288 if (IS_GEN2(dev_priv)) 2288 if (IS_GEN(dev_priv, 2))
2289 cpp = 4; 2289 cpp = 4;
2290 else 2290 else
2291 cpp = fb->format->cpp[0]; 2291 cpp = fb->format->cpp[0];
@@ -2300,7 +2300,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2300 planea_wm = wm_info->max_wm; 2300 planea_wm = wm_info->max_wm;
2301 } 2301 }
2302 2302
2303 if (IS_GEN2(dev_priv)) 2303 if (IS_GEN(dev_priv, 2))
2304 wm_info = &i830_bc_wm_info; 2304 wm_info = &i830_bc_wm_info;
2305 2305
2306 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); 2306 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
@@ -2312,7 +2312,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2312 crtc->base.primary->state->fb; 2312 crtc->base.primary->state->fb;
2313 int cpp; 2313 int cpp;
2314 2314
2315 if (IS_GEN2(dev_priv)) 2315 if (IS_GEN(dev_priv, 2))
2316 cpp = 4; 2316 cpp = 4;
2317 else 2317 else
2318 cpp = fb->format->cpp[0]; 2318 cpp = fb->format->cpp[0];
@@ -2923,7 +2923,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2923 uint16_t wm[5]) 2923 uint16_t wm[5])
2924{ 2924{
2925 /* ILK sprite LP0 latency is 1300 ns */ 2925 /* ILK sprite LP0 latency is 1300 ns */
2926 if (IS_GEN5(dev_priv)) 2926 if (IS_GEN(dev_priv, 5))
2927 wm[0] = 13; 2927 wm[0] = 13;
2928} 2928}
2929 2929
@@ -2931,7 +2931,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2931 uint16_t wm[5]) 2931 uint16_t wm[5])
2932{ 2932{
2933 /* ILK cursor LP0 latency is 1300 ns */ 2933 /* ILK cursor LP0 latency is 1300 ns */
2934 if (IS_GEN5(dev_priv)) 2934 if (IS_GEN(dev_priv, 5))
2935 wm[0] = 13; 2935 wm[0] = 13;
2936} 2936}
2937 2937
@@ -3058,7 +3058,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3058 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); 3058 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3059 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); 3059 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3060 3060
3061 if (IS_GEN6(dev_priv)) { 3061 if (IS_GEN(dev_priv, 6)) {
3062 snb_wm_latency_quirk(dev_priv); 3062 snb_wm_latency_quirk(dev_priv);
3063 snb_wm_lp3_irq_quirk(dev_priv); 3063 snb_wm_lp3_irq_quirk(dev_priv);
3064 } 3064 }
@@ -3314,7 +3314,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3314 * What we should check here is whether FBC can be 3314 * What we should check here is whether FBC can be
3315 * enabled sometime later. 3315 * enabled sometime later.
3316 */ 3316 */
3317 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && 3317 if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
3318 intel_fbc_is_active(dev_priv)) { 3318 intel_fbc_is_active(dev_priv)) {
3319 for (level = 2; level <= max_level; level++) { 3319 for (level = 2; level <= max_level; level++) {
3320 struct intel_wm_level *wm = &merged->wm[level]; 3320 struct intel_wm_level *wm = &merged->wm[level];
@@ -3751,9 +3751,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
3751 if (!intel_has_sagv(dev_priv)) 3751 if (!intel_has_sagv(dev_priv))
3752 return false; 3752 return false;
3753 3753
3754 if (IS_GEN9(dev_priv)) 3754 if (IS_GEN(dev_priv, 9))
3755 sagv_block_time_us = 30; 3755 sagv_block_time_us = 30;
3756 else if (IS_GEN10(dev_priv)) 3756 else if (IS_GEN(dev_priv, 10))
3757 sagv_block_time_us = 20; 3757 sagv_block_time_us = 20;
3758 else 3758 else
3759 sagv_block_time_us = 10; 3759 sagv_block_time_us = 10;
@@ -4657,7 +4657,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
4657 4657
4658 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, 4658 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4659 wp->y_min_scanlines); 4659 wp->y_min_scanlines);
4660 } else if (wp->x_tiled && IS_GEN9(dev_priv)) { 4660 } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
4661 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 4661 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4662 wp->dbuf_block_size); 4662 wp->dbuf_block_size);
4663 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); 4663 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
@@ -4716,7 +4716,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
4716 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { 4716 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
4717 selected_result = method2; 4717 selected_result = method2;
4718 } else if (latency >= wp->linetime_us) { 4718 } else if (latency >= wp->linetime_us) {
4719 if (IS_GEN9(dev_priv) && 4719 if (IS_GEN(dev_priv, 9) &&
4720 !IS_GEMINILAKE(dev_priv)) 4720 !IS_GEMINILAKE(dev_priv))
4721 selected_result = min_fixed16(method1, method2); 4721 selected_result = min_fixed16(method1, method2);
4722 else 4722 else
@@ -6908,7 +6908,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6908 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 6908 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6909 6909
6910 /* Program defaults and thresholds for RPS */ 6910 /* Program defaults and thresholds for RPS */
6911 if (IS_GEN9(dev_priv)) 6911 if (IS_GEN(dev_priv, 9))
6912 I915_WRITE(GEN6_RC_VIDEO_FREQ, 6912 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6913 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); 6913 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
6914 6914
@@ -7144,9 +7144,9 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
7144 7144
7145 rc6vids = 0; 7145 rc6vids = 0;
7146 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 7146 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
7147 if (IS_GEN6(dev_priv) && ret) { 7147 if (IS_GEN(dev_priv, 6) && ret) {
7148 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 7148 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
7149 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 7149 } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
7150 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 7150 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
7151 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 7151 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
7152 rc6vids &= 0xffff00; 7152 rc6vids &= 0xffff00;
@@ -7846,7 +7846,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7846{ 7846{
7847 unsigned long val; 7847 unsigned long val;
7848 7848
7849 if (!IS_GEN5(dev_priv)) 7849 if (!IS_GEN(dev_priv, 5))
7850 return 0; 7850 return 0;
7851 7851
7852 spin_lock_irq(&mchdev_lock); 7852 spin_lock_irq(&mchdev_lock);
@@ -7930,7 +7930,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7930 7930
7931void i915_update_gfx_val(struct drm_i915_private *dev_priv) 7931void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7932{ 7932{
7933 if (!IS_GEN5(dev_priv)) 7933 if (!IS_GEN(dev_priv, 5))
7934 return; 7934 return;
7935 7935
7936 spin_lock_irq(&mchdev_lock); 7936 spin_lock_irq(&mchdev_lock);
@@ -7981,7 +7981,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7981{ 7981{
7982 unsigned long val; 7982 unsigned long val;
7983 7983
7984 if (!IS_GEN5(dev_priv)) 7984 if (!IS_GEN(dev_priv, 5))
7985 return 0; 7985 return 0;
7986 7986
7987 spin_lock_irq(&mchdev_lock); 7987 spin_lock_irq(&mchdev_lock);
@@ -8269,7 +8269,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
8269 intel_freq_opcode(dev_priv, 450)); 8269 intel_freq_opcode(dev_priv, 450));
8270 8270
8271 /* After setting max-softlimit, find the overclock max freq */ 8271 /* After setting max-softlimit, find the overclock max freq */
8272 if (IS_GEN6(dev_priv) || 8272 if (IS_GEN(dev_priv, 6) ||
8273 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { 8273 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
8274 u32 params = 0; 8274 u32 params = 0;
8275 8275
@@ -9339,9 +9339,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9339 dev_priv->display.init_clock_gating = ivb_init_clock_gating; 9339 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9340 else if (IS_VALLEYVIEW(dev_priv)) 9340 else if (IS_VALLEYVIEW(dev_priv))
9341 dev_priv->display.init_clock_gating = vlv_init_clock_gating; 9341 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9342 else if (IS_GEN6(dev_priv)) 9342 else if (IS_GEN(dev_priv, 6))
9343 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 9343 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9344 else if (IS_GEN5(dev_priv)) 9344 else if (IS_GEN(dev_priv, 5))
9345 dev_priv->display.init_clock_gating = ilk_init_clock_gating; 9345 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9346 else if (IS_G4X(dev_priv)) 9346 else if (IS_G4X(dev_priv))
9347 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 9347 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
@@ -9349,11 +9349,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9349 dev_priv->display.init_clock_gating = i965gm_init_clock_gating; 9349 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9350 else if (IS_I965G(dev_priv)) 9350 else if (IS_I965G(dev_priv))
9351 dev_priv->display.init_clock_gating = i965g_init_clock_gating; 9351 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9352 else if (IS_GEN3(dev_priv)) 9352 else if (IS_GEN(dev_priv, 3))
9353 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 9353 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9354 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) 9354 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9355 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 9355 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9356 else if (IS_GEN2(dev_priv)) 9356 else if (IS_GEN(dev_priv, 2))
9357 dev_priv->display.init_clock_gating = i830_init_clock_gating; 9357 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9358 else { 9358 else {
9359 MISSING_CASE(INTEL_DEVID(dev_priv)); 9359 MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -9367,7 +9367,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
9367 /* For cxsr */ 9367 /* For cxsr */
9368 if (IS_PINEVIEW(dev_priv)) 9368 if (IS_PINEVIEW(dev_priv))
9369 i915_pineview_get_mem_freq(dev_priv); 9369 i915_pineview_get_mem_freq(dev_priv);
9370 else if (IS_GEN5(dev_priv)) 9370 else if (IS_GEN(dev_priv, 5))
9371 i915_ironlake_get_mem_freq(dev_priv); 9371 i915_ironlake_get_mem_freq(dev_priv);
9372 9372
9373 /* For FIFO watermark updates */ 9373 /* For FIFO watermark updates */
@@ -9379,9 +9379,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
9379 } else if (HAS_PCH_SPLIT(dev_priv)) { 9379 } else if (HAS_PCH_SPLIT(dev_priv)) {
9380 ilk_setup_wm_latency(dev_priv); 9380 ilk_setup_wm_latency(dev_priv);
9381 9381
9382 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && 9382 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
9383 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 9383 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9384 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && 9384 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
9385 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 9385 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9386 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; 9386 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9387 dev_priv->display.compute_intermediate_wm = 9387 dev_priv->display.compute_intermediate_wm =
@@ -9422,12 +9422,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
9422 dev_priv->display.update_wm = NULL; 9422 dev_priv->display.update_wm = NULL;
9423 } else 9423 } else
9424 dev_priv->display.update_wm = pineview_update_wm; 9424 dev_priv->display.update_wm = pineview_update_wm;
9425 } else if (IS_GEN4(dev_priv)) { 9425 } else if (IS_GEN(dev_priv, 4)) {
9426 dev_priv->display.update_wm = i965_update_wm; 9426 dev_priv->display.update_wm = i965_update_wm;
9427 } else if (IS_GEN3(dev_priv)) { 9427 } else if (IS_GEN(dev_priv, 3)) {
9428 dev_priv->display.update_wm = i9xx_update_wm; 9428 dev_priv->display.update_wm = i9xx_update_wm;
9429 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 9429 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9430 } else if (IS_GEN2(dev_priv)) { 9430 } else if (IS_GEN(dev_priv, 2)) {
9431 if (INTEL_INFO(dev_priv)->num_pipes == 1) { 9431 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9432 dev_priv->display.update_wm = i845_update_wm; 9432 dev_priv->display.update_wm = i845_update_wm;
9433 dev_priv->display.get_fifo_size = i845_get_fifo_size; 9433 dev_priv->display.get_fifo_size = i845_get_fifo_size;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4c4dd1c310ce..dce39f06b682 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -552,7 +552,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
552 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 552 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
553 psr_max_h = 4096; 553 psr_max_h = 4096;
554 psr_max_v = 2304; 554 psr_max_v = 2304;
555 } else if (IS_GEN9(dev_priv)) { 555 } else if (IS_GEN(dev_priv, 9)) {
556 psr_max_h = 3640; 556 psr_max_h = 3640;
557 psr_max_v = 2304; 557 psr_max_v = 2304;
558 } 558 }
@@ -686,7 +686,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
686 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 686 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
687 hsw_psr_setup_aux(intel_dp); 687 hsw_psr_setup_aux(intel_dp);
688 688
689 if (dev_priv->psr.psr2_enabled && (IS_GEN9(dev_priv) && 689 if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
690 !IS_GEMINILAKE(dev_priv))) { 690 !IS_GEMINILAKE(dev_priv))) {
691 i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, 691 i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
692 cpu_transcoder); 692 cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 720c11e0acd1..fdeca2b877c9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -133,7 +133,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
133 cmd = MI_FLUSH; 133 cmd = MI_FLUSH;
134 if (mode & EMIT_INVALIDATE) { 134 if (mode & EMIT_INVALIDATE) {
135 cmd |= MI_EXE_FLUSH; 135 cmd |= MI_EXE_FLUSH;
136 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) 136 if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5))
137 cmd |= MI_INVALIDATE_ISP; 137 cmd |= MI_INVALIDATE_ISP;
138 } 138 }
139 139
@@ -401,7 +401,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
401 /* The ring status page addresses are no longer next to the rest of 401 /* The ring status page addresses are no longer next to the rest of
402 * the ring registers as of gen7. 402 * the ring registers as of gen7.
403 */ 403 */
404 if (IS_GEN7(dev_priv)) { 404 if (IS_GEN(dev_priv, 7)) {
405 switch (engine->id) { 405 switch (engine->id) {
406 /* 406 /*
407 * No more rings exist on Gen7. Default case is only to shut up 407 * No more rings exist on Gen7. Default case is only to shut up
@@ -422,7 +422,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
422 mmio = VEBOX_HWS_PGA_GEN7; 422 mmio = VEBOX_HWS_PGA_GEN7;
423 break; 423 break;
424 } 424 }
425 } else if (IS_GEN6(dev_priv)) { 425 } else if (IS_GEN(dev_priv, 6)) {
426 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 426 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
427 } else { 427 } else {
428 mmio = RING_HWS_PGA(engine->mmio_base); 428 mmio = RING_HWS_PGA(engine->mmio_base);
@@ -693,17 +693,17 @@ static int init_render_ring(struct intel_engine_cs *engine)
693 693
694 /* Required for the hardware to program scanline values for waiting */ 694 /* Required for the hardware to program scanline values for waiting */
695 /* WaEnableFlushTlbInvalidationMode:snb */ 695 /* WaEnableFlushTlbInvalidationMode:snb */
696 if (IS_GEN6(dev_priv)) 696 if (IS_GEN(dev_priv, 6))
697 I915_WRITE(GFX_MODE, 697 I915_WRITE(GFX_MODE,
698 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); 698 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
699 699
700 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 700 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
701 if (IS_GEN7(dev_priv)) 701 if (IS_GEN(dev_priv, 7))
702 I915_WRITE(GFX_MODE_GEN7, 702 I915_WRITE(GFX_MODE_GEN7,
703 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | 703 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
704 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 704 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
705 705
706 if (IS_GEN6(dev_priv)) { 706 if (IS_GEN(dev_priv, 6)) {
707 /* From the Sandybridge PRM, volume 1 part 3, page 24: 707 /* From the Sandybridge PRM, volume 1 part 3, page 24:
708 * "If this bit is set, STCunit will have LRA as replacement 708 * "If this bit is set, STCunit will have LRA as replacement
709 * policy. [...] This bit must be reset. LRA replacement 709 * policy. [...] This bit must be reset. LRA replacement
@@ -1582,7 +1582,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
1582 enum intel_engine_id id; 1582 enum intel_engine_id id;
1583 const int num_rings = 1583 const int num_rings =
1584 /* Use an extended w/a on gen7 if signalling from other rings */ 1584 /* Use an extended w/a on gen7 if signalling from other rings */
1585 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? 1585 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN(i915, 7)) ?
1586 INTEL_INFO(i915)->num_rings - 1 : 1586 INTEL_INFO(i915)->num_rings - 1 :
1587 0; 1587 0;
1588 bool force_restore = false; 1588 bool force_restore = false;
@@ -1597,7 +1597,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
1597 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; 1597 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1598 1598
1599 len = 4; 1599 len = 4;
1600 if (IS_GEN7(i915)) 1600 if (IS_GEN(i915, 7))
1601 len += 2 + (num_rings ? 4*num_rings + 6 : 0); 1601 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1602 if (flags & MI_FORCE_RESTORE) { 1602 if (flags & MI_FORCE_RESTORE) {
1603 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); 1603 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
@@ -1611,7 +1611,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
1611 return PTR_ERR(cs); 1611 return PTR_ERR(cs);
1612 1612
1613 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ 1613 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1614 if (IS_GEN7(i915)) { 1614 if (IS_GEN(i915, 7)) {
1615 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1615 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1616 if (num_rings) { 1616 if (num_rings) {
1617 struct intel_engine_cs *signaller; 1617 struct intel_engine_cs *signaller;
@@ -1658,7 +1658,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
1658 */ 1658 */
1659 *cs++ = MI_NOOP; 1659 *cs++ = MI_NOOP;
1660 1660
1661 if (IS_GEN7(i915)) { 1661 if (IS_GEN(i915, 7)) {
1662 if (num_rings) { 1662 if (num_rings) {
1663 struct intel_engine_cs *signaller; 1663 struct intel_engine_cs *signaller;
1664 i915_reg_t last_reg = {}; /* keep gcc quiet */ 1664 i915_reg_t last_reg = {}; /* keep gcc quiet */
@@ -2283,9 +2283,9 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2283 if (INTEL_GEN(dev_priv) >= 6) { 2283 if (INTEL_GEN(dev_priv) >= 6) {
2284 engine->init_context = intel_rcs_ctx_init; 2284 engine->init_context = intel_rcs_ctx_init;
2285 engine->emit_flush = gen7_render_ring_flush; 2285 engine->emit_flush = gen7_render_ring_flush;
2286 if (IS_GEN6(dev_priv)) 2286 if (IS_GEN(dev_priv, 6))
2287 engine->emit_flush = gen6_render_ring_flush; 2287 engine->emit_flush = gen6_render_ring_flush;
2288 } else if (IS_GEN5(dev_priv)) { 2288 } else if (IS_GEN(dev_priv, 5)) {
2289 engine->emit_flush = gen4_render_ring_flush; 2289 engine->emit_flush = gen4_render_ring_flush;
2290 } else { 2290 } else {
2291 if (INTEL_GEN(dev_priv) < 4) 2291 if (INTEL_GEN(dev_priv) < 4)
@@ -2315,13 +2315,13 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2315 2315
2316 if (INTEL_GEN(dev_priv) >= 6) { 2316 if (INTEL_GEN(dev_priv) >= 6) {
2317 /* gen6 bsd needs a special wa for tail updates */ 2317 /* gen6 bsd needs a special wa for tail updates */
2318 if (IS_GEN6(dev_priv)) 2318 if (IS_GEN(dev_priv, 6))
2319 engine->set_default_submission = gen6_bsd_set_default_submission; 2319 engine->set_default_submission = gen6_bsd_set_default_submission;
2320 engine->emit_flush = gen6_bsd_ring_flush; 2320 engine->emit_flush = gen6_bsd_ring_flush;
2321 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; 2321 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2322 } else { 2322 } else {
2323 engine->emit_flush = bsd_ring_flush; 2323 engine->emit_flush = bsd_ring_flush;
2324 if (IS_GEN5(dev_priv)) 2324 if (IS_GEN(dev_priv, 5))
2325 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 2325 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2326 else 2326 else
2327 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; 2327 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 72edaa7ff411..1ae74e579386 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -94,11 +94,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
94#define I915_MAX_SUBSLICES 8 94#define I915_MAX_SUBSLICES 8
95 95
96#define instdone_slice_mask(dev_priv__) \ 96#define instdone_slice_mask(dev_priv__) \
97 (IS_GEN7(dev_priv__) ? \ 97 (IS_GEN(dev_priv__, 7) ? \
98 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) 98 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
99 99
100#define instdone_subslice_mask(dev_priv__) \ 100#define instdone_subslice_mask(dev_priv__) \
101 (IS_GEN7(dev_priv__) ? \ 101 (IS_GEN(dev_priv__, 7) ? \
102 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) 102 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
103 103
104#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ 104#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4350a5270423..9e9501f82f06 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -509,7 +509,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
509 * BIOS's own request bits, which are forced-on for these power wells 509 * BIOS's own request bits, which are forced-on for these power wells
510 * when exiting DC5/6. 510 * when exiting DC5/6.
511 */ 511 */
512 if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) && 512 if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) &&
513 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 513 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
514 val |= I915_READ(regs->bios); 514 val |= I915_READ(regs->bios);
515 515
@@ -3058,7 +3058,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
3058 * suspend/resume, so allow it unconditionally. 3058 * suspend/resume, so allow it unconditionally.
3059 */ 3059 */
3060 mask = DC_STATE_EN_DC9; 3060 mask = DC_STATE_EN_DC9;
3061 } else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) { 3061 } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
3062 max_dc = 2; 3062 max_dc = 2;
3063 mask = 0; 3063 mask = 0;
3064 } else if (IS_GEN9_LP(dev_priv)) { 3064 } else if (IS_GEN9_LP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d2e003d8f3db..f70d2c607902 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1087,7 +1087,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1087 1087
1088 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE; 1088 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
1089 1089
1090 if (IS_GEN6(dev_priv)) 1090 if (IS_GEN(dev_priv, 6))
1091 dvscntr |= DVS_TRICKLE_FEED_DISABLE; 1091 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1092 1092
1093 switch (fb->format->format) { 1093 switch (fb->format->format) {
@@ -1983,7 +1983,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1983 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 1983 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1984 return false; 1984 return false;
1985 1985
1986 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) 1986 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
1987 return false; 1987 return false;
1988 1988
1989 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 1989 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
@@ -2163,7 +2163,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2163 plane->check_plane = g4x_sprite_check; 2163 plane->check_plane = g4x_sprite_check;
2164 2164
2165 modifiers = i9xx_plane_format_modifiers; 2165 modifiers = i9xx_plane_format_modifiers;
2166 if (IS_GEN6(dev_priv)) { 2166 if (IS_GEN(dev_priv, 6)) {
2167 formats = snb_plane_formats; 2167 formats = snb_plane_formats;
2168 num_formats = ARRAY_SIZE(snb_plane_formats); 2168 num_formats = ARRAY_SIZE(snb_plane_formats);
2169 2169
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index b34c318b238d..447b1de77cc7 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -354,7 +354,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
354 354
355 /* WaEnableuKernelHeaderValidFix:skl */ 355 /* WaEnableuKernelHeaderValidFix:skl */
356 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ 356 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
357 if (IS_GEN9(i915)) 357 if (IS_GEN(i915, 9))
358 attempts = 3; 358 attempts = 3;
359 else 359 else
360 attempts = 1; 360 attempts = 1;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 631b4165fe00..c6eb053a8fad 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
528 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 528 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
529 ret |= vlv_check_for_unclaimed_mmio(dev_priv); 529 ret |= vlv_check_for_unclaimed_mmio(dev_priv);
530 530
531 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 531 if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
532 ret |= gen6_check_for_fifo_debug(dev_priv); 532 ret |= gen6_check_for_fifo_debug(dev_priv);
533 533
534 return ret; 534 return ret;
@@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
556 dev_priv->uncore.funcs.force_wake_get(dev_priv, 556 dev_priv->uncore.funcs.force_wake_get(dev_priv,
557 restore_forcewake); 557 restore_forcewake);
558 558
559 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 559 if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7))
560 dev_priv->uncore.fifo_count = 560 dev_priv->uncore.fifo_count =
561 fifo_free_entries(dev_priv); 561 fifo_free_entries(dev_priv);
562 spin_unlock_irq(&dev_priv->uncore.lock); 562 spin_unlock_irq(&dev_priv->uncore.lock);
@@ -1398,7 +1398,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1398 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) 1398 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
1399 return; 1399 return;
1400 1400
1401 if (IS_GEN6(dev_priv)) { 1401 if (IS_GEN(dev_priv, 6)) {
1402 dev_priv->uncore.fw_reset = 0; 1402 dev_priv->uncore.fw_reset = 0;
1403 dev_priv->uncore.fw_set = FORCEWAKE_KERNEL; 1403 dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
1404 dev_priv->uncore.fw_clear = 0; 1404 dev_priv->uncore.fw_clear = 0;
@@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1437 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 1437 FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1438 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 1438 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1439 } 1439 }
1440 } else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) { 1440 } else if (IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 9)) {
1441 dev_priv->uncore.funcs.force_wake_get = 1441 dev_priv->uncore.funcs.force_wake_get =
1442 fw_domains_get_with_fallback; 1442 fw_domains_get_with_fallback;
1443 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1443 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
@@ -1503,7 +1503,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1503 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1503 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1504 FORCEWAKE, FORCEWAKE_ACK); 1504 FORCEWAKE, FORCEWAKE_ACK);
1505 } 1505 }
1506 } else if (IS_GEN6(dev_priv)) { 1506 } else if (IS_GEN(dev_priv, 6)) {
1507 dev_priv->uncore.funcs.force_wake_get = 1507 dev_priv->uncore.funcs.force_wake_get =
1508 fw_domains_get_with_thread_status; 1508 fw_domains_get_with_thread_status;
1509 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1509 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
@@ -1570,7 +1570,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
1570 if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { 1570 if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
1571 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); 1571 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
1572 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); 1572 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
1573 } else if (IS_GEN5(dev_priv)) { 1573 } else if (IS_GEN(dev_priv, 5)) {
1574 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); 1574 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
1575 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); 1575 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
1576 } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { 1576 } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
@@ -1582,7 +1582,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
1582 } else { 1582 } else {
1583 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); 1583 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
1584 } 1584 }
1585 } else if (IS_GEN8(dev_priv)) { 1585 } else if (IS_GEN(dev_priv, 8)) {
1586 if (IS_CHERRYVIEW(dev_priv)) { 1586 if (IS_CHERRYVIEW(dev_priv)) {
1587 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); 1587 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1588 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); 1588 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
@@ -2173,7 +2173,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
2173 return gen8_reset_engines; 2173 return gen8_reset_engines;
2174 else if (INTEL_GEN(dev_priv) >= 6) 2174 else if (INTEL_GEN(dev_priv) >= 6)
2175 return gen6_reset_engines; 2175 return gen6_reset_engines;
2176 else if (IS_GEN5(dev_priv)) 2176 else if (IS_GEN(dev_priv, 5))
2177 return ironlake_do_reset; 2177 return ironlake_do_reset;
2178 else if (IS_G4X(dev_priv)) 2178 else if (IS_G4X(dev_priv))
2179 return g4x_do_reset; 2179 return g4x_do_reset;
@@ -2341,7 +2341,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
2341 fw_domains = __gen11_fwtable_reg_write_fw_domains(offset); 2341 fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
2342 } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { 2342 } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
2343 fw_domains = __fwtable_reg_write_fw_domains(offset); 2343 fw_domains = __fwtable_reg_write_fw_domains(offset);
2344 } else if (IS_GEN8(dev_priv)) { 2344 } else if (IS_GEN(dev_priv, 8)) {
2345 fw_domains = __gen8_reg_write_fw_domains(offset); 2345 fw_domains = __gen8_reg_write_fw_domains(offset);
2346 } else if (IS_GEN_RANGE(dev_priv, 6, 7)) { 2346 } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
2347 fw_domains = FORCEWAKE_RENDER; 2347 fw_domains = FORCEWAKE_RENDER;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 92cb82dd0c07..630c887682e8 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -130,11 +130,11 @@ static inline int check_hw_restriction(struct drm_i915_private *i915,
130{ 130{
131 int err = 0; 131 int err = 0;
132 132
133 if (IS_GEN9(i915)) 133 if (IS_GEN(i915, 9))
134 err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size); 134 err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
135 135
136 if (!err && 136 if (!err &&
137 (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) 137 (IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
138 err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size); 138 err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
139 139
140 return err; 140 return err;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 6bcac78a9c36..7a8618065491 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1186,7 +1186,7 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
1186 GEN7_DISABLE_SAMPLER_PREFETCH); 1186 GEN7_DISABLE_SAMPLER_PREFETCH);
1187 } 1187 }
1188 1188
1189 if (IS_GEN9(i915) || IS_CANNONLAKE(i915)) { 1189 if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
1190 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */ 1190 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
1191 wa_masked_en(wal, 1191 wa_masked_en(wal,
1192 GEN7_FF_SLICE_CS_CHICKEN1, 1192 GEN7_FF_SLICE_CS_CHICKEN1,
@@ -1207,7 +1207,7 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
1207 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1207 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1208 } 1208 }
1209 1209
1210 if (IS_GEN9(i915)) { 1210 if (IS_GEN(i915, 9)) {
1211 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1211 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1212 wa_masked_en(wal, 1212 wa_masked_en(wal,
1213 GEN9_CSFE_CHICKEN1_RCS, 1213 GEN9_CSFE_CHICKEN1_RCS,
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-06 12:45:51 -0400