1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 23f96e9c392f..ed4abb3d7e23 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -510,28 +510,28 @@ enum mvpp2_tag_type {
 /* Sram result info bits assignment */
 #define MVPP2_PRS_RI_MAC_ME_MASK                0x1
 #define MVPP2_PRS_RI_DSA_MASK                   0x2
-#define MVPP2_PRS_RI_VLAN_MASK                  0xc
-#define MVPP2_PRS_RI_VLAN_NONE                  ~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_MASK                  (BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_NONE                  0x0
 #define MVPP2_PRS_RI_VLAN_SINGLE                BIT(2)
 #define MVPP2_PRS_RI_VLAN_DOUBLE                BIT(3)
 #define MVPP2_PRS_RI_VLAN_TRIPLE                (BIT(2) | BIT(3))
 #define MVPP2_PRS_RI_CPU_CODE_MASK              0x70
 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC           BIT(4)
-#define MVPP2_PRS_RI_L2_CAST_MASK               0x600
-#define MVPP2_PRS_RI_L2_UCAST                   ~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_CAST_MASK               (BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_UCAST                   0x0
 #define MVPP2_PRS_RI_L2_MCAST                   BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                   BIT(10)
 #define MVPP2_PRS_RI_PPPOE_MASK                 0x800
-#define MVPP2_PRS_RI_L3_PROTO_MASK              0x7000
-#define MVPP2_PRS_RI_L3_UN                      ~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_PROTO_MASK              (BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_UN                      0x0
 #define MVPP2_PRS_RI_L3_IP4                     BIT(12)
 #define MVPP2_PRS_RI_L3_IP4_OPT                 BIT(13)
 #define MVPP2_PRS_RI_L3_IP4_OTHER               (BIT(12) | BIT(13))
 #define MVPP2_PRS_RI_L3_IP6                     BIT(14)
 #define MVPP2_PRS_RI_L3_IP6_EXT                 (BIT(12) | BIT(14))
 #define MVPP2_PRS_RI_L3_ARP                     (BIT(13) | BIT(14))
-#define MVPP2_PRS_RI_L3_ADDR_MASK               0x18000
-#define MVPP2_PRS_RI_L3_UCAST                   ~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_ADDR_MASK               (BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_UCAST                   0x0
 #define MVPP2_PRS_RI_L3_MCAST                   BIT(15)
 #define MVPP2_PRS_RI_L3_BCAST                   (BIT(15) | BIT(16))
 #define MVPP2_PRS_RI_IP_FRAG_MASK               0x20000