diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-02-21 05:28:11 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2017-02-21 13:16:16 -0500 |
commit | 8138affc4999bbe4ca5ed805b36f80b56354339e (patch) | |
tree | 54e9ca287378d388cfa72406444d06a73c0f27d2 | |
parent | 31d7677b91307e2771b6922fd9920542a92d376d (diff) |
net: mvpp2: simplify MVPP2_PRS_RI_* definitions
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.
Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.
For example:
#define MVPP2_PRS_RI_L2_CAST_MASK 0x600
#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
#define MVPP2_PRS_RI_L2_MCAST BIT(9)
#define MVPP2_PRS_RI_L2_BCAST BIT(10)
becomes
#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
#define MVPP2_PRS_RI_L2_UCAST 0x0
#define MVPP2_PRS_RI_L2_MCAST BIT(9)
#define MVPP2_PRS_RI_L2_BCAST BIT(10)
Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).
It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):
drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]
#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’
mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/marvell/mvpp2.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 23f96e9c392f..ed4abb3d7e23 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c | |||
@@ -510,28 +510,28 @@ enum mvpp2_tag_type { | |||
510 | /* Sram result info bits assignment */ | 510 | /* Sram result info bits assignment */ |
511 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 | 511 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 |
512 | #define MVPP2_PRS_RI_DSA_MASK 0x2 | 512 | #define MVPP2_PRS_RI_DSA_MASK 0x2 |
513 | #define MVPP2_PRS_RI_VLAN_MASK 0xc | 513 | #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) |
514 | #define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3)) | 514 | #define MVPP2_PRS_RI_VLAN_NONE 0x0 |
515 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) | 515 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) |
516 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) | 516 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) |
517 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) | 517 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) |
518 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 | 518 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 |
519 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) | 519 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) |
520 | #define MVPP2_PRS_RI_L2_CAST_MASK 0x600 | 520 | #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) |
521 | #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) | 521 | #define MVPP2_PRS_RI_L2_UCAST 0x0 |
522 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) | 522 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) |
523 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) | 523 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) |
524 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 | 524 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 |
525 | #define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000 | 525 | #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) |
526 | #define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14)) | 526 | #define MVPP2_PRS_RI_L3_UN 0x0 |
527 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) | 527 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) |
528 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) | 528 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) |
529 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) | 529 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) |
530 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) | 530 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) |
531 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) | 531 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) |
532 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) | 532 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) |
533 | #define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000 | 533 | #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) |
534 | #define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16)) | 534 | #define MVPP2_PRS_RI_L3_UCAST 0x0 |
535 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) | 535 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) |
536 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) | 536 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) |
537 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 | 537 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 |