diff options
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/execlist.c | 30 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 30 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_shrinker.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 15 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lpe_audio.c | 36 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/selftests/i915_gem_context.c | 8 |
10 files changed, 55 insertions, 79 deletions
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index dca989eb2d42..24fe04d6307b 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c | |||
| @@ -779,8 +779,26 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) | |||
| 779 | vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; | 779 | vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; |
| 780 | } | 780 | } |
| 781 | 781 | ||
| 782 | static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) | ||
| 783 | { | ||
| 784 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | ||
| 785 | struct intel_engine_cs *engine; | ||
| 786 | struct intel_vgpu_workload *pos, *n; | ||
| 787 | unsigned int tmp; | ||
| 788 | |||
| 789 | /* free the unsubmited workloads in the queues. */ | ||
| 790 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { | ||
| 791 | list_for_each_entry_safe(pos, n, | ||
| 792 | &vgpu->workload_q_head[engine->id], list) { | ||
| 793 | list_del_init(&pos->list); | ||
| 794 | free_workload(pos); | ||
| 795 | } | ||
| 796 | } | ||
| 797 | } | ||
| 798 | |||
| 782 | void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu) | 799 | void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu) |
| 783 | { | 800 | { |
| 801 | clean_workloads(vgpu, ALL_ENGINES); | ||
| 784 | kmem_cache_destroy(vgpu->workloads); | 802 | kmem_cache_destroy(vgpu->workloads); |
| 785 | } | 803 | } |
| 786 | 804 | ||
| @@ -811,17 +829,9 @@ void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, | |||
| 811 | { | 829 | { |
| 812 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | 830 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; |
| 813 | struct intel_engine_cs *engine; | 831 | struct intel_engine_cs *engine; |
| 814 | struct intel_vgpu_workload *pos, *n; | ||
| 815 | unsigned int tmp; | 832 | unsigned int tmp; |
| 816 | 833 | ||
| 817 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { | 834 | clean_workloads(vgpu, engine_mask); |
| 818 | /* free the unsubmited workload in the queue */ | 835 | for_each_engine_masked(engine, dev_priv, engine_mask, tmp) |
| 819 | list_for_each_entry_safe(pos, n, | ||
| 820 | &vgpu->workload_q_head[engine->id], list) { | ||
| 821 | list_del_init(&pos->list); | ||
| 822 | free_workload(pos); | ||
| 823 | } | ||
| 824 | |||
| 825 | init_vgpu_execlist(vgpu, engine->id); | 836 | init_vgpu_execlist(vgpu, engine->id); |
| 826 | } | ||
| 827 | } | 837 | } |
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index c995e540ff96..0ffd69654592 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c | |||
| @@ -1366,18 +1366,28 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, | |||
| 1366 | void *p_data, unsigned int bytes) | 1366 | void *p_data, unsigned int bytes) |
| 1367 | { | 1367 | { |
| 1368 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | 1368 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; |
| 1369 | i915_reg_t reg = {.reg = offset}; | 1369 | u32 v = *(u32 *)p_data; |
| 1370 | |||
| 1371 | if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) | ||
| 1372 | return intel_vgpu_default_mmio_write(vgpu, | ||
| 1373 | offset, p_data, bytes); | ||
| 1370 | 1374 | ||
| 1371 | switch (offset) { | 1375 | switch (offset) { |
| 1372 | case 0x4ddc: | 1376 | case 0x4ddc: |
| 1373 | vgpu_vreg(vgpu, offset) = 0x8000003c; | 1377 | /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ |
| 1374 | /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ | 1378 | vgpu_vreg(vgpu, offset) = v & ~(1 << 31); |
| 1375 | I915_WRITE(reg, vgpu_vreg(vgpu, offset)); | ||
| 1376 | break; | 1379 | break; |
| 1377 | case 0x42080: | 1380 | case 0x42080: |
| 1378 | vgpu_vreg(vgpu, offset) = 0x8000; | 1381 | /* bypass WaCompressedResourceDisplayNewHashMode */ |
| 1379 | /* WaCompressedResourceDisplayNewHashMode:skl */ | 1382 | vgpu_vreg(vgpu, offset) = v & ~(1 << 15); |
| 1380 | I915_WRITE(reg, vgpu_vreg(vgpu, offset)); | 1383 | break; |
| 1384 | case 0xe194: | ||
| 1385 | /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ | ||
| 1386 | vgpu_vreg(vgpu, offset) = v & ~(1 << 8); | ||
| 1387 | break; | ||
| 1388 | case 0x7014: | ||
| 1389 | /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ | ||
| 1390 | vgpu_vreg(vgpu, offset) = v & ~(1 << 13); | ||
| 1381 | break; | 1391 | break; |
| 1382 | default: | 1392 | default: |
| 1383 | return -EINVAL; | 1393 | return -EINVAL; |
| @@ -1634,7 +1644,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) | |||
| 1634 | MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); | 1644 | MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); |
| 1635 | MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, | 1645 | MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, |
| 1636 | NULL, NULL); | 1646 | NULL, NULL); |
| 1637 | MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | 1647 | MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, |
| 1648 | skl_misc_ctl_write); | ||
| 1638 | MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); | 1649 | MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); |
| 1639 | MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); | 1650 | MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); |
| 1640 | MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); | 1651 | MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); |
| @@ -2568,7 +2579,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) | |||
| 2568 | MMIO_D(0x6e570, D_BDW_PLUS); | 2579 | MMIO_D(0x6e570, D_BDW_PLUS); |
| 2569 | MMIO_D(0x65f10, D_BDW_PLUS); | 2580 | MMIO_D(0x65f10, D_BDW_PLUS); |
| 2570 | 2581 | ||
| 2571 | MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | 2582 | MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, |
| 2583 | skl_misc_ctl_write); | ||
| 2572 | MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | 2584 | MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
| 2573 | MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | 2585 | MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
| 2574 | MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | 2586 | MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3036d4835b0f..c994fe6e65b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
| @@ -1272,10 +1272,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 1272 | 1272 | ||
| 1273 | dev_priv->ipc_enabled = false; | 1273 | dev_priv->ipc_enabled = false; |
| 1274 | 1274 | ||
| 1275 | /* Everything is in place, we can now relax! */ | ||
| 1276 | DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", | ||
| 1277 | driver.name, driver.major, driver.minor, driver.patchlevel, | ||
| 1278 | driver.date, pci_name(pdev), dev_priv->drm.primary->index); | ||
| 1279 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) | 1275 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) |
| 1280 | DRM_INFO("DRM_I915_DEBUG enabled\n"); | 1276 | DRM_INFO("DRM_I915_DEBUG enabled\n"); |
| 1281 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) | 1277 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a0563e18d753..50b8f1139ff9 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
| @@ -2313,7 +2313,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |||
| 2313 | appgtt->base.allocate_va_range) { | 2313 | appgtt->base.allocate_va_range) { |
| 2314 | ret = appgtt->base.allocate_va_range(&appgtt->base, | 2314 | ret = appgtt->base.allocate_va_range(&appgtt->base, |
| 2315 | vma->node.start, | 2315 | vma->node.start, |
| 2316 | vma->node.size); | 2316 | vma->size); |
| 2317 | if (ret) | 2317 | if (ret) |
| 2318 | goto err_pages; | 2318 | goto err_pages; |
| 2319 | } | 2319 | } |
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 129ed303a6c4..57d9f7f4ef15 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c | |||
| @@ -59,9 +59,6 @@ static void i915_gem_shrinker_unlock(struct drm_device *dev, bool unlock) | |||
| 59 | return; | 59 | return; |
| 60 | 60 | ||
| 61 | mutex_unlock(&dev->struct_mutex); | 61 | mutex_unlock(&dev->struct_mutex); |
| 62 | |||
| 63 | /* expedite the RCU grace period to free some request slabs */ | ||
| 64 | synchronize_rcu_expedited(); | ||
| 65 | } | 62 | } |
| 66 | 63 | ||
| 67 | static bool any_vma_pinned(struct drm_i915_gem_object *obj) | 64 | static bool any_vma_pinned(struct drm_i915_gem_object *obj) |
| @@ -274,8 +271,6 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |||
| 274 | I915_SHRINK_ACTIVE); | 271 | I915_SHRINK_ACTIVE); |
| 275 | intel_runtime_pm_put(dev_priv); | 272 | intel_runtime_pm_put(dev_priv); |
| 276 | 273 | ||
| 277 | synchronize_rcu(); /* wait for our earlier RCU delayed slab frees */ | ||
| 278 | |||
| 279 | return freed; | 274 | return freed; |
| 280 | } | 275 | } |
| 281 | 276 | ||
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fd97fe00cd0d..190f6aa5d15e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
| @@ -2953,7 +2953,6 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) | |||
| 2953 | u32 pipestat_mask; | 2953 | u32 pipestat_mask; |
| 2954 | u32 enable_mask; | 2954 | u32 enable_mask; |
| 2955 | enum pipe pipe; | 2955 | enum pipe pipe; |
| 2956 | u32 val; | ||
| 2957 | 2956 | ||
| 2958 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | 2957 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 2959 | PIPE_CRC_DONE_INTERRUPT_STATUS; | 2958 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
| @@ -2964,18 +2963,16 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) | |||
| 2964 | 2963 | ||
| 2965 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | | 2964 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 2966 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | 2965 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2967 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | 2966 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2967 | I915_LPE_PIPE_A_INTERRUPT | | ||
| 2968 | I915_LPE_PIPE_B_INTERRUPT; | ||
| 2969 | |||
| 2968 | if (IS_CHERRYVIEW(dev_priv)) | 2970 | if (IS_CHERRYVIEW(dev_priv)) |
| 2969 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | 2971 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | |
| 2972 | I915_LPE_PIPE_C_INTERRUPT; | ||
| 2970 | 2973 | ||
| 2971 | WARN_ON(dev_priv->irq_mask != ~0); | 2974 | WARN_ON(dev_priv->irq_mask != ~0); |
| 2972 | 2975 | ||
| 2973 | val = (I915_LPE_PIPE_A_INTERRUPT | | ||
| 2974 | I915_LPE_PIPE_B_INTERRUPT | | ||
| 2975 | I915_LPE_PIPE_C_INTERRUPT); | ||
| 2976 | |||
| 2977 | enable_mask |= val; | ||
| 2978 | |||
| 2979 | dev_priv->irq_mask = ~enable_mask; | 2976 | dev_priv->irq_mask = ~enable_mask; |
| 2980 | 2977 | ||
| 2981 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | 2978 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5a7c63e64381..65b837e96fe6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -8280,7 +8280,7 @@ enum { | |||
| 8280 | 8280 | ||
| 8281 | /* MIPI DSI registers */ | 8281 | /* MIPI DSI registers */ |
| 8282 | 8282 | ||
| 8283 | #define _MIPI_PORT(port, a, c) ((port) ? c : a) /* ports A and C only */ | 8283 | #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ |
| 8284 | #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) | 8284 | #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) |
| 8285 | 8285 | ||
| 8286 | #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) | 8286 | #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) |
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c index 668f00480d97..292fedf30b00 100644 --- a/drivers/gpu/drm/i915/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/intel_lpe_audio.c | |||
| @@ -149,44 +149,10 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) | |||
| 149 | 149 | ||
| 150 | static void lpe_audio_irq_unmask(struct irq_data *d) | 150 | static void lpe_audio_irq_unmask(struct irq_data *d) |
| 151 | { | 151 | { |
| 152 | struct drm_i915_private *dev_priv = d->chip_data; | ||
| 153 | unsigned long irqflags; | ||
| 154 | u32 val = (I915_LPE_PIPE_A_INTERRUPT | | ||
| 155 | I915_LPE_PIPE_B_INTERRUPT); | ||
| 156 | |||
| 157 | if (IS_CHERRYVIEW(dev_priv)) | ||
| 158 | val |= I915_LPE_PIPE_C_INTERRUPT; | ||
| 159 | |||
| 160 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | ||
| 161 | |||
| 162 | dev_priv->irq_mask &= ~val; | ||
| 163 | I915_WRITE(VLV_IIR, val); | ||
| 164 | I915_WRITE(VLV_IIR, val); | ||
| 165 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | ||
| 166 | POSTING_READ(VLV_IMR); | ||
| 167 | |||
| 168 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
| 169 | } | 152 | } |
| 170 | 153 | ||
| 171 | static void lpe_audio_irq_mask(struct irq_data *d) | 154 | static void lpe_audio_irq_mask(struct irq_data *d) |
| 172 | { | 155 | { |
| 173 | struct drm_i915_private *dev_priv = d->chip_data; | ||
| 174 | unsigned long irqflags; | ||
| 175 | u32 val = (I915_LPE_PIPE_A_INTERRUPT | | ||
| 176 | I915_LPE_PIPE_B_INTERRUPT); | ||
| 177 | |||
| 178 | if (IS_CHERRYVIEW(dev_priv)) | ||
| 179 | val |= I915_LPE_PIPE_C_INTERRUPT; | ||
| 180 | |||
| 181 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | ||
| 182 | |||
| 183 | dev_priv->irq_mask |= val; | ||
| 184 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | ||
| 185 | I915_WRITE(VLV_IIR, val); | ||
| 186 | I915_WRITE(VLV_IIR, val); | ||
| 187 | POSTING_READ(VLV_IIR); | ||
| 188 | |||
| 189 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
| 190 | } | 156 | } |
| 191 | 157 | ||
| 192 | static struct irq_chip lpe_audio_irqchip = { | 158 | static struct irq_chip lpe_audio_irqchip = { |
| @@ -330,8 +296,6 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) | |||
| 330 | 296 | ||
| 331 | desc = irq_to_desc(dev_priv->lpe_audio.irq); | 297 | desc = irq_to_desc(dev_priv->lpe_audio.irq); |
| 332 | 298 | ||
| 333 | lpe_audio_irq_mask(&desc->irq_data); | ||
| 334 | |||
| 335 | lpe_audio_platdev_destroy(dev_priv); | 299 | lpe_audio_platdev_destroy(dev_priv); |
| 336 | 300 | ||
| 337 | irq_free_desc(dev_priv->lpe_audio.irq); | 301 | irq_free_desc(dev_priv->lpe_audio.irq); |
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c8f7c631fc1f..dac4e003c1f3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c | |||
| @@ -1989,7 +1989,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, | |||
| 1989 | 1989 | ||
| 1990 | ce->ring = ring; | 1990 | ce->ring = ring; |
| 1991 | ce->state = vma; | 1991 | ce->state = vma; |
| 1992 | ce->initialised = engine->init_context == NULL; | 1992 | ce->initialised |= engine->init_context == NULL; |
| 1993 | 1993 | ||
| 1994 | return 0; | 1994 | return 0; |
| 1995 | 1995 | ||
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 1afb8b06e3e1..12b85b3278cd 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c | |||
| @@ -320,7 +320,7 @@ static unsigned long max_dwords(struct drm_i915_gem_object *obj) | |||
| 320 | static int igt_ctx_exec(void *arg) | 320 | static int igt_ctx_exec(void *arg) |
| 321 | { | 321 | { |
| 322 | struct drm_i915_private *i915 = arg; | 322 | struct drm_i915_private *i915 = arg; |
| 323 | struct drm_i915_gem_object *obj; | 323 | struct drm_i915_gem_object *obj = NULL; |
| 324 | struct drm_file *file; | 324 | struct drm_file *file; |
| 325 | IGT_TIMEOUT(end_time); | 325 | IGT_TIMEOUT(end_time); |
| 326 | LIST_HEAD(objects); | 326 | LIST_HEAD(objects); |
| @@ -359,7 +359,7 @@ static int igt_ctx_exec(void *arg) | |||
| 359 | } | 359 | } |
| 360 | 360 | ||
| 361 | for_each_engine(engine, i915, id) { | 361 | for_each_engine(engine, i915, id) { |
| 362 | if (dw == 0) { | 362 | if (!obj) { |
| 363 | obj = create_test_object(ctx, file, &objects); | 363 | obj = create_test_object(ctx, file, &objects); |
| 364 | if (IS_ERR(obj)) { | 364 | if (IS_ERR(obj)) { |
| 365 | err = PTR_ERR(obj); | 365 | err = PTR_ERR(obj); |
| @@ -376,8 +376,10 @@ static int igt_ctx_exec(void *arg) | |||
| 376 | goto out_unlock; | 376 | goto out_unlock; |
| 377 | } | 377 | } |
| 378 | 378 | ||
| 379 | if (++dw == max_dwords(obj)) | 379 | if (++dw == max_dwords(obj)) { |
| 380 | obj = NULL; | ||
| 380 | dw = 0; | 381 | dw = 0; |
| 382 | } | ||
| 381 | ndwords++; | 383 | ndwords++; |
| 382 | } | 384 | } |
| 383 | ncontexts++; | 385 | ncontexts++; |
