diff options
author | Andi Kleen <ak@linux.intel.com> | 2016-03-21 11:56:33 -0400 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2016-03-22 09:01:45 -0400 |
commit | 4ca0d8193f8b6b2c74d05d9bbcbaa99fdd553503 (patch) | |
tree | a2179975234d8c61d43ef9d6fe5591115926cfa3 /tools | |
parent | 3c52b658b8e4fbbf7975932bbdc4798421dbcb15 (diff) |
perf list: Fix documentation of :ppp
Correctly document what is implemented for :ppp on Intel CPUs in recent
kernels.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1458575793-12091-2-git-send-email-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools')
-rw-r--r-- | tools/perf/Documentation/perf-list.txt | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index 79483f40e991..ec723d0a5bb3 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt | |||
@@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times: | |||
40 | 0 - SAMPLE_IP can have arbitrary skid | 40 | 0 - SAMPLE_IP can have arbitrary skid |
41 | 1 - SAMPLE_IP must have constant skid | 41 | 1 - SAMPLE_IP must have constant skid |
42 | 2 - SAMPLE_IP requested to have 0 skid | 42 | 2 - SAMPLE_IP requested to have 0 skid |
43 | 3 - SAMPLE_IP must have 0 skid | 43 | 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid |
44 | sample shadowing effects. | ||
44 | 45 | ||
45 | For Intel systems precise event sampling is implemented with PEBS | 46 | For Intel systems precise event sampling is implemented with PEBS |
46 | which supports up to precise-level 2. | 47 | which supports up to precise-level 2, and precise level 3 for |
48 | some special cases | ||
47 | 49 | ||
48 | On AMD systems it is implemented using IBS (up to precise-level 2). | 50 | On AMD systems it is implemented using IBS (up to precise-level 2). |
49 | The precise modifier works with event types 0x76 (cpu-cycles, CPU | 51 | The precise modifier works with event types 0x76 (cpu-cycles, CPU |