diff options
| author | Oder Chiou <oder_chiou@realtek.com> | 2014-04-28 07:59:10 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-05-03 13:36:10 -0400 |
| commit | 1319b2f6a565231ca2e3f368ab7f74fc4714c799 (patch) | |
| tree | 53c72251c9aa2f864e56dce60729bb446e5140ea /sound/soc/codecs/rt5645.h | |
| parent | 871c131dcbee80e9459bf695c8c5cfd6bf0d26d6 (diff) | |
ASoC: rt5645: Add codec driver
This patch adds the Realtek ALC5645 codec driver. It is the base
version that because the jack detect function is not implemented to
it, the headphone and AMIC1 are not workable. We will fill up the
further functions later.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/codecs/rt5645.h')
| -rw-r--r-- | sound/soc/codecs/rt5645.h | 2188 |
1 files changed, 2188 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h new file mode 100644 index 000000000000..345aa3f5d14f --- /dev/null +++ b/sound/soc/codecs/rt5645.h | |||
| @@ -0,0 +1,2188 @@ | |||
| 1 | /* | ||
| 2 | * rt5645.h -- RT5645 ALSA SoC audio driver | ||
| 3 | * | ||
| 4 | * Copyright 2013 Realtek Microelectronics | ||
| 5 | * Author: Bard Liao <bardliao@realtek.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __RT5645_H__ | ||
| 13 | #define __RT5645_H__ | ||
| 14 | |||
| 15 | #include <sound/rt5645.h> | ||
| 16 | |||
| 17 | /* Info */ | ||
| 18 | #define RT5645_RESET 0x00 | ||
| 19 | #define RT5645_VENDOR_ID 0xfd | ||
| 20 | #define RT5645_VENDOR_ID1 0xfe | ||
| 21 | #define RT5645_VENDOR_ID2 0xff | ||
| 22 | /* I/O - Output */ | ||
| 23 | #define RT5645_SPK_VOL 0x01 | ||
| 24 | #define RT5645_HP_VOL 0x02 | ||
| 25 | #define RT5645_LOUT1 0x03 | ||
| 26 | #define RT5645_LOUT_CTRL 0x05 | ||
| 27 | /* I/O - Input */ | ||
| 28 | #define RT5645_IN1_CTRL1 0x0a | ||
| 29 | #define RT5645_IN1_CTRL2 0x0b | ||
| 30 | #define RT5645_IN1_CTRL3 0x0c | ||
| 31 | #define RT5645_IN2_CTRL 0x0d | ||
| 32 | #define RT5645_INL1_INR1_VOL 0x0f | ||
| 33 | #define RT5645_SPK_FUNC_LIM 0x14 | ||
| 34 | #define RT5645_ADJ_HPF_CTRL 0x16 | ||
| 35 | /* I/O - ADC/DAC/DMIC */ | ||
| 36 | #define RT5645_DAC1_DIG_VOL 0x19 | ||
| 37 | #define RT5645_DAC2_DIG_VOL 0x1a | ||
| 38 | #define RT5645_DAC_CTRL 0x1b | ||
| 39 | #define RT5645_STO1_ADC_DIG_VOL 0x1c | ||
| 40 | #define RT5645_MONO_ADC_DIG_VOL 0x1d | ||
| 41 | #define RT5645_ADC_BST_VOL1 0x1e | ||
| 42 | /* Mixer - D-D */ | ||
| 43 | #define RT5645_ADC_BST_VOL2 0x20 | ||
| 44 | #define RT5645_STO1_ADC_MIXER 0x27 | ||
| 45 | #define RT5645_MONO_ADC_MIXER 0x28 | ||
| 46 | #define RT5645_AD_DA_MIXER 0x29 | ||
| 47 | #define RT5645_STO_DAC_MIXER 0x2a | ||
| 48 | #define RT5645_MONO_DAC_MIXER 0x2b | ||
| 49 | #define RT5645_DIG_MIXER 0x2c | ||
| 50 | #define RT5645_DIG_INF1_DATA 0x2f | ||
| 51 | /* Mixer - PDM */ | ||
| 52 | #define RT5645_PDM_OUT_CTRL 0x31 | ||
| 53 | /* Mixer - ADC */ | ||
| 54 | #define RT5645_REC_L1_MIXER 0x3b | ||
| 55 | #define RT5645_REC_L2_MIXER 0x3c | ||
| 56 | #define RT5645_REC_R1_MIXER 0x3d | ||
| 57 | #define RT5645_REC_R2_MIXER 0x3e | ||
| 58 | /* Mixer - DAC */ | ||
| 59 | #define RT5645_HPMIXL_CTRL 0x3f | ||
| 60 | #define RT5645_HPOMIXL_CTRL 0x40 | ||
| 61 | #define RT5645_HPMIXR_CTRL 0x41 | ||
| 62 | #define RT5645_HPOMIXR_CTRL 0x42 | ||
| 63 | #define RT5645_HPO_MIXER 0x45 | ||
| 64 | #define RT5645_SPK_L_MIXER 0x46 | ||
| 65 | #define RT5645_SPK_R_MIXER 0x47 | ||
| 66 | #define RT5645_SPO_MIXER 0x48 | ||
| 67 | #define RT5645_SPO_CLSD_RATIO 0x4a | ||
| 68 | #define RT5645_OUT_L_GAIN1 0x4d | ||
| 69 | #define RT5645_OUT_L_GAIN2 0x4e | ||
| 70 | #define RT5645_OUT_L1_MIXER 0x4f | ||
| 71 | #define RT5645_OUT_R_GAIN1 0x50 | ||
| 72 | #define RT5645_OUT_R_GAIN2 0x51 | ||
| 73 | #define RT5645_OUT_R1_MIXER 0x52 | ||
| 74 | #define RT5645_LOUT_MIXER 0x53 | ||
| 75 | /* Haptic */ | ||
| 76 | #define RT5645_HAPTIC_CTRL1 0x56 | ||
| 77 | #define RT5645_HAPTIC_CTRL2 0x57 | ||
| 78 | #define RT5645_HAPTIC_CTRL3 0x58 | ||
| 79 | #define RT5645_HAPTIC_CTRL4 0x59 | ||
| 80 | #define RT5645_HAPTIC_CTRL5 0x5a | ||
| 81 | #define RT5645_HAPTIC_CTRL6 0x5b | ||
| 82 | #define RT5645_HAPTIC_CTRL7 0x5c | ||
| 83 | #define RT5645_HAPTIC_CTRL8 0x5d | ||
| 84 | #define RT5645_HAPTIC_CTRL9 0x5e | ||
| 85 | #define RT5645_HAPTIC_CTRL10 0x5f | ||
| 86 | /* Power */ | ||
| 87 | #define RT5645_PWR_DIG1 0x61 | ||
| 88 | #define RT5645_PWR_DIG2 0x62 | ||
| 89 | #define RT5645_PWR_ANLG1 0x63 | ||
| 90 | #define RT5645_PWR_ANLG2 0x64 | ||
| 91 | #define RT5645_PWR_MIXER 0x65 | ||
| 92 | #define RT5645_PWR_VOL 0x66 | ||
| 93 | /* Private Register Control */ | ||
| 94 | #define RT5645_PRIV_INDEX 0x6a | ||
| 95 | #define RT5645_PRIV_DATA 0x6c | ||
| 96 | /* Format - ADC/DAC */ | ||
| 97 | #define RT5645_I2S1_SDP 0x70 | ||
| 98 | #define RT5645_I2S2_SDP 0x71 | ||
| 99 | #define RT5645_ADDA_CLK1 0x73 | ||
| 100 | #define RT5645_ADDA_CLK2 0x74 | ||
| 101 | #define RT5645_DMIC_CTRL1 0x75 | ||
| 102 | #define RT5645_DMIC_CTRL2 0x76 | ||
| 103 | /* Format - TDM Control */ | ||
| 104 | #define RT5645_TDM_CTRL_1 0x77 | ||
| 105 | #define RT5645_TDM_CTRL_2 0x78 | ||
| 106 | #define RT5645_TDM_CTRL_3 0x79 | ||
| 107 | |||
| 108 | /* Function - Analog */ | ||
| 109 | #define RT5645_GLB_CLK 0x80 | ||
| 110 | #define RT5645_PLL_CTRL1 0x81 | ||
| 111 | #define RT5645_PLL_CTRL2 0x82 | ||
| 112 | #define RT5645_ASRC_1 0x83 | ||
| 113 | #define RT5645_ASRC_2 0x84 | ||
| 114 | #define RT5645_ASRC_3 0x85 | ||
| 115 | #define RT5645_ASRC_4 0x8a | ||
| 116 | #define RT5645_DEPOP_M1 0x8e | ||
| 117 | #define RT5645_DEPOP_M2 0x8f | ||
| 118 | #define RT5645_DEPOP_M3 0x90 | ||
| 119 | #define RT5645_CHARGE_PUMP 0x91 | ||
| 120 | #define RT5645_MICBIAS 0x93 | ||
| 121 | #define RT5645_A_JD_CTRL1 0x94 | ||
| 122 | #define RT5645_VAD_CTRL4 0x9d | ||
| 123 | #define RT5645_CLSD_OUT_CTRL 0xa0 | ||
| 124 | /* Function - Digital */ | ||
| 125 | #define RT5645_ADC_EQ_CTRL1 0xae | ||
| 126 | #define RT5645_ADC_EQ_CTRL2 0xaf | ||
| 127 | #define RT5645_EQ_CTRL1 0xb0 | ||
| 128 | #define RT5645_EQ_CTRL2 0xb1 | ||
| 129 | #define RT5645_ALC_CTRL_1 0xb3 | ||
| 130 | #define RT5645_ALC_CTRL_2 0xb4 | ||
| 131 | #define RT5645_ALC_CTRL_3 0xb5 | ||
| 132 | #define RT5645_ALC_CTRL_4 0xb6 | ||
| 133 | #define RT5645_ALC_CTRL_5 0xb7 | ||
| 134 | #define RT5645_JD_CTRL 0xbb | ||
| 135 | #define RT5645_IRQ_CTRL1 0xbc | ||
| 136 | #define RT5645_IRQ_CTRL2 0xbd | ||
| 137 | #define RT5645_IRQ_CTRL3 0xbe | ||
| 138 | #define RT5645_INT_IRQ_ST 0xbf | ||
| 139 | #define RT5645_GPIO_CTRL1 0xc0 | ||
| 140 | #define RT5645_GPIO_CTRL2 0xc1 | ||
| 141 | #define RT5645_GPIO_CTRL3 0xc2 | ||
| 142 | #define RT5645_BASS_BACK 0xcf | ||
| 143 | #define RT5645_MP3_PLUS1 0xd0 | ||
| 144 | #define RT5645_MP3_PLUS2 0xd1 | ||
| 145 | #define RT5645_ADJ_HPF1 0xd3 | ||
| 146 | #define RT5645_ADJ_HPF2 0xd4 | ||
| 147 | #define RT5645_HP_CALIB_AMP_DET 0xd6 | ||
| 148 | #define RT5645_SV_ZCD1 0xd9 | ||
| 149 | #define RT5645_SV_ZCD2 0xda | ||
| 150 | #define RT5645_IL_CMD 0xdb | ||
| 151 | #define RT5645_IL_CMD2 0xdc | ||
| 152 | #define RT5645_IL_CMD3 0xdd | ||
| 153 | #define RT5645_DRC1_HL_CTRL1 0xe7 | ||
| 154 | #define RT5645_DRC2_HL_CTRL1 0xe9 | ||
| 155 | #define RT5645_MUTI_DRC_CTRL1 0xea | ||
| 156 | #define RT5645_ADC_MONO_HP_CTRL1 0xec | ||
| 157 | #define RT5645_ADC_MONO_HP_CTRL2 0xed | ||
| 158 | #define RT5645_DRC2_CTRL1 0xf0 | ||
| 159 | #define RT5645_DRC2_CTRL2 0xf1 | ||
| 160 | #define RT5645_DRC2_CTRL3 0xf2 | ||
| 161 | #define RT5645_DRC2_CTRL4 0xf3 | ||
| 162 | #define RT5645_DRC2_CTRL5 0xf4 | ||
| 163 | #define RT5645_JD_CTRL3 0xf8 | ||
| 164 | #define RT5645_JD_CTRL4 0xf9 | ||
| 165 | /* General Control */ | ||
| 166 | #define RT5645_GEN_CTRL1 0xfa | ||
| 167 | #define RT5645_GEN_CTRL2 0xfb | ||
| 168 | #define RT5645_GEN_CTRL3 0xfc | ||
| 169 | |||
| 170 | |||
| 171 | /* Index of Codec Private Register definition */ | ||
| 172 | #define RT5645_DIG_VOL 0x00 | ||
| 173 | #define RT5645_PR_ALC_CTRL_1 0x01 | ||
| 174 | #define RT5645_PR_ALC_CTRL_2 0x02 | ||
| 175 | #define RT5645_PR_ALC_CTRL_3 0x03 | ||
| 176 | #define RT5645_PR_ALC_CTRL_4 0x04 | ||
| 177 | #define RT5645_PR_ALC_CTRL_5 0x05 | ||
| 178 | #define RT5645_PR_ALC_CTRL_6 0x06 | ||
| 179 | #define RT5645_BIAS_CUR1 0x12 | ||
| 180 | #define RT5645_BIAS_CUR3 0x14 | ||
| 181 | #define RT5645_CLSD_INT_REG1 0x1c | ||
| 182 | #define RT5645_MAMP_INT_REG2 0x37 | ||
| 183 | #define RT5645_CHOP_DAC_ADC 0x3d | ||
| 184 | #define RT5645_MIXER_INT_REG 0x3f | ||
| 185 | #define RT5645_3D_SPK 0x63 | ||
| 186 | #define RT5645_WND_1 0x6c | ||
| 187 | #define RT5645_WND_2 0x6d | ||
| 188 | #define RT5645_WND_3 0x6e | ||
| 189 | #define RT5645_WND_4 0x6f | ||
| 190 | #define RT5645_WND_5 0x70 | ||
| 191 | #define RT5645_WND_8 0x73 | ||
| 192 | #define RT5645_DIP_SPK_INF 0x75 | ||
| 193 | #define RT5645_HP_DCC_INT1 0x77 | ||
| 194 | #define RT5645_EQ_BW_LOP 0xa0 | ||
| 195 | #define RT5645_EQ_GN_LOP 0xa1 | ||
| 196 | #define RT5645_EQ_FC_BP1 0xa2 | ||
| 197 | #define RT5645_EQ_BW_BP1 0xa3 | ||
| 198 | #define RT5645_EQ_GN_BP1 0xa4 | ||
| 199 | #define RT5645_EQ_FC_BP2 0xa5 | ||
| 200 | #define RT5645_EQ_BW_BP2 0xa6 | ||
| 201 | #define RT5645_EQ_GN_BP2 0xa7 | ||
| 202 | #define RT5645_EQ_FC_BP3 0xa8 | ||
| 203 | #define RT5645_EQ_BW_BP3 0xa9 | ||
| 204 | #define RT5645_EQ_GN_BP3 0xaa | ||
| 205 | #define RT5645_EQ_FC_BP4 0xab | ||
| 206 | #define RT5645_EQ_BW_BP4 0xac | ||
| 207 | #define RT5645_EQ_GN_BP4 0xad | ||
| 208 | #define RT5645_EQ_FC_HIP1 0xae | ||
| 209 | #define RT5645_EQ_GN_HIP1 0xaf | ||
| 210 | #define RT5645_EQ_FC_HIP2 0xb0 | ||
| 211 | #define RT5645_EQ_BW_HIP2 0xb1 | ||
| 212 | #define RT5645_EQ_GN_HIP2 0xb2 | ||
| 213 | #define RT5645_EQ_PRE_VOL 0xb3 | ||
| 214 | #define RT5645_EQ_PST_VOL 0xb4 | ||
| 215 | |||
| 216 | |||
| 217 | /* global definition */ | ||
| 218 | #define RT5645_L_MUTE (0x1 << 15) | ||
| 219 | #define RT5645_L_MUTE_SFT 15 | ||
| 220 | #define RT5645_VOL_L_MUTE (0x1 << 14) | ||
| 221 | #define RT5645_VOL_L_SFT 14 | ||
| 222 | #define RT5645_R_MUTE (0x1 << 7) | ||
| 223 | #define RT5645_R_MUTE_SFT 7 | ||
| 224 | #define RT5645_VOL_R_MUTE (0x1 << 6) | ||
| 225 | #define RT5645_VOL_R_SFT 6 | ||
| 226 | #define RT5645_L_VOL_MASK (0x3f << 8) | ||
| 227 | #define RT5645_L_VOL_SFT 8 | ||
| 228 | #define RT5645_R_VOL_MASK (0x3f) | ||
| 229 | #define RT5645_R_VOL_SFT 0 | ||
| 230 | |||
| 231 | /* IN1 Control 1 (0x0a) */ | ||
| 232 | #define RT5645_CBJ_BST1_MASK (0xf << 12) | ||
| 233 | #define RT5645_CBJ_BST1_SFT (12) | ||
| 234 | #define RT5645_CBJ_JD_HP_EN (0x1 << 9) | ||
| 235 | #define RT5645_CBJ_JD_MIC_EN (0x1 << 8) | ||
| 236 | #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7) | ||
| 237 | #define RT5645_CBJ_MIC_SEL_R (0x1 << 6) | ||
| 238 | #define RT5645_CBJ_MIC_SEL_L (0x1 << 5) | ||
| 239 | #define RT5645_CBJ_MIC_SW (0x1 << 4) | ||
| 240 | #define RT5645_CBJ_BST1_EN (0x1 << 2) | ||
| 241 | |||
| 242 | /* IN1 Control 2 (0x0b) */ | ||
| 243 | #define RT5645_CBJ_MN_JD (0x1 << 12) | ||
| 244 | #define RT5645_CAPLESS_EN (0x1 << 11) | ||
| 245 | #define RT5645_CBJ_DET_MODE (0x1 << 7) | ||
| 246 | |||
| 247 | /* IN1 Control 3 (0x0c) */ | ||
| 248 | #define RT5645_CBJ_TIE_G_L (0x1 << 15) | ||
| 249 | #define RT5645_CBJ_TIE_G_R (0x1 << 14) | ||
| 250 | |||
| 251 | /* IN2 Control (0x0d) */ | ||
| 252 | #define RT5645_BST_MASK1 (0xf<<12) | ||
| 253 | #define RT5645_BST_SFT1 12 | ||
| 254 | #define RT5645_BST_MASK2 (0xf<<8) | ||
| 255 | #define RT5645_BST_SFT2 8 | ||
| 256 | #define RT5645_IN_DF2 (0x1 << 6) | ||
| 257 | #define RT5645_IN_SFT2 6 | ||
| 258 | |||
| 259 | /* INL and INR Volume Control (0x0f) */ | ||
| 260 | #define RT5645_INL_SEL_MASK (0x1 << 15) | ||
| 261 | #define RT5645_INL_SEL_SFT 15 | ||
| 262 | #define RT5645_INL_SEL_IN4P (0x0 << 15) | ||
| 263 | #define RT5645_INL_SEL_MONOP (0x1 << 15) | ||
| 264 | #define RT5645_INL_VOL_MASK (0x1f << 8) | ||
| 265 | #define RT5645_INL_VOL_SFT 8 | ||
| 266 | #define RT5645_INR_SEL_MASK (0x1 << 7) | ||
| 267 | #define RT5645_INR_SEL_SFT 7 | ||
| 268 | #define RT5645_INR_SEL_IN4N (0x0 << 7) | ||
| 269 | #define RT5645_INR_SEL_MONON (0x1 << 7) | ||
| 270 | #define RT5645_INR_VOL_MASK (0x1f) | ||
| 271 | #define RT5645_INR_VOL_SFT 0 | ||
| 272 | |||
| 273 | /* DAC1 Digital Volume (0x19) */ | ||
| 274 | #define RT5645_DAC_L1_VOL_MASK (0xff << 8) | ||
| 275 | #define RT5645_DAC_L1_VOL_SFT 8 | ||
| 276 | #define RT5645_DAC_R1_VOL_MASK (0xff) | ||
| 277 | #define RT5645_DAC_R1_VOL_SFT 0 | ||
| 278 | |||
| 279 | /* DAC2 Digital Volume (0x1a) */ | ||
| 280 | #define RT5645_DAC_L2_VOL_MASK (0xff << 8) | ||
| 281 | #define RT5645_DAC_L2_VOL_SFT 8 | ||
| 282 | #define RT5645_DAC_R2_VOL_MASK (0xff) | ||
| 283 | #define RT5645_DAC_R2_VOL_SFT 0 | ||
| 284 | |||
| 285 | /* DAC2 Control (0x1b) */ | ||
| 286 | #define RT5645_M_DAC_L2_VOL (0x1 << 13) | ||
| 287 | #define RT5645_M_DAC_L2_VOL_SFT 13 | ||
| 288 | #define RT5645_M_DAC_R2_VOL (0x1 << 12) | ||
| 289 | #define RT5645_M_DAC_R2_VOL_SFT 12 | ||
| 290 | #define RT5645_DAC2_L_SEL_MASK (0x7 << 4) | ||
| 291 | #define RT5645_DAC2_L_SEL_SFT 4 | ||
| 292 | #define RT5645_DAC2_R_SEL_MASK (0x7 << 0) | ||
| 293 | #define RT5645_DAC2_R_SEL_SFT 0 | ||
| 294 | |||
| 295 | /* ADC Digital Volume Control (0x1c) */ | ||
| 296 | #define RT5645_ADC_L_VOL_MASK (0x7f << 8) | ||
| 297 | #define RT5645_ADC_L_VOL_SFT 8 | ||
| 298 | #define RT5645_ADC_R_VOL_MASK (0x7f) | ||
| 299 | #define RT5645_ADC_R_VOL_SFT 0 | ||
| 300 | |||
| 301 | /* Mono ADC Digital Volume Control (0x1d) */ | ||
| 302 | #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8) | ||
| 303 | #define RT5645_MONO_ADC_L_VOL_SFT 8 | ||
| 304 | #define RT5645_MONO_ADC_R_VOL_MASK (0x7f) | ||
| 305 | #define RT5645_MONO_ADC_R_VOL_SFT 0 | ||
| 306 | |||
| 307 | /* ADC Boost Volume Control (0x1e) */ | ||
| 308 | #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14) | ||
| 309 | #define RT5645_STO1_ADC_L_BST_SFT 14 | ||
| 310 | #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12) | ||
| 311 | #define RT5645_STO1_ADC_R_BST_SFT 12 | ||
| 312 | #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10) | ||
| 313 | #define RT5645_STO1_ADC_COMP_SFT 10 | ||
| 314 | #define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8) | ||
| 315 | #define RT5645_STO2_ADC_L_BST_SFT 8 | ||
| 316 | #define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6) | ||
| 317 | #define RT5645_STO2_ADC_R_BST_SFT 6 | ||
| 318 | #define RT5645_STO2_ADC_COMP_MASK (0x3 << 4) | ||
| 319 | #define RT5645_STO2_ADC_COMP_SFT 4 | ||
| 320 | |||
| 321 | /* Stereo2 ADC Mixer Control (0x26) */ | ||
| 322 | #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15) | ||
| 323 | #define RT5645_STO2_ADC_SRC_SFT 15 | ||
| 324 | |||
| 325 | /* Stereo ADC Mixer Control (0x27) */ | ||
| 326 | #define RT5645_M_ADC_L1 (0x1 << 14) | ||
| 327 | #define RT5645_M_ADC_L1_SFT 14 | ||
| 328 | #define RT5645_M_ADC_L2 (0x1 << 13) | ||
| 329 | #define RT5645_M_ADC_L2_SFT 13 | ||
| 330 | #define RT5645_ADC_1_SRC_MASK (0x1 << 12) | ||
| 331 | #define RT5645_ADC_1_SRC_SFT 12 | ||
| 332 | #define RT5645_ADC_1_SRC_ADC (0x1 << 12) | ||
| 333 | #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12) | ||
| 334 | #define RT5645_ADC_2_SRC_MASK (0x1 << 11) | ||
| 335 | #define RT5645_ADC_2_SRC_SFT 11 | ||
| 336 | #define RT5645_DMIC_SRC_MASK (0x1 << 8) | ||
| 337 | #define RT5645_DMIC_SRC_SFT 8 | ||
| 338 | #define RT5645_M_ADC_R1 (0x1 << 6) | ||
| 339 | #define RT5645_M_ADC_R1_SFT 6 | ||
| 340 | #define RT5645_M_ADC_R2 (0x1 << 5) | ||
| 341 | #define RT5645_M_ADC_R2_SFT 5 | ||
| 342 | #define RT5645_DMIC3_SRC_MASK (0x1 << 1) | ||
| 343 | #define RT5645_DMIC3_SRC_SFT 0 | ||
| 344 | |||
| 345 | /* Mono ADC Mixer Control (0x28) */ | ||
| 346 | #define RT5645_M_MONO_ADC_L1 (0x1 << 14) | ||
| 347 | #define RT5645_M_MONO_ADC_L1_SFT 14 | ||
| 348 | #define RT5645_M_MONO_ADC_L2 (0x1 << 13) | ||
| 349 | #define RT5645_M_MONO_ADC_L2_SFT 13 | ||
| 350 | #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12) | ||
| 351 | #define RT5645_MONO_ADC_L1_SRC_SFT 12 | ||
| 352 | #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) | ||
| 353 | #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12) | ||
| 354 | #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11) | ||
| 355 | #define RT5645_MONO_ADC_L2_SRC_SFT 11 | ||
| 356 | #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8) | ||
| 357 | #define RT5645_MONO_DMIC_L_SRC_SFT 8 | ||
| 358 | #define RT5645_M_MONO_ADC_R1 (0x1 << 6) | ||
| 359 | #define RT5645_M_MONO_ADC_R1_SFT 6 | ||
| 360 | #define RT5645_M_MONO_ADC_R2 (0x1 << 5) | ||
| 361 | #define RT5645_M_MONO_ADC_R2_SFT 5 | ||
| 362 | #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4) | ||
| 363 | #define RT5645_MONO_ADC_R1_SRC_SFT 4 | ||
| 364 | #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4) | ||
| 365 | #define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) | ||
| 366 | #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3) | ||
| 367 | #define RT5645_MONO_ADC_R2_SRC_SFT 3 | ||
| 368 | #define RT5645_MONO_DMIC_R_SRC_MASK (0x3) | ||
| 369 | #define RT5645_MONO_DMIC_R_SRC_SFT 0 | ||
| 370 | |||
| 371 | /* ADC Mixer to DAC Mixer Control (0x29) */ | ||
| 372 | #define RT5645_M_ADCMIX_L (0x1 << 15) | ||
| 373 | #define RT5645_M_ADCMIX_L_SFT 15 | ||
| 374 | #define RT5645_M_DAC1_L (0x1 << 14) | ||
| 375 | #define RT5645_M_DAC1_L_SFT 14 | ||
| 376 | #define RT5645_DAC1_R_SEL_MASK (0x3 << 10) | ||
| 377 | #define RT5645_DAC1_R_SEL_SFT 10 | ||
| 378 | #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10) | ||
| 379 | #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10) | ||
| 380 | #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10) | ||
| 381 | #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10) | ||
| 382 | #define RT5645_DAC1_L_SEL_MASK (0x3 << 8) | ||
| 383 | #define RT5645_DAC1_L_SEL_SFT 8 | ||
| 384 | #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8) | ||
| 385 | #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8) | ||
| 386 | #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8) | ||
| 387 | #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8) | ||
| 388 | #define RT5645_M_ADCMIX_R (0x1 << 7) | ||
| 389 | #define RT5645_M_ADCMIX_R_SFT 7 | ||
| 390 | #define RT5645_M_DAC1_R (0x1 << 6) | ||
| 391 | #define RT5645_M_DAC1_R_SFT 6 | ||
| 392 | |||
| 393 | /* Stereo DAC Mixer Control (0x2a) */ | ||
| 394 | #define RT5645_M_DAC_L1 (0x1 << 14) | ||
| 395 | #define RT5645_M_DAC_L1_SFT 14 | ||
| 396 | #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13) | ||
| 397 | #define RT5645_DAC_L1_STO_L_VOL_SFT 13 | ||
| 398 | #define RT5645_M_DAC_L2 (0x1 << 12) | ||
| 399 | #define RT5645_M_DAC_L2_SFT 12 | ||
| 400 | #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11) | ||
| 401 | #define RT5645_DAC_L2_STO_L_VOL_SFT 11 | ||
| 402 | #define RT5645_M_ANC_DAC_L (0x1 << 10) | ||
| 403 | #define RT5645_M_ANC_DAC_L_SFT 10 | ||
| 404 | #define RT5645_M_DAC_R1_STO_L (0x1 << 9) | ||
| 405 | #define RT5645_M_DAC_R1_STO_L_SFT 9 | ||
| 406 | #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8) | ||
| 407 | #define RT5645_DAC_R1_STO_L_VOL_SFT 8 | ||
| 408 | #define RT5645_M_DAC_R1 (0x1 << 6) | ||
| 409 | #define RT5645_M_DAC_R1_SFT 6 | ||
| 410 | #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5) | ||
| 411 | #define RT5645_DAC_R1_STO_R_VOL_SFT 5 | ||
| 412 | #define RT5645_M_DAC_R2 (0x1 << 4) | ||
| 413 | #define RT5645_M_DAC_R2_SFT 4 | ||
| 414 | #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3) | ||
| 415 | #define RT5645_DAC_R2_STO_R_VOL_SFT 3 | ||
| 416 | #define RT5645_M_ANC_DAC_R (0x1 << 2) | ||
| 417 | #define RT5645_M_ANC_DAC_R_SFT 2 | ||
| 418 | #define RT5645_M_DAC_L1_STO_R (0x1 << 1) | ||
| 419 | #define RT5645_M_DAC_L1_STO_R_SFT 1 | ||
| 420 | #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1) | ||
| 421 | #define RT5645_DAC_L1_STO_R_VOL_SFT 0 | ||
| 422 | |||
| 423 | /* Mono DAC Mixer Control (0x2b) */ | ||
| 424 | #define RT5645_M_DAC_L1_MONO_L (0x1 << 14) | ||
| 425 | #define RT5645_M_DAC_L1_MONO_L_SFT 14 | ||
| 426 | #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) | ||
| 427 | #define RT5645_DAC_L1_MONO_L_VOL_SFT 13 | ||
| 428 | #define RT5645_M_DAC_L2_MONO_L (0x1 << 12) | ||
| 429 | #define RT5645_M_DAC_L2_MONO_L_SFT 12 | ||
| 430 | #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) | ||
| 431 | #define RT5645_DAC_L2_MONO_L_VOL_SFT 11 | ||
| 432 | #define RT5645_M_DAC_R2_MONO_L (0x1 << 10) | ||
| 433 | #define RT5645_M_DAC_R2_MONO_L_SFT 10 | ||
| 434 | #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) | ||
| 435 | #define RT5645_DAC_R2_MONO_L_VOL_SFT 9 | ||
| 436 | #define RT5645_M_DAC_R1_MONO_R (0x1 << 6) | ||
| 437 | #define RT5645_M_DAC_R1_MONO_R_SFT 6 | ||
| 438 | #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) | ||
| 439 | #define RT5645_DAC_R1_MONO_R_VOL_SFT 5 | ||
| 440 | #define RT5645_M_DAC_R2_MONO_R (0x1 << 4) | ||
| 441 | #define RT5645_M_DAC_R2_MONO_R_SFT 4 | ||
| 442 | #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) | ||
| 443 | #define RT5645_DAC_R2_MONO_R_VOL_SFT 3 | ||
| 444 | #define RT5645_M_DAC_L2_MONO_R (0x1 << 2) | ||
| 445 | #define RT5645_M_DAC_L2_MONO_R_SFT 2 | ||
| 446 | #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) | ||
| 447 | #define RT5645_DAC_L2_MONO_R_VOL_SFT 1 | ||
| 448 | |||
| 449 | /* Digital Mixer Control (0x2c) */ | ||
| 450 | #define RT5645_M_STO_L_DAC_L (0x1 << 15) | ||
| 451 | #define RT5645_M_STO_L_DAC_L_SFT 15 | ||
| 452 | #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14) | ||
| 453 | #define RT5645_STO_L_DAC_L_VOL_SFT 14 | ||
| 454 | #define RT5645_M_DAC_L2_DAC_L (0x1 << 13) | ||
| 455 | #define RT5645_M_DAC_L2_DAC_L_SFT 13 | ||
| 456 | #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) | ||
| 457 | #define RT5645_DAC_L2_DAC_L_VOL_SFT 12 | ||
| 458 | #define RT5645_M_STO_R_DAC_R (0x1 << 11) | ||
| 459 | #define RT5645_M_STO_R_DAC_R_SFT 11 | ||
| 460 | #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10) | ||
| 461 | #define RT5645_STO_R_DAC_R_VOL_SFT 10 | ||
| 462 | #define RT5645_M_DAC_R2_DAC_R (0x1 << 9) | ||
| 463 | #define RT5645_M_DAC_R2_DAC_R_SFT 9 | ||
| 464 | #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) | ||
| 465 | #define RT5645_DAC_R2_DAC_R_VOL_SFT 8 | ||
| 466 | #define RT5645_M_DAC_R2_DAC_L (0x1 << 7) | ||
| 467 | #define RT5645_M_DAC_R2_DAC_L_SFT 7 | ||
| 468 | #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6) | ||
| 469 | #define RT5645_DAC_R2_DAC_L_VOL_SFT 6 | ||
| 470 | #define RT5645_M_DAC_L2_DAC_R (0x1 << 5) | ||
| 471 | #define RT5645_M_DAC_L2_DAC_R_SFT 5 | ||
| 472 | #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4) | ||
| 473 | #define RT5645_DAC_L2_DAC_R_VOL_SFT 4 | ||
| 474 | |||
| 475 | /* Digital Interface Data Control (0x2f) */ | ||
| 476 | #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15) | ||
| 477 | #define RT5645_IF1_ADC2_IN_SFT 15 | ||
| 478 | #define RT5645_IF2_ADC_IN_MASK (0x7 << 12) | ||
| 479 | #define RT5645_IF2_ADC_IN_SFT 12 | ||
| 480 | #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10) | ||
| 481 | #define RT5645_IF2_DAC_SEL_SFT 10 | ||
| 482 | #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8) | ||
| 483 | #define RT5645_IF2_ADC_SEL_SFT 8 | ||
| 484 | #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6) | ||
| 485 | #define RT5645_IF3_DAC_SEL_SFT 6 | ||
| 486 | #define RT5645_IF3_ADC_SEL_MASK (0x3 << 4) | ||
| 487 | #define RT5645_IF3_ADC_SEL_SFT 4 | ||
| 488 | #define RT5645_IF3_ADC_IN_MASK (0x7) | ||
| 489 | #define RT5645_IF3_ADC_IN_SFT 0 | ||
| 490 | |||
| 491 | /* PDM Output Control (0x31) */ | ||
| 492 | #define RT5645_PDM1_L_MASK (0x1 << 15) | ||
| 493 | #define RT5645_PDM1_L_SFT 15 | ||
| 494 | #define RT5645_M_PDM1_L (0x1 << 14) | ||
| 495 | #define RT5645_M_PDM1_L_SFT 14 | ||
| 496 | #define RT5645_PDM1_R_MASK (0x1 << 13) | ||
| 497 | #define RT5645_PDM1_R_SFT 13 | ||
| 498 | #define RT5645_M_PDM1_R (0x1 << 12) | ||
| 499 | #define RT5645_M_PDM1_R_SFT 12 | ||
| 500 | #define RT5645_PDM2_L_MASK (0x1 << 11) | ||
| 501 | #define RT5645_PDM2_L_SFT 11 | ||
| 502 | #define RT5645_M_PDM2_L (0x1 << 10) | ||
| 503 | #define RT5645_M_PDM2_L_SFT 10 | ||
| 504 | #define RT5645_PDM2_R_MASK (0x1 << 9) | ||
| 505 | #define RT5645_PDM2_R_SFT 9 | ||
| 506 | #define RT5645_M_PDM2_R (0x1 << 8) | ||
| 507 | #define RT5645_M_PDM2_R_SFT 8 | ||
| 508 | #define RT5645_PDM2_BUSY (0x1 << 7) | ||
| 509 | #define RT5645_PDM1_BUSY (0x1 << 6) | ||
| 510 | #define RT5645_PDM_PATTERN (0x1 << 5) | ||
| 511 | #define RT5645_PDM_GAIN (0x1 << 4) | ||
| 512 | #define RT5645_PDM_DIV_MASK (0x3) | ||
| 513 | |||
| 514 | /* REC Left Mixer Control 1 (0x3b) */ | ||
| 515 | #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13) | ||
| 516 | #define RT5645_G_HP_L_RM_L_SFT 13 | ||
| 517 | #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10) | ||
| 518 | #define RT5645_G_IN_L_RM_L_SFT 10 | ||
| 519 | #define RT5645_G_BST4_RM_L_MASK (0x7 << 7) | ||
| 520 | #define RT5645_G_BST4_RM_L_SFT 7 | ||
| 521 | #define RT5645_G_BST3_RM_L_MASK (0x7 << 4) | ||
| 522 | #define RT5645_G_BST3_RM_L_SFT 4 | ||
| 523 | #define RT5645_G_BST2_RM_L_MASK (0x7 << 1) | ||
| 524 | #define RT5645_G_BST2_RM_L_SFT 1 | ||
| 525 | |||
| 526 | /* REC Left Mixer Control 2 (0x3c) */ | ||
| 527 | #define RT5645_G_BST1_RM_L_MASK (0x7 << 13) | ||
| 528 | #define RT5645_G_BST1_RM_L_SFT 13 | ||
| 529 | #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10) | ||
| 530 | #define RT5645_G_OM_L_RM_L_SFT 10 | ||
| 531 | #define RT5645_M_MM_L_RM_L (0x1 << 6) | ||
| 532 | #define RT5645_M_MM_L_RM_L_SFT 6 | ||
| 533 | #define RT5645_M_IN_L_RM_L (0x1 << 5) | ||
| 534 | #define RT5645_M_IN_L_RM_L_SFT 5 | ||
| 535 | #define RT5645_M_HP_L_RM_L (0x1 << 4) | ||
| 536 | #define RT5645_M_HP_L_RM_L_SFT 4 | ||
| 537 | #define RT5645_M_BST3_RM_L (0x1 << 3) | ||
| 538 | #define RT5645_M_BST3_RM_L_SFT 3 | ||
| 539 | #define RT5645_M_BST2_RM_L (0x1 << 2) | ||
| 540 | #define RT5645_M_BST2_RM_L_SFT 2 | ||
| 541 | #define RT5645_M_BST1_RM_L (0x1 << 1) | ||
| 542 | #define RT5645_M_BST1_RM_L_SFT 1 | ||
| 543 | #define RT5645_M_OM_L_RM_L (0x1) | ||
| 544 | #define RT5645_M_OM_L_RM_L_SFT 0 | ||
| 545 | |||
| 546 | /* REC Right Mixer Control 1 (0x3d) */ | ||
| 547 | #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13) | ||
| 548 | #define RT5645_G_HP_R_RM_R_SFT 13 | ||
| 549 | #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10) | ||
| 550 | #define RT5645_G_IN_R_RM_R_SFT 10 | ||
| 551 | #define RT5645_G_BST4_RM_R_MASK (0x7 << 7) | ||
| 552 | #define RT5645_G_BST4_RM_R_SFT 7 | ||
| 553 | #define RT5645_G_BST3_RM_R_MASK (0x7 << 4) | ||
| 554 | #define RT5645_G_BST3_RM_R_SFT 4 | ||
| 555 | #define RT5645_G_BST2_RM_R_MASK (0x7 << 1) | ||
| 556 | #define RT5645_G_BST2_RM_R_SFT 1 | ||
| 557 | |||
| 558 | /* REC Right Mixer Control 2 (0x3e) */ | ||
| 559 | #define RT5645_G_BST1_RM_R_MASK (0x7 << 13) | ||
| 560 | #define RT5645_G_BST1_RM_R_SFT 13 | ||
| 561 | #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10) | ||
| 562 | #define RT5645_G_OM_R_RM_R_SFT 10 | ||
| 563 | #define RT5645_M_MM_R_RM_R (0x1 << 6) | ||
| 564 | #define RT5645_M_MM_R_RM_R_SFT 6 | ||
| 565 | #define RT5645_M_IN_R_RM_R (0x1 << 5) | ||
| 566 | #define RT5645_M_IN_R_RM_R_SFT 5 | ||
| 567 | #define RT5645_M_HP_R_RM_R (0x1 << 4) | ||
| 568 | #define RT5645_M_HP_R_RM_R_SFT 4 | ||
| 569 | #define RT5645_M_BST3_RM_R (0x1 << 3) | ||
| 570 | #define RT5645_M_BST3_RM_R_SFT 3 | ||
| 571 | #define RT5645_M_BST2_RM_R (0x1 << 2) | ||
| 572 | #define RT5645_M_BST2_RM_R_SFT 2 | ||
| 573 | #define RT5645_M_BST1_RM_R (0x1 << 1) | ||
| 574 | #define RT5645_M_BST1_RM_R_SFT 1 | ||
| 575 | #define RT5645_M_OM_R_RM_R (0x1) | ||
| 576 | #define RT5645_M_OM_R_RM_R_SFT 0 | ||
| 577 | |||
| 578 | /* HPOMIX Control (0x40) (0x42) */ | ||
| 579 | #define RT5645_M_BST1_HV (0x1 << 4) | ||
| 580 | #define RT5645_M_BST1_HV_SFT 4 | ||
| 581 | #define RT5645_M_BST2_HV (0x1 << 4) | ||
| 582 | #define RT5645_M_BST2_HV_SFT 4 | ||
| 583 | #define RT5645_M_BST3_HV (0x1 << 3) | ||
| 584 | #define RT5645_M_BST3_HV_SFT 3 | ||
| 585 | #define RT5645_M_IN_HV (0x1 << 2) | ||
| 586 | #define RT5645_M_IN_HV_SFT 2 | ||
| 587 | #define RT5645_M_DAC2_HV (0x1 << 1) | ||
| 588 | #define RT5645_M_DAC2_HV_SFT 1 | ||
| 589 | #define RT5645_M_DAC1_HV (0x1 << 0) | ||
| 590 | #define RT5645_M_DAC1_HV_SFT 0 | ||
| 591 | |||
| 592 | /* HPMIX Control (0x45) */ | ||
| 593 | #define RT5645_M_DAC1_HM (0x1 << 14) | ||
| 594 | #define RT5645_M_DAC1_HM_SFT 14 | ||
| 595 | #define RT5645_M_HPVOL_HM (0x1 << 13) | ||
| 596 | #define RT5645_M_HPVOL_HM_SFT 13 | ||
| 597 | |||
| 598 | /* SPK Left Mixer Control (0x46) */ | ||
| 599 | #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) | ||
| 600 | #define RT5645_G_RM_L_SM_L_SFT 14 | ||
| 601 | #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12) | ||
| 602 | #define RT5645_G_IN_L_SM_L_SFT 12 | ||
| 603 | #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10) | ||
| 604 | #define RT5645_G_DAC_L1_SM_L_SFT 10 | ||
| 605 | #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8) | ||
| 606 | #define RT5645_G_DAC_L2_SM_L_SFT 8 | ||
| 607 | #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6) | ||
| 608 | #define RT5645_G_OM_L_SM_L_SFT 6 | ||
| 609 | #define RT5645_M_BST1_L_SM_L (0x1 << 5) | ||
| 610 | #define RT5645_M_BST1_L_SM_L_SFT 5 | ||
| 611 | #define RT5645_M_IN_L_SM_L (0x1 << 3) | ||
| 612 | #define RT5645_M_IN_L_SM_L_SFT 3 | ||
| 613 | #define RT5645_M_DAC_L1_SM_L (0x1 << 1) | ||
| 614 | #define RT5645_M_DAC_L1_SM_L_SFT 1 | ||
| 615 | #define RT5645_M_DAC_L2_SM_L (0x1 << 2) | ||
| 616 | #define RT5645_M_DAC_L2_SM_L_SFT 2 | ||
| 617 | #define RT5645_M_BST3_L_SM_L (0x1 << 4) | ||
| 618 | #define RT5645_M_BST3_L_SM_L_SFT 4 | ||
| 619 | |||
| 620 | /* SPK Right Mixer Control (0x47) */ | ||
| 621 | #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14) | ||
| 622 | #define RT5645_G_RM_R_SM_R_SFT 14 | ||
| 623 | #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12) | ||
| 624 | #define RT5645_G_IN_R_SM_R_SFT 12 | ||
| 625 | #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10) | ||
| 626 | #define RT5645_G_DAC_R1_SM_R_SFT 10 | ||
| 627 | #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8) | ||
| 628 | #define RT5645_G_DAC_R2_SM_R_SFT 8 | ||
| 629 | #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6) | ||
| 630 | #define RT5645_G_OM_R_SM_R_SFT 6 | ||
| 631 | #define RT5645_M_BST2_R_SM_R (0x1 << 5) | ||
| 632 | #define RT5645_M_BST2_R_SM_R_SFT 5 | ||
| 633 | #define RT5645_M_IN_R_SM_R (0x1 << 3) | ||
| 634 | #define RT5645_M_IN_R_SM_R_SFT 3 | ||
| 635 | #define RT5645_M_DAC_R1_SM_R (0x1 << 1) | ||
| 636 | #define RT5645_M_DAC_R1_SM_R_SFT 1 | ||
| 637 | #define RT5645_M_DAC_R2_SM_R (0x1 << 2) | ||
| 638 | #define RT5645_M_DAC_R2_SM_R_SFT 2 | ||
| 639 | #define RT5645_M_BST3_R_SM_R (0x1 << 4) | ||
| 640 | #define RT5645_M_BST3_R_SM_R_SFT 4 | ||
| 641 | |||
| 642 | /* SPOLMIX Control (0x48) */ | ||
| 643 | #define RT5645_M_DAC_L1_SPM_L (0x1 << 15) | ||
| 644 | #define RT5645_M_DAC_L1_SPM_L_SFT 15 | ||
| 645 | #define RT5645_M_DAC_R1_SPM_L (0x1 << 14) | ||
| 646 | #define RT5645_M_DAC_R1_SPM_L_SFT 14 | ||
| 647 | #define RT5645_M_SV_L_SPM_L (0x1 << 13) | ||
| 648 | #define RT5645_M_SV_L_SPM_L_SFT 13 | ||
| 649 | #define RT5645_M_SV_R_SPM_L (0x1 << 12) | ||
| 650 | #define RT5645_M_SV_R_SPM_L_SFT 12 | ||
| 651 | #define RT5645_M_BST3_SPM_L (0x1 << 11) | ||
| 652 | #define RT5645_M_BST3_SPM_L_SFT 11 | ||
| 653 | #define RT5645_M_DAC_R1_SPM_R (0x1 << 2) | ||
| 654 | #define RT5645_M_DAC_R1_SPM_R_SFT 2 | ||
| 655 | #define RT5645_M_BST3_SPM_R (0x1 << 1) | ||
| 656 | #define RT5645_M_BST3_SPM_R_SFT 1 | ||
| 657 | #define RT5645_M_SV_R_SPM_R (0x1 << 0) | ||
| 658 | #define RT5645_M_SV_R_SPM_R_SFT 0 | ||
| 659 | |||
| 660 | /* Mono Output Mixer Control (0x4c) */ | ||
| 661 | #define RT5645_M_OV_L_MM (0x1 << 9) | ||
| 662 | #define RT5645_M_OV_L_MM_SFT 9 | ||
| 663 | #define RT5645_M_DAC_L2_MA (0x1 << 8) | ||
| 664 | #define RT5645_M_DAC_L2_MA_SFT 8 | ||
| 665 | #define RT5645_G_MONOMIX_MASK (0x1 << 10) | ||
| 666 | #define RT5645_G_MONOMIX_SFT 10 | ||
| 667 | #define RT5645_M_BST2_MM (0x1 << 4) | ||
| 668 | #define RT5645_M_BST2_MM_SFT 4 | ||
| 669 | #define RT5645_M_DAC_R1_MM (0x1 << 3) | ||
| 670 | #define RT5645_M_DAC_R1_MM_SFT 3 | ||
| 671 | #define RT5645_M_DAC_R2_MM (0x1 << 2) | ||
| 672 | #define RT5645_M_DAC_R2_MM_SFT 2 | ||
| 673 | #define RT5645_M_DAC_L2_MM (0x1 << 1) | ||
| 674 | #define RT5645_M_DAC_L2_MM_SFT 1 | ||
| 675 | #define RT5645_M_BST3_MM (0x1 << 0) | ||
| 676 | #define RT5645_M_BST3_MM_SFT 0 | ||
| 677 | |||
| 678 | /* Output Left Mixer Control 1 (0x4d) */ | ||
| 679 | #define RT5645_G_BST3_OM_L_MASK (0x7 << 13) | ||
| 680 | #define RT5645_G_BST3_OM_L_SFT 13 | ||
| 681 | #define RT5645_G_BST2_OM_L_MASK (0x7 << 10) | ||
| 682 | #define RT5645_G_BST2_OM_L_SFT 10 | ||
| 683 | #define RT5645_G_BST1_OM_L_MASK (0x7 << 7) | ||
| 684 | #define RT5645_G_BST1_OM_L_SFT 7 | ||
| 685 | #define RT5645_G_IN_L_OM_L_MASK (0x7 << 4) | ||
| 686 | #define RT5645_G_IN_L_OM_L_SFT 4 | ||
| 687 | #define RT5645_G_RM_L_OM_L_MASK (0x7 << 1) | ||
| 688 | #define RT5645_G_RM_L_OM_L_SFT 1 | ||
| 689 | |||
| 690 | /* Output Left Mixer Control 2 (0x4e) */ | ||
| 691 | #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13) | ||
| 692 | #define RT5645_G_DAC_R2_OM_L_SFT 13 | ||
| 693 | #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10) | ||
| 694 | #define RT5645_G_DAC_L2_OM_L_SFT 10 | ||
| 695 | #define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7) | ||
| 696 | #define RT5645_G_DAC_L1_OM_L_SFT 7 | ||
| 697 | |||
| 698 | /* Output Left Mixer Control 3 (0x4f) */ | ||
| 699 | #define RT5645_M_BST3_OM_L (0x1 << 4) | ||
| 700 | #define RT5645_M_BST3_OM_L_SFT 4 | ||
| 701 | #define RT5645_M_BST1_OM_L (0x1 << 3) | ||
| 702 | #define RT5645_M_BST1_OM_L_SFT 3 | ||
| 703 | #define RT5645_M_IN_L_OM_L (0x1 << 2) | ||
| 704 | #define RT5645_M_IN_L_OM_L_SFT 2 | ||
| 705 | #define RT5645_M_DAC_L2_OM_L (0x1 << 1) | ||
| 706 | #define RT5645_M_DAC_L2_OM_L_SFT 1 | ||
| 707 | #define RT5645_M_DAC_L1_OM_L (0x1) | ||
| 708 | #define RT5645_M_DAC_L1_OM_L_SFT 0 | ||
| 709 | |||
| 710 | /* Output Right Mixer Control 1 (0x50) */ | ||
| 711 | #define RT5645_G_BST4_OM_R_MASK (0x7 << 13) | ||
| 712 | #define RT5645_G_BST4_OM_R_SFT 13 | ||
| 713 | #define RT5645_G_BST2_OM_R_MASK (0x7 << 10) | ||
| 714 | #define RT5645_G_BST2_OM_R_SFT 10 | ||
| 715 | #define RT5645_G_BST1_OM_R_MASK (0x7 << 7) | ||
| 716 | #define RT5645_G_BST1_OM_R_SFT 7 | ||
| 717 | #define RT5645_G_IN_R_OM_R_MASK (0x7 << 4) | ||
| 718 | #define RT5645_G_IN_R_OM_R_SFT 4 | ||
| 719 | #define RT5645_G_RM_R_OM_R_MASK (0x7 << 1) | ||
| 720 | #define RT5645_G_RM_R_OM_R_SFT 1 | ||
| 721 | |||
| 722 | /* Output Right Mixer Control 2 (0x51) */ | ||
| 723 | #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13) | ||
| 724 | #define RT5645_G_DAC_L2_OM_R_SFT 13 | ||
| 725 | #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10) | ||
| 726 | #define RT5645_G_DAC_R2_OM_R_SFT 10 | ||
| 727 | #define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7) | ||
| 728 | #define RT5645_G_DAC_R1_OM_R_SFT 7 | ||
| 729 | |||
| 730 | /* Output Right Mixer Control 3 (0x52) */ | ||
| 731 | #define RT5645_M_BST3_OM_R (0x1 << 4) | ||
| 732 | #define RT5645_M_BST3_OM_R_SFT 4 | ||
| 733 | #define RT5645_M_BST2_OM_R (0x1 << 3) | ||
| 734 | #define RT5645_M_BST2_OM_R_SFT 3 | ||
| 735 | #define RT5645_M_IN_R_OM_R (0x1 << 2) | ||
| 736 | #define RT5645_M_IN_R_OM_R_SFT 2 | ||
| 737 | #define RT5645_M_DAC_R2_OM_R (0x1 << 1) | ||
| 738 | #define RT5645_M_DAC_R2_OM_R_SFT 1 | ||
| 739 | #define RT5645_M_DAC_R1_OM_R (0x1) | ||
| 740 | #define RT5645_M_DAC_R1_OM_R_SFT 0 | ||
| 741 | |||
| 742 | /* LOUT Mixer Control (0x53) */ | ||
| 743 | #define RT5645_M_DAC_L1_LM (0x1 << 15) | ||
| 744 | #define RT5645_M_DAC_L1_LM_SFT 15 | ||
| 745 | #define RT5645_M_DAC_R1_LM (0x1 << 14) | ||
| 746 | #define RT5645_M_DAC_R1_LM_SFT 14 | ||
| 747 | #define RT5645_M_OV_L_LM (0x1 << 13) | ||
| 748 | #define RT5645_M_OV_L_LM_SFT 13 | ||
| 749 | #define RT5645_M_OV_R_LM (0x1 << 12) | ||
| 750 | #define RT5645_M_OV_R_LM_SFT 12 | ||
| 751 | #define RT5645_G_LOUTMIX_MASK (0x1 << 11) | ||
| 752 | #define RT5645_G_LOUTMIX_SFT 11 | ||
| 753 | |||
| 754 | /* Power Management for Digital 1 (0x61) */ | ||
| 755 | #define RT5645_PWR_I2S1 (0x1 << 15) | ||
| 756 | #define RT5645_PWR_I2S1_BIT 15 | ||
| 757 | #define RT5645_PWR_I2S2 (0x1 << 14) | ||
| 758 | #define RT5645_PWR_I2S2_BIT 14 | ||
| 759 | #define RT5645_PWR_I2S3 (0x1 << 13) | ||
| 760 | #define RT5645_PWR_I2S3_BIT 13 | ||
| 761 | #define RT5645_PWR_DAC_L1 (0x1 << 12) | ||
| 762 | #define RT5645_PWR_DAC_L1_BIT 12 | ||
| 763 | #define RT5645_PWR_DAC_R1 (0x1 << 11) | ||
| 764 | #define RT5645_PWR_DAC_R1_BIT 11 | ||
| 765 | #define RT5645_PWR_CLS_D_R (0x1 << 9) | ||
| 766 | #define RT5645_PWR_CLS_D_R_BIT 9 | ||
| 767 | #define RT5645_PWR_CLS_D_L (0x1 << 8) | ||
| 768 | #define RT5645_PWR_CLS_D_L_BIT 8 | ||
| 769 | #define RT5645_PWR_ADC_R (0x1 << 1) | ||
| 770 | #define RT5645_PWR_ADC_R_BIT 1 | ||
| 771 | #define RT5645_PWR_DAC_L2 (0x1 << 7) | ||
| 772 | #define RT5645_PWR_DAC_L2_BIT 7 | ||
| 773 | #define RT5645_PWR_DAC_R2 (0x1 << 6) | ||
| 774 | #define RT5645_PWR_DAC_R2_BIT 6 | ||
| 775 | #define RT5645_PWR_ADC_L (0x1 << 2) | ||
| 776 | #define RT5645_PWR_ADC_L_BIT 2 | ||
| 777 | #define RT5645_PWR_ADC_R (0x1 << 1) | ||
| 778 | #define RT5645_PWR_ADC_R_BIT 1 | ||
| 779 | #define RT5645_PWR_CLS_D (0x1) | ||
| 780 | #define RT5645_PWR_CLS_D_BIT 0 | ||
| 781 | |||
| 782 | /* Power Management for Digital 2 (0x62) */ | ||
| 783 | #define RT5645_PWR_ADC_S1F (0x1 << 15) | ||
| 784 | #define RT5645_PWR_ADC_S1F_BIT 15 | ||
| 785 | #define RT5645_PWR_ADC_MF_L (0x1 << 14) | ||
| 786 | #define RT5645_PWR_ADC_MF_L_BIT 14 | ||
| 787 | #define RT5645_PWR_ADC_MF_R (0x1 << 13) | ||
| 788 | #define RT5645_PWR_ADC_MF_R_BIT 13 | ||
| 789 | #define RT5645_PWR_I2S_DSP (0x1 << 12) | ||
| 790 | #define RT5645_PWR_I2S_DSP_BIT 12 | ||
| 791 | #define RT5645_PWR_DAC_S1F (0x1 << 11) | ||
| 792 | #define RT5645_PWR_DAC_S1F_BIT 11 | ||
| 793 | #define RT5645_PWR_DAC_MF_L (0x1 << 10) | ||
| 794 | #define RT5645_PWR_DAC_MF_L_BIT 10 | ||
| 795 | #define RT5645_PWR_DAC_MF_R (0x1 << 9) | ||
| 796 | #define RT5645_PWR_DAC_MF_R_BIT 9 | ||
| 797 | #define RT5645_PWR_ADC_S2F (0x1 << 8) | ||
| 798 | #define RT5645_PWR_ADC_S2F_BIT 8 | ||
| 799 | #define RT5645_PWR_PDM1 (0x1 << 7) | ||
| 800 | #define RT5645_PWR_PDM1_BIT 7 | ||
| 801 | #define RT5645_PWR_PDM2 (0x1 << 6) | ||
| 802 | #define RT5645_PWR_PDM2_BIT 6 | ||
| 803 | #define RT5645_PWR_IPTV (0x1 << 1) | ||
| 804 | #define RT5645_PWR_IPTV_BIT 1 | ||
| 805 | #define RT5645_PWR_PAD (0x1) | ||
| 806 | #define RT5645_PWR_PAD_BIT 0 | ||
| 807 | |||
| 808 | /* Power Management for Analog 1 (0x63) */ | ||
| 809 | #define RT5645_PWR_VREF1 (0x1 << 15) | ||
| 810 | #define RT5645_PWR_VREF1_BIT 15 | ||
| 811 | #define RT5645_PWR_FV1 (0x1 << 14) | ||
| 812 | #define RT5645_PWR_FV1_BIT 14 | ||
| 813 | #define RT5645_PWR_MB (0x1 << 13) | ||
| 814 | #define RT5645_PWR_MB_BIT 13 | ||
| 815 | #define RT5645_PWR_LM (0x1 << 12) | ||
| 816 | #define RT5645_PWR_LM_BIT 12 | ||
| 817 | #define RT5645_PWR_BG (0x1 << 11) | ||
| 818 | #define RT5645_PWR_BG_BIT 11 | ||
| 819 | #define RT5645_PWR_MA (0x1 << 10) | ||
| 820 | #define RT5645_PWR_MA_BIT 10 | ||
| 821 | #define RT5645_PWR_HP_L (0x1 << 7) | ||
| 822 | #define RT5645_PWR_HP_L_BIT 7 | ||
| 823 | #define RT5645_PWR_HP_R (0x1 << 6) | ||
| 824 | #define RT5645_PWR_HP_R_BIT 6 | ||
| 825 | #define RT5645_PWR_HA (0x1 << 5) | ||
| 826 | #define RT5645_PWR_HA_BIT 5 | ||
| 827 | #define RT5645_PWR_VREF2 (0x1 << 4) | ||
| 828 | #define RT5645_PWR_VREF2_BIT 4 | ||
| 829 | #define RT5645_PWR_FV2 (0x1 << 3) | ||
| 830 | #define RT5645_PWR_FV2_BIT 3 | ||
| 831 | #define RT5645_LDO_SEL_MASK (0x3) | ||
| 832 | #define RT5645_LDO_SEL_SFT 0 | ||
| 833 | |||
| 834 | /* Power Management for Analog 2 (0x64) */ | ||
| 835 | #define RT5645_PWR_BST1 (0x1 << 15) | ||
| 836 | #define RT5645_PWR_BST1_BIT 15 | ||
| 837 | #define RT5645_PWR_BST2 (0x1 << 14) | ||
| 838 | #define RT5645_PWR_BST2_BIT 14 | ||
| 839 | #define RT5645_PWR_BST3 (0x1 << 13) | ||
| 840 | #define RT5645_PWR_BST3_BIT 13 | ||
| 841 | #define RT5645_PWR_BST4 (0x1 << 12) | ||
| 842 | #define RT5645_PWR_BST4_BIT 12 | ||
| 843 | #define RT5645_PWR_MB1 (0x1 << 11) | ||
| 844 | #define RT5645_PWR_MB1_BIT 11 | ||
| 845 | #define RT5645_PWR_MB2 (0x1 << 10) | ||
| 846 | #define RT5645_PWR_MB2_BIT 10 | ||
| 847 | #define RT5645_PWR_PLL (0x1 << 9) | ||
| 848 | #define RT5645_PWR_PLL_BIT 9 | ||
| 849 | #define RT5645_PWR_BST2_P (0x1 << 5) | ||
| 850 | #define RT5645_PWR_BST2_P_BIT 5 | ||
| 851 | #define RT5645_PWR_BST3_P (0x1 << 4) | ||
| 852 | #define RT5645_PWR_BST3_P_BIT 4 | ||
| 853 | #define RT5645_PWR_BST4_P (0x1 << 3) | ||
| 854 | #define RT5645_PWR_BST4_P_BIT 3 | ||
| 855 | #define RT5645_PWR_JD1 (0x1 << 2) | ||
| 856 | #define RT5645_PWR_JD1_BIT 2 | ||
| 857 | #define RT5645_PWR_JD (0x1 << 1) | ||
| 858 | #define RT5645_PWR_JD_BIT 1 | ||
| 859 | |||
| 860 | /* Power Management for Mixer (0x65) */ | ||
| 861 | #define RT5645_PWR_OM_L (0x1 << 15) | ||
| 862 | #define RT5645_PWR_OM_L_BIT 15 | ||
| 863 | #define RT5645_PWR_OM_R (0x1 << 14) | ||
| 864 | #define RT5645_PWR_OM_R_BIT 14 | ||
| 865 | #define RT5645_PWR_SM_L (0x1 << 13) | ||
| 866 | #define RT5645_PWR_SM_L_BIT 13 | ||
| 867 | #define RT5645_PWR_SM_R (0x1 << 12) | ||
| 868 | #define RT5645_PWR_SM_R_BIT 12 | ||
| 869 | #define RT5645_PWR_RM_L (0x1 << 11) | ||
| 870 | #define RT5645_PWR_RM_L_BIT 11 | ||
| 871 | #define RT5645_PWR_RM_R (0x1 << 10) | ||
| 872 | #define RT5645_PWR_RM_R_BIT 10 | ||
| 873 | #define RT5645_PWR_MM (0x1 << 8) | ||
| 874 | #define RT5645_PWR_MM_BIT 8 | ||
| 875 | #define RT5645_PWR_HM_L (0x1 << 7) | ||
| 876 | #define RT5645_PWR_HM_L_BIT 7 | ||
| 877 | #define RT5645_PWR_HM_R (0x1 << 6) | ||
| 878 | #define RT5645_PWR_HM_R_BIT 6 | ||
| 879 | #define RT5645_PWR_LDO2 (0x1 << 1) | ||
| 880 | #define RT5645_PWR_LDO2_BIT 1 | ||
| 881 | |||
| 882 | /* Power Management for Volume (0x66) */ | ||
| 883 | #define RT5645_PWR_SV_L (0x1 << 15) | ||
| 884 | #define RT5645_PWR_SV_L_BIT 15 | ||
| 885 | #define RT5645_PWR_SV_R (0x1 << 14) | ||
| 886 | #define RT5645_PWR_SV_R_BIT 14 | ||
| 887 | #define RT5645_PWR_HV_L (0x1 << 11) | ||
| 888 | #define RT5645_PWR_HV_L_BIT 11 | ||
| 889 | #define RT5645_PWR_HV_R (0x1 << 10) | ||
| 890 | #define RT5645_PWR_HV_R_BIT 10 | ||
| 891 | #define RT5645_PWR_IN_L (0x1 << 9) | ||
| 892 | #define RT5645_PWR_IN_L_BIT 9 | ||
| 893 | #define RT5645_PWR_IN_R (0x1 << 8) | ||
| 894 | #define RT5645_PWR_IN_R_BIT 8 | ||
| 895 | #define RT5645_PWR_MIC_DET (0x1 << 5) | ||
| 896 | #define RT5645_PWR_MIC_DET_BIT 5 | ||
| 897 | |||
| 898 | /* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */ | ||
| 899 | #define RT5645_I2S_MS_MASK (0x1 << 15) | ||
| 900 | #define RT5645_I2S_MS_SFT 15 | ||
| 901 | #define RT5645_I2S_MS_M (0x0 << 15) | ||
| 902 | #define RT5645_I2S_MS_S (0x1 << 15) | ||
| 903 | #define RT5645_I2S_O_CP_MASK (0x3 << 10) | ||
| 904 | #define RT5645_I2S_O_CP_SFT 10 | ||
| 905 | #define RT5645_I2S_O_CP_OFF (0x0 << 10) | ||
| 906 | #define RT5645_I2S_O_CP_U_LAW (0x1 << 10) | ||
| 907 | #define RT5645_I2S_O_CP_A_LAW (0x2 << 10) | ||
| 908 | #define RT5645_I2S_I_CP_MASK (0x3 << 8) | ||
| 909 | #define RT5645_I2S_I_CP_SFT 8 | ||
| 910 | #define RT5645_I2S_I_CP_OFF (0x0 << 8) | ||
| 911 | #define RT5645_I2S_I_CP_U_LAW (0x1 << 8) | ||
| 912 | #define RT5645_I2S_I_CP_A_LAW (0x2 << 8) | ||
| 913 | #define RT5645_I2S_BP_MASK (0x1 << 7) | ||
| 914 | #define RT5645_I2S_BP_SFT 7 | ||
| 915 | #define RT5645_I2S_BP_NOR (0x0 << 7) | ||
| 916 | #define RT5645_I2S_BP_INV (0x1 << 7) | ||
| 917 | #define RT5645_I2S_DL_MASK (0x3 << 2) | ||
| 918 | #define RT5645_I2S_DL_SFT 2 | ||
| 919 | #define RT5645_I2S_DL_16 (0x0 << 2) | ||
| 920 | #define RT5645_I2S_DL_20 (0x1 << 2) | ||
| 921 | #define RT5645_I2S_DL_24 (0x2 << 2) | ||
| 922 | #define RT5645_I2S_DL_8 (0x3 << 2) | ||
| 923 | #define RT5645_I2S_DF_MASK (0x3) | ||
| 924 | #define RT5645_I2S_DF_SFT 0 | ||
| 925 | #define RT5645_I2S_DF_I2S (0x0) | ||
| 926 | #define RT5645_I2S_DF_LEFT (0x1) | ||
| 927 | #define RT5645_I2S_DF_PCM_A (0x2) | ||
| 928 | #define RT5645_I2S_DF_PCM_B (0x3) | ||
| 929 | |||
| 930 | /* I2S2 Audio Serial Data Port Control (0x71) */ | ||
| 931 | #define RT5645_I2S2_SDI_MASK (0x1 << 6) | ||
| 932 | #define RT5645_I2S2_SDI_SFT 6 | ||
| 933 | #define RT5645_I2S2_SDI_I2S1 (0x0 << 6) | ||
| 934 | #define RT5645_I2S2_SDI_I2S2 (0x1 << 6) | ||
| 935 | |||
| 936 | /* ADC/DAC Clock Control 1 (0x73) */ | ||
| 937 | #define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15) | ||
| 938 | #define RT5645_I2S_BCLK_MS1_SFT 15 | ||
| 939 | #define RT5645_I2S_BCLK_MS1_32 (0x0 << 15) | ||
| 940 | #define RT5645_I2S_BCLK_MS1_64 (0x1 << 15) | ||
| 941 | #define RT5645_I2S_PD1_MASK (0x7 << 12) | ||
| 942 | #define RT5645_I2S_PD1_SFT 12 | ||
| 943 | #define RT5645_I2S_PD1_1 (0x0 << 12) | ||
| 944 | #define RT5645_I2S_PD1_2 (0x1 << 12) | ||
| 945 | #define RT5645_I2S_PD1_3 (0x2 << 12) | ||
| 946 | #define RT5645_I2S_PD1_4 (0x3 << 12) | ||
| 947 | #define RT5645_I2S_PD1_6 (0x4 << 12) | ||
| 948 | #define RT5645_I2S_PD1_8 (0x5 << 12) | ||
| 949 | #define RT5645_I2S_PD1_12 (0x6 << 12) | ||
| 950 | #define RT5645_I2S_PD1_16 (0x7 << 12) | ||
| 951 | #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11) | ||
| 952 | #define RT5645_I2S_BCLK_MS2_SFT 11 | ||
| 953 | #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11) | ||
| 954 | #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11) | ||
| 955 | #define RT5645_I2S_PD2_MASK (0x7 << 8) | ||
| 956 | #define RT5645_I2S_PD2_SFT 8 | ||
| 957 | #define RT5645_I2S_PD2_1 (0x0 << 8) | ||
| 958 | #define RT5645_I2S_PD2_2 (0x1 << 8) | ||
| 959 | #define RT5645_I2S_PD2_3 (0x2 << 8) | ||
| 960 | #define RT5645_I2S_PD2_4 (0x3 << 8) | ||
| 961 | #define RT5645_I2S_PD2_6 (0x4 << 8) | ||
| 962 | #define RT5645_I2S_PD2_8 (0x5 << 8) | ||
| 963 | #define RT5645_I2S_PD2_12 (0x6 << 8) | ||
| 964 | #define RT5645_I2S_PD2_16 (0x7 << 8) | ||
| 965 | #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7) | ||
| 966 | #define RT5645_I2S_BCLK_MS3_SFT 7 | ||
| 967 | #define RT5645_I2S_BCLK_MS3_32 (0x0 << 7) | ||
| 968 | #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7) | ||
| 969 | #define RT5645_I2S_PD3_MASK (0x7 << 4) | ||
| 970 | #define RT5645_I2S_PD3_SFT 4 | ||
| 971 | #define RT5645_I2S_PD3_1 (0x0 << 4) | ||
| 972 | #define RT5645_I2S_PD3_2 (0x1 << 4) | ||
| 973 | #define RT5645_I2S_PD3_3 (0x2 << 4) | ||
| 974 | #define RT5645_I2S_PD3_4 (0x3 << 4) | ||
| 975 | #define RT5645_I2S_PD3_6 (0x4 << 4) | ||
| 976 | #define RT5645_I2S_PD3_8 (0x5 << 4) | ||
| 977 | #define RT5645_I2S_PD3_12 (0x6 << 4) | ||
| 978 | #define RT5645_I2S_PD3_16 (0x7 << 4) | ||
| 979 | #define RT5645_DAC_OSR_MASK (0x3 << 2) | ||
| 980 | #define RT5645_DAC_OSR_SFT 2 | ||
| 981 | #define RT5645_DAC_OSR_128 (0x0 << 2) | ||
| 982 | #define RT5645_DAC_OSR_64 (0x1 << 2) | ||
| 983 | #define RT5645_DAC_OSR_32 (0x2 << 2) | ||
| 984 | #define RT5645_DAC_OSR_16 (0x3 << 2) | ||
| 985 | #define RT5645_ADC_OSR_MASK (0x3) | ||
| 986 | #define RT5645_ADC_OSR_SFT 0 | ||
| 987 | #define RT5645_ADC_OSR_128 (0x0) | ||
| 988 | #define RT5645_ADC_OSR_64 (0x1) | ||
| 989 | #define RT5645_ADC_OSR_32 (0x2) | ||
| 990 | #define RT5645_ADC_OSR_16 (0x3) | ||
| 991 | |||
| 992 | /* ADC/DAC Clock Control 2 (0x74) */ | ||
| 993 | #define RT5645_DAC_L_OSR_MASK (0x3 << 14) | ||
| 994 | #define RT5645_DAC_L_OSR_SFT 14 | ||
| 995 | #define RT5645_DAC_L_OSR_128 (0x0 << 14) | ||
| 996 | #define RT5645_DAC_L_OSR_64 (0x1 << 14) | ||
| 997 | #define RT5645_DAC_L_OSR_32 (0x2 << 14) | ||
| 998 | #define RT5645_DAC_L_OSR_16 (0x3 << 14) | ||
| 999 | #define RT5645_ADC_R_OSR_MASK (0x3 << 12) | ||
| 1000 | #define RT5645_ADC_R_OSR_SFT 12 | ||
| 1001 | #define RT5645_ADC_R_OSR_128 (0x0 << 12) | ||
| 1002 | #define RT5645_ADC_R_OSR_64 (0x1 << 12) | ||
| 1003 | #define RT5645_ADC_R_OSR_32 (0x2 << 12) | ||
| 1004 | #define RT5645_ADC_R_OSR_16 (0x3 << 12) | ||
| 1005 | #define RT5645_DAHPF_EN (0x1 << 11) | ||
| 1006 | #define RT5645_DAHPF_EN_SFT 11 | ||
| 1007 | #define RT5645_ADHPF_EN (0x1 << 10) | ||
| 1008 | #define RT5645_ADHPF_EN_SFT 10 | ||
| 1009 | |||
| 1010 | /* Digital Microphone Control (0x75) */ | ||
| 1011 | #define RT5645_DMIC_1_EN_MASK (0x1 << 15) | ||
| 1012 | #define RT5645_DMIC_1_EN_SFT 15 | ||
| 1013 | #define RT5645_DMIC_1_DIS (0x0 << 15) | ||
| 1014 | #define RT5645_DMIC_1_EN (0x1 << 15) | ||
| 1015 | #define RT5645_DMIC_2_EN_MASK (0x1 << 14) | ||
| 1016 | #define RT5645_DMIC_2_EN_SFT 14 | ||
| 1017 | #define RT5645_DMIC_2_DIS (0x0 << 14) | ||
| 1018 | #define RT5645_DMIC_2_EN (0x1 << 14) | ||
| 1019 | #define RT5645_DMIC_1L_LH_MASK (0x1 << 13) | ||
| 1020 | #define RT5645_DMIC_1L_LH_SFT 13 | ||
| 1021 | #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13) | ||
| 1022 | #define RT5645_DMIC_1L_LH_RISING (0x1 << 13) | ||
| 1023 | #define RT5645_DMIC_1R_LH_MASK (0x1 << 12) | ||
| 1024 | #define RT5645_DMIC_1R_LH_SFT 12 | ||
| 1025 | #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12) | ||
| 1026 | #define RT5645_DMIC_1R_LH_RISING (0x1 << 12) | ||
| 1027 | #define RT5645_DMIC_2_DP_MASK (0x3 << 10) | ||
| 1028 | #define RT5645_DMIC_2_DP_SFT 10 | ||
| 1029 | #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10) | ||
| 1030 | #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10) | ||
| 1031 | #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10) | ||
| 1032 | #define RT5645_DMIC_2_DP_IN2P (0x3 << 10) | ||
| 1033 | #define RT5645_DMIC_2L_LH_MASK (0x1 << 9) | ||
| 1034 | #define RT5645_DMIC_2L_LH_SFT 9 | ||
| 1035 | #define RT5645_DMIC_2L_LH_FALLING (0x0 << 9) | ||
| 1036 | #define RT5645_DMIC_2L_LH_RISING (0x1 << 9) | ||
| 1037 | #define RT5645_DMIC_2R_LH_MASK (0x1 << 8) | ||
| 1038 | #define RT5645_DMIC_2R_LH_SFT 8 | ||
| 1039 | #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8) | ||
| 1040 | #define RT5645_DMIC_2R_LH_RISING (0x1 << 8) | ||
| 1041 | #define RT5645_DMIC_CLK_MASK (0x7 << 5) | ||
| 1042 | #define RT5645_DMIC_CLK_SFT 5 | ||
| 1043 | #define RT5645_DMIC_3_EN_MASK (0x1 << 4) | ||
| 1044 | #define RT5645_DMIC_3_EN_SFT 4 | ||
| 1045 | #define RT5645_DMIC_3_DIS (0x0 << 4) | ||
| 1046 | #define RT5645_DMIC_3_EN (0x1 << 4) | ||
| 1047 | #define RT5645_DMIC_1_DP_MASK (0x3 << 0) | ||
| 1048 | #define RT5645_DMIC_1_DP_SFT 0 | ||
| 1049 | #define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0) | ||
| 1050 | #define RT5645_DMIC_1_DP_IN2N (0x1 << 0) | ||
| 1051 | #define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0) | ||
| 1052 | |||
| 1053 | /* TDM Control 1 (0x77) */ | ||
| 1054 | #define RT5645_IF1_ADC_IN_MASK (0x3 << 8) | ||
| 1055 | #define RT5645_IF1_ADC_IN_SFT 8 | ||
| 1056 | |||
| 1057 | /* Global Clock Control (0x80) */ | ||
| 1058 | #define RT5645_SCLK_SRC_MASK (0x3 << 14) | ||
| 1059 | #define RT5645_SCLK_SRC_SFT 14 | ||
| 1060 | #define RT5645_SCLK_SRC_MCLK (0x0 << 14) | ||
| 1061 | #define RT5645_SCLK_SRC_PLL1 (0x1 << 14) | ||
| 1062 | #define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */ | ||
| 1063 | #define RT5645_PLL1_SRC_MASK (0x3 << 12) | ||
| 1064 | #define RT5645_PLL1_SRC_SFT 12 | ||
| 1065 | #define RT5645_PLL1_SRC_MCLK (0x0 << 12) | ||
| 1066 | #define RT5645_PLL1_SRC_BCLK1 (0x1 << 12) | ||
| 1067 | #define RT5645_PLL1_SRC_BCLK2 (0x2 << 12) | ||
| 1068 | #define RT5645_PLL1_SRC_BCLK3 (0x3 << 12) | ||
| 1069 | #define RT5645_PLL1_PD_MASK (0x1 << 3) | ||
| 1070 | #define RT5645_PLL1_PD_SFT 3 | ||
| 1071 | #define RT5645_PLL1_PD_1 (0x0 << 3) | ||
| 1072 | #define RT5645_PLL1_PD_2 (0x1 << 3) | ||
| 1073 | |||
| 1074 | #define RT5645_PLL_INP_MAX 40000000 | ||
| 1075 | #define RT5645_PLL_INP_MIN 256000 | ||
| 1076 | /* PLL M/N/K Code Control 1 (0x81) */ | ||
| 1077 | #define RT5645_PLL_N_MAX 0x1ff | ||
| 1078 | #define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7) | ||
| 1079 | #define RT5645_PLL_N_SFT 7 | ||
| 1080 | #define RT5645_PLL_K_MAX 0x1f | ||
| 1081 | #define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX) | ||
| 1082 | #define RT5645_PLL_K_SFT 0 | ||
| 1083 | |||
| 1084 | /* PLL M/N/K Code Control 2 (0x82) */ | ||
| 1085 | #define RT5645_PLL_M_MAX 0xf | ||
| 1086 | #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12) | ||
| 1087 | #define RT5645_PLL_M_SFT 12 | ||
| 1088 | #define RT5645_PLL_M_BP (0x1 << 11) | ||
| 1089 | #define RT5645_PLL_M_BP_SFT 11 | ||
| 1090 | |||
| 1091 | /* ASRC Control 1 (0x83) */ | ||
| 1092 | #define RT5645_STO_T_MASK (0x1 << 15) | ||
| 1093 | #define RT5645_STO_T_SFT 15 | ||
| 1094 | #define RT5645_STO_T_SCLK (0x0 << 15) | ||
| 1095 | #define RT5645_STO_T_LRCK1 (0x1 << 15) | ||
| 1096 | #define RT5645_M1_T_MASK (0x1 << 14) | ||
| 1097 | #define RT5645_M1_T_SFT 14 | ||
| 1098 | #define RT5645_M1_T_I2S2 (0x0 << 14) | ||
| 1099 | #define RT5645_M1_T_I2S2_D3 (0x1 << 14) | ||
| 1100 | #define RT5645_I2S2_F_MASK (0x1 << 12) | ||
| 1101 | #define RT5645_I2S2_F_SFT 12 | ||
| 1102 | #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12) | ||
| 1103 | #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12) | ||
| 1104 | #define RT5645_DMIC_1_M_MASK (0x1 << 9) | ||
| 1105 | #define RT5645_DMIC_1_M_SFT 9 | ||
| 1106 | #define RT5645_DMIC_1_M_NOR (0x0 << 9) | ||
| 1107 | #define RT5645_DMIC_1_M_ASYN (0x1 << 9) | ||
| 1108 | #define RT5645_DMIC_2_M_MASK (0x1 << 8) | ||
| 1109 | #define RT5645_DMIC_2_M_SFT 8 | ||
| 1110 | #define RT5645_DMIC_2_M_NOR (0x0 << 8) | ||
| 1111 | #define RT5645_DMIC_2_M_ASYN (0x1 << 8) | ||
| 1112 | |||
| 1113 | /* ASRC Control 2 (0x84) */ | ||
| 1114 | #define RT5645_MDA_L_M_MASK (0x1 << 15) | ||
| 1115 | #define RT5645_MDA_L_M_SFT 15 | ||
| 1116 | #define RT5645_MDA_L_M_NOR (0x0 << 15) | ||
| 1117 | #define RT5645_MDA_L_M_ASYN (0x1 << 15) | ||
| 1118 | #define RT5645_MDA_R_M_MASK (0x1 << 14) | ||
| 1119 | #define RT5645_MDA_R_M_SFT 14 | ||
| 1120 | #define RT5645_MDA_R_M_NOR (0x0 << 14) | ||
| 1121 | #define RT5645_MDA_R_M_ASYN (0x1 << 14) | ||
| 1122 | #define RT5645_MAD_L_M_MASK (0x1 << 13) | ||
| 1123 | #define RT5645_MAD_L_M_SFT 13 | ||
| 1124 | #define RT5645_MAD_L_M_NOR (0x0 << 13) | ||
| 1125 | #define RT5645_MAD_L_M_ASYN (0x1 << 13) | ||
| 1126 | #define RT5645_MAD_R_M_MASK (0x1 << 12) | ||
| 1127 | #define RT5645_MAD_R_M_SFT 12 | ||
| 1128 | #define RT5645_MAD_R_M_NOR (0x0 << 12) | ||
| 1129 | #define RT5645_MAD_R_M_ASYN (0x1 << 12) | ||
| 1130 | #define RT5645_ADC_M_MASK (0x1 << 11) | ||
| 1131 | #define RT5645_ADC_M_SFT 11 | ||
| 1132 | #define RT5645_ADC_M_NOR (0x0 << 11) | ||
| 1133 | #define RT5645_ADC_M_ASYN (0x1 << 11) | ||
| 1134 | #define RT5645_STO_DAC_M_MASK (0x1 << 5) | ||
| 1135 | #define RT5645_STO_DAC_M_SFT 5 | ||
| 1136 | #define RT5645_STO_DAC_M_NOR (0x0 << 5) | ||
| 1137 | #define RT5645_STO_DAC_M_ASYN (0x1 << 5) | ||
| 1138 | #define RT5645_I2S1_R_D_MASK (0x1 << 4) | ||
| 1139 | #define RT5645_I2S1_R_D_SFT 4 | ||
| 1140 | #define RT5645_I2S1_R_D_DIS (0x0 << 4) | ||
| 1141 | #define RT5645_I2S1_R_D_EN (0x1 << 4) | ||
| 1142 | #define RT5645_I2S2_R_D_MASK (0x1 << 3) | ||
| 1143 | #define RT5645_I2S2_R_D_SFT 3 | ||
| 1144 | #define RT5645_I2S2_R_D_DIS (0x0 << 3) | ||
| 1145 | #define RT5645_I2S2_R_D_EN (0x1 << 3) | ||
| 1146 | #define RT5645_PRE_SCLK_MASK (0x3) | ||
| 1147 | #define RT5645_PRE_SCLK_SFT 0 | ||
| 1148 | #define RT5645_PRE_SCLK_512 (0x0) | ||
| 1149 | #define RT5645_PRE_SCLK_1024 (0x1) | ||
| 1150 | #define RT5645_PRE_SCLK_2048 (0x2) | ||
| 1151 | |||
| 1152 | /* ASRC Control 3 (0x85) */ | ||
| 1153 | #define RT5645_I2S1_RATE_MASK (0xf << 12) | ||
| 1154 | #define RT5645_I2S1_RATE_SFT 12 | ||
| 1155 | #define RT5645_I2S2_RATE_MASK (0xf << 8) | ||
| 1156 | #define RT5645_I2S2_RATE_SFT 8 | ||
| 1157 | |||
| 1158 | /* ASRC Control 4 (0x89) */ | ||
| 1159 | #define RT5645_I2S1_PD_MASK (0x7 << 12) | ||
| 1160 | #define RT5645_I2S1_PD_SFT 12 | ||
| 1161 | #define RT5645_I2S2_PD_MASK (0x7 << 8) | ||
| 1162 | #define RT5645_I2S2_PD_SFT 8 | ||
| 1163 | |||
| 1164 | /* HPOUT Over Current Detection (0x8b) */ | ||
| 1165 | #define RT5645_HP_OVCD_MASK (0x1 << 10) | ||
| 1166 | #define RT5645_HP_OVCD_SFT 10 | ||
| 1167 | #define RT5645_HP_OVCD_DIS (0x0 << 10) | ||
| 1168 | #define RT5645_HP_OVCD_EN (0x1 << 10) | ||
| 1169 | #define RT5645_HP_OC_TH_MASK (0x3 << 8) | ||
| 1170 | #define RT5645_HP_OC_TH_SFT 8 | ||
| 1171 | #define RT5645_HP_OC_TH_90 (0x0 << 8) | ||
| 1172 | #define RT5645_HP_OC_TH_105 (0x1 << 8) | ||
| 1173 | #define RT5645_HP_OC_TH_120 (0x2 << 8) | ||
| 1174 | #define RT5645_HP_OC_TH_135 (0x3 << 8) | ||
| 1175 | |||
| 1176 | /* Class D Over Current Control (0x8c) */ | ||
| 1177 | #define RT5645_CLSD_OC_MASK (0x1 << 9) | ||
| 1178 | #define RT5645_CLSD_OC_SFT 9 | ||
| 1179 | #define RT5645_CLSD_OC_PU (0x0 << 9) | ||
| 1180 | #define RT5645_CLSD_OC_PD (0x1 << 9) | ||
| 1181 | #define RT5645_AUTO_PD_MASK (0x1 << 8) | ||
| 1182 | #define RT5645_AUTO_PD_SFT 8 | ||
| 1183 | #define RT5645_AUTO_PD_DIS (0x0 << 8) | ||
| 1184 | #define RT5645_AUTO_PD_EN (0x1 << 8) | ||
| 1185 | #define RT5645_CLSD_OC_TH_MASK (0x3f) | ||
| 1186 | #define RT5645_CLSD_OC_TH_SFT 0 | ||
| 1187 | |||
| 1188 | /* Class D Output Control (0x8d) */ | ||
| 1189 | #define RT5645_CLSD_RATIO_MASK (0xf << 12) | ||
| 1190 | #define RT5645_CLSD_RATIO_SFT 12 | ||
| 1191 | #define RT5645_CLSD_OM_MASK (0x1 << 11) | ||
| 1192 | #define RT5645_CLSD_OM_SFT 11 | ||
| 1193 | #define RT5645_CLSD_OM_MONO (0x0 << 11) | ||
| 1194 | #define RT5645_CLSD_OM_STO (0x1 << 11) | ||
| 1195 | #define RT5645_CLSD_SCH_MASK (0x1 << 10) | ||
| 1196 | #define RT5645_CLSD_SCH_SFT 10 | ||
| 1197 | #define RT5645_CLSD_SCH_L (0x0 << 10) | ||
| 1198 | #define RT5645_CLSD_SCH_S (0x1 << 10) | ||
| 1199 | |||
| 1200 | /* Depop Mode Control 1 (0x8e) */ | ||
| 1201 | #define RT5645_SMT_TRIG_MASK (0x1 << 15) | ||
| 1202 | #define RT5645_SMT_TRIG_SFT 15 | ||
| 1203 | #define RT5645_SMT_TRIG_DIS (0x0 << 15) | ||
| 1204 | #define RT5645_SMT_TRIG_EN (0x1 << 15) | ||
| 1205 | #define RT5645_HP_L_SMT_MASK (0x1 << 9) | ||
| 1206 | #define RT5645_HP_L_SMT_SFT 9 | ||
| 1207 | #define RT5645_HP_L_SMT_DIS (0x0 << 9) | ||
| 1208 | #define RT5645_HP_L_SMT_EN (0x1 << 9) | ||
| 1209 | #define RT5645_HP_R_SMT_MASK (0x1 << 8) | ||
| 1210 | #define RT5645_HP_R_SMT_SFT 8 | ||
| 1211 | #define RT5645_HP_R_SMT_DIS (0x0 << 8) | ||
| 1212 | #define RT5645_HP_R_SMT_EN (0x1 << 8) | ||
| 1213 | #define RT5645_HP_CD_PD_MASK (0x1 << 7) | ||
| 1214 | #define RT5645_HP_CD_PD_SFT 7 | ||
| 1215 | #define RT5645_HP_CD_PD_DIS (0x0 << 7) | ||
| 1216 | #define RT5645_HP_CD_PD_EN (0x1 << 7) | ||
| 1217 | #define RT5645_RSTN_MASK (0x1 << 6) | ||
| 1218 | #define RT5645_RSTN_SFT 6 | ||
| 1219 | #define RT5645_RSTN_DIS (0x0 << 6) | ||
| 1220 | #define RT5645_RSTN_EN (0x1 << 6) | ||
| 1221 | #define RT5645_RSTP_MASK (0x1 << 5) | ||
| 1222 | #define RT5645_RSTP_SFT 5 | ||
| 1223 | #define RT5645_RSTP_DIS (0x0 << 5) | ||
| 1224 | #define RT5645_RSTP_EN (0x1 << 5) | ||
| 1225 | #define RT5645_HP_CO_MASK (0x1 << 4) | ||
| 1226 | #define RT5645_HP_CO_SFT 4 | ||
| 1227 | #define RT5645_HP_CO_DIS (0x0 << 4) | ||
| 1228 | #define RT5645_HP_CO_EN (0x1 << 4) | ||
| 1229 | #define RT5645_HP_CP_MASK (0x1 << 3) | ||
| 1230 | #define RT5645_HP_CP_SFT 3 | ||
| 1231 | #define RT5645_HP_CP_PD (0x0 << 3) | ||
| 1232 | #define RT5645_HP_CP_PU (0x1 << 3) | ||
| 1233 | #define RT5645_HP_SG_MASK (0x1 << 2) | ||
| 1234 | #define RT5645_HP_SG_SFT 2 | ||
| 1235 | #define RT5645_HP_SG_DIS (0x0 << 2) | ||
| 1236 | #define RT5645_HP_SG_EN (0x1 << 2) | ||
| 1237 | #define RT5645_HP_DP_MASK (0x1 << 1) | ||
| 1238 | #define RT5645_HP_DP_SFT 1 | ||
| 1239 | #define RT5645_HP_DP_PD (0x0 << 1) | ||
| 1240 | #define RT5645_HP_DP_PU (0x1 << 1) | ||
| 1241 | #define RT5645_HP_CB_MASK (0x1) | ||
| 1242 | #define RT5645_HP_CB_SFT 0 | ||
| 1243 | #define RT5645_HP_CB_PD (0x0) | ||
| 1244 | #define RT5645_HP_CB_PU (0x1) | ||
| 1245 | |||
| 1246 | /* Depop Mode Control 2 (0x8f) */ | ||
| 1247 | #define RT5645_DEPOP_MASK (0x1 << 13) | ||
| 1248 | #define RT5645_DEPOP_SFT 13 | ||
| 1249 | #define RT5645_DEPOP_AUTO (0x0 << 13) | ||
| 1250 | #define RT5645_DEPOP_MAN (0x1 << 13) | ||
| 1251 | #define RT5645_RAMP_MASK (0x1 << 12) | ||
| 1252 | #define RT5645_RAMP_SFT 12 | ||
| 1253 | #define RT5645_RAMP_DIS (0x0 << 12) | ||
| 1254 | #define RT5645_RAMP_EN (0x1 << 12) | ||
| 1255 | #define RT5645_BPS_MASK (0x1 << 11) | ||
| 1256 | #define RT5645_BPS_SFT 11 | ||
| 1257 | #define RT5645_BPS_DIS (0x0 << 11) | ||
| 1258 | #define RT5645_BPS_EN (0x1 << 11) | ||
| 1259 | #define RT5645_FAST_UPDN_MASK (0x1 << 10) | ||
| 1260 | #define RT5645_FAST_UPDN_SFT 10 | ||
| 1261 | #define RT5645_FAST_UPDN_DIS (0x0 << 10) | ||
| 1262 | #define RT5645_FAST_UPDN_EN (0x1 << 10) | ||
| 1263 | #define RT5645_MRES_MASK (0x3 << 8) | ||
| 1264 | #define RT5645_MRES_SFT 8 | ||
| 1265 | #define RT5645_MRES_15MO (0x0 << 8) | ||
| 1266 | #define RT5645_MRES_25MO (0x1 << 8) | ||
| 1267 | #define RT5645_MRES_35MO (0x2 << 8) | ||
| 1268 | #define RT5645_MRES_45MO (0x3 << 8) | ||
| 1269 | #define RT5645_VLO_MASK (0x1 << 7) | ||
| 1270 | #define RT5645_VLO_SFT 7 | ||
| 1271 | #define RT5645_VLO_3V (0x0 << 7) | ||
| 1272 | #define RT5645_VLO_32V (0x1 << 7) | ||
| 1273 | #define RT5645_DIG_DP_MASK (0x1 << 6) | ||
| 1274 | #define RT5645_DIG_DP_SFT 6 | ||
| 1275 | #define RT5645_DIG_DP_DIS (0x0 << 6) | ||
| 1276 | #define RT5645_DIG_DP_EN (0x1 << 6) | ||
| 1277 | #define RT5645_DP_TH_MASK (0x3 << 4) | ||
| 1278 | #define RT5645_DP_TH_SFT 4 | ||
| 1279 | |||
| 1280 | /* Depop Mode Control 3 (0x90) */ | ||
| 1281 | #define RT5645_CP_SYS_MASK (0x7 << 12) | ||
| 1282 | #define RT5645_CP_SYS_SFT 12 | ||
| 1283 | #define RT5645_CP_FQ1_MASK (0x7 << 8) | ||
| 1284 | #define RT5645_CP_FQ1_SFT 8 | ||
| 1285 | #define RT5645_CP_FQ2_MASK (0x7 << 4) | ||
| 1286 | #define RT5645_CP_FQ2_SFT 4 | ||
| 1287 | #define RT5645_CP_FQ3_MASK (0x7) | ||
| 1288 | #define RT5645_CP_FQ3_SFT 0 | ||
| 1289 | #define RT5645_CP_FQ_1_5_KHZ 0 | ||
| 1290 | #define RT5645_CP_FQ_3_KHZ 1 | ||
| 1291 | #define RT5645_CP_FQ_6_KHZ 2 | ||
| 1292 | #define RT5645_CP_FQ_12_KHZ 3 | ||
| 1293 | #define RT5645_CP_FQ_24_KHZ 4 | ||
| 1294 | #define RT5645_CP_FQ_48_KHZ 5 | ||
| 1295 | #define RT5645_CP_FQ_96_KHZ 6 | ||
| 1296 | #define RT5645_CP_FQ_192_KHZ 7 | ||
| 1297 | |||
| 1298 | /* PV detection and SPK gain control (0x92) */ | ||
| 1299 | #define RT5645_PVDD_DET_MASK (0x1 << 15) | ||
| 1300 | #define RT5645_PVDD_DET_SFT 15 | ||
| 1301 | #define RT5645_PVDD_DET_DIS (0x0 << 15) | ||
| 1302 | #define RT5645_PVDD_DET_EN (0x1 << 15) | ||
| 1303 | #define RT5645_SPK_AG_MASK (0x1 << 14) | ||
| 1304 | #define RT5645_SPK_AG_SFT 14 | ||
| 1305 | #define RT5645_SPK_AG_DIS (0x0 << 14) | ||
| 1306 | #define RT5645_SPK_AG_EN (0x1 << 14) | ||
| 1307 | |||
| 1308 | /* Micbias Control (0x93) */ | ||
| 1309 | #define RT5645_MIC1_BS_MASK (0x1 << 15) | ||
| 1310 | #define RT5645_MIC1_BS_SFT 15 | ||
| 1311 | #define RT5645_MIC1_BS_9AV (0x0 << 15) | ||
| 1312 | #define RT5645_MIC1_BS_75AV (0x1 << 15) | ||
| 1313 | #define RT5645_MIC2_BS_MASK (0x1 << 14) | ||
| 1314 | #define RT5645_MIC2_BS_SFT 14 | ||
| 1315 | #define RT5645_MIC2_BS_9AV (0x0 << 14) | ||
| 1316 | #define RT5645_MIC2_BS_75AV (0x1 << 14) | ||
| 1317 | #define RT5645_MIC1_CLK_MASK (0x1 << 13) | ||
| 1318 | #define RT5645_MIC1_CLK_SFT 13 | ||
| 1319 | #define RT5645_MIC1_CLK_DIS (0x0 << 13) | ||
| 1320 | #define RT5645_MIC1_CLK_EN (0x1 << 13) | ||
| 1321 | #define RT5645_MIC2_CLK_MASK (0x1 << 12) | ||
| 1322 | #define RT5645_MIC2_CLK_SFT 12 | ||
| 1323 | #define RT5645_MIC2_CLK_DIS (0x0 << 12) | ||
| 1324 | #define RT5645_MIC2_CLK_EN (0x1 << 12) | ||
| 1325 | #define RT5645_MIC1_OVCD_MASK (0x1 << 11) | ||
| 1326 | #define RT5645_MIC1_OVCD_SFT 11 | ||
| 1327 | #define RT5645_MIC1_OVCD_DIS (0x0 << 11) | ||
| 1328 | #define RT5645_MIC1_OVCD_EN (0x1 << 11) | ||
| 1329 | #define RT5645_MIC1_OVTH_MASK (0x3 << 9) | ||
| 1330 | #define RT5645_MIC1_OVTH_SFT 9 | ||
| 1331 | #define RT5645_MIC1_OVTH_600UA (0x0 << 9) | ||
| 1332 | #define RT5645_MIC1_OVTH_1500UA (0x1 << 9) | ||
| 1333 | #define RT5645_MIC1_OVTH_2000UA (0x2 << 9) | ||
| 1334 | #define RT5645_MIC2_OVCD_MASK (0x1 << 8) | ||
| 1335 | #define RT5645_MIC2_OVCD_SFT 8 | ||
| 1336 | #define RT5645_MIC2_OVCD_DIS (0x0 << 8) | ||
| 1337 | #define RT5645_MIC2_OVCD_EN (0x1 << 8) | ||
| 1338 | #define RT5645_MIC2_OVTH_MASK (0x3 << 6) | ||
| 1339 | #define RT5645_MIC2_OVTH_SFT 6 | ||
| 1340 | #define RT5645_MIC2_OVTH_600UA (0x0 << 6) | ||
| 1341 | #define RT5645_MIC2_OVTH_1500UA (0x1 << 6) | ||
| 1342 | #define RT5645_MIC2_OVTH_2000UA (0x2 << 6) | ||
| 1343 | #define RT5645_PWR_MB_MASK (0x1 << 5) | ||
| 1344 | #define RT5645_PWR_MB_SFT 5 | ||
| 1345 | #define RT5645_PWR_MB_PD (0x0 << 5) | ||
| 1346 | #define RT5645_PWR_MB_PU (0x1 << 5) | ||
| 1347 | #define RT5645_PWR_CLK25M_MASK (0x1 << 4) | ||
| 1348 | #define RT5645_PWR_CLK25M_SFT 4 | ||
| 1349 | #define RT5645_PWR_CLK25M_PD (0x0 << 4) | ||
| 1350 | #define RT5645_PWR_CLK25M_PU (0x1 << 4) | ||
| 1351 | |||
| 1352 | /* VAD Control 4 (0x9d) */ | ||
| 1353 | #define RT5645_VAD_SEL_MASK (0x3 << 8) | ||
| 1354 | #define RT5645_VAD_SEL_SFT 8 | ||
| 1355 | |||
| 1356 | /* EQ Control 1 (0xb0) */ | ||
| 1357 | #define RT5645_EQ_SRC_MASK (0x1 << 15) | ||
| 1358 | #define RT5645_EQ_SRC_SFT 15 | ||
| 1359 | #define RT5645_EQ_SRC_DAC (0x0 << 15) | ||
| 1360 | #define RT5645_EQ_SRC_ADC (0x1 << 15) | ||
| 1361 | #define RT5645_EQ_UPD (0x1 << 14) | ||
| 1362 | #define RT5645_EQ_UPD_BIT 14 | ||
| 1363 | #define RT5645_EQ_CD_MASK (0x1 << 13) | ||
| 1364 | #define RT5645_EQ_CD_SFT 13 | ||
| 1365 | #define RT5645_EQ_CD_DIS (0x0 << 13) | ||
| 1366 | #define RT5645_EQ_CD_EN (0x1 << 13) | ||
| 1367 | #define RT5645_EQ_DITH_MASK (0x3 << 8) | ||
| 1368 | #define RT5645_EQ_DITH_SFT 8 | ||
| 1369 | #define RT5645_EQ_DITH_NOR (0x0 << 8) | ||
| 1370 | #define RT5645_EQ_DITH_LSB (0x1 << 8) | ||
| 1371 | #define RT5645_EQ_DITH_LSB_1 (0x2 << 8) | ||
| 1372 | #define RT5645_EQ_DITH_LSB_2 (0x3 << 8) | ||
| 1373 | |||
| 1374 | /* EQ Control 2 (0xb1) */ | ||
| 1375 | #define RT5645_EQ_HPF1_M_MASK (0x1 << 8) | ||
| 1376 | #define RT5645_EQ_HPF1_M_SFT 8 | ||
| 1377 | #define RT5645_EQ_HPF1_M_HI (0x0 << 8) | ||
| 1378 | #define RT5645_EQ_HPF1_M_1ST (0x1 << 8) | ||
| 1379 | #define RT5645_EQ_LPF1_M_MASK (0x1 << 7) | ||
| 1380 | #define RT5645_EQ_LPF1_M_SFT 7 | ||
| 1381 | #define RT5645_EQ_LPF1_M_LO (0x0 << 7) | ||
| 1382 | #define RT5645_EQ_LPF1_M_1ST (0x1 << 7) | ||
| 1383 | #define RT5645_EQ_HPF2_MASK (0x1 << 6) | ||
| 1384 | #define RT5645_EQ_HPF2_SFT 6 | ||
| 1385 | #define RT5645_EQ_HPF2_DIS (0x0 << 6) | ||
| 1386 | #define RT5645_EQ_HPF2_EN (0x1 << 6) | ||
| 1387 | #define RT5645_EQ_HPF1_MASK (0x1 << 5) | ||
| 1388 | #define RT5645_EQ_HPF1_SFT 5 | ||
| 1389 | #define RT5645_EQ_HPF1_DIS (0x0 << 5) | ||
| 1390 | #define RT5645_EQ_HPF1_EN (0x1 << 5) | ||
| 1391 | #define RT5645_EQ_BPF4_MASK (0x1 << 4) | ||
| 1392 | #define RT5645_EQ_BPF4_SFT 4 | ||
| 1393 | #define RT5645_EQ_BPF4_DIS (0x0 << 4) | ||
| 1394 | #define RT5645_EQ_BPF4_EN (0x1 << 4) | ||
| 1395 | #define RT5645_EQ_BPF3_MASK (0x1 << 3) | ||
| 1396 | #define RT5645_EQ_BPF3_SFT 3 | ||
| 1397 | #define RT5645_EQ_BPF3_DIS (0x0 << 3) | ||
| 1398 | #define RT5645_EQ_BPF3_EN (0x1 << 3) | ||
| 1399 | #define RT5645_EQ_BPF2_MASK (0x1 << 2) | ||
| 1400 | #define RT5645_EQ_BPF2_SFT 2 | ||
| 1401 | #define RT5645_EQ_BPF2_DIS (0x0 << 2) | ||
| 1402 | #define RT5645_EQ_BPF2_EN (0x1 << 2) | ||
| 1403 | #define RT5645_EQ_BPF1_MASK (0x1 << 1) | ||
| 1404 | #define RT5645_EQ_BPF1_SFT 1 | ||
| 1405 | #define RT5645_EQ_BPF1_DIS (0x0 << 1) | ||
| 1406 | #define RT5645_EQ_BPF1_EN (0x1 << 1) | ||
| 1407 | #define RT5645_EQ_LPF_MASK (0x1) | ||
| 1408 | #define RT5645_EQ_LPF_SFT 0 | ||
| 1409 | #define RT5645_EQ_LPF_DIS (0x0) | ||
| 1410 | #define RT5645_EQ_LPF_EN (0x1) | ||
| 1411 | #define RT5645_EQ_CTRL_MASK (0x7f) | ||
| 1412 | |||
| 1413 | /* Memory Test (0xb2) */ | ||
| 1414 | #define RT5645_MT_MASK (0x1 << 15) | ||
| 1415 | #define RT5645_MT_SFT 15 | ||
| 1416 | #define RT5645_MT_DIS (0x0 << 15) | ||
| 1417 | #define RT5645_MT_EN (0x1 << 15) | ||
| 1418 | |||
| 1419 | /* DRC/AGC Control 1 (0xb4) */ | ||
| 1420 | #define RT5645_DRC_AGC_P_MASK (0x1 << 15) | ||
| 1421 | #define RT5645_DRC_AGC_P_SFT 15 | ||
| 1422 | #define RT5645_DRC_AGC_P_DAC (0x0 << 15) | ||
| 1423 | #define RT5645_DRC_AGC_P_ADC (0x1 << 15) | ||
| 1424 | #define RT5645_DRC_AGC_MASK (0x1 << 14) | ||
| 1425 | #define RT5645_DRC_AGC_SFT 14 | ||
| 1426 | #define RT5645_DRC_AGC_DIS (0x0 << 14) | ||
| 1427 | #define RT5645_DRC_AGC_EN (0x1 << 14) | ||
| 1428 | #define RT5645_DRC_AGC_UPD (0x1 << 13) | ||
| 1429 | #define RT5645_DRC_AGC_UPD_BIT 13 | ||
| 1430 | #define RT5645_DRC_AGC_AR_MASK (0x1f << 8) | ||
| 1431 | #define RT5645_DRC_AGC_AR_SFT 8 | ||
| 1432 | #define RT5645_DRC_AGC_R_MASK (0x7 << 5) | ||
| 1433 | #define RT5645_DRC_AGC_R_SFT 5 | ||
| 1434 | #define RT5645_DRC_AGC_R_48K (0x1 << 5) | ||
| 1435 | #define RT5645_DRC_AGC_R_96K (0x2 << 5) | ||
| 1436 | #define RT5645_DRC_AGC_R_192K (0x3 << 5) | ||
| 1437 | #define RT5645_DRC_AGC_R_441K (0x5 << 5) | ||
| 1438 | #define RT5645_DRC_AGC_R_882K (0x6 << 5) | ||
| 1439 | #define RT5645_DRC_AGC_R_1764K (0x7 << 5) | ||
| 1440 | #define RT5645_DRC_AGC_RC_MASK (0x1f) | ||
| 1441 | #define RT5645_DRC_AGC_RC_SFT 0 | ||
| 1442 | |||
| 1443 | /* DRC/AGC Control 2 (0xb5) */ | ||
| 1444 | #define RT5645_DRC_AGC_POB_MASK (0x3f << 8) | ||
| 1445 | #define RT5645_DRC_AGC_POB_SFT 8 | ||
| 1446 | #define RT5645_DRC_AGC_CP_MASK (0x1 << 7) | ||
| 1447 | #define RT5645_DRC_AGC_CP_SFT 7 | ||
| 1448 | #define RT5645_DRC_AGC_CP_DIS (0x0 << 7) | ||
| 1449 | #define RT5645_DRC_AGC_CP_EN (0x1 << 7) | ||
| 1450 | #define RT5645_DRC_AGC_CPR_MASK (0x3 << 5) | ||
| 1451 | #define RT5645_DRC_AGC_CPR_SFT 5 | ||
| 1452 | #define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5) | ||
| 1453 | #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5) | ||
| 1454 | #define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5) | ||
| 1455 | #define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5) | ||
| 1456 | #define RT5645_DRC_AGC_PRB_MASK (0x1f) | ||
| 1457 | #define RT5645_DRC_AGC_PRB_SFT 0 | ||
| 1458 | |||
| 1459 | /* DRC/AGC Control 3 (0xb6) */ | ||
| 1460 | #define RT5645_DRC_AGC_NGB_MASK (0xf << 12) | ||
| 1461 | #define RT5645_DRC_AGC_NGB_SFT 12 | ||
| 1462 | #define RT5645_DRC_AGC_TAR_MASK (0x1f << 7) | ||
| 1463 | #define RT5645_DRC_AGC_TAR_SFT 7 | ||
| 1464 | #define RT5645_DRC_AGC_NG_MASK (0x1 << 6) | ||
| 1465 | #define RT5645_DRC_AGC_NG_SFT 6 | ||
| 1466 | #define RT5645_DRC_AGC_NG_DIS (0x0 << 6) | ||
| 1467 | #define RT5645_DRC_AGC_NG_EN (0x1 << 6) | ||
| 1468 | #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5) | ||
| 1469 | #define RT5645_DRC_AGC_NGH_SFT 5 | ||
| 1470 | #define RT5645_DRC_AGC_NGH_DIS (0x0 << 5) | ||
| 1471 | #define RT5645_DRC_AGC_NGH_EN (0x1 << 5) | ||
| 1472 | #define RT5645_DRC_AGC_NGT_MASK (0x1f) | ||
| 1473 | #define RT5645_DRC_AGC_NGT_SFT 0 | ||
| 1474 | |||
| 1475 | /* ANC Control 1 (0xb8) */ | ||
| 1476 | #define RT5645_ANC_M_MASK (0x1 << 15) | ||
| 1477 | #define RT5645_ANC_M_SFT 15 | ||
| 1478 | #define RT5645_ANC_M_NOR (0x0 << 15) | ||
| 1479 | #define RT5645_ANC_M_REV (0x1 << 15) | ||
| 1480 | #define RT5645_ANC_MASK (0x1 << 14) | ||
| 1481 | #define RT5645_ANC_SFT 14 | ||
| 1482 | #define RT5645_ANC_DIS (0x0 << 14) | ||
| 1483 | #define RT5645_ANC_EN (0x1 << 14) | ||
| 1484 | #define RT5645_ANC_MD_MASK (0x3 << 12) | ||
| 1485 | #define RT5645_ANC_MD_SFT 12 | ||
| 1486 | #define RT5645_ANC_MD_DIS (0x0 << 12) | ||
| 1487 | #define RT5645_ANC_MD_67MS (0x1 << 12) | ||
| 1488 | #define RT5645_ANC_MD_267MS (0x2 << 12) | ||
| 1489 | #define RT5645_ANC_MD_1067MS (0x3 << 12) | ||
| 1490 | #define RT5645_ANC_SN_MASK (0x1 << 11) | ||
| 1491 | #define RT5645_ANC_SN_SFT 11 | ||
| 1492 | #define RT5645_ANC_SN_DIS (0x0 << 11) | ||
| 1493 | #define RT5645_ANC_SN_EN (0x1 << 11) | ||
| 1494 | #define RT5645_ANC_CLK_MASK (0x1 << 10) | ||
| 1495 | #define RT5645_ANC_CLK_SFT 10 | ||
| 1496 | #define RT5645_ANC_CLK_ANC (0x0 << 10) | ||
| 1497 | #define RT5645_ANC_CLK_REG (0x1 << 10) | ||
| 1498 | #define RT5645_ANC_ZCD_MASK (0x3 << 8) | ||
| 1499 | #define RT5645_ANC_ZCD_SFT 8 | ||
| 1500 | #define RT5645_ANC_ZCD_DIS (0x0 << 8) | ||
| 1501 | #define RT5645_ANC_ZCD_T1 (0x1 << 8) | ||
| 1502 | #define RT5645_ANC_ZCD_T2 (0x2 << 8) | ||
| 1503 | #define RT5645_ANC_ZCD_WT (0x3 << 8) | ||
| 1504 | #define RT5645_ANC_CS_MASK (0x1 << 7) | ||
| 1505 | #define RT5645_ANC_CS_SFT 7 | ||
| 1506 | #define RT5645_ANC_CS_DIS (0x0 << 7) | ||
| 1507 | #define RT5645_ANC_CS_EN (0x1 << 7) | ||
| 1508 | #define RT5645_ANC_SW_MASK (0x1 << 6) | ||
| 1509 | #define RT5645_ANC_SW_SFT 6 | ||
| 1510 | #define RT5645_ANC_SW_NOR (0x0 << 6) | ||
| 1511 | #define RT5645_ANC_SW_AUTO (0x1 << 6) | ||
| 1512 | #define RT5645_ANC_CO_L_MASK (0x3f) | ||
| 1513 | #define RT5645_ANC_CO_L_SFT 0 | ||
| 1514 | |||
| 1515 | /* ANC Control 2 (0xb6) */ | ||
| 1516 | #define RT5645_ANC_FG_R_MASK (0xf << 12) | ||
| 1517 | #define RT5645_ANC_FG_R_SFT 12 | ||
| 1518 | #define RT5645_ANC_FG_L_MASK (0xf << 8) | ||
| 1519 | #define RT5645_ANC_FG_L_SFT 8 | ||
| 1520 | #define RT5645_ANC_CG_R_MASK (0xf << 4) | ||
| 1521 | #define RT5645_ANC_CG_R_SFT 4 | ||
| 1522 | #define RT5645_ANC_CG_L_MASK (0xf) | ||
| 1523 | #define RT5645_ANC_CG_L_SFT 0 | ||
| 1524 | |||
| 1525 | /* ANC Control 3 (0xb6) */ | ||
| 1526 | #define RT5645_ANC_CD_MASK (0x1 << 6) | ||
| 1527 | #define RT5645_ANC_CD_SFT 6 | ||
| 1528 | #define RT5645_ANC_CD_BOTH (0x0 << 6) | ||
| 1529 | #define RT5645_ANC_CD_IND (0x1 << 6) | ||
| 1530 | #define RT5645_ANC_CO_R_MASK (0x3f) | ||
| 1531 | #define RT5645_ANC_CO_R_SFT 0 | ||
| 1532 | |||
| 1533 | /* Jack Detect Control (0xbb) */ | ||
| 1534 | #define RT5645_JD_MASK (0x7 << 13) | ||
| 1535 | #define RT5645_JD_SFT 13 | ||
| 1536 | #define RT5645_JD_DIS (0x0 << 13) | ||
| 1537 | #define RT5645_JD_GPIO1 (0x1 << 13) | ||
| 1538 | #define RT5645_JD_JD1_IN4P (0x2 << 13) | ||
| 1539 | #define RT5645_JD_JD2_IN4N (0x3 << 13) | ||
| 1540 | #define RT5645_JD_GPIO2 (0x4 << 13) | ||
| 1541 | #define RT5645_JD_GPIO3 (0x5 << 13) | ||
| 1542 | #define RT5645_JD_GPIO4 (0x6 << 13) | ||
| 1543 | #define RT5645_JD_HP_MASK (0x1 << 11) | ||
| 1544 | #define RT5645_JD_HP_SFT 11 | ||
| 1545 | #define RT5645_JD_HP_DIS (0x0 << 11) | ||
| 1546 | #define RT5645_JD_HP_EN (0x1 << 11) | ||
| 1547 | #define RT5645_JD_HP_TRG_MASK (0x1 << 10) | ||
| 1548 | #define RT5645_JD_HP_TRG_SFT 10 | ||
| 1549 | #define RT5645_JD_HP_TRG_LO (0x0 << 10) | ||
| 1550 | #define RT5645_JD_HP_TRG_HI (0x1 << 10) | ||
| 1551 | #define RT5645_JD_SPL_MASK (0x1 << 9) | ||
| 1552 | #define RT5645_JD_SPL_SFT 9 | ||
| 1553 | #define RT5645_JD_SPL_DIS (0x0 << 9) | ||
| 1554 | #define RT5645_JD_SPL_EN (0x1 << 9) | ||
| 1555 | #define RT5645_JD_SPL_TRG_MASK (0x1 << 8) | ||
| 1556 | #define RT5645_JD_SPL_TRG_SFT 8 | ||
| 1557 | #define RT5645_JD_SPL_TRG_LO (0x0 << 8) | ||
| 1558 | #define RT5645_JD_SPL_TRG_HI (0x1 << 8) | ||
| 1559 | #define RT5645_JD_SPR_MASK (0x1 << 7) | ||
| 1560 | #define RT5645_JD_SPR_SFT 7 | ||
| 1561 | #define RT5645_JD_SPR_DIS (0x0 << 7) | ||
| 1562 | #define RT5645_JD_SPR_EN (0x1 << 7) | ||
| 1563 | #define RT5645_JD_SPR_TRG_MASK (0x1 << 6) | ||
| 1564 | #define RT5645_JD_SPR_TRG_SFT 6 | ||
| 1565 | #define RT5645_JD_SPR_TRG_LO (0x0 << 6) | ||
| 1566 | #define RT5645_JD_SPR_TRG_HI (0x1 << 6) | ||
| 1567 | #define RT5645_JD_MO_MASK (0x1 << 5) | ||
| 1568 | #define RT5645_JD_MO_SFT 5 | ||
| 1569 | #define RT5645_JD_MO_DIS (0x0 << 5) | ||
| 1570 | #define RT5645_JD_MO_EN (0x1 << 5) | ||
| 1571 | #define RT5645_JD_MO_TRG_MASK (0x1 << 4) | ||
| 1572 | #define RT5645_JD_MO_TRG_SFT 4 | ||
| 1573 | #define RT5645_JD_MO_TRG_LO (0x0 << 4) | ||
| 1574 | #define RT5645_JD_MO_TRG_HI (0x1 << 4) | ||
| 1575 | #define RT5645_JD_LO_MASK (0x1 << 3) | ||
| 1576 | #define RT5645_JD_LO_SFT 3 | ||
| 1577 | #define RT5645_JD_LO_DIS (0x0 << 3) | ||
| 1578 | #define RT5645_JD_LO_EN (0x1 << 3) | ||
| 1579 | #define RT5645_JD_LO_TRG_MASK (0x1 << 2) | ||
| 1580 | #define RT5645_JD_LO_TRG_SFT 2 | ||
| 1581 | #define RT5645_JD_LO_TRG_LO (0x0 << 2) | ||
| 1582 | #define RT5645_JD_LO_TRG_HI (0x1 << 2) | ||
| 1583 | #define RT5645_JD1_IN4P_MASK (0x1 << 1) | ||
| 1584 | #define RT5645_JD1_IN4P_SFT 1 | ||
| 1585 | #define RT5645_JD1_IN4P_DIS (0x0 << 1) | ||
| 1586 | #define RT5645_JD1_IN4P_EN (0x1 << 1) | ||
| 1587 | #define RT5645_JD2_IN4N_MASK (0x1) | ||
| 1588 | #define RT5645_JD2_IN4N_SFT 0 | ||
| 1589 | #define RT5645_JD2_IN4N_DIS (0x0) | ||
| 1590 | #define RT5645_JD2_IN4N_EN (0x1) | ||
| 1591 | |||
| 1592 | /* Jack detect for ANC (0xbc) */ | ||
| 1593 | #define RT5645_ANC_DET_MASK (0x3 << 4) | ||
| 1594 | #define RT5645_ANC_DET_SFT 4 | ||
| 1595 | #define RT5645_ANC_DET_DIS (0x0 << 4) | ||
| 1596 | #define RT5645_ANC_DET_MB1 (0x1 << 4) | ||
| 1597 | #define RT5645_ANC_DET_MB2 (0x2 << 4) | ||
| 1598 | #define RT5645_ANC_DET_JD (0x3 << 4) | ||
| 1599 | #define RT5645_AD_TRG_MASK (0x1 << 3) | ||
| 1600 | #define RT5645_AD_TRG_SFT 3 | ||
| 1601 | #define RT5645_AD_TRG_LO (0x0 << 3) | ||
| 1602 | #define RT5645_AD_TRG_HI (0x1 << 3) | ||
| 1603 | #define RT5645_ANCM_DET_MASK (0x3 << 4) | ||
| 1604 | #define RT5645_ANCM_DET_SFT 4 | ||
| 1605 | #define RT5645_ANCM_DET_DIS (0x0 << 4) | ||
| 1606 | #define RT5645_ANCM_DET_MB1 (0x1 << 4) | ||
| 1607 | #define RT5645_ANCM_DET_MB2 (0x2 << 4) | ||
| 1608 | #define RT5645_ANCM_DET_JD (0x3 << 4) | ||
| 1609 | #define RT5645_AMD_TRG_MASK (0x1 << 3) | ||
| 1610 | #define RT5645_AMD_TRG_SFT 3 | ||
| 1611 | #define RT5645_AMD_TRG_LO (0x0 << 3) | ||
| 1612 | #define RT5645_AMD_TRG_HI (0x1 << 3) | ||
| 1613 | |||
| 1614 | /* IRQ Control 1 (0xbd) */ | ||
| 1615 | #define RT5645_IRQ_JD_MASK (0x1 << 15) | ||
| 1616 | #define RT5645_IRQ_JD_SFT 15 | ||
| 1617 | #define RT5645_IRQ_JD_BP (0x0 << 15) | ||
| 1618 | #define RT5645_IRQ_JD_NOR (0x1 << 15) | ||
| 1619 | #define RT5645_IRQ_OT_MASK (0x1 << 14) | ||
| 1620 | #define RT5645_IRQ_OT_SFT 14 | ||
| 1621 | #define RT5645_IRQ_OT_BP (0x0 << 14) | ||
| 1622 | #define RT5645_IRQ_OT_NOR (0x1 << 14) | ||
| 1623 | #define RT5645_JD_STKY_MASK (0x1 << 13) | ||
| 1624 | #define RT5645_JD_STKY_SFT 13 | ||
| 1625 | #define RT5645_JD_STKY_DIS (0x0 << 13) | ||
| 1626 | #define RT5645_JD_STKY_EN (0x1 << 13) | ||
| 1627 | #define RT5645_OT_STKY_MASK (0x1 << 12) | ||
| 1628 | #define RT5645_OT_STKY_SFT 12 | ||
| 1629 | #define RT5645_OT_STKY_DIS (0x0 << 12) | ||
| 1630 | #define RT5645_OT_STKY_EN (0x1 << 12) | ||
| 1631 | #define RT5645_JD_P_MASK (0x1 << 11) | ||
| 1632 | #define RT5645_JD_P_SFT 11 | ||
| 1633 | #define RT5645_JD_P_NOR (0x0 << 11) | ||
| 1634 | #define RT5645_JD_P_INV (0x1 << 11) | ||
| 1635 | #define RT5645_OT_P_MASK (0x1 << 10) | ||
| 1636 | #define RT5645_OT_P_SFT 10 | ||
| 1637 | #define RT5645_OT_P_NOR (0x0 << 10) | ||
| 1638 | #define RT5645_OT_P_INV (0x1 << 10) | ||
| 1639 | |||
| 1640 | /* IRQ Control 2 (0xbe) */ | ||
| 1641 | #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) | ||
| 1642 | #define RT5645_IRQ_MB1_OC_SFT 15 | ||
| 1643 | #define RT5645_IRQ_MB1_OC_BP (0x0 << 15) | ||
| 1644 | #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15) | ||
| 1645 | #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14) | ||
| 1646 | #define RT5645_IRQ_MB2_OC_SFT 14 | ||
| 1647 | #define RT5645_IRQ_MB2_OC_BP (0x0 << 14) | ||
| 1648 | #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14) | ||
| 1649 | #define RT5645_MB1_OC_STKY_MASK (0x1 << 13) | ||
| 1650 | #define RT5645_MB1_OC_STKY_SFT 13 | ||
| 1651 | #define RT5645_MB1_OC_STKY_DIS (0x0 << 13) | ||
| 1652 | #define RT5645_MB1_OC_STKY_EN (0x1 << 13) | ||
| 1653 | #define RT5645_MB2_OC_STKY_MASK (0x1 << 12) | ||
| 1654 | #define RT5645_MB2_OC_STKY_SFT 12 | ||
| 1655 | #define RT5645_MB2_OC_STKY_DIS (0x0 << 12) | ||
| 1656 | #define RT5645_MB2_OC_STKY_EN (0x1 << 12) | ||
| 1657 | #define RT5645_MB1_OC_P_MASK (0x1 << 7) | ||
| 1658 | #define RT5645_MB1_OC_P_SFT 7 | ||
| 1659 | #define RT5645_MB1_OC_P_NOR (0x0 << 7) | ||
| 1660 | #define RT5645_MB1_OC_P_INV (0x1 << 7) | ||
| 1661 | #define RT5645_MB2_OC_P_MASK (0x1 << 6) | ||
| 1662 | #define RT5645_MB2_OC_P_SFT 6 | ||
| 1663 | #define RT5645_MB2_OC_P_NOR (0x0 << 6) | ||
| 1664 | #define RT5645_MB2_OC_P_INV (0x1 << 6) | ||
| 1665 | #define RT5645_MB1_OC_CLR (0x1 << 3) | ||
| 1666 | #define RT5645_MB1_OC_CLR_SFT 3 | ||
| 1667 | #define RT5645_MB2_OC_CLR (0x1 << 2) | ||
| 1668 | #define RT5645_MB2_OC_CLR_SFT 2 | ||
| 1669 | |||
| 1670 | /* GPIO Control 1 (0xc0) */ | ||
| 1671 | #define RT5645_GP1_PIN_MASK (0x1 << 15) | ||
| 1672 | #define RT5645_GP1_PIN_SFT 15 | ||
| 1673 | #define RT5645_GP1_PIN_GPIO1 (0x0 << 15) | ||
| 1674 | #define RT5645_GP1_PIN_IRQ (0x1 << 15) | ||
| 1675 | #define RT5645_GP2_PIN_MASK (0x1 << 14) | ||
| 1676 | #define RT5645_GP2_PIN_SFT 14 | ||
| 1677 | #define RT5645_GP2_PIN_GPIO2 (0x0 << 14) | ||
| 1678 | #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14) | ||
| 1679 | #define RT5645_GP3_PIN_MASK (0x3 << 12) | ||
| 1680 | #define RT5645_GP3_PIN_SFT 12 | ||
| 1681 | #define RT5645_GP3_PIN_GPIO3 (0x0 << 12) | ||
| 1682 | #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12) | ||
| 1683 | #define RT5645_GP3_PIN_IRQ (0x2 << 12) | ||
| 1684 | #define RT5645_GP4_PIN_MASK (0x1 << 11) | ||
| 1685 | #define RT5645_GP4_PIN_SFT 11 | ||
| 1686 | #define RT5645_GP4_PIN_GPIO4 (0x0 << 11) | ||
| 1687 | #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11) | ||
| 1688 | #define RT5645_DP_SIG_MASK (0x1 << 10) | ||
| 1689 | #define RT5645_DP_SIG_SFT 10 | ||
| 1690 | #define RT5645_DP_SIG_TEST (0x0 << 10) | ||
| 1691 | #define RT5645_DP_SIG_AP (0x1 << 10) | ||
| 1692 | #define RT5645_GPIO_M_MASK (0x1 << 9) | ||
| 1693 | #define RT5645_GPIO_M_SFT 9 | ||
| 1694 | #define RT5645_GPIO_M_FLT (0x0 << 9) | ||
| 1695 | #define RT5645_GPIO_M_PH (0x1 << 9) | ||
| 1696 | #define RT5645_I2S2_SEL (0x1 << 8) | ||
| 1697 | #define RT5645_I2S2_SEL_SFT 8 | ||
| 1698 | #define RT5645_GP5_PIN_MASK (0x1 << 7) | ||
| 1699 | #define RT5645_GP5_PIN_SFT 7 | ||
| 1700 | #define RT5645_GP5_PIN_GPIO5 (0x0 << 7) | ||
| 1701 | #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7) | ||
| 1702 | #define RT5645_GP6_PIN_MASK (0x1 << 6) | ||
| 1703 | #define RT5645_GP6_PIN_SFT 6 | ||
| 1704 | #define RT5645_GP6_PIN_GPIO6 (0x0 << 6) | ||
| 1705 | #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6) | ||
| 1706 | #define RT5645_GP8_PIN_MASK (0x1 << 3) | ||
| 1707 | #define RT5645_GP8_PIN_SFT 3 | ||
| 1708 | #define RT5645_GP8_PIN_GPIO8 (0x0 << 3) | ||
| 1709 | #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3) | ||
| 1710 | #define RT5645_GP12_PIN_MASK (0x1 << 2) | ||
| 1711 | #define RT5645_GP12_PIN_SFT 2 | ||
| 1712 | #define RT5645_GP12_PIN_GPIO12 (0x0 << 2) | ||
| 1713 | #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2) | ||
| 1714 | #define RT5645_GP11_PIN_MASK (0x1 << 1) | ||
| 1715 | #define RT5645_GP11_PIN_SFT 1 | ||
| 1716 | #define RT5645_GP11_PIN_GPIO11 (0x0 << 1) | ||
| 1717 | #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1) | ||
| 1718 | #define RT5645_GP10_PIN_MASK (0x1) | ||
| 1719 | #define RT5645_GP10_PIN_SFT 0 | ||
| 1720 | #define RT5645_GP10_PIN_GPIO10 (0x0) | ||
| 1721 | #define RT5645_GP10_PIN_DMIC2_SDA (0x1) | ||
| 1722 | |||
| 1723 | /* GPIO Control 3 (0xc2) */ | ||
| 1724 | #define RT5645_GP4_PF_MASK (0x1 << 11) | ||
| 1725 | #define RT5645_GP4_PF_SFT 11 | ||
| 1726 | #define RT5645_GP4_PF_IN (0x0 << 11) | ||
| 1727 | #define RT5645_GP4_PF_OUT (0x1 << 11) | ||
| 1728 | #define RT5645_GP4_OUT_MASK (0x1 << 10) | ||
| 1729 | #define RT5645_GP4_OUT_SFT 10 | ||
| 1730 | #define RT5645_GP4_OUT_LO (0x0 << 10) | ||
| 1731 | #define RT5645_GP4_OUT_HI (0x1 << 10) | ||
| 1732 | #define RT5645_GP4_P_MASK (0x1 << 9) | ||
| 1733 | #define RT5645_GP4_P_SFT 9 | ||
| 1734 | #define RT5645_GP4_P_NOR (0x0 << 9) | ||
| 1735 | #define RT5645_GP4_P_INV (0x1 << 9) | ||
| 1736 | #define RT5645_GP3_PF_MASK (0x1 << 8) | ||
| 1737 | #define RT5645_GP3_PF_SFT 8 | ||
| 1738 | #define RT5645_GP3_PF_IN (0x0 << 8) | ||
| 1739 | #define RT5645_GP3_PF_OUT (0x1 << 8) | ||
| 1740 | #define RT5645_GP3_OUT_MASK (0x1 << 7) | ||
| 1741 | #define RT5645_GP3_OUT_SFT 7 | ||
| 1742 | #define RT5645_GP3_OUT_LO (0x0 << 7) | ||
| 1743 | #define RT5645_GP3_OUT_HI (0x1 << 7) | ||
| 1744 | #define RT5645_GP3_P_MASK (0x1 << 6) | ||
| 1745 | #define RT5645_GP3_P_SFT 6 | ||
| 1746 | #define RT5645_GP3_P_NOR (0x0 << 6) | ||
| 1747 | #define RT5645_GP3_P_INV (0x1 << 6) | ||
| 1748 | #define RT5645_GP2_PF_MASK (0x1 << 5) | ||
| 1749 | #define RT5645_GP2_PF_SFT 5 | ||
| 1750 | #define RT5645_GP2_PF_IN (0x0 << 5) | ||
| 1751 | #define RT5645_GP2_PF_OUT (0x1 << 5) | ||
| 1752 | #define RT5645_GP2_OUT_MASK (0x1 << 4) | ||
| 1753 | #define RT5645_GP2_OUT_SFT 4 | ||
| 1754 | #define RT5645_GP2_OUT_LO (0x0 << 4) | ||
| 1755 | #define RT5645_GP2_OUT_HI (0x1 << 4) | ||
| 1756 | #define RT5645_GP2_P_MASK (0x1 << 3) | ||
| 1757 | #define RT5645_GP2_P_SFT 3 | ||
| 1758 | #define RT5645_GP2_P_NOR (0x0 << 3) | ||
| 1759 | #define RT5645_GP2_P_INV (0x1 << 3) | ||
| 1760 | #define RT5645_GP1_PF_MASK (0x1 << 2) | ||
| 1761 | #define RT5645_GP1_PF_SFT 2 | ||
| 1762 | #define RT5645_GP1_PF_IN (0x0 << 2) | ||
| 1763 | #define RT5645_GP1_PF_OUT (0x1 << 2) | ||
| 1764 | #define RT5645_GP1_OUT_MASK (0x1 << 1) | ||
| 1765 | #define RT5645_GP1_OUT_SFT 1 | ||
| 1766 | #define RT5645_GP1_OUT_LO (0x0 << 1) | ||
| 1767 | #define RT5645_GP1_OUT_HI (0x1 << 1) | ||
| 1768 | #define RT5645_GP1_P_MASK (0x1) | ||
| 1769 | #define RT5645_GP1_P_SFT 0 | ||
| 1770 | #define RT5645_GP1_P_NOR (0x0) | ||
| 1771 | #define RT5645_GP1_P_INV (0x1) | ||
| 1772 | |||
| 1773 | /* Programmable Register Array Control 1 (0xc8) */ | ||
| 1774 | #define RT5645_REG_SEQ_MASK (0xf << 12) | ||
| 1775 | #define RT5645_REG_SEQ_SFT 12 | ||
| 1776 | #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/ | ||
| 1777 | #define RT5645_SEQ1_ST_SFT 11 | ||
| 1778 | #define RT5645_SEQ1_ST_RUN (0x0 << 11) | ||
| 1779 | #define RT5645_SEQ1_ST_FIN (0x1 << 11) | ||
| 1780 | #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/ | ||
| 1781 | #define RT5645_SEQ2_ST_SFT 10 | ||
| 1782 | #define RT5645_SEQ2_ST_RUN (0x0 << 10) | ||
| 1783 | #define RT5645_SEQ2_ST_FIN (0x1 << 10) | ||
| 1784 | #define RT5645_REG_LV_MASK (0x1 << 9) | ||
| 1785 | #define RT5645_REG_LV_SFT 9 | ||
| 1786 | #define RT5645_REG_LV_MX (0x0 << 9) | ||
| 1787 | #define RT5645_REG_LV_PR (0x1 << 9) | ||
| 1788 | #define RT5645_SEQ_2_PT_MASK (0x1 << 8) | ||
| 1789 | #define RT5645_SEQ_2_PT_BIT 8 | ||
| 1790 | #define RT5645_REG_IDX_MASK (0xff) | ||
| 1791 | #define RT5645_REG_IDX_SFT 0 | ||
| 1792 | |||
| 1793 | /* Programmable Register Array Control 2 (0xc9) */ | ||
| 1794 | #define RT5645_REG_DAT_MASK (0xffff) | ||
| 1795 | #define RT5645_REG_DAT_SFT 0 | ||
| 1796 | |||
| 1797 | /* Programmable Register Array Control 3 (0xca) */ | ||
| 1798 | #define RT5645_SEQ_DLY_MASK (0xff << 8) | ||
| 1799 | #define RT5645_SEQ_DLY_SFT 8 | ||
| 1800 | #define RT5645_PROG_MASK (0x1 << 7) | ||
| 1801 | #define RT5645_PROG_SFT 7 | ||
| 1802 | #define RT5645_PROG_DIS (0x0 << 7) | ||
| 1803 | #define RT5645_PROG_EN (0x1 << 7) | ||
| 1804 | #define RT5645_SEQ1_PT_RUN (0x1 << 6) | ||
| 1805 | #define RT5645_SEQ1_PT_RUN_BIT 6 | ||
| 1806 | #define RT5645_SEQ2_PT_RUN (0x1 << 5) | ||
| 1807 | #define RT5645_SEQ2_PT_RUN_BIT 5 | ||
| 1808 | |||
| 1809 | /* Programmable Register Array Control 4 (0xcb) */ | ||
| 1810 | #define RT5645_SEQ1_START_MASK (0xf << 8) | ||
| 1811 | #define RT5645_SEQ1_START_SFT 8 | ||
| 1812 | #define RT5645_SEQ1_END_MASK (0xf) | ||
| 1813 | #define RT5645_SEQ1_END_SFT 0 | ||
| 1814 | |||
| 1815 | /* Programmable Register Array Control 5 (0xcc) */ | ||
| 1816 | #define RT5645_SEQ2_START_MASK (0xf << 8) | ||
| 1817 | #define RT5645_SEQ2_START_SFT 8 | ||
| 1818 | #define RT5645_SEQ2_END_MASK (0xf) | ||
| 1819 | #define RT5645_SEQ2_END_SFT 0 | ||
| 1820 | |||
| 1821 | /* Scramble Function (0xcd) */ | ||
| 1822 | #define RT5645_SCB_KEY_MASK (0xff) | ||
| 1823 | #define RT5645_SCB_KEY_SFT 0 | ||
| 1824 | |||
| 1825 | /* Scramble Control (0xce) */ | ||
| 1826 | #define RT5645_SCB_SWAP_MASK (0x1 << 15) | ||
| 1827 | #define RT5645_SCB_SWAP_SFT 15 | ||
| 1828 | #define RT5645_SCB_SWAP_DIS (0x0 << 15) | ||
| 1829 | #define RT5645_SCB_SWAP_EN (0x1 << 15) | ||
| 1830 | #define RT5645_SCB_MASK (0x1 << 14) | ||
| 1831 | #define RT5645_SCB_SFT 14 | ||
| 1832 | #define RT5645_SCB_DIS (0x0 << 14) | ||
| 1833 | #define RT5645_SCB_EN (0x1 << 14) | ||
| 1834 | |||
| 1835 | /* Baseback Control (0xcf) */ | ||
| 1836 | #define RT5645_BB_MASK (0x1 << 15) | ||
| 1837 | #define RT5645_BB_SFT 15 | ||
| 1838 | #define RT5645_BB_DIS (0x0 << 15) | ||
| 1839 | #define RT5645_BB_EN (0x1 << 15) | ||
| 1840 | #define RT5645_BB_CT_MASK (0x7 << 12) | ||
| 1841 | #define RT5645_BB_CT_SFT 12 | ||
| 1842 | #define RT5645_BB_CT_A (0x0 << 12) | ||
| 1843 | #define RT5645_BB_CT_B (0x1 << 12) | ||
| 1844 | #define RT5645_BB_CT_C (0x2 << 12) | ||
| 1845 | #define RT5645_BB_CT_D (0x3 << 12) | ||
| 1846 | #define RT5645_M_BB_L_MASK (0x1 << 9) | ||
| 1847 | #define RT5645_M_BB_L_SFT 9 | ||
| 1848 | #define RT5645_M_BB_R_MASK (0x1 << 8) | ||
| 1849 | #define RT5645_M_BB_R_SFT 8 | ||
| 1850 | #define RT5645_M_BB_HPF_L_MASK (0x1 << 7) | ||
| 1851 | #define RT5645_M_BB_HPF_L_SFT 7 | ||
| 1852 | #define RT5645_M_BB_HPF_R_MASK (0x1 << 6) | ||
| 1853 | #define RT5645_M_BB_HPF_R_SFT 6 | ||
| 1854 | #define RT5645_G_BB_BST_MASK (0x3f) | ||
| 1855 | #define RT5645_G_BB_BST_SFT 0 | ||
| 1856 | |||
| 1857 | /* MP3 Plus Control 1 (0xd0) */ | ||
| 1858 | #define RT5645_M_MP3_L_MASK (0x1 << 15) | ||
| 1859 | #define RT5645_M_MP3_L_SFT 15 | ||
| 1860 | #define RT5645_M_MP3_R_MASK (0x1 << 14) | ||
| 1861 | #define RT5645_M_MP3_R_SFT 14 | ||
| 1862 | #define RT5645_M_MP3_MASK (0x1 << 13) | ||
| 1863 | #define RT5645_M_MP3_SFT 13 | ||
| 1864 | #define RT5645_M_MP3_DIS (0x0 << 13) | ||
| 1865 | #define RT5645_M_MP3_EN (0x1 << 13) | ||
| 1866 | #define RT5645_EG_MP3_MASK (0x1f << 8) | ||
| 1867 | #define RT5645_EG_MP3_SFT 8 | ||
| 1868 | #define RT5645_MP3_HLP_MASK (0x1 << 7) | ||
| 1869 | #define RT5645_MP3_HLP_SFT 7 | ||
| 1870 | #define RT5645_MP3_HLP_DIS (0x0 << 7) | ||
| 1871 | #define RT5645_MP3_HLP_EN (0x1 << 7) | ||
| 1872 | #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6) | ||
| 1873 | #define RT5645_M_MP3_ORG_L_SFT 6 | ||
| 1874 | #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5) | ||
| 1875 | #define RT5645_M_MP3_ORG_R_SFT 5 | ||
| 1876 | |||
| 1877 | /* MP3 Plus Control 2 (0xd1) */ | ||
| 1878 | #define RT5645_MP3_WT_MASK (0x1 << 13) | ||
| 1879 | #define RT5645_MP3_WT_SFT 13 | ||
| 1880 | #define RT5645_MP3_WT_1_4 (0x0 << 13) | ||
| 1881 | #define RT5645_MP3_WT_1_2 (0x1 << 13) | ||
| 1882 | #define RT5645_OG_MP3_MASK (0x1f << 8) | ||
| 1883 | #define RT5645_OG_MP3_SFT 8 | ||
| 1884 | #define RT5645_HG_MP3_MASK (0x3f) | ||
| 1885 | #define RT5645_HG_MP3_SFT 0 | ||
| 1886 | |||
| 1887 | /* 3D HP Control 1 (0xd2) */ | ||
| 1888 | #define RT5645_3D_CF_MASK (0x1 << 15) | ||
| 1889 | #define RT5645_3D_CF_SFT 15 | ||
| 1890 | #define RT5645_3D_CF_DIS (0x0 << 15) | ||
| 1891 | #define RT5645_3D_CF_EN (0x1 << 15) | ||
| 1892 | #define RT5645_3D_HP_MASK (0x1 << 14) | ||
| 1893 | #define RT5645_3D_HP_SFT 14 | ||
| 1894 | #define RT5645_3D_HP_DIS (0x0 << 14) | ||
| 1895 | #define RT5645_3D_HP_EN (0x1 << 14) | ||
| 1896 | #define RT5645_3D_BT_MASK (0x1 << 13) | ||
| 1897 | #define RT5645_3D_BT_SFT 13 | ||
| 1898 | #define RT5645_3D_BT_DIS (0x0 << 13) | ||
| 1899 | #define RT5645_3D_BT_EN (0x1 << 13) | ||
| 1900 | #define RT5645_3D_1F_MIX_MASK (0x3 << 11) | ||
| 1901 | #define RT5645_3D_1F_MIX_SFT 11 | ||
| 1902 | #define RT5645_3D_HP_M_MASK (0x1 << 10) | ||
| 1903 | #define RT5645_3D_HP_M_SFT 10 | ||
| 1904 | #define RT5645_3D_HP_M_SUR (0x0 << 10) | ||
| 1905 | #define RT5645_3D_HP_M_FRO (0x1 << 10) | ||
| 1906 | #define RT5645_M_3D_HRTF_MASK (0x1 << 9) | ||
| 1907 | #define RT5645_M_3D_HRTF_SFT 9 | ||
| 1908 | #define RT5645_M_3D_D2H_MASK (0x1 << 8) | ||
| 1909 | #define RT5645_M_3D_D2H_SFT 8 | ||
| 1910 | #define RT5645_M_3D_D2R_MASK (0x1 << 7) | ||
| 1911 | #define RT5645_M_3D_D2R_SFT 7 | ||
| 1912 | #define RT5645_M_3D_REVB_MASK (0x1 << 6) | ||
| 1913 | #define RT5645_M_3D_REVB_SFT 6 | ||
| 1914 | |||
| 1915 | /* Adjustable high pass filter control 1 (0xd3) */ | ||
| 1916 | #define RT5645_2ND_HPF_MASK (0x1 << 15) | ||
| 1917 | #define RT5645_2ND_HPF_SFT 15 | ||
| 1918 | #define RT5645_2ND_HPF_DIS (0x0 << 15) | ||
| 1919 | #define RT5645_2ND_HPF_EN (0x1 << 15) | ||
| 1920 | #define RT5645_HPF_CF_L_MASK (0x7 << 12) | ||
| 1921 | #define RT5645_HPF_CF_L_SFT 12 | ||
| 1922 | #define RT5645_1ST_HPF_MASK (0x1 << 11) | ||
| 1923 | #define RT5645_1ST_HPF_SFT 11 | ||
| 1924 | #define RT5645_1ST_HPF_DIS (0x0 << 11) | ||
| 1925 | #define RT5645_1ST_HPF_EN (0x1 << 11) | ||
| 1926 | #define RT5645_HPF_CF_R_MASK (0x7 << 8) | ||
| 1927 | #define RT5645_HPF_CF_R_SFT 8 | ||
| 1928 | #define RT5645_ZD_T_MASK (0x3 << 6) | ||
| 1929 | #define RT5645_ZD_T_SFT 6 | ||
| 1930 | #define RT5645_ZD_F_MASK (0x3 << 4) | ||
| 1931 | #define RT5645_ZD_F_SFT 4 | ||
| 1932 | #define RT5645_ZD_F_IM (0x0 << 4) | ||
| 1933 | #define RT5645_ZD_F_ZC_IM (0x1 << 4) | ||
| 1934 | #define RT5645_ZD_F_ZC_IOD (0x2 << 4) | ||
| 1935 | #define RT5645_ZD_F_UN (0x3 << 4) | ||
| 1936 | |||
| 1937 | /* HP calibration control and Amp detection (0xd6) */ | ||
| 1938 | #define RT5645_SI_DAC_MASK (0x1 << 11) | ||
| 1939 | #define RT5645_SI_DAC_SFT 11 | ||
| 1940 | #define RT5645_SI_DAC_AUTO (0x0 << 11) | ||
| 1941 | #define RT5645_SI_DAC_TEST (0x1 << 11) | ||
| 1942 | #define RT5645_DC_CAL_M_MASK (0x1 << 10) | ||
| 1943 | #define RT5645_DC_CAL_M_SFT 10 | ||
| 1944 | #define RT5645_DC_CAL_M_CAL (0x0 << 10) | ||
| 1945 | #define RT5645_DC_CAL_M_NOR (0x1 << 10) | ||
| 1946 | #define RT5645_DC_CAL_MASK (0x1 << 9) | ||
| 1947 | #define RT5645_DC_CAL_SFT 9 | ||
| 1948 | #define RT5645_DC_CAL_DIS (0x0 << 9) | ||
| 1949 | #define RT5645_DC_CAL_EN (0x1 << 9) | ||
| 1950 | #define RT5645_HPD_RCV_MASK (0x7 << 6) | ||
| 1951 | #define RT5645_HPD_RCV_SFT 6 | ||
| 1952 | #define RT5645_HPD_PS_MASK (0x1 << 5) | ||
| 1953 | #define RT5645_HPD_PS_SFT 5 | ||
| 1954 | #define RT5645_HPD_PS_DIS (0x0 << 5) | ||
| 1955 | #define RT5645_HPD_PS_EN (0x1 << 5) | ||
| 1956 | #define RT5645_CAL_M_MASK (0x1 << 4) | ||
| 1957 | #define RT5645_CAL_M_SFT 4 | ||
| 1958 | #define RT5645_CAL_M_DEP (0x0 << 4) | ||
| 1959 | #define RT5645_CAL_M_CAL (0x1 << 4) | ||
| 1960 | #define RT5645_CAL_MASK (0x1 << 3) | ||
| 1961 | #define RT5645_CAL_SFT 3 | ||
| 1962 | #define RT5645_CAL_DIS (0x0 << 3) | ||
| 1963 | #define RT5645_CAL_EN (0x1 << 3) | ||
| 1964 | #define RT5645_CAL_TEST_MASK (0x1 << 2) | ||
| 1965 | #define RT5645_CAL_TEST_SFT 2 | ||
| 1966 | #define RT5645_CAL_TEST_DIS (0x0 << 2) | ||
| 1967 | #define RT5645_CAL_TEST_EN (0x1 << 2) | ||
| 1968 | #define RT5645_CAL_P_MASK (0x3) | ||
| 1969 | #define RT5645_CAL_P_SFT 0 | ||
| 1970 | #define RT5645_CAL_P_NONE (0x0) | ||
| 1971 | #define RT5645_CAL_P_CAL (0x1) | ||
| 1972 | #define RT5645_CAL_P_DAC_CAL (0x2) | ||
| 1973 | |||
| 1974 | /* Soft volume and zero cross control 1 (0xd9) */ | ||
| 1975 | #define RT5645_SV_MASK (0x1 << 15) | ||
| 1976 | #define RT5645_SV_SFT 15 | ||
| 1977 | #define RT5645_SV_DIS (0x0 << 15) | ||
| 1978 | #define RT5645_SV_EN (0x1 << 15) | ||
| 1979 | #define RT5645_SPO_SV_MASK (0x1 << 14) | ||
| 1980 | #define RT5645_SPO_SV_SFT 14 | ||
| 1981 | #define RT5645_SPO_SV_DIS (0x0 << 14) | ||
| 1982 | #define RT5645_SPO_SV_EN (0x1 << 14) | ||
| 1983 | #define RT5645_OUT_SV_MASK (0x1 << 13) | ||
| 1984 | #define RT5645_OUT_SV_SFT 13 | ||
| 1985 | #define RT5645_OUT_SV_DIS (0x0 << 13) | ||
| 1986 | #define RT5645_OUT_SV_EN (0x1 << 13) | ||
| 1987 | #define RT5645_HP_SV_MASK (0x1 << 12) | ||
| 1988 | #define RT5645_HP_SV_SFT 12 | ||
| 1989 | #define RT5645_HP_SV_DIS (0x0 << 12) | ||
| 1990 | #define RT5645_HP_SV_EN (0x1 << 12) | ||
| 1991 | #define RT5645_ZCD_DIG_MASK (0x1 << 11) | ||
| 1992 | #define RT5645_ZCD_DIG_SFT 11 | ||
| 1993 | #define RT5645_ZCD_DIG_DIS (0x0 << 11) | ||
| 1994 | #define RT5645_ZCD_DIG_EN (0x1 << 11) | ||
| 1995 | #define RT5645_ZCD_MASK (0x1 << 10) | ||
| 1996 | #define RT5645_ZCD_SFT 10 | ||
| 1997 | #define RT5645_ZCD_PD (0x0 << 10) | ||
| 1998 | #define RT5645_ZCD_PU (0x1 << 10) | ||
| 1999 | #define RT5645_M_ZCD_MASK (0x3f << 4) | ||
| 2000 | #define RT5645_M_ZCD_SFT 4 | ||
| 2001 | #define RT5645_M_ZCD_RM_L (0x1 << 9) | ||
| 2002 | #define RT5645_M_ZCD_RM_R (0x1 << 8) | ||
| 2003 | #define RT5645_M_ZCD_SM_L (0x1 << 7) | ||
| 2004 | #define RT5645_M_ZCD_SM_R (0x1 << 6) | ||
| 2005 | #define RT5645_M_ZCD_OM_L (0x1 << 5) | ||
| 2006 | #define RT5645_M_ZCD_OM_R (0x1 << 4) | ||
| 2007 | #define RT5645_SV_DLY_MASK (0xf) | ||
| 2008 | #define RT5645_SV_DLY_SFT 0 | ||
| 2009 | |||
| 2010 | /* Soft volume and zero cross control 2 (0xda) */ | ||
| 2011 | #define RT5645_ZCD_HP_MASK (0x1 << 15) | ||
| 2012 | #define RT5645_ZCD_HP_SFT 15 | ||
| 2013 | #define RT5645_ZCD_HP_DIS (0x0 << 15) | ||
| 2014 | #define RT5645_ZCD_HP_EN (0x1 << 15) | ||
| 2015 | |||
| 2016 | |||
| 2017 | /* Codec Private Register definition */ | ||
| 2018 | /* 3D Speaker Control (0x63) */ | ||
| 2019 | #define RT5645_3D_SPK_MASK (0x1 << 15) | ||
| 2020 | #define RT5645_3D_SPK_SFT 15 | ||
| 2021 | #define RT5645_3D_SPK_DIS (0x0 << 15) | ||
| 2022 | #define RT5645_3D_SPK_EN (0x1 << 15) | ||
| 2023 | #define RT5645_3D_SPK_M_MASK (0x3 << 13) | ||
| 2024 | #define RT5645_3D_SPK_M_SFT 13 | ||
| 2025 | #define RT5645_3D_SPK_CG_MASK (0x1f << 8) | ||
| 2026 | #define RT5645_3D_SPK_CG_SFT 8 | ||
| 2027 | #define RT5645_3D_SPK_SG_MASK (0x1f) | ||
| 2028 | #define RT5645_3D_SPK_SG_SFT 0 | ||
| 2029 | |||
| 2030 | /* Wind Noise Detection Control 1 (0x6c) */ | ||
| 2031 | #define RT5645_WND_MASK (0x1 << 15) | ||
| 2032 | #define RT5645_WND_SFT 15 | ||
| 2033 | #define RT5645_WND_DIS (0x0 << 15) | ||
| 2034 | #define RT5645_WND_EN (0x1 << 15) | ||
| 2035 | |||
| 2036 | /* Wind Noise Detection Control 2 (0x6d) */ | ||
| 2037 | #define RT5645_WND_FC_NW_MASK (0x3f << 10) | ||
| 2038 | #define RT5645_WND_FC_NW_SFT 10 | ||
| 2039 | #define RT5645_WND_FC_WK_MASK (0x3f << 4) | ||
| 2040 | #define RT5645_WND_FC_WK_SFT 4 | ||
| 2041 | |||
| 2042 | /* Wind Noise Detection Control 3 (0x6e) */ | ||
| 2043 | #define RT5645_HPF_FC_MASK (0x3f << 6) | ||
| 2044 | #define RT5645_HPF_FC_SFT 6 | ||
| 2045 | #define RT5645_WND_FC_ST_MASK (0x3f) | ||
| 2046 | #define RT5645_WND_FC_ST_SFT 0 | ||
| 2047 | |||
| 2048 | /* Wind Noise Detection Control 4 (0x6f) */ | ||
| 2049 | #define RT5645_WND_TH_LO_MASK (0x3ff) | ||
| 2050 | #define RT5645_WND_TH_LO_SFT 0 | ||
| 2051 | |||
| 2052 | /* Wind Noise Detection Control 5 (0x70) */ | ||
| 2053 | #define RT5645_WND_TH_HI_MASK (0x3ff) | ||
| 2054 | #define RT5645_WND_TH_HI_SFT 0 | ||
| 2055 | |||
| 2056 | /* Wind Noise Detection Control 8 (0x73) */ | ||
| 2057 | #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */ | ||
| 2058 | #define RT5645_WND_WIND_SFT 13 | ||
| 2059 | #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ | ||
| 2060 | #define RT5645_WND_STRONG_SFT 12 | ||
| 2061 | enum { | ||
| 2062 | RT5645_NO_WIND, | ||
| 2063 | RT5645_BREEZE, | ||
| 2064 | RT5645_STORM, | ||
| 2065 | }; | ||
| 2066 | |||
| 2067 | /* Dipole Speaker Interface (0x75) */ | ||
| 2068 | #define RT5645_DP_ATT_MASK (0x3 << 14) | ||
| 2069 | #define RT5645_DP_ATT_SFT 14 | ||
| 2070 | #define RT5645_DP_SPK_MASK (0x1 << 10) | ||
| 2071 | #define RT5645_DP_SPK_SFT 10 | ||
| 2072 | #define RT5645_DP_SPK_DIS (0x0 << 10) | ||
| 2073 | #define RT5645_DP_SPK_EN (0x1 << 10) | ||
| 2074 | |||
| 2075 | /* EQ Pre Volume Control (0xb3) */ | ||
| 2076 | #define RT5645_EQ_PRE_VOL_MASK (0xffff) | ||
| 2077 | #define RT5645_EQ_PRE_VOL_SFT 0 | ||
| 2078 | |||
| 2079 | /* EQ Post Volume Control (0xb4) */ | ||
| 2080 | #define RT5645_EQ_PST_VOL_MASK (0xffff) | ||
| 2081 | #define RT5645_EQ_PST_VOL_SFT 0 | ||
| 2082 | |||
| 2083 | /* Jack Detect Control 3 (0xf8) */ | ||
| 2084 | #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12) | ||
| 2085 | #define RT5645_JD_CBJ_EN (0x1 << 7) | ||
| 2086 | #define RT5645_JD_CBJ_POL (0x1 << 6) | ||
| 2087 | #define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3) | ||
| 2088 | #define RT5645_JD_TRI_CBJ_SEL_SFT (3) | ||
| 2089 | #define RT5645_JD_TRI_HPO_SEL_MASK (0x7) | ||
| 2090 | #define RT5645_JD_TRI_HPO_SEL_SFT (0) | ||
| 2091 | #define RT5645_JD_F_GPIO_JD1 (0x0) | ||
| 2092 | #define RT5645_JD_F_JD1_1 (0x1) | ||
| 2093 | #define RT5645_JD_F_JD1_2 (0x2) | ||
| 2094 | #define RT5645_JD_F_JD2 (0x3) | ||
| 2095 | #define RT5645_JD_F_JD3 (0x4) | ||
| 2096 | #define RT5645_JD_F_GPIO_JD2 (0x5) | ||
| 2097 | #define RT5645_JD_F_MX0B_12 (0x6) | ||
| 2098 | |||
| 2099 | /* Digital Misc Control (0xfa) */ | ||
| 2100 | #define RT5645_RST_DSP (0x1 << 13) | ||
| 2101 | #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12) | ||
| 2102 | #define RT5645_IF1_ADC1_IN1_SFT 12 | ||
| 2103 | #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11) | ||
| 2104 | #define RT5645_IF1_ADC1_IN2_SFT 11 | ||
| 2105 | #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10) | ||
| 2106 | #define RT5645_IF1_ADC2_IN1_SFT 10 | ||
| 2107 | #define RT5645_DIG_GATE_CTRL 0x1 | ||
| 2108 | |||
| 2109 | /* General Control2 (0xfb) */ | ||
| 2110 | #define RT5645_RXDC_SRC_MASK (0x1 << 7) | ||
| 2111 | #define RT5645_RXDC_SRC_STO (0x0 << 7) | ||
| 2112 | #define RT5645_RXDC_SRC_MONO (0x1 << 7) | ||
| 2113 | #define RT5645_RXDC_SRC_SFT (7) | ||
| 2114 | #define RT5645_RXDP2_SEL_MASK (0x1 << 3) | ||
| 2115 | #define RT5645_RXDP2_SEL_IF2 (0x0 << 3) | ||
| 2116 | #define RT5645_RXDP2_SEL_ADC (0x1 << 3) | ||
| 2117 | #define RT5645_RXDP2_SEL_SFT (3) | ||
| 2118 | |||
| 2119 | |||
| 2120 | /* Vendor ID (0xfd) */ | ||
| 2121 | #define RT5645_VER_C 0x2 | ||
| 2122 | #define RT5645_VER_D 0x3 | ||
| 2123 | |||
| 2124 | |||
| 2125 | /* Volume Rescale */ | ||
| 2126 | #define RT5645_VOL_RSCL_MAX 0x27 | ||
| 2127 | #define RT5645_VOL_RSCL_RANGE 0x1F | ||
| 2128 | /* Debug String Length */ | ||
| 2129 | #define RT5645_REG_DISP_LEN 23 | ||
| 2130 | |||
| 2131 | |||
| 2132 | /* System Clock Source */ | ||
| 2133 | enum { | ||
| 2134 | RT5645_SCLK_S_MCLK, | ||
| 2135 | RT5645_SCLK_S_PLL1, | ||
| 2136 | RT5645_SCLK_S_RCCLK, | ||
| 2137 | }; | ||
| 2138 | |||
| 2139 | /* PLL1 Source */ | ||
| 2140 | enum { | ||
| 2141 | RT5645_PLL1_S_MCLK, | ||
| 2142 | RT5645_PLL1_S_BCLK1, | ||
| 2143 | RT5645_PLL1_S_BCLK2, | ||
| 2144 | }; | ||
| 2145 | |||
| 2146 | enum { | ||
| 2147 | RT5645_AIF1, | ||
| 2148 | RT5645_AIF2, | ||
| 2149 | RT5645_AIFS, | ||
| 2150 | }; | ||
| 2151 | |||
| 2152 | enum { | ||
| 2153 | RT5645_DMIC_DATA_IN2P, | ||
| 2154 | RT5645_DMIC_DATA_GPIO6, | ||
| 2155 | RT5645_DMIC_DATA_GPIO10, | ||
| 2156 | RT5645_DMIC_DATA_GPIO12, | ||
| 2157 | }; | ||
| 2158 | |||
| 2159 | enum { | ||
| 2160 | RT5645_DMIC_DATA_IN2N, | ||
| 2161 | RT5645_DMIC_DATA_GPIO5, | ||
| 2162 | RT5645_DMIC_DATA_GPIO11, | ||
| 2163 | }; | ||
| 2164 | |||
| 2165 | struct rt5645_pll_code { | ||
| 2166 | bool m_bp; /* Indicates bypass m code or not. */ | ||
| 2167 | int m_code; | ||
| 2168 | int n_code; | ||
| 2169 | int k_code; | ||
| 2170 | }; | ||
| 2171 | |||
| 2172 | struct rt5645_priv { | ||
| 2173 | struct snd_soc_codec *codec; | ||
| 2174 | struct rt5645_platform_data pdata; | ||
| 2175 | struct regmap *regmap; | ||
| 2176 | |||
| 2177 | int sysclk; | ||
| 2178 | int sysclk_src; | ||
| 2179 | int lrck[RT5645_AIFS]; | ||
| 2180 | int bclk[RT5645_AIFS]; | ||
| 2181 | int master[RT5645_AIFS]; | ||
| 2182 | |||
| 2183 | int pll_src; | ||
| 2184 | int pll_in; | ||
| 2185 | int pll_out; | ||
| 2186 | }; | ||
| 2187 | |||
| 2188 | #endif /* __RT5645_H__ */ | ||