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authorOder Chiou <oder_chiou@realtek.com>2014-04-28 07:59:10 -0400
committerMark Brown <broonie@linaro.org>2014-05-03 13:36:10 -0400
commit1319b2f6a565231ca2e3f368ab7f74fc4714c799 (patch)
tree53c72251c9aa2f864e56dce60729bb446e5140ea
parent871c131dcbee80e9459bf695c8c5cfd6bf0d26d6 (diff)
ASoC: rt5645: Add codec driver
This patch adds the Realtek ALC5645 codec driver. It is the base version that because the jack detect function is not implemented to it, the headphone and AMIC1 are not workable. We will fill up the further functions later. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Oder Chiou <oder_chiou@realtek.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat
-rw-r--r--include/sound/rt5645.h25
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5645.c2476
-rw-r--r--sound/soc/codecs/rt5645.h2188
5 files changed, 4695 insertions, 0 deletions
diff --git a/include/sound/rt5645.h b/include/sound/rt5645.h
new file mode 100644
index 000000000000..1de744c242f6
--- /dev/null
+++ b/include/sound/rt5645.h
@@ -0,0 +1,25 @@
1/*
2 * linux/sound/rt5645.h -- Platform data for RT5645
3 *
4 * Copyright 2013 Realtek Microelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_RT5645_H
12#define __LINUX_SND_RT5645_H
13
14struct rt5645_platform_data {
15 /* IN2 can optionally be differential */
16 bool in2_diff;
17
18 bool dmic_en;
19 unsigned int dmic1_data_pin;
20 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
21 unsigned int dmic2_data_pin;
22 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
23};
24
25#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index deba71bad6e9..d29f19b44638 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -71,6 +71,7 @@ config SND_SOC_ALL_CODECS
71 select SND_SOC_PCM512x_SPI if SPI_MASTER 71 select SND_SOC_PCM512x_SPI if SPI_MASTER
72 select SND_SOC_RT5631 if I2C 72 select SND_SOC_RT5631 if I2C
73 select SND_SOC_RT5640 if I2C 73 select SND_SOC_RT5640 if I2C
74 select SND_SOC_RT5645 if I2C
74 select SND_SOC_RT5651 if I2C 75 select SND_SOC_RT5651 if I2C
75 select SND_SOC_SGTL5000 if I2C 76 select SND_SOC_SGTL5000 if I2C
76 select SND_SOC_SI476X if MFD_SI476X_CORE 77 select SND_SOC_SI476X if MFD_SI476X_CORE
@@ -397,6 +398,9 @@ config SND_SOC_RT5631
397config SND_SOC_RT5640 398config SND_SOC_RT5640
398 tristate 399 tristate
399 400
401config SND_SOC_RT5645
402 tristate
403
400config SND_SOC_RT5651 404config SND_SOC_RT5651
401 tristate 405 tristate
402 406
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index e76938ee82f4..a3d12b4af1e7 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -60,6 +60,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
60snd-soc-pcm512x-spi-objs := pcm512x-spi.o 60snd-soc-pcm512x-spi-objs := pcm512x-spi.o
61snd-soc-rt5631-objs := rt5631.o 61snd-soc-rt5631-objs := rt5631.o
62snd-soc-rt5640-objs := rt5640.o 62snd-soc-rt5640-objs := rt5640.o
63snd-soc-rt5645-objs := rt5645.o
63snd-soc-rt5651-objs := rt5651.o 64snd-soc-rt5651-objs := rt5651.o
64snd-soc-sgtl5000-objs := sgtl5000.o 65snd-soc-sgtl5000-objs := sgtl5000.o
65snd-soc-alc5623-objs := alc5623.o 66snd-soc-alc5623-objs := alc5623.o
@@ -212,6 +213,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
212obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o 213obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
213obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 214obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
214obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 215obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
216obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
215obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 217obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
216obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 218obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
217obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 219obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
new file mode 100644
index 000000000000..7d8cc1688fb5
--- /dev/null
+++ b/sound/soc/codecs/rt5645.c
@@ -0,0 +1,2476 @@
1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "rt5645.h"
30
31#define RT5645_DEVICE_ID 0x6308
32
33#define RT5645_PR_RANGE_BASE (0xff + 1)
34#define RT5645_PR_SPACING 0x100
35
36#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
37
38static const struct regmap_range_cfg rt5645_ranges[] = {
39 {
40 .name = "PR",
41 .range_min = RT5645_PR_BASE,
42 .range_max = RT5645_PR_BASE + 0xf8,
43 .selector_reg = RT5645_PRIV_INDEX,
44 .selector_mask = 0xff,
45 .selector_shift = 0x0,
46 .window_start = RT5645_PRIV_DATA,
47 .window_len = 0x1,
48 },
49};
50
51static const struct reg_default init_list[] = {
52 {RT5645_PR_BASE + 0x3d, 0x3600},
53};
54#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
55
56static const struct reg_default rt5645_reg[] = {
57 { 0x00, 0x0000 },
58 { 0x01, 0xc8c8 },
59 { 0x02, 0xc8c8 },
60 { 0x03, 0xc8c8 },
61 { 0x0a, 0x0002 },
62 { 0x0b, 0x2827 },
63 { 0x0c, 0xe000 },
64 { 0x0d, 0x0000 },
65 { 0x0e, 0x0000 },
66 { 0x0f, 0x0808 },
67 { 0x14, 0x3333 },
68 { 0x16, 0x4b00 },
69 { 0x18, 0x018b },
70 { 0x19, 0xafaf },
71 { 0x1a, 0xafaf },
72 { 0x1b, 0x0001 },
73 { 0x1c, 0x2f2f },
74 { 0x1d, 0x2f2f },
75 { 0x1e, 0x0000 },
76 { 0x20, 0x0000 },
77 { 0x27, 0x7060 },
78 { 0x28, 0x7070 },
79 { 0x29, 0x8080 },
80 { 0x2a, 0x5656 },
81 { 0x2b, 0x5454 },
82 { 0x2c, 0xaaa0 },
83 { 0x2f, 0x1002 },
84 { 0x31, 0x5000 },
85 { 0x32, 0x0000 },
86 { 0x33, 0x0000 },
87 { 0x34, 0x0000 },
88 { 0x35, 0x0000 },
89 { 0x3b, 0x0000 },
90 { 0x3c, 0x007f },
91 { 0x3d, 0x0000 },
92 { 0x3e, 0x007f },
93 { 0x3f, 0x0000 },
94 { 0x40, 0x001f },
95 { 0x41, 0x0000 },
96 { 0x42, 0x001f },
97 { 0x45, 0x6000 },
98 { 0x46, 0x003e },
99 { 0x47, 0x003e },
100 { 0x48, 0xf807 },
101 { 0x4a, 0x0004 },
102 { 0x4d, 0x0000 },
103 { 0x4e, 0x0000 },
104 { 0x4f, 0x01ff },
105 { 0x50, 0x0000 },
106 { 0x51, 0x0000 },
107 { 0x52, 0x01ff },
108 { 0x53, 0xf000 },
109 { 0x56, 0x0111 },
110 { 0x57, 0x0064 },
111 { 0x58, 0xef0e },
112 { 0x59, 0xf0f0 },
113 { 0x5a, 0xef0e },
114 { 0x5b, 0xf0f0 },
115 { 0x5c, 0xef0e },
116 { 0x5d, 0xf0f0 },
117 { 0x5e, 0xf000 },
118 { 0x5f, 0x0000 },
119 { 0x61, 0x0300 },
120 { 0x62, 0x0000 },
121 { 0x63, 0x00c2 },
122 { 0x64, 0x0000 },
123 { 0x65, 0x0000 },
124 { 0x66, 0x0000 },
125 { 0x6a, 0x0000 },
126 { 0x6c, 0x0aaa },
127 { 0x70, 0x8000 },
128 { 0x71, 0x8000 },
129 { 0x72, 0x8000 },
130 { 0x73, 0x7770 },
131 { 0x74, 0x3e00 },
132 { 0x75, 0x2409 },
133 { 0x76, 0x000a },
134 { 0x77, 0x0c00 },
135 { 0x78, 0x0000 },
136 { 0x80, 0x0000 },
137 { 0x81, 0x0000 },
138 { 0x82, 0x0000 },
139 { 0x83, 0x0000 },
140 { 0x84, 0x0000 },
141 { 0x85, 0x0000 },
142 { 0x8a, 0x0000 },
143 { 0x8e, 0x0004 },
144 { 0x8f, 0x1100 },
145 { 0x90, 0x0646 },
146 { 0x91, 0x0c06 },
147 { 0x93, 0x0000 },
148 { 0x94, 0x0200 },
149 { 0x95, 0x0000 },
150 { 0x9a, 0x2184 },
151 { 0x9b, 0x010a },
152 { 0x9c, 0x0aea },
153 { 0x9d, 0x000c },
154 { 0x9e, 0x0400 },
155 { 0xa0, 0xa0a8 },
156 { 0xa1, 0x0059 },
157 { 0xa2, 0x0001 },
158 { 0xae, 0x6000 },
159 { 0xaf, 0x0000 },
160 { 0xb0, 0x6000 },
161 { 0xb1, 0x0000 },
162 { 0xb2, 0x0000 },
163 { 0xb3, 0x001f },
164 { 0xb4, 0x020c },
165 { 0xb5, 0x1f00 },
166 { 0xb6, 0x0000 },
167 { 0xbb, 0x0000 },
168 { 0xbc, 0x0000 },
169 { 0xbd, 0x0000 },
170 { 0xbe, 0x0000 },
171 { 0xbf, 0x3100 },
172 { 0xc0, 0x0000 },
173 { 0xc1, 0x0000 },
174 { 0xc2, 0x0000 },
175 { 0xc3, 0x2000 },
176 { 0xcd, 0x0000 },
177 { 0xce, 0x0000 },
178 { 0xcf, 0x1813 },
179 { 0xd0, 0x0690 },
180 { 0xd1, 0x1c17 },
181 { 0xd3, 0xb320 },
182 { 0xd4, 0x0000 },
183 { 0xd6, 0x0400 },
184 { 0xd9, 0x0809 },
185 { 0xda, 0x0000 },
186 { 0xdb, 0x0003 },
187 { 0xdc, 0x0049 },
188 { 0xdd, 0x001b },
189 { 0xe6, 0x8000 },
190 { 0xe7, 0x0200 },
191 { 0xec, 0xb300 },
192 { 0xed, 0x0000 },
193 { 0xf0, 0x001f },
194 { 0xf1, 0x020c },
195 { 0xf2, 0x1f00 },
196 { 0xf3, 0x0000 },
197 { 0xf4, 0x4000 },
198 { 0xf8, 0x0000 },
199 { 0xf9, 0x0000 },
200 { 0xfa, 0x2060 },
201 { 0xfb, 0x4040 },
202 { 0xfc, 0x0000 },
203 { 0xfd, 0x0002 },
204 { 0xfe, 0x10ec },
205 { 0xff, 0x6308 },
206};
207
208static int rt5645_reset(struct snd_soc_codec *codec)
209{
210 return snd_soc_write(codec, RT5645_RESET, 0);
211}
212
213static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
214{
215 int i;
216
217 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
218 if (reg >= rt5645_ranges[i].range_min &&
219 reg <= rt5645_ranges[i].range_max) {
220 return true;
221 }
222 }
223
224 switch (reg) {
225 case RT5645_RESET:
226 case RT5645_PRIV_DATA:
227 case RT5645_IN1_CTRL1:
228 case RT5645_IN1_CTRL2:
229 case RT5645_IN1_CTRL3:
230 case RT5645_A_JD_CTRL1:
231 case RT5645_ADC_EQ_CTRL1:
232 case RT5645_EQ_CTRL1:
233 case RT5645_ALC_CTRL_1:
234 case RT5645_IRQ_CTRL2:
235 case RT5645_IRQ_CTRL3:
236 case RT5645_INT_IRQ_ST:
237 case RT5645_IL_CMD:
238 case RT5645_VENDOR_ID:
239 case RT5645_VENDOR_ID1:
240 case RT5645_VENDOR_ID2:
241 return 1;
242 default:
243 return 0;
244 }
245}
246
247static bool rt5645_readable_register(struct device *dev, unsigned int reg)
248{
249 int i;
250
251 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
252 if (reg >= rt5645_ranges[i].range_min &&
253 reg <= rt5645_ranges[i].range_max) {
254 return true;
255 }
256 }
257
258 switch (reg) {
259 case RT5645_RESET:
260 case RT5645_SPK_VOL:
261 case RT5645_HP_VOL:
262 case RT5645_LOUT1:
263 case RT5645_IN1_CTRL1:
264 case RT5645_IN1_CTRL2:
265 case RT5645_IN1_CTRL3:
266 case RT5645_IN2_CTRL:
267 case RT5645_INL1_INR1_VOL:
268 case RT5645_SPK_FUNC_LIM:
269 case RT5645_ADJ_HPF_CTRL:
270 case RT5645_DAC1_DIG_VOL:
271 case RT5645_DAC2_DIG_VOL:
272 case RT5645_DAC_CTRL:
273 case RT5645_STO1_ADC_DIG_VOL:
274 case RT5645_MONO_ADC_DIG_VOL:
275 case RT5645_ADC_BST_VOL1:
276 case RT5645_ADC_BST_VOL2:
277 case RT5645_STO1_ADC_MIXER:
278 case RT5645_MONO_ADC_MIXER:
279 case RT5645_AD_DA_MIXER:
280 case RT5645_STO_DAC_MIXER:
281 case RT5645_MONO_DAC_MIXER:
282 case RT5645_DIG_MIXER:
283 case RT5645_DIG_INF1_DATA:
284 case RT5645_PDM_OUT_CTRL:
285 case RT5645_REC_L1_MIXER:
286 case RT5645_REC_L2_MIXER:
287 case RT5645_REC_R1_MIXER:
288 case RT5645_REC_R2_MIXER:
289 case RT5645_HPMIXL_CTRL:
290 case RT5645_HPOMIXL_CTRL:
291 case RT5645_HPMIXR_CTRL:
292 case RT5645_HPOMIXR_CTRL:
293 case RT5645_HPO_MIXER:
294 case RT5645_SPK_L_MIXER:
295 case RT5645_SPK_R_MIXER:
296 case RT5645_SPO_MIXER:
297 case RT5645_SPO_CLSD_RATIO:
298 case RT5645_OUT_L1_MIXER:
299 case RT5645_OUT_R1_MIXER:
300 case RT5645_OUT_L_GAIN1:
301 case RT5645_OUT_L_GAIN2:
302 case RT5645_OUT_R_GAIN1:
303 case RT5645_OUT_R_GAIN2:
304 case RT5645_LOUT_MIXER:
305 case RT5645_HAPTIC_CTRL1:
306 case RT5645_HAPTIC_CTRL2:
307 case RT5645_HAPTIC_CTRL3:
308 case RT5645_HAPTIC_CTRL4:
309 case RT5645_HAPTIC_CTRL5:
310 case RT5645_HAPTIC_CTRL6:
311 case RT5645_HAPTIC_CTRL7:
312 case RT5645_HAPTIC_CTRL8:
313 case RT5645_HAPTIC_CTRL9:
314 case RT5645_HAPTIC_CTRL10:
315 case RT5645_PWR_DIG1:
316 case RT5645_PWR_DIG2:
317 case RT5645_PWR_ANLG1:
318 case RT5645_PWR_ANLG2:
319 case RT5645_PWR_MIXER:
320 case RT5645_PWR_VOL:
321 case RT5645_PRIV_INDEX:
322 case RT5645_PRIV_DATA:
323 case RT5645_I2S1_SDP:
324 case RT5645_I2S2_SDP:
325 case RT5645_ADDA_CLK1:
326 case RT5645_ADDA_CLK2:
327 case RT5645_DMIC_CTRL1:
328 case RT5645_DMIC_CTRL2:
329 case RT5645_TDM_CTRL_1:
330 case RT5645_TDM_CTRL_2:
331 case RT5645_GLB_CLK:
332 case RT5645_PLL_CTRL1:
333 case RT5645_PLL_CTRL2:
334 case RT5645_ASRC_1:
335 case RT5645_ASRC_2:
336 case RT5645_ASRC_3:
337 case RT5645_ASRC_4:
338 case RT5645_DEPOP_M1:
339 case RT5645_DEPOP_M2:
340 case RT5645_DEPOP_M3:
341 case RT5645_MICBIAS:
342 case RT5645_A_JD_CTRL1:
343 case RT5645_VAD_CTRL4:
344 case RT5645_CLSD_OUT_CTRL:
345 case RT5645_ADC_EQ_CTRL1:
346 case RT5645_ADC_EQ_CTRL2:
347 case RT5645_EQ_CTRL1:
348 case RT5645_EQ_CTRL2:
349 case RT5645_ALC_CTRL_1:
350 case RT5645_ALC_CTRL_2:
351 case RT5645_ALC_CTRL_3:
352 case RT5645_ALC_CTRL_4:
353 case RT5645_ALC_CTRL_5:
354 case RT5645_JD_CTRL:
355 case RT5645_IRQ_CTRL1:
356 case RT5645_IRQ_CTRL2:
357 case RT5645_IRQ_CTRL3:
358 case RT5645_INT_IRQ_ST:
359 case RT5645_GPIO_CTRL1:
360 case RT5645_GPIO_CTRL2:
361 case RT5645_GPIO_CTRL3:
362 case RT5645_BASS_BACK:
363 case RT5645_MP3_PLUS1:
364 case RT5645_MP3_PLUS2:
365 case RT5645_ADJ_HPF1:
366 case RT5645_ADJ_HPF2:
367 case RT5645_HP_CALIB_AMP_DET:
368 case RT5645_SV_ZCD1:
369 case RT5645_SV_ZCD2:
370 case RT5645_IL_CMD:
371 case RT5645_IL_CMD2:
372 case RT5645_IL_CMD3:
373 case RT5645_DRC1_HL_CTRL1:
374 case RT5645_DRC2_HL_CTRL1:
375 case RT5645_ADC_MONO_HP_CTRL1:
376 case RT5645_ADC_MONO_HP_CTRL2:
377 case RT5645_DRC2_CTRL1:
378 case RT5645_DRC2_CTRL2:
379 case RT5645_DRC2_CTRL3:
380 case RT5645_DRC2_CTRL4:
381 case RT5645_DRC2_CTRL5:
382 case RT5645_JD_CTRL3:
383 case RT5645_JD_CTRL4:
384 case RT5645_GEN_CTRL1:
385 case RT5645_GEN_CTRL2:
386 case RT5645_GEN_CTRL3:
387 case RT5645_VENDOR_ID:
388 case RT5645_VENDOR_ID1:
389 case RT5645_VENDOR_ID2:
390 return 1;
391 default:
392 return 0;
393 }
394}
395
396static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
397static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
398static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
399static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
400static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
401
402/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
403static unsigned int bst_tlv[] = {
404 TLV_DB_RANGE_HEAD(7),
405 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
406 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
407 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
408 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
409 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
410 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
411 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
412};
413
414static const char * const rt5645_tdm_data_swap_select[] = {
415 "L/R", "R/L", "L/L", "R/R"
416};
417
418static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
419 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
420
421static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
422 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
423
424static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
425 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
426
427static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
428 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
429
430static const char * const rt5645_tdm_adc_data_select[] = {
431 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
432};
433
434static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
435 RT5645_TDM_CTRL_1, 8,
436 rt5645_tdm_adc_data_select);
437
438static const struct snd_kcontrol_new rt5645_snd_controls[] = {
439 /* Speaker Output Volume */
440 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
441 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
442 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
443 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
444
445 /* Headphone Output Volume */
446 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
447 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
448 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
449 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
450
451 /* OUTPUT Control */
452 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
453 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
454 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
455 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
456 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
457 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
458
459 /* DAC Digital Volume */
460 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
461 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
462 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
463 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
464 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
465 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
466
467 /* IN1/IN2 Control */
468 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
469 RT5645_BST_SFT1, 8, 0, bst_tlv),
470 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
471 RT5645_BST_SFT2, 8, 0, bst_tlv),
472
473 /* INL/INR Volume Control */
474 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
475 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
476
477 /* ADC Digital Volume Control */
478 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
479 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
480 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
481 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
482 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
483 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
484 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
485 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
486
487 /* ADC Boost Volume Control */
488 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
489 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
490 adc_bst_tlv),
491 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
492 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
493 adc_bst_tlv),
494
495 /* I2S2 function select */
496 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
497 1, 1),
498
499 /* TDM */
500 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
501 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
502 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
503 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
504 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
505 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
506 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
507 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
508 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
509};
510
511/**
512 * set_dmic_clk - Set parameter of dmic.
513 *
514 * @w: DAPM widget.
515 * @kcontrol: The kcontrol of this widget.
516 * @event: Event id.
517 *
518 * Choose dmic clock between 1MHz and 3MHz.
519 * It is better for clock to approximate 3MHz.
520 */
521static int set_dmic_clk(struct snd_soc_dapm_widget *w,
522 struct snd_kcontrol *kcontrol, int event)
523{
524 struct snd_soc_codec *codec = w->codec;
525 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
526 int div[] = {2, 3, 4, 6, 8, 12};
527 int idx = -EINVAL, i;
528 int rate, red, bound, temp;
529
530 rate = rt5645->sysclk;
531 red = 3000000 * 12;
532 for (i = 0; i < ARRAY_SIZE(div); i++) {
533 bound = div[i] * 3000000;
534 if (rate > bound)
535 continue;
536 temp = bound - rate;
537 if (temp < red) {
538 red = temp;
539 idx = i;
540 }
541 }
542
543 if (idx < 0)
544 dev_err(codec->dev, "Failed to set DMIC clock\n");
545 else
546 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
547 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
548 return idx;
549}
550
551static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
552 struct snd_soc_dapm_widget *sink)
553{
554 unsigned int val;
555
556 val = snd_soc_read(source->codec, RT5645_GLB_CLK);
557 val &= RT5645_SCLK_SRC_MASK;
558 if (val == RT5645_SCLK_SRC_PLL1)
559 return 1;
560 else
561 return 0;
562}
563
564/* Digital Mixer */
565static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
566 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
567 RT5645_M_ADC_L1_SFT, 1, 1),
568 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
569 RT5645_M_ADC_L2_SFT, 1, 1),
570};
571
572static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
573 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
574 RT5645_M_ADC_R1_SFT, 1, 1),
575 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
576 RT5645_M_ADC_R2_SFT, 1, 1),
577};
578
579static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
580 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
581 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
582 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
583 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
584};
585
586static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
587 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
588 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
589 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
590 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
591};
592
593static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
594 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
595 RT5645_M_ADCMIX_L_SFT, 1, 1),
596 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
597 RT5645_M_DAC1_L_SFT, 1, 1),
598};
599
600static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
601 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
602 RT5645_M_ADCMIX_R_SFT, 1, 1),
603 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
604 RT5645_M_DAC1_R_SFT, 1, 1),
605};
606
607static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
608 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
609 RT5645_M_DAC_L1_SFT, 1, 1),
610 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
611 RT5645_M_DAC_L2_SFT, 1, 1),
612 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
613 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
614};
615
616static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
617 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
618 RT5645_M_DAC_R1_SFT, 1, 1),
619 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
620 RT5645_M_DAC_R2_SFT, 1, 1),
621 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
622 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
623};
624
625static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
626 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
627 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
628 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
629 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
630 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
631 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
632};
633
634static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
635 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
636 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
637 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
638 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
639 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
640 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
641};
642
643static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
644 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
645 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
646 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
647 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
648 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
649 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
650};
651
652static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
653 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
654 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
655 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
656 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
657 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
658 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
659};
660
661/* Analog Input Mixer */
662static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
663 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
664 RT5645_M_HP_L_RM_L_SFT, 1, 1),
665 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
666 RT5645_M_IN_L_RM_L_SFT, 1, 1),
667 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
668 RT5645_M_BST2_RM_L_SFT, 1, 1),
669 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
670 RT5645_M_BST1_RM_L_SFT, 1, 1),
671 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
672 RT5645_M_OM_L_RM_L_SFT, 1, 1),
673};
674
675static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
676 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
677 RT5645_M_HP_R_RM_R_SFT, 1, 1),
678 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
679 RT5645_M_IN_R_RM_R_SFT, 1, 1),
680 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
681 RT5645_M_BST2_RM_R_SFT, 1, 1),
682 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
683 RT5645_M_BST1_RM_R_SFT, 1, 1),
684 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
685 RT5645_M_OM_R_RM_R_SFT, 1, 1),
686};
687
688static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
689 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
690 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
691 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
692 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
693 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
694 RT5645_M_IN_L_SM_L_SFT, 1, 1),
695 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
696 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
697};
698
699static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
700 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
701 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
702 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
703 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
704 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
705 RT5645_M_IN_R_SM_R_SFT, 1, 1),
706 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
707 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
708};
709
710static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
711 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
712 RT5645_M_BST1_OM_L_SFT, 1, 1),
713 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
714 RT5645_M_IN_L_OM_L_SFT, 1, 1),
715 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
716 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
717 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
718 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
719};
720
721static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
722 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
723 RT5645_M_BST2_OM_R_SFT, 1, 1),
724 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
725 RT5645_M_IN_R_OM_R_SFT, 1, 1),
726 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
727 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
728 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
729 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
730};
731
732static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
733 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
734 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
735 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
736 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
737 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
738 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
739 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
740 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
741};
742
743static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
744 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
745 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
746 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
747 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
748};
749
750static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
751 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
752 RT5645_M_DAC1_HM_SFT, 1, 1),
753 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
754 RT5645_M_HPVOL_HM_SFT, 1, 1),
755};
756
757static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
758 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
759 RT5645_M_DAC1_HV_SFT, 1, 1),
760 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
761 RT5645_M_DAC2_HV_SFT, 1, 1),
762 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
763 RT5645_M_IN_HV_SFT, 1, 1),
764 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
765 RT5645_M_BST1_HV_SFT, 1, 1),
766};
767
768static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
769 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
770 RT5645_M_DAC1_HV_SFT, 1, 1),
771 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
772 RT5645_M_DAC2_HV_SFT, 1, 1),
773 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
774 RT5645_M_IN_HV_SFT, 1, 1),
775 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
776 RT5645_M_BST2_HV_SFT, 1, 1),
777};
778
779static const struct snd_kcontrol_new rt5645_lout_mix[] = {
780 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
781 RT5645_M_DAC_L1_LM_SFT, 1, 1),
782 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
783 RT5645_M_DAC_R1_LM_SFT, 1, 1),
784 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
785 RT5645_M_OV_L_LM_SFT, 1, 1),
786 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
787 RT5645_M_OV_R_LM_SFT, 1, 1),
788};
789
790/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
791static const char * const rt5645_dac1_src[] = {
792 "IF1 DAC", "IF2 DAC", "IF3 DAC"
793};
794
795static SOC_ENUM_SINGLE_DECL(
796 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
797 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
798
799static const struct snd_kcontrol_new rt5645_dac1l_mux =
800 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
801
802static SOC_ENUM_SINGLE_DECL(
803 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
804 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
805
806static const struct snd_kcontrol_new rt5645_dac1r_mux =
807 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
808
809/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
810static const char * const rt5645_dac12_src[] = {
811 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
812};
813
814static SOC_ENUM_SINGLE_DECL(
815 rt5645_dac2l_enum, RT5645_DAC_CTRL,
816 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
817
818static const struct snd_kcontrol_new rt5645_dac_l2_mux =
819 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
820
821static const char * const rt5645_dacr2_src[] = {
822 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
823};
824
825static SOC_ENUM_SINGLE_DECL(
826 rt5645_dac2r_enum, RT5645_DAC_CTRL,
827 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
828
829static const struct snd_kcontrol_new rt5645_dac_r2_mux =
830 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
831
832
833/* INL/R source */
834static const char * const rt5645_inl_src[] = {
835 "IN2P", "MonoP"
836};
837
838static SOC_ENUM_SINGLE_DECL(
839 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
840 RT5645_INL_SEL_SFT, rt5645_inl_src);
841
842static const struct snd_kcontrol_new rt5645_inl_mux =
843 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
844
845static const char * const rt5645_inr_src[] = {
846 "IN2N", "MonoN"
847};
848
849static SOC_ENUM_SINGLE_DECL(
850 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
851 RT5645_INR_SEL_SFT, rt5645_inr_src);
852
853static const struct snd_kcontrol_new rt5645_inr_mux =
854 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
855
856/* Stereo1 ADC source */
857/* MX-27 [12] */
858static const char * const rt5645_stereo_adc1_src[] = {
859 "DAC MIX", "ADC"
860};
861
862static SOC_ENUM_SINGLE_DECL(
863 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
864 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
865
866static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
867 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
868
869/* MX-27 [11] */
870static const char * const rt5645_stereo_adc2_src[] = {
871 "DAC MIX", "DMIC"
872};
873
874static SOC_ENUM_SINGLE_DECL(
875 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
876 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
877
878static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
879 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
880
881/* MX-27 [8] */
882static const char * const rt5645_stereo_dmic_src[] = {
883 "DMIC1", "DMIC2"
884};
885
886static SOC_ENUM_SINGLE_DECL(
887 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
888 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
889
890static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
891 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
892
893/* Mono ADC source */
894/* MX-28 [12] */
895static const char * const rt5645_mono_adc_l1_src[] = {
896 "Mono DAC MIXL", "ADC"
897};
898
899static SOC_ENUM_SINGLE_DECL(
900 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
901 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
902
903static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
904 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
905/* MX-28 [11] */
906static const char * const rt5645_mono_adc_l2_src[] = {
907 "Mono DAC MIXL", "DMIC"
908};
909
910static SOC_ENUM_SINGLE_DECL(
911 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
912 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
913
914static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
915 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
916
917/* MX-28 [8] */
918static const char * const rt5645_mono_dmic_src[] = {
919 "DMIC1", "DMIC2"
920};
921
922static SOC_ENUM_SINGLE_DECL(
923 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
924 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
925
926static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
927 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
928/* MX-28 [1:0] */
929static SOC_ENUM_SINGLE_DECL(
930 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
931 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
932
933static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
934 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
935/* MX-28 [4] */
936static const char * const rt5645_mono_adc_r1_src[] = {
937 "Mono DAC MIXR", "ADC"
938};
939
940static SOC_ENUM_SINGLE_DECL(
941 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
942 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
943
944static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
945 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
946/* MX-28 [3] */
947static const char * const rt5645_mono_adc_r2_src[] = {
948 "Mono DAC MIXR", "DMIC"
949};
950
951static SOC_ENUM_SINGLE_DECL(
952 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
953 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
954
955static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
956 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
957
958/* MX-77 [9:8] */
959static const char * const rt5645_if1_adc_in_src[] = {
960 "IF_ADC1", "IF_ADC2", "VAD_ADC"
961};
962
963static SOC_ENUM_SINGLE_DECL(
964 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
965 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
966
967static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
968 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
969
970/* MX-2F [13:12] */
971static const char * const rt5645_if2_adc_in_src[] = {
972 "IF_ADC1", "IF_ADC2", "VAD_ADC"
973};
974
975static SOC_ENUM_SINGLE_DECL(
976 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
977 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
978
979static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
980 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
981
982/* MX-2F [1:0] */
983static const char * const rt5645_if3_adc_in_src[] = {
984 "IF_ADC1", "IF_ADC2", "VAD_ADC"
985};
986
987static SOC_ENUM_SINGLE_DECL(
988 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
989 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
990
991static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
992 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
993
994/* MX-31 [15] [13] [11] [9] */
995static const char * const rt5645_pdm_src[] = {
996 "Mono DAC", "Stereo DAC"
997};
998
999static SOC_ENUM_SINGLE_DECL(
1000 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1001 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1002
1003static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1004 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1005
1006static SOC_ENUM_SINGLE_DECL(
1007 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1008 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1009
1010static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1011 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1012
1013/* MX-9D [9:8] */
1014static const char * const rt5645_vad_adc_src[] = {
1015 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1016};
1017
1018static SOC_ENUM_SINGLE_DECL(
1019 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1020 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1021
1022static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1023 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1024
1025static const struct snd_kcontrol_new spk_l_vol_control =
1026 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1027 RT5645_L_MUTE_SFT, 1, 1);
1028
1029static const struct snd_kcontrol_new spk_r_vol_control =
1030 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1031 RT5645_R_MUTE_SFT, 1, 1);
1032
1033static const struct snd_kcontrol_new hp_l_vol_control =
1034 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1035 RT5645_L_MUTE_SFT, 1, 1);
1036
1037static const struct snd_kcontrol_new hp_r_vol_control =
1038 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1039 RT5645_R_MUTE_SFT, 1, 1);
1040
1041static const struct snd_kcontrol_new pdm1_l_vol_control =
1042 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1043 RT5645_M_PDM1_L, 1, 1);
1044
1045static const struct snd_kcontrol_new pdm1_r_vol_control =
1046 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1047 RT5645_M_PDM1_R, 1, 1);
1048
1049static void hp_amp_power(struct snd_soc_codec *codec, int on)
1050{
1051 static int hp_amp_power_count;
1052 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1053
1054 if (on) {
1055 if (hp_amp_power_count <= 0) {
1056 /* depop parameters */
1057 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1058 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1059 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1060 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1061 RT5645_HP_DCC_INT1, 0x9f01);
1062 mdelay(150);
1063 /* headphone amp power on */
1064 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1065 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1066 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1067 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1068 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1069 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1070 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1071 RT5645_PWR_HA,
1072 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1073 RT5645_PWR_HA);
1074 mdelay(5);
1075 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1076 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1077 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1078
1079 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1080 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1081 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1082 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1083 0x14, 0x1aaa);
1084 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1085 0x24, 0x0430);
1086 }
1087 hp_amp_power_count++;
1088 } else {
1089 hp_amp_power_count--;
1090 if (hp_amp_power_count <= 0) {
1091 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1092 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1093 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1094 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1095 /* headphone amp power down */
1096 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1097 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1098 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1099 RT5645_PWR_HA, 0);
1100 }
1101 }
1102}
1103
1104static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1105 struct snd_kcontrol *kcontrol, int event)
1106{
1107 struct snd_soc_codec *codec = w->codec;
1108 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1109
1110 switch (event) {
1111 case SND_SOC_DAPM_POST_PMU:
1112 hp_amp_power(codec, 1);
1113 /* headphone unmute sequence */
1114 snd_soc_update_bits(codec, RT5645_DEPOP_M3, RT5645_CP_FQ1_MASK |
1115 RT5645_CP_FQ2_MASK | RT5645_CP_FQ3_MASK,
1116 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1117 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1118 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1119 regmap_write(rt5645->regmap,
1120 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1121 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1122 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1123 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1124 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1125 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1126 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1127 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1128 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1129 msleep(40);
1130 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1131 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1132 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1133 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1134 break;
1135
1136 case SND_SOC_DAPM_PRE_PMD:
1137 /* headphone mute sequence */
1138 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1139 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1140 RT5645_CP_FQ3_MASK,
1141 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1142 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1143 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1144 regmap_write(rt5645->regmap,
1145 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1146 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1147 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1148 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1149 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1150 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1151 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1152 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1153 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1154 msleep(30);
1155 hp_amp_power(codec, 0);
1156 break;
1157
1158 default:
1159 return 0;
1160 }
1161
1162 return 0;
1163}
1164
1165static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1166 struct snd_kcontrol *kcontrol, int event)
1167{
1168 struct snd_soc_codec *codec = w->codec;
1169 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1170
1171 switch (event) {
1172 case SND_SOC_DAPM_POST_PMU:
1173 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1174 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1175 RT5645_PWR_CLS_D_L,
1176 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1177 RT5645_PWR_CLS_D_L);
1178 break;
1179
1180 case SND_SOC_DAPM_PRE_PMD:
1181 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1182 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1183 RT5645_PWR_CLS_D_L, 0);
1184 break;
1185
1186 default:
1187 return 0;
1188 }
1189
1190 return 0;
1191}
1192
1193static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1194 struct snd_kcontrol *kcontrol, int event)
1195{
1196 struct snd_soc_codec *codec = w->codec;
1197
1198 switch (event) {
1199 case SND_SOC_DAPM_POST_PMU:
1200 hp_amp_power(codec, 1);
1201 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1202 RT5645_PWR_LM, RT5645_PWR_LM);
1203 snd_soc_update_bits(codec, RT5645_LOUT1,
1204 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1205 break;
1206
1207 case SND_SOC_DAPM_PRE_PMD:
1208 snd_soc_update_bits(codec, RT5645_LOUT1,
1209 RT5645_L_MUTE | RT5645_R_MUTE,
1210 RT5645_L_MUTE | RT5645_R_MUTE);
1211 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1212 RT5645_PWR_LM, 0);
1213 hp_amp_power(codec, 0);
1214 break;
1215
1216 default:
1217 return 0;
1218 }
1219
1220 return 0;
1221}
1222
1223static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1224 struct snd_kcontrol *kcontrol, int event)
1225{
1226 struct snd_soc_codec *codec = w->codec;
1227
1228 switch (event) {
1229 case SND_SOC_DAPM_POST_PMU:
1230 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1231 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1232 break;
1233
1234 case SND_SOC_DAPM_PRE_PMD:
1235 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1236 RT5645_PWR_BST2_P, 0);
1237 break;
1238
1239 default:
1240 return 0;
1241 }
1242
1243 return 0;
1244}
1245
1246static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1247 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1248 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1249 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1250 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1251
1252 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1253 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1254 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1255 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1256
1257 /* Input Side */
1258 /* micbias */
1259 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1260 RT5645_PWR_MB1_BIT, 0),
1261 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1262 RT5645_PWR_MB2_BIT, 0),
1263 /* Input Lines */
1264 SND_SOC_DAPM_INPUT("DMIC L1"),
1265 SND_SOC_DAPM_INPUT("DMIC R1"),
1266 SND_SOC_DAPM_INPUT("DMIC L2"),
1267 SND_SOC_DAPM_INPUT("DMIC R2"),
1268
1269 SND_SOC_DAPM_INPUT("IN1P"),
1270 SND_SOC_DAPM_INPUT("IN1N"),
1271 SND_SOC_DAPM_INPUT("IN2P"),
1272 SND_SOC_DAPM_INPUT("IN2N"),
1273
1274 SND_SOC_DAPM_INPUT("Haptic Generator"),
1275
1276 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1277 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1278 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1279 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1280 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1281 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1282 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1283 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1284 /* Boost */
1285 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1286 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1287 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1288 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1289 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1290 /* Input Volume */
1291 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1292 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1293 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1294 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1295 /* REC Mixer */
1296 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1297 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1298 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1299 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1300 /* ADCs */
1301 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1302 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1303
1304 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1305 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1306 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1307 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1308
1309 /* ADC Mux */
1310 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1311 &rt5645_sto1_dmic_mux),
1312 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1313 &rt5645_sto_adc2_mux),
1314 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1315 &rt5645_sto_adc2_mux),
1316 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1317 &rt5645_sto_adc1_mux),
1318 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1319 &rt5645_sto_adc1_mux),
1320 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1321 &rt5645_mono_dmic_l_mux),
1322 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1323 &rt5645_mono_dmic_r_mux),
1324 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1325 &rt5645_mono_adc_l2_mux),
1326 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1327 &rt5645_mono_adc_l1_mux),
1328 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1329 &rt5645_mono_adc_r1_mux),
1330 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1331 &rt5645_mono_adc_r2_mux),
1332 /* ADC Mixer */
1333
1334 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1335 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1336 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1337 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1338 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1339 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1340 NULL, 0),
1341 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1342 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1343 NULL, 0),
1344 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1345 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1346 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1347 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1348 NULL, 0),
1349 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1350 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1351 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1352 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1353 NULL, 0),
1354
1355 /* ADC PGA */
1356 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1357 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1358 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1359 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1360 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1361 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1362 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1363 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1364 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1365 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1366
1367 /* IF1 2 Mux */
1368 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1369 0, 0, &rt5645_if1_adc_in_mux),
1370 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1371 0, 0, &rt5645_if2_adc_in_mux),
1372
1373 /* Digital Interface */
1374 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1375 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1376 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1377 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1378 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1379 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1380 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1381 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1382 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1383 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1384 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1385 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1386 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1387 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1388 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1389 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1390 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1391
1392 /* Digital Interface Select */
1393 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1394 0, 0, &rt5645_vad_adc_mux),
1395
1396 /* Audio Interface */
1397 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1398 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1399 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1400 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1401
1402 /* Output Side */
1403 /* DAC mixer before sound effect */
1404 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1405 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1406 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1407 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1408
1409 /* DAC2 channel Mux */
1410 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1411 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1412 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1413 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1414 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1415 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1416
1417 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1418 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1419
1420 /* DAC Mixer */
1421 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1422 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1423 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1424 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1425 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1426 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1427 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1428 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1429 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1430 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1431 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1432 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1433 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1434 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1435 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1436 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1437 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1438 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1439
1440 /* DACs */
1441 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1442 0),
1443 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1444 0),
1445 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1446 0),
1447 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1448 0),
1449 /* OUT Mixer */
1450 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1451 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1452 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1453 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1454 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1455 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1456 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1457 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1458 /* Ouput Volume */
1459 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1460 &spk_l_vol_control),
1461 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1462 &spk_r_vol_control),
1463 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1464 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1465 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1466 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1467 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1468 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1469 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1470 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1471 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1472 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1473 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1474 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1475 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1476
1477 /* HPO/LOUT/Mono Mixer */
1478 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1479 ARRAY_SIZE(rt5645_spo_l_mix)),
1480 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1481 ARRAY_SIZE(rt5645_spo_r_mix)),
1482 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1483 ARRAY_SIZE(rt5645_hpo_mix)),
1484 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1485 ARRAY_SIZE(rt5645_lout_mix)),
1486
1487 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1488 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1489 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1490 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1491 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1492 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1493
1494 /* PDM */
1495 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1496 0, NULL, 0),
1497 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1498 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1499
1500 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1501 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1502
1503 /* Output Lines */
1504 SND_SOC_DAPM_OUTPUT("HPOL"),
1505 SND_SOC_DAPM_OUTPUT("HPOR"),
1506 SND_SOC_DAPM_OUTPUT("LOUTL"),
1507 SND_SOC_DAPM_OUTPUT("LOUTR"),
1508 SND_SOC_DAPM_OUTPUT("PDM1L"),
1509 SND_SOC_DAPM_OUTPUT("PDM1R"),
1510 SND_SOC_DAPM_OUTPUT("SPOL"),
1511 SND_SOC_DAPM_OUTPUT("SPOR"),
1512};
1513
1514static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1515 { "IN1P", NULL, "LDO2" },
1516 { "IN2P", NULL, "LDO2" },
1517
1518 { "DMIC1", NULL, "DMIC L1" },
1519 { "DMIC1", NULL, "DMIC R1" },
1520 { "DMIC2", NULL, "DMIC L2" },
1521 { "DMIC2", NULL, "DMIC R2" },
1522
1523 { "BST1", NULL, "IN1P" },
1524 { "BST1", NULL, "IN1N" },
1525 { "BST1", NULL, "JD Power" },
1526 { "BST1", NULL, "Mic Det Power" },
1527 { "BST2", NULL, "IN2P" },
1528 { "BST2", NULL, "IN2N" },
1529
1530 { "INL VOL", NULL, "IN2P" },
1531 { "INR VOL", NULL, "IN2N" },
1532
1533 { "RECMIXL", "HPOL Switch", "HPOL" },
1534 { "RECMIXL", "INL Switch", "INL VOL" },
1535 { "RECMIXL", "BST2 Switch", "BST2" },
1536 { "RECMIXL", "BST1 Switch", "BST1" },
1537 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1538
1539 { "RECMIXR", "HPOR Switch", "HPOR" },
1540 { "RECMIXR", "INR Switch", "INR VOL" },
1541 { "RECMIXR", "BST2 Switch", "BST2" },
1542 { "RECMIXR", "BST1 Switch", "BST1" },
1543 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1544
1545 { "ADC L", NULL, "RECMIXL" },
1546 { "ADC L", NULL, "ADC L power" },
1547 { "ADC R", NULL, "RECMIXR" },
1548 { "ADC R", NULL, "ADC R power" },
1549
1550 {"DMIC L1", NULL, "DMIC CLK"},
1551 {"DMIC L1", NULL, "DMIC1 Power"},
1552 {"DMIC R1", NULL, "DMIC CLK"},
1553 {"DMIC R1", NULL, "DMIC1 Power"},
1554 {"DMIC L2", NULL, "DMIC CLK"},
1555 {"DMIC L2", NULL, "DMIC2 Power"},
1556 {"DMIC R2", NULL, "DMIC CLK"},
1557 {"DMIC R2", NULL, "DMIC2 Power"},
1558
1559 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1560 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1561
1562 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1563 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1564
1565 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1566 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1567
1568 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1569 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1570 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1571 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1572
1573 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1574 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1575 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1576 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1577
1578 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1579 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1580 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1581 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1582
1583 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1584 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1585 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1586 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1587
1588 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1589 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1590 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1591 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1592
1593 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1594 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1595 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1596
1597 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1598 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1599 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1600
1601 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1602 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1603 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1604 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1605
1606 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1607 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1608 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1609 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1610
1611 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1612 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1613 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1614
1615 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1616 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1617 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1618 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1619 { "VAD_ADC", NULL, "VAD ADC Mux" },
1620
1621 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1622 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1623 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1624
1625 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1626 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1627 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1628
1629 { "IF1 ADC", NULL, "I2S1" },
1630 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1631 { "IF2 ADC", NULL, "I2S2" },
1632 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1633
1634 { "AIF1TX", NULL, "IF1 ADC" },
1635 { "AIF1TX", NULL, "IF2 ADC" },
1636 { "AIF2TX", NULL, "IF2 ADC" },
1637
1638 { "IF1 DAC1", NULL, "AIF1RX" },
1639 { "IF1 DAC2", NULL, "AIF1RX" },
1640 { "IF2 DAC", NULL, "AIF2RX" },
1641
1642 { "IF1 DAC1", NULL, "I2S1" },
1643 { "IF1 DAC2", NULL, "I2S1" },
1644 { "IF2 DAC", NULL, "I2S2" },
1645
1646 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1647 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1648 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1649 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1650 { "IF2 DAC L", NULL, "IF2 DAC" },
1651 { "IF2 DAC R", NULL, "IF2 DAC" },
1652
1653 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1654 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1655
1656 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1657 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1658
1659 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1660 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1661 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1662 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1663 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1664 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1665
1666 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1667 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1668 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1669 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1670 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1671 { "DAC L2 Volume", NULL, "dac mono left filter" },
1672
1673 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1674 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1675 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1676 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1677 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1678 { "DAC R2 Volume", NULL, "dac mono right filter" },
1679
1680 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1681 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1682 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1683 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1684 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1685 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1686 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1687 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1688
1689 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1690 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1691 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1692 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1693 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1694 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1695 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1696 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1697
1698 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1699 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1700 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1701 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1702 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1703 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1704
1705 { "DAC L1", NULL, "Stereo DAC MIXL" },
1706 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1707 { "DAC R1", NULL, "Stereo DAC MIXR" },
1708 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1709 { "DAC L2", NULL, "Mono DAC MIXL" },
1710 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1711 { "DAC R2", NULL, "Mono DAC MIXR" },
1712 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1713
1714 { "SPK MIXL", "BST1 Switch", "BST1" },
1715 { "SPK MIXL", "INL Switch", "INL VOL" },
1716 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1717 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1718 { "SPK MIXR", "BST2 Switch", "BST2" },
1719 { "SPK MIXR", "INR Switch", "INR VOL" },
1720 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1721 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1722
1723 { "OUT MIXL", "BST1 Switch", "BST1" },
1724 { "OUT MIXL", "INL Switch", "INL VOL" },
1725 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1726 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1727
1728 { "OUT MIXR", "BST2 Switch", "BST2" },
1729 { "OUT MIXR", "INR Switch", "INR VOL" },
1730 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1731 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1732
1733 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1734 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1735 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1736 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1737 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1738 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1739 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1740 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1741 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1742 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1743
1744 { "DAC 2", NULL, "DAC L2" },
1745 { "DAC 2", NULL, "DAC R2" },
1746 { "DAC 1", NULL, "DAC L1" },
1747 { "DAC 1", NULL, "DAC R1" },
1748 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1749 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1750 { "HPOVOL", NULL, "HPOVOL L" },
1751 { "HPOVOL", NULL, "HPOVOL R" },
1752 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1753 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1754
1755 { "SPKVOL L", "Switch", "SPK MIXL" },
1756 { "SPKVOL R", "Switch", "SPK MIXR" },
1757
1758 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1759 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1760 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1761 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1762 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1763 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1764
1765 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1766 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1767 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1768 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1769
1770 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1771 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1772 { "PDM1 L Mux", NULL, "PDM1 Power" },
1773 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1774 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1775 { "PDM1 R Mux", NULL, "PDM1 Power" },
1776
1777 { "HP amp", NULL, "HPO MIX" },
1778 { "HP amp", NULL, "JD Power" },
1779 { "HP amp", NULL, "Mic Det Power" },
1780 { "HP amp", NULL, "LDO2" },
1781 { "HPOL", NULL, "HP amp" },
1782 { "HPOR", NULL, "HP amp" },
1783
1784 { "LOUT amp", NULL, "LOUT MIX" },
1785 { "LOUTL", NULL, "LOUT amp" },
1786 { "LOUTR", NULL, "LOUT amp" },
1787
1788 { "PDM1 L", "Switch", "PDM1 L Mux" },
1789 { "PDM1 R", "Switch", "PDM1 R Mux" },
1790
1791 { "PDM1L", NULL, "PDM1 L" },
1792 { "PDM1R", NULL, "PDM1 R" },
1793
1794 { "SPK amp", NULL, "SPOL MIX" },
1795 { "SPK amp", NULL, "SPOR MIX" },
1796 { "SPOL", NULL, "SPK amp" },
1797 { "SPOR", NULL, "SPK amp" },
1798};
1799
1800static int get_clk_info(int sclk, int rate)
1801{
1802 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1803
1804 if (sclk <= 0 || rate <= 0)
1805 return -EINVAL;
1806
1807 rate = rate << 8;
1808 for (i = 0; i < ARRAY_SIZE(pd); i++)
1809 if (sclk == rate * pd[i])
1810 return i;
1811
1812 return -EINVAL;
1813}
1814
1815static int rt5645_hw_params(struct snd_pcm_substream *substream,
1816 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1817{
1818 struct snd_soc_codec *codec = dai->codec;
1819 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1820 unsigned int val_len = 0, val_clk, mask_clk;
1821 int pre_div, bclk_ms, frame_size;
1822
1823 rt5645->lrck[dai->id] = params_rate(params);
1824 pre_div = get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1825 if (pre_div < 0) {
1826 dev_err(codec->dev, "Unsupported clock setting\n");
1827 return -EINVAL;
1828 }
1829 frame_size = snd_soc_params_to_frame_size(params);
1830 if (frame_size < 0) {
1831 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1832 return -EINVAL;
1833 }
1834 bclk_ms = frame_size > 32;
1835 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
1836
1837 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1838 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
1839 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1840 bclk_ms, pre_div, dai->id);
1841
1842 switch (params_width(params)) {
1843 case 16:
1844 break;
1845 case 20:
1846 val_len |= RT5645_I2S_DL_20;
1847 break;
1848 case 24:
1849 val_len |= RT5645_I2S_DL_24;
1850 break;
1851 case 8:
1852 val_len |= RT5645_I2S_DL_8;
1853 break;
1854 default:
1855 return -EINVAL;
1856 }
1857
1858 switch (dai->id) {
1859 case RT5645_AIF1:
1860 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
1861 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
1862 pre_div << RT5645_I2S_PD1_SFT;
1863 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1864 RT5645_I2S_DL_MASK, val_len);
1865 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1866 break;
1867 case RT5645_AIF2:
1868 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
1869 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
1870 pre_div << RT5645_I2S_PD2_SFT;
1871 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1872 RT5645_I2S_DL_MASK, val_len);
1873 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1874 break;
1875 default:
1876 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1877 return -EINVAL;
1878 }
1879
1880 return 0;
1881}
1882
1883static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1884{
1885 struct snd_soc_codec *codec = dai->codec;
1886 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1887 unsigned int reg_val = 0;
1888
1889 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1890 case SND_SOC_DAIFMT_CBM_CFM:
1891 rt5645->master[dai->id] = 1;
1892 break;
1893 case SND_SOC_DAIFMT_CBS_CFS:
1894 reg_val |= RT5645_I2S_MS_S;
1895 rt5645->master[dai->id] = 0;
1896 break;
1897 default:
1898 return -EINVAL;
1899 }
1900
1901 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1902 case SND_SOC_DAIFMT_NB_NF:
1903 break;
1904 case SND_SOC_DAIFMT_IB_NF:
1905 reg_val |= RT5645_I2S_BP_INV;
1906 break;
1907 default:
1908 return -EINVAL;
1909 }
1910
1911 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1912 case SND_SOC_DAIFMT_I2S:
1913 break;
1914 case SND_SOC_DAIFMT_LEFT_J:
1915 reg_val |= RT5645_I2S_DF_LEFT;
1916 break;
1917 case SND_SOC_DAIFMT_DSP_A:
1918 reg_val |= RT5645_I2S_DF_PCM_A;
1919 break;
1920 case SND_SOC_DAIFMT_DSP_B:
1921 reg_val |= RT5645_I2S_DF_PCM_B;
1922 break;
1923 default:
1924 return -EINVAL;
1925 }
1926 switch (dai->id) {
1927 case RT5645_AIF1:
1928 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1929 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1930 RT5645_I2S_DF_MASK, reg_val);
1931 break;
1932 case RT5645_AIF2:
1933 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1934 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1935 RT5645_I2S_DF_MASK, reg_val);
1936 break;
1937 default:
1938 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1939 return -EINVAL;
1940 }
1941 return 0;
1942}
1943
1944static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
1945 int clk_id, unsigned int freq, int dir)
1946{
1947 struct snd_soc_codec *codec = dai->codec;
1948 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1949 unsigned int reg_val = 0;
1950
1951 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
1952 return 0;
1953
1954 switch (clk_id) {
1955 case RT5645_SCLK_S_MCLK:
1956 reg_val |= RT5645_SCLK_SRC_MCLK;
1957 break;
1958 case RT5645_SCLK_S_PLL1:
1959 reg_val |= RT5645_SCLK_SRC_PLL1;
1960 break;
1961 case RT5645_SCLK_S_RCCLK:
1962 reg_val |= RT5645_SCLK_SRC_RCCLK;
1963 break;
1964 default:
1965 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1966 return -EINVAL;
1967 }
1968 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1969 RT5645_SCLK_SRC_MASK, reg_val);
1970 rt5645->sysclk = freq;
1971 rt5645->sysclk_src = clk_id;
1972
1973 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1974
1975 return 0;
1976}
1977
1978/**
1979 * rt5645_pll_calc - Calcualte PLL M/N/K code.
1980 * @freq_in: external clock provided to codec.
1981 * @freq_out: target clock which codec works on.
1982 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1983 *
1984 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1985 * which make calculation more efficiently.
1986 *
1987 * Returns 0 for success or negative error code.
1988 */
1989static int rt5645_pll_calc(const unsigned int freq_in,
1990 const unsigned int freq_out, struct rt5645_pll_code *pll_code)
1991{
1992 int max_n = RT5645_PLL_N_MAX, max_m = RT5645_PLL_M_MAX;
1993 int k, n = 0, m = 0, red, n_t, m_t, pll_out, in_t, out_t;
1994 int red_t = abs(freq_out - freq_in);
1995 bool bypass = false;
1996
1997 if (RT5645_PLL_INP_MAX < freq_in || RT5645_PLL_INP_MIN > freq_in)
1998 return -EINVAL;
1999
2000 k = 100000000 / freq_out - 2;
2001 if (k > RT5645_PLL_K_MAX)
2002 k = RT5645_PLL_K_MAX;
2003 for (n_t = 0; n_t <= max_n; n_t++) {
2004 in_t = freq_in / (k + 2);
2005 pll_out = freq_out / (n_t + 2);
2006 if (in_t < 0)
2007 continue;
2008 if (in_t == pll_out) {
2009 bypass = true;
2010 n = n_t;
2011 goto code_find;
2012 }
2013 red = abs(in_t - pll_out);
2014 if (red < red_t) {
2015 bypass = true;
2016 n = n_t;
2017 m = m_t;
2018 if (red == 0)
2019 goto code_find;
2020 red_t = red;
2021 }
2022 for (m_t = 0; m_t <= max_m; m_t++) {
2023 out_t = in_t / (m_t + 2);
2024 red = abs(out_t - pll_out);
2025 if (red < red_t) {
2026 bypass = false;
2027 n = n_t;
2028 m = m_t;
2029 if (red == 0)
2030 goto code_find;
2031 red_t = red;
2032 }
2033 }
2034 }
2035 pr_debug("Only get approximation about PLL\n");
2036
2037code_find:
2038
2039 pll_code->m_bp = bypass;
2040 pll_code->m_code = m;
2041 pll_code->n_code = n;
2042 pll_code->k_code = k;
2043 return 0;
2044}
2045
2046static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2047 unsigned int freq_in, unsigned int freq_out)
2048{
2049 struct snd_soc_codec *codec = dai->codec;
2050 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2051 struct rt5645_pll_code pll_code;
2052 int ret;
2053
2054 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2055 freq_out == rt5645->pll_out)
2056 return 0;
2057
2058 if (!freq_in || !freq_out) {
2059 dev_dbg(codec->dev, "PLL disabled\n");
2060
2061 rt5645->pll_in = 0;
2062 rt5645->pll_out = 0;
2063 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2064 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2065 return 0;
2066 }
2067
2068 switch (source) {
2069 case RT5645_PLL1_S_MCLK:
2070 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2071 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2072 break;
2073 case RT5645_PLL1_S_BCLK1:
2074 case RT5645_PLL1_S_BCLK2:
2075 switch (dai->id) {
2076 case RT5645_AIF1:
2077 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2078 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2079 break;
2080 case RT5645_AIF2:
2081 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2082 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2083 break;
2084 default:
2085 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2086 return -EINVAL;
2087 }
2088 break;
2089 default:
2090 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2091 return -EINVAL;
2092 }
2093
2094 ret = rt5645_pll_calc(freq_in, freq_out, &pll_code);
2095 if (ret < 0) {
2096 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2097 return ret;
2098 }
2099
2100 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2101 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2102 pll_code.n_code, pll_code.k_code);
2103
2104 snd_soc_write(codec, RT5645_PLL_CTRL1,
2105 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2106 snd_soc_write(codec, RT5645_PLL_CTRL2,
2107 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2108 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2109
2110 rt5645->pll_in = freq_in;
2111 rt5645->pll_out = freq_out;
2112 rt5645->pll_src = source;
2113
2114 return 0;
2115}
2116
2117static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2118 unsigned int rx_mask, int slots, int slot_width)
2119{
2120 struct snd_soc_codec *codec = dai->codec;
2121 unsigned int val = 0;
2122
2123 if (rx_mask || tx_mask)
2124 val |= (1 << 14);
2125
2126 switch (slots) {
2127 case 4:
2128 val |= (1 << 12);
2129 break;
2130 case 6:
2131 val |= (2 << 12);
2132 break;
2133 case 8:
2134 val |= (3 << 12);
2135 break;
2136 case 2:
2137 default:
2138 break;
2139 }
2140
2141 switch (slot_width) {
2142 case 20:
2143 val |= (1 << 10);
2144 break;
2145 case 24:
2146 val |= (2 << 10);
2147 break;
2148 case 32:
2149 val |= (3 << 10);
2150 break;
2151 case 16:
2152 default:
2153 break;
2154 }
2155
2156 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2157
2158 return 0;
2159}
2160
2161static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2162 enum snd_soc_bias_level level)
2163{
2164 switch (level) {
2165 case SND_SOC_BIAS_STANDBY:
2166 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2167 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2168 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2169 RT5645_PWR_BG | RT5645_PWR_VREF2,
2170 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2171 RT5645_PWR_BG | RT5645_PWR_VREF2);
2172 mdelay(10);
2173 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2174 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2175 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2176 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2177 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2178 }
2179 break;
2180
2181 case SND_SOC_BIAS_OFF:
2182 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2183 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
2184 snd_soc_write(codec, RT5645_PWR_DIG1, 0x0000);
2185 snd_soc_write(codec, RT5645_PWR_DIG2, 0x0000);
2186 snd_soc_write(codec, RT5645_PWR_VOL, 0x0000);
2187 snd_soc_write(codec, RT5645_PWR_MIXER, 0x0000);
2188 snd_soc_write(codec, RT5645_PWR_ANLG1, 0x0000);
2189 snd_soc_write(codec, RT5645_PWR_ANLG2, 0x0000);
2190 break;
2191
2192 default:
2193 break;
2194 }
2195 codec->dapm.bias_level = level;
2196
2197 return 0;
2198}
2199
2200static int rt5645_probe(struct snd_soc_codec *codec)
2201{
2202 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2203
2204 rt5645->codec = codec;
2205
2206 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2207
2208 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2209 snd_soc_write(codec, RT5645_PR_BASE + 0x1c, 0xfd20);
2210 snd_soc_write(codec, RT5645_PR_BASE + 0x20, 0x611f);
2211 snd_soc_write(codec, RT5645_PR_BASE + 0x21, 0x4040);
2212 snd_soc_write(codec, RT5645_PR_BASE + 0x23, 0x0004);
2213
2214 return 0;
2215}
2216
2217static int rt5645_remove(struct snd_soc_codec *codec)
2218{
2219 rt5645_reset(codec);
2220 return 0;
2221}
2222
2223#ifdef CONFIG_PM
2224static int rt5645_suspend(struct snd_soc_codec *codec)
2225{
2226 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2227
2228 regcache_cache_only(rt5645->regmap, true);
2229 regcache_mark_dirty(rt5645->regmap);
2230
2231 return 0;
2232}
2233
2234static int rt5645_resume(struct snd_soc_codec *codec)
2235{
2236 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2237
2238 regcache_cache_only(rt5645->regmap, false);
2239 snd_soc_cache_sync(codec);
2240
2241 return 0;
2242}
2243#else
2244#define rt5645_suspend NULL
2245#define rt5645_resume NULL
2246#endif
2247
2248#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2249#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2250 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2251
2252struct snd_soc_dai_ops rt5645_aif_dai_ops = {
2253 .hw_params = rt5645_hw_params,
2254 .set_fmt = rt5645_set_dai_fmt,
2255 .set_sysclk = rt5645_set_dai_sysclk,
2256 .set_tdm_slot = rt5645_set_tdm_slot,
2257 .set_pll = rt5645_set_dai_pll,
2258};
2259
2260struct snd_soc_dai_driver rt5645_dai[] = {
2261 {
2262 .name = "rt5645-aif1",
2263 .id = RT5645_AIF1,
2264 .playback = {
2265 .stream_name = "AIF1 Playback",
2266 .channels_min = 1,
2267 .channels_max = 2,
2268 .rates = RT5645_STEREO_RATES,
2269 .formats = RT5645_FORMATS,
2270 },
2271 .capture = {
2272 .stream_name = "AIF1 Capture",
2273 .channels_min = 1,
2274 .channels_max = 2,
2275 .rates = RT5645_STEREO_RATES,
2276 .formats = RT5645_FORMATS,
2277 },
2278 .ops = &rt5645_aif_dai_ops,
2279 },
2280 {
2281 .name = "rt5645-aif2",
2282 .id = RT5645_AIF2,
2283 .playback = {
2284 .stream_name = "AIF2 Playback",
2285 .channels_min = 1,
2286 .channels_max = 2,
2287 .rates = RT5645_STEREO_RATES,
2288 .formats = RT5645_FORMATS,
2289 },
2290 .capture = {
2291 .stream_name = "AIF2 Capture",
2292 .channels_min = 1,
2293 .channels_max = 2,
2294 .rates = RT5645_STEREO_RATES,
2295 .formats = RT5645_FORMATS,
2296 },
2297 .ops = &rt5645_aif_dai_ops,
2298 },
2299};
2300
2301static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2302 .probe = rt5645_probe,
2303 .remove = rt5645_remove,
2304 .suspend = rt5645_suspend,
2305 .resume = rt5645_resume,
2306 .set_bias_level = rt5645_set_bias_level,
2307 .idle_bias_off = true,
2308 .controls = rt5645_snd_controls,
2309 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2310 .dapm_widgets = rt5645_dapm_widgets,
2311 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2312 .dapm_routes = rt5645_dapm_routes,
2313 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2314};
2315
2316static const struct regmap_config rt5645_regmap = {
2317 .reg_bits = 8,
2318 .val_bits = 16,
2319
2320 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2321 RT5645_PR_SPACING),
2322 .volatile_reg = rt5645_volatile_register,
2323 .readable_reg = rt5645_readable_register,
2324
2325 .cache_type = REGCACHE_RBTREE,
2326 .reg_defaults = rt5645_reg,
2327 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2328 .ranges = rt5645_ranges,
2329 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2330};
2331
2332static const struct i2c_device_id rt5645_i2c_id[] = {
2333 { "rt5645", 0 },
2334 { }
2335};
2336MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2337
2338static int rt5645_i2c_probe(struct i2c_client *i2c,
2339 const struct i2c_device_id *id)
2340{
2341 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2342 struct rt5645_priv *rt5645;
2343 int ret;
2344 unsigned int val;
2345
2346 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2347 GFP_KERNEL);
2348 if (rt5645 == NULL)
2349 return -ENOMEM;
2350
2351 i2c_set_clientdata(i2c, rt5645);
2352
2353 if (pdata)
2354 rt5645->pdata = *pdata;
2355
2356 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2357 if (IS_ERR(rt5645->regmap)) {
2358 ret = PTR_ERR(rt5645->regmap);
2359 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2360 ret);
2361 return ret;
2362 }
2363
2364 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
2365 if (val != RT5645_DEVICE_ID) {
2366 dev_err(&i2c->dev,
2367 "Device with ID register %x is not rt5645\n", val);
2368 return -ENODEV;
2369 }
2370
2371 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2372
2373 ret = regmap_register_patch(rt5645->regmap, init_list,
2374 ARRAY_SIZE(init_list));
2375 if (ret != 0)
2376 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2377
2378 if (rt5645->pdata.in2_diff)
2379 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2380 RT5645_IN_DF2, RT5645_IN_DF2);
2381
2382 if (rt5645->pdata.dmic_en) {
2383 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2384 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2385
2386 switch (rt5645->pdata.dmic1_data_pin) {
2387 case RT5645_DMIC_DATA_IN2N:
2388 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2389 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2390 break;
2391
2392 case RT5645_DMIC_DATA_GPIO5:
2393 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2394 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2395 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2396 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2397 break;
2398
2399 case RT5645_DMIC_DATA_GPIO11:
2400 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2401 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2402 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2403 RT5645_GP11_PIN_MASK,
2404 RT5645_GP11_PIN_DMIC1_SDA);
2405 break;
2406
2407 default:
2408 break;
2409 }
2410
2411 switch (rt5645->pdata.dmic2_data_pin) {
2412 case RT5645_DMIC_DATA_IN2P:
2413 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2414 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2415 break;
2416
2417 case RT5645_DMIC_DATA_GPIO6:
2418 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2419 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2420 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2421 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2422 break;
2423
2424 case RT5645_DMIC_DATA_GPIO10:
2425 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2426 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2427 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2428 RT5645_GP10_PIN_MASK,
2429 RT5645_GP10_PIN_DMIC2_SDA);
2430 break;
2431
2432 case RT5645_DMIC_DATA_GPIO12:
2433 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2434 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2435 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2436 RT5645_GP12_PIN_MASK,
2437 RT5645_GP12_PIN_DMIC2_SDA);
2438 break;
2439
2440 default:
2441 break;
2442 }
2443
2444 }
2445
2446 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2447 rt5645_dai, ARRAY_SIZE(rt5645_dai));
2448 if (ret < 0)
2449 goto err;
2450
2451 return 0;
2452err:
2453 return ret;
2454}
2455
2456static int rt5645_i2c_remove(struct i2c_client *i2c)
2457{
2458 snd_soc_unregister_codec(&i2c->dev);
2459
2460 return 0;
2461}
2462
2463struct i2c_driver rt5645_i2c_driver = {
2464 .driver = {
2465 .name = "rt5645",
2466 .owner = THIS_MODULE,
2467 },
2468 .probe = rt5645_i2c_probe,
2469 .remove = rt5645_i2c_remove,
2470 .id_table = rt5645_i2c_id,
2471};
2472module_i2c_driver(rt5645_i2c_driver);
2473
2474MODULE_DESCRIPTION("ASoC RT5645 driver");
2475MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2476MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
new file mode 100644
index 000000000000..345aa3f5d14f
--- /dev/null
+++ b/sound/soc/codecs/rt5645.h
@@ -0,0 +1,2188 @@
1/*
2 * rt5645.h -- RT5645 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5645_H__
13#define __RT5645_H__
14
15#include <sound/rt5645.h>
16
17/* Info */
18#define RT5645_RESET 0x00
19#define RT5645_VENDOR_ID 0xfd
20#define RT5645_VENDOR_ID1 0xfe
21#define RT5645_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5645_SPK_VOL 0x01
24#define RT5645_HP_VOL 0x02
25#define RT5645_LOUT1 0x03
26#define RT5645_LOUT_CTRL 0x05
27/* I/O - Input */
28#define RT5645_IN1_CTRL1 0x0a
29#define RT5645_IN1_CTRL2 0x0b
30#define RT5645_IN1_CTRL3 0x0c
31#define RT5645_IN2_CTRL 0x0d
32#define RT5645_INL1_INR1_VOL 0x0f
33#define RT5645_SPK_FUNC_LIM 0x14
34#define RT5645_ADJ_HPF_CTRL 0x16
35/* I/O - ADC/DAC/DMIC */
36#define RT5645_DAC1_DIG_VOL 0x19
37#define RT5645_DAC2_DIG_VOL 0x1a
38#define RT5645_DAC_CTRL 0x1b
39#define RT5645_STO1_ADC_DIG_VOL 0x1c
40#define RT5645_MONO_ADC_DIG_VOL 0x1d
41#define RT5645_ADC_BST_VOL1 0x1e
42/* Mixer - D-D */
43#define RT5645_ADC_BST_VOL2 0x20
44#define RT5645_STO1_ADC_MIXER 0x27
45#define RT5645_MONO_ADC_MIXER 0x28
46#define RT5645_AD_DA_MIXER 0x29
47#define RT5645_STO_DAC_MIXER 0x2a
48#define RT5645_MONO_DAC_MIXER 0x2b
49#define RT5645_DIG_MIXER 0x2c
50#define RT5645_DIG_INF1_DATA 0x2f
51/* Mixer - PDM */
52#define RT5645_PDM_OUT_CTRL 0x31
53/* Mixer - ADC */
54#define RT5645_REC_L1_MIXER 0x3b
55#define RT5645_REC_L2_MIXER 0x3c
56#define RT5645_REC_R1_MIXER 0x3d
57#define RT5645_REC_R2_MIXER 0x3e
58/* Mixer - DAC */
59#define RT5645_HPMIXL_CTRL 0x3f
60#define RT5645_HPOMIXL_CTRL 0x40
61#define RT5645_HPMIXR_CTRL 0x41
62#define RT5645_HPOMIXR_CTRL 0x42
63#define RT5645_HPO_MIXER 0x45
64#define RT5645_SPK_L_MIXER 0x46
65#define RT5645_SPK_R_MIXER 0x47
66#define RT5645_SPO_MIXER 0x48
67#define RT5645_SPO_CLSD_RATIO 0x4a
68#define RT5645_OUT_L_GAIN1 0x4d
69#define RT5645_OUT_L_GAIN2 0x4e
70#define RT5645_OUT_L1_MIXER 0x4f
71#define RT5645_OUT_R_GAIN1 0x50
72#define RT5645_OUT_R_GAIN2 0x51
73#define RT5645_OUT_R1_MIXER 0x52
74#define RT5645_LOUT_MIXER 0x53
75/* Haptic */
76#define RT5645_HAPTIC_CTRL1 0x56
77#define RT5645_HAPTIC_CTRL2 0x57
78#define RT5645_HAPTIC_CTRL3 0x58
79#define RT5645_HAPTIC_CTRL4 0x59
80#define RT5645_HAPTIC_CTRL5 0x5a
81#define RT5645_HAPTIC_CTRL6 0x5b
82#define RT5645_HAPTIC_CTRL7 0x5c
83#define RT5645_HAPTIC_CTRL8 0x5d
84#define RT5645_HAPTIC_CTRL9 0x5e
85#define RT5645_HAPTIC_CTRL10 0x5f
86/* Power */
87#define RT5645_PWR_DIG1 0x61
88#define RT5645_PWR_DIG2 0x62
89#define RT5645_PWR_ANLG1 0x63
90#define RT5645_PWR_ANLG2 0x64
91#define RT5645_PWR_MIXER 0x65
92#define RT5645_PWR_VOL 0x66
93/* Private Register Control */
94#define RT5645_PRIV_INDEX 0x6a
95#define RT5645_PRIV_DATA 0x6c
96/* Format - ADC/DAC */
97#define RT5645_I2S1_SDP 0x70
98#define RT5645_I2S2_SDP 0x71
99#define RT5645_ADDA_CLK1 0x73
100#define RT5645_ADDA_CLK2 0x74
101#define RT5645_DMIC_CTRL1 0x75
102#define RT5645_DMIC_CTRL2 0x76
103/* Format - TDM Control */
104#define RT5645_TDM_CTRL_1 0x77
105#define RT5645_TDM_CTRL_2 0x78
106#define RT5645_TDM_CTRL_3 0x79
107
108/* Function - Analog */
109#define RT5645_GLB_CLK 0x80
110#define RT5645_PLL_CTRL1 0x81
111#define RT5645_PLL_CTRL2 0x82
112#define RT5645_ASRC_1 0x83
113#define RT5645_ASRC_2 0x84
114#define RT5645_ASRC_3 0x85
115#define RT5645_ASRC_4 0x8a
116#define RT5645_DEPOP_M1 0x8e
117#define RT5645_DEPOP_M2 0x8f
118#define RT5645_DEPOP_M3 0x90
119#define RT5645_CHARGE_PUMP 0x91
120#define RT5645_MICBIAS 0x93
121#define RT5645_A_JD_CTRL1 0x94
122#define RT5645_VAD_CTRL4 0x9d
123#define RT5645_CLSD_OUT_CTRL 0xa0
124/* Function - Digital */
125#define RT5645_ADC_EQ_CTRL1 0xae
126#define RT5645_ADC_EQ_CTRL2 0xaf
127#define RT5645_EQ_CTRL1 0xb0
128#define RT5645_EQ_CTRL2 0xb1
129#define RT5645_ALC_CTRL_1 0xb3
130#define RT5645_ALC_CTRL_2 0xb4
131#define RT5645_ALC_CTRL_3 0xb5
132#define RT5645_ALC_CTRL_4 0xb6
133#define RT5645_ALC_CTRL_5 0xb7
134#define RT5645_JD_CTRL 0xbb
135#define RT5645_IRQ_CTRL1 0xbc
136#define RT5645_IRQ_CTRL2 0xbd
137#define RT5645_IRQ_CTRL3 0xbe
138#define RT5645_INT_IRQ_ST 0xbf
139#define RT5645_GPIO_CTRL1 0xc0
140#define RT5645_GPIO_CTRL2 0xc1
141#define RT5645_GPIO_CTRL3 0xc2
142#define RT5645_BASS_BACK 0xcf
143#define RT5645_MP3_PLUS1 0xd0
144#define RT5645_MP3_PLUS2 0xd1
145#define RT5645_ADJ_HPF1 0xd3
146#define RT5645_ADJ_HPF2 0xd4
147#define RT5645_HP_CALIB_AMP_DET 0xd6
148#define RT5645_SV_ZCD1 0xd9
149#define RT5645_SV_ZCD2 0xda
150#define RT5645_IL_CMD 0xdb
151#define RT5645_IL_CMD2 0xdc
152#define RT5645_IL_CMD3 0xdd
153#define RT5645_DRC1_HL_CTRL1 0xe7
154#define RT5645_DRC2_HL_CTRL1 0xe9
155#define RT5645_MUTI_DRC_CTRL1 0xea
156#define RT5645_ADC_MONO_HP_CTRL1 0xec
157#define RT5645_ADC_MONO_HP_CTRL2 0xed
158#define RT5645_DRC2_CTRL1 0xf0
159#define RT5645_DRC2_CTRL2 0xf1
160#define RT5645_DRC2_CTRL3 0xf2
161#define RT5645_DRC2_CTRL4 0xf3
162#define RT5645_DRC2_CTRL5 0xf4
163#define RT5645_JD_CTRL3 0xf8
164#define RT5645_JD_CTRL4 0xf9
165/* General Control */
166#define RT5645_GEN_CTRL1 0xfa
167#define RT5645_GEN_CTRL2 0xfb
168#define RT5645_GEN_CTRL3 0xfc
169
170
171/* Index of Codec Private Register definition */
172#define RT5645_DIG_VOL 0x00
173#define RT5645_PR_ALC_CTRL_1 0x01
174#define RT5645_PR_ALC_CTRL_2 0x02
175#define RT5645_PR_ALC_CTRL_3 0x03
176#define RT5645_PR_ALC_CTRL_4 0x04
177#define RT5645_PR_ALC_CTRL_5 0x05
178#define RT5645_PR_ALC_CTRL_6 0x06
179#define RT5645_BIAS_CUR1 0x12
180#define RT5645_BIAS_CUR3 0x14
181#define RT5645_CLSD_INT_REG1 0x1c
182#define RT5645_MAMP_INT_REG2 0x37
183#define RT5645_CHOP_DAC_ADC 0x3d
184#define RT5645_MIXER_INT_REG 0x3f
185#define RT5645_3D_SPK 0x63
186#define RT5645_WND_1 0x6c
187#define RT5645_WND_2 0x6d
188#define RT5645_WND_3 0x6e
189#define RT5645_WND_4 0x6f
190#define RT5645_WND_5 0x70
191#define RT5645_WND_8 0x73
192#define RT5645_DIP_SPK_INF 0x75
193#define RT5645_HP_DCC_INT1 0x77
194#define RT5645_EQ_BW_LOP 0xa0
195#define RT5645_EQ_GN_LOP 0xa1
196#define RT5645_EQ_FC_BP1 0xa2
197#define RT5645_EQ_BW_BP1 0xa3
198#define RT5645_EQ_GN_BP1 0xa4
199#define RT5645_EQ_FC_BP2 0xa5
200#define RT5645_EQ_BW_BP2 0xa6
201#define RT5645_EQ_GN_BP2 0xa7
202#define RT5645_EQ_FC_BP3 0xa8
203#define RT5645_EQ_BW_BP3 0xa9
204#define RT5645_EQ_GN_BP3 0xaa
205#define RT5645_EQ_FC_BP4 0xab
206#define RT5645_EQ_BW_BP4 0xac
207#define RT5645_EQ_GN_BP4 0xad
208#define RT5645_EQ_FC_HIP1 0xae
209#define RT5645_EQ_GN_HIP1 0xaf
210#define RT5645_EQ_FC_HIP2 0xb0
211#define RT5645_EQ_BW_HIP2 0xb1
212#define RT5645_EQ_GN_HIP2 0xb2
213#define RT5645_EQ_PRE_VOL 0xb3
214#define RT5645_EQ_PST_VOL 0xb4
215
216
217/* global definition */
218#define RT5645_L_MUTE (0x1 << 15)
219#define RT5645_L_MUTE_SFT 15
220#define RT5645_VOL_L_MUTE (0x1 << 14)
221#define RT5645_VOL_L_SFT 14
222#define RT5645_R_MUTE (0x1 << 7)
223#define RT5645_R_MUTE_SFT 7
224#define RT5645_VOL_R_MUTE (0x1 << 6)
225#define RT5645_VOL_R_SFT 6
226#define RT5645_L_VOL_MASK (0x3f << 8)
227#define RT5645_L_VOL_SFT 8
228#define RT5645_R_VOL_MASK (0x3f)
229#define RT5645_R_VOL_SFT 0
230
231/* IN1 Control 1 (0x0a) */
232#define RT5645_CBJ_BST1_MASK (0xf << 12)
233#define RT5645_CBJ_BST1_SFT (12)
234#define RT5645_CBJ_JD_HP_EN (0x1 << 9)
235#define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
236#define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
237#define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
238#define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
239#define RT5645_CBJ_MIC_SW (0x1 << 4)
240#define RT5645_CBJ_BST1_EN (0x1 << 2)
241
242/* IN1 Control 2 (0x0b) */
243#define RT5645_CBJ_MN_JD (0x1 << 12)
244#define RT5645_CAPLESS_EN (0x1 << 11)
245#define RT5645_CBJ_DET_MODE (0x1 << 7)
246
247/* IN1 Control 3 (0x0c) */
248#define RT5645_CBJ_TIE_G_L (0x1 << 15)
249#define RT5645_CBJ_TIE_G_R (0x1 << 14)
250
251/* IN2 Control (0x0d) */
252#define RT5645_BST_MASK1 (0xf<<12)
253#define RT5645_BST_SFT1 12
254#define RT5645_BST_MASK2 (0xf<<8)
255#define RT5645_BST_SFT2 8
256#define RT5645_IN_DF2 (0x1 << 6)
257#define RT5645_IN_SFT2 6
258
259/* INL and INR Volume Control (0x0f) */
260#define RT5645_INL_SEL_MASK (0x1 << 15)
261#define RT5645_INL_SEL_SFT 15
262#define RT5645_INL_SEL_IN4P (0x0 << 15)
263#define RT5645_INL_SEL_MONOP (0x1 << 15)
264#define RT5645_INL_VOL_MASK (0x1f << 8)
265#define RT5645_INL_VOL_SFT 8
266#define RT5645_INR_SEL_MASK (0x1 << 7)
267#define RT5645_INR_SEL_SFT 7
268#define RT5645_INR_SEL_IN4N (0x0 << 7)
269#define RT5645_INR_SEL_MONON (0x1 << 7)
270#define RT5645_INR_VOL_MASK (0x1f)
271#define RT5645_INR_VOL_SFT 0
272
273/* DAC1 Digital Volume (0x19) */
274#define RT5645_DAC_L1_VOL_MASK (0xff << 8)
275#define RT5645_DAC_L1_VOL_SFT 8
276#define RT5645_DAC_R1_VOL_MASK (0xff)
277#define RT5645_DAC_R1_VOL_SFT 0
278
279/* DAC2 Digital Volume (0x1a) */
280#define RT5645_DAC_L2_VOL_MASK (0xff << 8)
281#define RT5645_DAC_L2_VOL_SFT 8
282#define RT5645_DAC_R2_VOL_MASK (0xff)
283#define RT5645_DAC_R2_VOL_SFT 0
284
285/* DAC2 Control (0x1b) */
286#define RT5645_M_DAC_L2_VOL (0x1 << 13)
287#define RT5645_M_DAC_L2_VOL_SFT 13
288#define RT5645_M_DAC_R2_VOL (0x1 << 12)
289#define RT5645_M_DAC_R2_VOL_SFT 12
290#define RT5645_DAC2_L_SEL_MASK (0x7 << 4)
291#define RT5645_DAC2_L_SEL_SFT 4
292#define RT5645_DAC2_R_SEL_MASK (0x7 << 0)
293#define RT5645_DAC2_R_SEL_SFT 0
294
295/* ADC Digital Volume Control (0x1c) */
296#define RT5645_ADC_L_VOL_MASK (0x7f << 8)
297#define RT5645_ADC_L_VOL_SFT 8
298#define RT5645_ADC_R_VOL_MASK (0x7f)
299#define RT5645_ADC_R_VOL_SFT 0
300
301/* Mono ADC Digital Volume Control (0x1d) */
302#define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
303#define RT5645_MONO_ADC_L_VOL_SFT 8
304#define RT5645_MONO_ADC_R_VOL_MASK (0x7f)
305#define RT5645_MONO_ADC_R_VOL_SFT 0
306
307/* ADC Boost Volume Control (0x1e) */
308#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
309#define RT5645_STO1_ADC_L_BST_SFT 14
310#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
311#define RT5645_STO1_ADC_R_BST_SFT 12
312#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
313#define RT5645_STO1_ADC_COMP_SFT 10
314#define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8)
315#define RT5645_STO2_ADC_L_BST_SFT 8
316#define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6)
317#define RT5645_STO2_ADC_R_BST_SFT 6
318#define RT5645_STO2_ADC_COMP_MASK (0x3 << 4)
319#define RT5645_STO2_ADC_COMP_SFT 4
320
321/* Stereo2 ADC Mixer Control (0x26) */
322#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
323#define RT5645_STO2_ADC_SRC_SFT 15
324
325/* Stereo ADC Mixer Control (0x27) */
326#define RT5645_M_ADC_L1 (0x1 << 14)
327#define RT5645_M_ADC_L1_SFT 14
328#define RT5645_M_ADC_L2 (0x1 << 13)
329#define RT5645_M_ADC_L2_SFT 13
330#define RT5645_ADC_1_SRC_MASK (0x1 << 12)
331#define RT5645_ADC_1_SRC_SFT 12
332#define RT5645_ADC_1_SRC_ADC (0x1 << 12)
333#define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
334#define RT5645_ADC_2_SRC_MASK (0x1 << 11)
335#define RT5645_ADC_2_SRC_SFT 11
336#define RT5645_DMIC_SRC_MASK (0x1 << 8)
337#define RT5645_DMIC_SRC_SFT 8
338#define RT5645_M_ADC_R1 (0x1 << 6)
339#define RT5645_M_ADC_R1_SFT 6
340#define RT5645_M_ADC_R2 (0x1 << 5)
341#define RT5645_M_ADC_R2_SFT 5
342#define RT5645_DMIC3_SRC_MASK (0x1 << 1)
343#define RT5645_DMIC3_SRC_SFT 0
344
345/* Mono ADC Mixer Control (0x28) */
346#define RT5645_M_MONO_ADC_L1 (0x1 << 14)
347#define RT5645_M_MONO_ADC_L1_SFT 14
348#define RT5645_M_MONO_ADC_L2 (0x1 << 13)
349#define RT5645_M_MONO_ADC_L2_SFT 13
350#define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
351#define RT5645_MONO_ADC_L1_SRC_SFT 12
352#define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
353#define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
354#define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
355#define RT5645_MONO_ADC_L2_SRC_SFT 11
356#define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
357#define RT5645_MONO_DMIC_L_SRC_SFT 8
358#define RT5645_M_MONO_ADC_R1 (0x1 << 6)
359#define RT5645_M_MONO_ADC_R1_SFT 6
360#define RT5645_M_MONO_ADC_R2 (0x1 << 5)
361#define RT5645_M_MONO_ADC_R2_SFT 5
362#define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
363#define RT5645_MONO_ADC_R1_SRC_SFT 4
364#define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
365#define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
366#define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
367#define RT5645_MONO_ADC_R2_SRC_SFT 3
368#define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
369#define RT5645_MONO_DMIC_R_SRC_SFT 0
370
371/* ADC Mixer to DAC Mixer Control (0x29) */
372#define RT5645_M_ADCMIX_L (0x1 << 15)
373#define RT5645_M_ADCMIX_L_SFT 15
374#define RT5645_M_DAC1_L (0x1 << 14)
375#define RT5645_M_DAC1_L_SFT 14
376#define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
377#define RT5645_DAC1_R_SEL_SFT 10
378#define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
379#define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
380#define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
381#define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
382#define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
383#define RT5645_DAC1_L_SEL_SFT 8
384#define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
385#define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
386#define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
387#define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
388#define RT5645_M_ADCMIX_R (0x1 << 7)
389#define RT5645_M_ADCMIX_R_SFT 7
390#define RT5645_M_DAC1_R (0x1 << 6)
391#define RT5645_M_DAC1_R_SFT 6
392
393/* Stereo DAC Mixer Control (0x2a) */
394#define RT5645_M_DAC_L1 (0x1 << 14)
395#define RT5645_M_DAC_L1_SFT 14
396#define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
397#define RT5645_DAC_L1_STO_L_VOL_SFT 13
398#define RT5645_M_DAC_L2 (0x1 << 12)
399#define RT5645_M_DAC_L2_SFT 12
400#define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
401#define RT5645_DAC_L2_STO_L_VOL_SFT 11
402#define RT5645_M_ANC_DAC_L (0x1 << 10)
403#define RT5645_M_ANC_DAC_L_SFT 10
404#define RT5645_M_DAC_R1_STO_L (0x1 << 9)
405#define RT5645_M_DAC_R1_STO_L_SFT 9
406#define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
407#define RT5645_DAC_R1_STO_L_VOL_SFT 8
408#define RT5645_M_DAC_R1 (0x1 << 6)
409#define RT5645_M_DAC_R1_SFT 6
410#define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
411#define RT5645_DAC_R1_STO_R_VOL_SFT 5
412#define RT5645_M_DAC_R2 (0x1 << 4)
413#define RT5645_M_DAC_R2_SFT 4
414#define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
415#define RT5645_DAC_R2_STO_R_VOL_SFT 3
416#define RT5645_M_ANC_DAC_R (0x1 << 2)
417#define RT5645_M_ANC_DAC_R_SFT 2
418#define RT5645_M_DAC_L1_STO_R (0x1 << 1)
419#define RT5645_M_DAC_L1_STO_R_SFT 1
420#define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
421#define RT5645_DAC_L1_STO_R_VOL_SFT 0
422
423/* Mono DAC Mixer Control (0x2b) */
424#define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
425#define RT5645_M_DAC_L1_MONO_L_SFT 14
426#define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
427#define RT5645_DAC_L1_MONO_L_VOL_SFT 13
428#define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
429#define RT5645_M_DAC_L2_MONO_L_SFT 12
430#define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
431#define RT5645_DAC_L2_MONO_L_VOL_SFT 11
432#define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
433#define RT5645_M_DAC_R2_MONO_L_SFT 10
434#define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
435#define RT5645_DAC_R2_MONO_L_VOL_SFT 9
436#define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
437#define RT5645_M_DAC_R1_MONO_R_SFT 6
438#define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
439#define RT5645_DAC_R1_MONO_R_VOL_SFT 5
440#define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
441#define RT5645_M_DAC_R2_MONO_R_SFT 4
442#define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
443#define RT5645_DAC_R2_MONO_R_VOL_SFT 3
444#define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
445#define RT5645_M_DAC_L2_MONO_R_SFT 2
446#define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
447#define RT5645_DAC_L2_MONO_R_VOL_SFT 1
448
449/* Digital Mixer Control (0x2c) */
450#define RT5645_M_STO_L_DAC_L (0x1 << 15)
451#define RT5645_M_STO_L_DAC_L_SFT 15
452#define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
453#define RT5645_STO_L_DAC_L_VOL_SFT 14
454#define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
455#define RT5645_M_DAC_L2_DAC_L_SFT 13
456#define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
457#define RT5645_DAC_L2_DAC_L_VOL_SFT 12
458#define RT5645_M_STO_R_DAC_R (0x1 << 11)
459#define RT5645_M_STO_R_DAC_R_SFT 11
460#define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
461#define RT5645_STO_R_DAC_R_VOL_SFT 10
462#define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
463#define RT5645_M_DAC_R2_DAC_R_SFT 9
464#define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
465#define RT5645_DAC_R2_DAC_R_VOL_SFT 8
466#define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
467#define RT5645_M_DAC_R2_DAC_L_SFT 7
468#define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
469#define RT5645_DAC_R2_DAC_L_VOL_SFT 6
470#define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
471#define RT5645_M_DAC_L2_DAC_R_SFT 5
472#define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
473#define RT5645_DAC_L2_DAC_R_VOL_SFT 4
474
475/* Digital Interface Data Control (0x2f) */
476#define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
477#define RT5645_IF1_ADC2_IN_SFT 15
478#define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
479#define RT5645_IF2_ADC_IN_SFT 12
480#define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
481#define RT5645_IF2_DAC_SEL_SFT 10
482#define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
483#define RT5645_IF2_ADC_SEL_SFT 8
484#define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
485#define RT5645_IF3_DAC_SEL_SFT 6
486#define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)
487#define RT5645_IF3_ADC_SEL_SFT 4
488#define RT5645_IF3_ADC_IN_MASK (0x7)
489#define RT5645_IF3_ADC_IN_SFT 0
490
491/* PDM Output Control (0x31) */
492#define RT5645_PDM1_L_MASK (0x1 << 15)
493#define RT5645_PDM1_L_SFT 15
494#define RT5645_M_PDM1_L (0x1 << 14)
495#define RT5645_M_PDM1_L_SFT 14
496#define RT5645_PDM1_R_MASK (0x1 << 13)
497#define RT5645_PDM1_R_SFT 13
498#define RT5645_M_PDM1_R (0x1 << 12)
499#define RT5645_M_PDM1_R_SFT 12
500#define RT5645_PDM2_L_MASK (0x1 << 11)
501#define RT5645_PDM2_L_SFT 11
502#define RT5645_M_PDM2_L (0x1 << 10)
503#define RT5645_M_PDM2_L_SFT 10
504#define RT5645_PDM2_R_MASK (0x1 << 9)
505#define RT5645_PDM2_R_SFT 9
506#define RT5645_M_PDM2_R (0x1 << 8)
507#define RT5645_M_PDM2_R_SFT 8
508#define RT5645_PDM2_BUSY (0x1 << 7)
509#define RT5645_PDM1_BUSY (0x1 << 6)
510#define RT5645_PDM_PATTERN (0x1 << 5)
511#define RT5645_PDM_GAIN (0x1 << 4)
512#define RT5645_PDM_DIV_MASK (0x3)
513
514/* REC Left Mixer Control 1 (0x3b) */
515#define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
516#define RT5645_G_HP_L_RM_L_SFT 13
517#define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
518#define RT5645_G_IN_L_RM_L_SFT 10
519#define RT5645_G_BST4_RM_L_MASK (0x7 << 7)
520#define RT5645_G_BST4_RM_L_SFT 7
521#define RT5645_G_BST3_RM_L_MASK (0x7 << 4)
522#define RT5645_G_BST3_RM_L_SFT 4
523#define RT5645_G_BST2_RM_L_MASK (0x7 << 1)
524#define RT5645_G_BST2_RM_L_SFT 1
525
526/* REC Left Mixer Control 2 (0x3c) */
527#define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
528#define RT5645_G_BST1_RM_L_SFT 13
529#define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
530#define RT5645_G_OM_L_RM_L_SFT 10
531#define RT5645_M_MM_L_RM_L (0x1 << 6)
532#define RT5645_M_MM_L_RM_L_SFT 6
533#define RT5645_M_IN_L_RM_L (0x1 << 5)
534#define RT5645_M_IN_L_RM_L_SFT 5
535#define RT5645_M_HP_L_RM_L (0x1 << 4)
536#define RT5645_M_HP_L_RM_L_SFT 4
537#define RT5645_M_BST3_RM_L (0x1 << 3)
538#define RT5645_M_BST3_RM_L_SFT 3
539#define RT5645_M_BST2_RM_L (0x1 << 2)
540#define RT5645_M_BST2_RM_L_SFT 2
541#define RT5645_M_BST1_RM_L (0x1 << 1)
542#define RT5645_M_BST1_RM_L_SFT 1
543#define RT5645_M_OM_L_RM_L (0x1)
544#define RT5645_M_OM_L_RM_L_SFT 0
545
546/* REC Right Mixer Control 1 (0x3d) */
547#define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
548#define RT5645_G_HP_R_RM_R_SFT 13
549#define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
550#define RT5645_G_IN_R_RM_R_SFT 10
551#define RT5645_G_BST4_RM_R_MASK (0x7 << 7)
552#define RT5645_G_BST4_RM_R_SFT 7
553#define RT5645_G_BST3_RM_R_MASK (0x7 << 4)
554#define RT5645_G_BST3_RM_R_SFT 4
555#define RT5645_G_BST2_RM_R_MASK (0x7 << 1)
556#define RT5645_G_BST2_RM_R_SFT 1
557
558/* REC Right Mixer Control 2 (0x3e) */
559#define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
560#define RT5645_G_BST1_RM_R_SFT 13
561#define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
562#define RT5645_G_OM_R_RM_R_SFT 10
563#define RT5645_M_MM_R_RM_R (0x1 << 6)
564#define RT5645_M_MM_R_RM_R_SFT 6
565#define RT5645_M_IN_R_RM_R (0x1 << 5)
566#define RT5645_M_IN_R_RM_R_SFT 5
567#define RT5645_M_HP_R_RM_R (0x1 << 4)
568#define RT5645_M_HP_R_RM_R_SFT 4
569#define RT5645_M_BST3_RM_R (0x1 << 3)
570#define RT5645_M_BST3_RM_R_SFT 3
571#define RT5645_M_BST2_RM_R (0x1 << 2)
572#define RT5645_M_BST2_RM_R_SFT 2
573#define RT5645_M_BST1_RM_R (0x1 << 1)
574#define RT5645_M_BST1_RM_R_SFT 1
575#define RT5645_M_OM_R_RM_R (0x1)
576#define RT5645_M_OM_R_RM_R_SFT 0
577
578/* HPOMIX Control (0x40) (0x42) */
579#define RT5645_M_BST1_HV (0x1 << 4)
580#define RT5645_M_BST1_HV_SFT 4
581#define RT5645_M_BST2_HV (0x1 << 4)
582#define RT5645_M_BST2_HV_SFT 4
583#define RT5645_M_BST3_HV (0x1 << 3)
584#define RT5645_M_BST3_HV_SFT 3
585#define RT5645_M_IN_HV (0x1 << 2)
586#define RT5645_M_IN_HV_SFT 2
587#define RT5645_M_DAC2_HV (0x1 << 1)
588#define RT5645_M_DAC2_HV_SFT 1
589#define RT5645_M_DAC1_HV (0x1 << 0)
590#define RT5645_M_DAC1_HV_SFT 0
591
592/* HPMIX Control (0x45) */
593#define RT5645_M_DAC1_HM (0x1 << 14)
594#define RT5645_M_DAC1_HM_SFT 14
595#define RT5645_M_HPVOL_HM (0x1 << 13)
596#define RT5645_M_HPVOL_HM_SFT 13
597
598/* SPK Left Mixer Control (0x46) */
599#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
600#define RT5645_G_RM_L_SM_L_SFT 14
601#define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
602#define RT5645_G_IN_L_SM_L_SFT 12
603#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
604#define RT5645_G_DAC_L1_SM_L_SFT 10
605#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
606#define RT5645_G_DAC_L2_SM_L_SFT 8
607#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
608#define RT5645_G_OM_L_SM_L_SFT 6
609#define RT5645_M_BST1_L_SM_L (0x1 << 5)
610#define RT5645_M_BST1_L_SM_L_SFT 5
611#define RT5645_M_IN_L_SM_L (0x1 << 3)
612#define RT5645_M_IN_L_SM_L_SFT 3
613#define RT5645_M_DAC_L1_SM_L (0x1 << 1)
614#define RT5645_M_DAC_L1_SM_L_SFT 1
615#define RT5645_M_DAC_L2_SM_L (0x1 << 2)
616#define RT5645_M_DAC_L2_SM_L_SFT 2
617#define RT5645_M_BST3_L_SM_L (0x1 << 4)
618#define RT5645_M_BST3_L_SM_L_SFT 4
619
620/* SPK Right Mixer Control (0x47) */
621#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
622#define RT5645_G_RM_R_SM_R_SFT 14
623#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
624#define RT5645_G_IN_R_SM_R_SFT 12
625#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
626#define RT5645_G_DAC_R1_SM_R_SFT 10
627#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
628#define RT5645_G_DAC_R2_SM_R_SFT 8
629#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
630#define RT5645_G_OM_R_SM_R_SFT 6
631#define RT5645_M_BST2_R_SM_R (0x1 << 5)
632#define RT5645_M_BST2_R_SM_R_SFT 5
633#define RT5645_M_IN_R_SM_R (0x1 << 3)
634#define RT5645_M_IN_R_SM_R_SFT 3
635#define RT5645_M_DAC_R1_SM_R (0x1 << 1)
636#define RT5645_M_DAC_R1_SM_R_SFT 1
637#define RT5645_M_DAC_R2_SM_R (0x1 << 2)
638#define RT5645_M_DAC_R2_SM_R_SFT 2
639#define RT5645_M_BST3_R_SM_R (0x1 << 4)
640#define RT5645_M_BST3_R_SM_R_SFT 4
641
642/* SPOLMIX Control (0x48) */
643#define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
644#define RT5645_M_DAC_L1_SPM_L_SFT 15
645#define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
646#define RT5645_M_DAC_R1_SPM_L_SFT 14
647#define RT5645_M_SV_L_SPM_L (0x1 << 13)
648#define RT5645_M_SV_L_SPM_L_SFT 13
649#define RT5645_M_SV_R_SPM_L (0x1 << 12)
650#define RT5645_M_SV_R_SPM_L_SFT 12
651#define RT5645_M_BST3_SPM_L (0x1 << 11)
652#define RT5645_M_BST3_SPM_L_SFT 11
653#define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
654#define RT5645_M_DAC_R1_SPM_R_SFT 2
655#define RT5645_M_BST3_SPM_R (0x1 << 1)
656#define RT5645_M_BST3_SPM_R_SFT 1
657#define RT5645_M_SV_R_SPM_R (0x1 << 0)
658#define RT5645_M_SV_R_SPM_R_SFT 0
659
660/* Mono Output Mixer Control (0x4c) */
661#define RT5645_M_OV_L_MM (0x1 << 9)
662#define RT5645_M_OV_L_MM_SFT 9
663#define RT5645_M_DAC_L2_MA (0x1 << 8)
664#define RT5645_M_DAC_L2_MA_SFT 8
665#define RT5645_G_MONOMIX_MASK (0x1 << 10)
666#define RT5645_G_MONOMIX_SFT 10
667#define RT5645_M_BST2_MM (0x1 << 4)
668#define RT5645_M_BST2_MM_SFT 4
669#define RT5645_M_DAC_R1_MM (0x1 << 3)
670#define RT5645_M_DAC_R1_MM_SFT 3
671#define RT5645_M_DAC_R2_MM (0x1 << 2)
672#define RT5645_M_DAC_R2_MM_SFT 2
673#define RT5645_M_DAC_L2_MM (0x1 << 1)
674#define RT5645_M_DAC_L2_MM_SFT 1
675#define RT5645_M_BST3_MM (0x1 << 0)
676#define RT5645_M_BST3_MM_SFT 0
677
678/* Output Left Mixer Control 1 (0x4d) */
679#define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
680#define RT5645_G_BST3_OM_L_SFT 13
681#define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
682#define RT5645_G_BST2_OM_L_SFT 10
683#define RT5645_G_BST1_OM_L_MASK (0x7 << 7)
684#define RT5645_G_BST1_OM_L_SFT 7
685#define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)
686#define RT5645_G_IN_L_OM_L_SFT 4
687#define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)
688#define RT5645_G_RM_L_OM_L_SFT 1
689
690/* Output Left Mixer Control 2 (0x4e) */
691#define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
692#define RT5645_G_DAC_R2_OM_L_SFT 13
693#define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
694#define RT5645_G_DAC_L2_OM_L_SFT 10
695#define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)
696#define RT5645_G_DAC_L1_OM_L_SFT 7
697
698/* Output Left Mixer Control 3 (0x4f) */
699#define RT5645_M_BST3_OM_L (0x1 << 4)
700#define RT5645_M_BST3_OM_L_SFT 4
701#define RT5645_M_BST1_OM_L (0x1 << 3)
702#define RT5645_M_BST1_OM_L_SFT 3
703#define RT5645_M_IN_L_OM_L (0x1 << 2)
704#define RT5645_M_IN_L_OM_L_SFT 2
705#define RT5645_M_DAC_L2_OM_L (0x1 << 1)
706#define RT5645_M_DAC_L2_OM_L_SFT 1
707#define RT5645_M_DAC_L1_OM_L (0x1)
708#define RT5645_M_DAC_L1_OM_L_SFT 0
709
710/* Output Right Mixer Control 1 (0x50) */
711#define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
712#define RT5645_G_BST4_OM_R_SFT 13
713#define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
714#define RT5645_G_BST2_OM_R_SFT 10
715#define RT5645_G_BST1_OM_R_MASK (0x7 << 7)
716#define RT5645_G_BST1_OM_R_SFT 7
717#define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)
718#define RT5645_G_IN_R_OM_R_SFT 4
719#define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)
720#define RT5645_G_RM_R_OM_R_SFT 1
721
722/* Output Right Mixer Control 2 (0x51) */
723#define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
724#define RT5645_G_DAC_L2_OM_R_SFT 13
725#define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
726#define RT5645_G_DAC_R2_OM_R_SFT 10
727#define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)
728#define RT5645_G_DAC_R1_OM_R_SFT 7
729
730/* Output Right Mixer Control 3 (0x52) */
731#define RT5645_M_BST3_OM_R (0x1 << 4)
732#define RT5645_M_BST3_OM_R_SFT 4
733#define RT5645_M_BST2_OM_R (0x1 << 3)
734#define RT5645_M_BST2_OM_R_SFT 3
735#define RT5645_M_IN_R_OM_R (0x1 << 2)
736#define RT5645_M_IN_R_OM_R_SFT 2
737#define RT5645_M_DAC_R2_OM_R (0x1 << 1)
738#define RT5645_M_DAC_R2_OM_R_SFT 1
739#define RT5645_M_DAC_R1_OM_R (0x1)
740#define RT5645_M_DAC_R1_OM_R_SFT 0
741
742/* LOUT Mixer Control (0x53) */
743#define RT5645_M_DAC_L1_LM (0x1 << 15)
744#define RT5645_M_DAC_L1_LM_SFT 15
745#define RT5645_M_DAC_R1_LM (0x1 << 14)
746#define RT5645_M_DAC_R1_LM_SFT 14
747#define RT5645_M_OV_L_LM (0x1 << 13)
748#define RT5645_M_OV_L_LM_SFT 13
749#define RT5645_M_OV_R_LM (0x1 << 12)
750#define RT5645_M_OV_R_LM_SFT 12
751#define RT5645_G_LOUTMIX_MASK (0x1 << 11)
752#define RT5645_G_LOUTMIX_SFT 11
753
754/* Power Management for Digital 1 (0x61) */
755#define RT5645_PWR_I2S1 (0x1 << 15)
756#define RT5645_PWR_I2S1_BIT 15
757#define RT5645_PWR_I2S2 (0x1 << 14)
758#define RT5645_PWR_I2S2_BIT 14
759#define RT5645_PWR_I2S3 (0x1 << 13)
760#define RT5645_PWR_I2S3_BIT 13
761#define RT5645_PWR_DAC_L1 (0x1 << 12)
762#define RT5645_PWR_DAC_L1_BIT 12
763#define RT5645_PWR_DAC_R1 (0x1 << 11)
764#define RT5645_PWR_DAC_R1_BIT 11
765#define RT5645_PWR_CLS_D_R (0x1 << 9)
766#define RT5645_PWR_CLS_D_R_BIT 9
767#define RT5645_PWR_CLS_D_L (0x1 << 8)
768#define RT5645_PWR_CLS_D_L_BIT 8
769#define RT5645_PWR_ADC_R (0x1 << 1)
770#define RT5645_PWR_ADC_R_BIT 1
771#define RT5645_PWR_DAC_L2 (0x1 << 7)
772#define RT5645_PWR_DAC_L2_BIT 7
773#define RT5645_PWR_DAC_R2 (0x1 << 6)
774#define RT5645_PWR_DAC_R2_BIT 6
775#define RT5645_PWR_ADC_L (0x1 << 2)
776#define RT5645_PWR_ADC_L_BIT 2
777#define RT5645_PWR_ADC_R (0x1 << 1)
778#define RT5645_PWR_ADC_R_BIT 1
779#define RT5645_PWR_CLS_D (0x1)
780#define RT5645_PWR_CLS_D_BIT 0
781
782/* Power Management for Digital 2 (0x62) */
783#define RT5645_PWR_ADC_S1F (0x1 << 15)
784#define RT5645_PWR_ADC_S1F_BIT 15
785#define RT5645_PWR_ADC_MF_L (0x1 << 14)
786#define RT5645_PWR_ADC_MF_L_BIT 14
787#define RT5645_PWR_ADC_MF_R (0x1 << 13)
788#define RT5645_PWR_ADC_MF_R_BIT 13
789#define RT5645_PWR_I2S_DSP (0x1 << 12)
790#define RT5645_PWR_I2S_DSP_BIT 12
791#define RT5645_PWR_DAC_S1F (0x1 << 11)
792#define RT5645_PWR_DAC_S1F_BIT 11
793#define RT5645_PWR_DAC_MF_L (0x1 << 10)
794#define RT5645_PWR_DAC_MF_L_BIT 10
795#define RT5645_PWR_DAC_MF_R (0x1 << 9)
796#define RT5645_PWR_DAC_MF_R_BIT 9
797#define RT5645_PWR_ADC_S2F (0x1 << 8)
798#define RT5645_PWR_ADC_S2F_BIT 8
799#define RT5645_PWR_PDM1 (0x1 << 7)
800#define RT5645_PWR_PDM1_BIT 7
801#define RT5645_PWR_PDM2 (0x1 << 6)
802#define RT5645_PWR_PDM2_BIT 6
803#define RT5645_PWR_IPTV (0x1 << 1)
804#define RT5645_PWR_IPTV_BIT 1
805#define RT5645_PWR_PAD (0x1)
806#define RT5645_PWR_PAD_BIT 0
807
808/* Power Management for Analog 1 (0x63) */
809#define RT5645_PWR_VREF1 (0x1 << 15)
810#define RT5645_PWR_VREF1_BIT 15
811#define RT5645_PWR_FV1 (0x1 << 14)
812#define RT5645_PWR_FV1_BIT 14
813#define RT5645_PWR_MB (0x1 << 13)
814#define RT5645_PWR_MB_BIT 13
815#define RT5645_PWR_LM (0x1 << 12)
816#define RT5645_PWR_LM_BIT 12
817#define RT5645_PWR_BG (0x1 << 11)
818#define RT5645_PWR_BG_BIT 11
819#define RT5645_PWR_MA (0x1 << 10)
820#define RT5645_PWR_MA_BIT 10
821#define RT5645_PWR_HP_L (0x1 << 7)
822#define RT5645_PWR_HP_L_BIT 7
823#define RT5645_PWR_HP_R (0x1 << 6)
824#define RT5645_PWR_HP_R_BIT 6
825#define RT5645_PWR_HA (0x1 << 5)
826#define RT5645_PWR_HA_BIT 5
827#define RT5645_PWR_VREF2 (0x1 << 4)
828#define RT5645_PWR_VREF2_BIT 4
829#define RT5645_PWR_FV2 (0x1 << 3)
830#define RT5645_PWR_FV2_BIT 3
831#define RT5645_LDO_SEL_MASK (0x3)
832#define RT5645_LDO_SEL_SFT 0
833
834/* Power Management for Analog 2 (0x64) */
835#define RT5645_PWR_BST1 (0x1 << 15)
836#define RT5645_PWR_BST1_BIT 15
837#define RT5645_PWR_BST2 (0x1 << 14)
838#define RT5645_PWR_BST2_BIT 14
839#define RT5645_PWR_BST3 (0x1 << 13)
840#define RT5645_PWR_BST3_BIT 13
841#define RT5645_PWR_BST4 (0x1 << 12)
842#define RT5645_PWR_BST4_BIT 12
843#define RT5645_PWR_MB1 (0x1 << 11)
844#define RT5645_PWR_MB1_BIT 11
845#define RT5645_PWR_MB2 (0x1 << 10)
846#define RT5645_PWR_MB2_BIT 10
847#define RT5645_PWR_PLL (0x1 << 9)
848#define RT5645_PWR_PLL_BIT 9
849#define RT5645_PWR_BST2_P (0x1 << 5)
850#define RT5645_PWR_BST2_P_BIT 5
851#define RT5645_PWR_BST3_P (0x1 << 4)
852#define RT5645_PWR_BST3_P_BIT 4
853#define RT5645_PWR_BST4_P (0x1 << 3)
854#define RT5645_PWR_BST4_P_BIT 3
855#define RT5645_PWR_JD1 (0x1 << 2)
856#define RT5645_PWR_JD1_BIT 2
857#define RT5645_PWR_JD (0x1 << 1)
858#define RT5645_PWR_JD_BIT 1
859
860/* Power Management for Mixer (0x65) */
861#define RT5645_PWR_OM_L (0x1 << 15)
862#define RT5645_PWR_OM_L_BIT 15
863#define RT5645_PWR_OM_R (0x1 << 14)
864#define RT5645_PWR_OM_R_BIT 14
865#define RT5645_PWR_SM_L (0x1 << 13)
866#define RT5645_PWR_SM_L_BIT 13
867#define RT5645_PWR_SM_R (0x1 << 12)
868#define RT5645_PWR_SM_R_BIT 12
869#define RT5645_PWR_RM_L (0x1 << 11)
870#define RT5645_PWR_RM_L_BIT 11
871#define RT5645_PWR_RM_R (0x1 << 10)
872#define RT5645_PWR_RM_R_BIT 10
873#define RT5645_PWR_MM (0x1 << 8)
874#define RT5645_PWR_MM_BIT 8
875#define RT5645_PWR_HM_L (0x1 << 7)
876#define RT5645_PWR_HM_L_BIT 7
877#define RT5645_PWR_HM_R (0x1 << 6)
878#define RT5645_PWR_HM_R_BIT 6
879#define RT5645_PWR_LDO2 (0x1 << 1)
880#define RT5645_PWR_LDO2_BIT 1
881
882/* Power Management for Volume (0x66) */
883#define RT5645_PWR_SV_L (0x1 << 15)
884#define RT5645_PWR_SV_L_BIT 15
885#define RT5645_PWR_SV_R (0x1 << 14)
886#define RT5645_PWR_SV_R_BIT 14
887#define RT5645_PWR_HV_L (0x1 << 11)
888#define RT5645_PWR_HV_L_BIT 11
889#define RT5645_PWR_HV_R (0x1 << 10)
890#define RT5645_PWR_HV_R_BIT 10
891#define RT5645_PWR_IN_L (0x1 << 9)
892#define RT5645_PWR_IN_L_BIT 9
893#define RT5645_PWR_IN_R (0x1 << 8)
894#define RT5645_PWR_IN_R_BIT 8
895#define RT5645_PWR_MIC_DET (0x1 << 5)
896#define RT5645_PWR_MIC_DET_BIT 5
897
898/* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */
899#define RT5645_I2S_MS_MASK (0x1 << 15)
900#define RT5645_I2S_MS_SFT 15
901#define RT5645_I2S_MS_M (0x0 << 15)
902#define RT5645_I2S_MS_S (0x1 << 15)
903#define RT5645_I2S_O_CP_MASK (0x3 << 10)
904#define RT5645_I2S_O_CP_SFT 10
905#define RT5645_I2S_O_CP_OFF (0x0 << 10)
906#define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
907#define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
908#define RT5645_I2S_I_CP_MASK (0x3 << 8)
909#define RT5645_I2S_I_CP_SFT 8
910#define RT5645_I2S_I_CP_OFF (0x0 << 8)
911#define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
912#define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
913#define RT5645_I2S_BP_MASK (0x1 << 7)
914#define RT5645_I2S_BP_SFT 7
915#define RT5645_I2S_BP_NOR (0x0 << 7)
916#define RT5645_I2S_BP_INV (0x1 << 7)
917#define RT5645_I2S_DL_MASK (0x3 << 2)
918#define RT5645_I2S_DL_SFT 2
919#define RT5645_I2S_DL_16 (0x0 << 2)
920#define RT5645_I2S_DL_20 (0x1 << 2)
921#define RT5645_I2S_DL_24 (0x2 << 2)
922#define RT5645_I2S_DL_8 (0x3 << 2)
923#define RT5645_I2S_DF_MASK (0x3)
924#define RT5645_I2S_DF_SFT 0
925#define RT5645_I2S_DF_I2S (0x0)
926#define RT5645_I2S_DF_LEFT (0x1)
927#define RT5645_I2S_DF_PCM_A (0x2)
928#define RT5645_I2S_DF_PCM_B (0x3)
929
930/* I2S2 Audio Serial Data Port Control (0x71) */
931#define RT5645_I2S2_SDI_MASK (0x1 << 6)
932#define RT5645_I2S2_SDI_SFT 6
933#define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
934#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
935
936/* ADC/DAC Clock Control 1 (0x73) */
937#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15)
938#define RT5645_I2S_BCLK_MS1_SFT 15
939#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15)
940#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15)
941#define RT5645_I2S_PD1_MASK (0x7 << 12)
942#define RT5645_I2S_PD1_SFT 12
943#define RT5645_I2S_PD1_1 (0x0 << 12)
944#define RT5645_I2S_PD1_2 (0x1 << 12)
945#define RT5645_I2S_PD1_3 (0x2 << 12)
946#define RT5645_I2S_PD1_4 (0x3 << 12)
947#define RT5645_I2S_PD1_6 (0x4 << 12)
948#define RT5645_I2S_PD1_8 (0x5 << 12)
949#define RT5645_I2S_PD1_12 (0x6 << 12)
950#define RT5645_I2S_PD1_16 (0x7 << 12)
951#define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
952#define RT5645_I2S_BCLK_MS2_SFT 11
953#define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
954#define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
955#define RT5645_I2S_PD2_MASK (0x7 << 8)
956#define RT5645_I2S_PD2_SFT 8
957#define RT5645_I2S_PD2_1 (0x0 << 8)
958#define RT5645_I2S_PD2_2 (0x1 << 8)
959#define RT5645_I2S_PD2_3 (0x2 << 8)
960#define RT5645_I2S_PD2_4 (0x3 << 8)
961#define RT5645_I2S_PD2_6 (0x4 << 8)
962#define RT5645_I2S_PD2_8 (0x5 << 8)
963#define RT5645_I2S_PD2_12 (0x6 << 8)
964#define RT5645_I2S_PD2_16 (0x7 << 8)
965#define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
966#define RT5645_I2S_BCLK_MS3_SFT 7
967#define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)
968#define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
969#define RT5645_I2S_PD3_MASK (0x7 << 4)
970#define RT5645_I2S_PD3_SFT 4
971#define RT5645_I2S_PD3_1 (0x0 << 4)
972#define RT5645_I2S_PD3_2 (0x1 << 4)
973#define RT5645_I2S_PD3_3 (0x2 << 4)
974#define RT5645_I2S_PD3_4 (0x3 << 4)
975#define RT5645_I2S_PD3_6 (0x4 << 4)
976#define RT5645_I2S_PD3_8 (0x5 << 4)
977#define RT5645_I2S_PD3_12 (0x6 << 4)
978#define RT5645_I2S_PD3_16 (0x7 << 4)
979#define RT5645_DAC_OSR_MASK (0x3 << 2)
980#define RT5645_DAC_OSR_SFT 2
981#define RT5645_DAC_OSR_128 (0x0 << 2)
982#define RT5645_DAC_OSR_64 (0x1 << 2)
983#define RT5645_DAC_OSR_32 (0x2 << 2)
984#define RT5645_DAC_OSR_16 (0x3 << 2)
985#define RT5645_ADC_OSR_MASK (0x3)
986#define RT5645_ADC_OSR_SFT 0
987#define RT5645_ADC_OSR_128 (0x0)
988#define RT5645_ADC_OSR_64 (0x1)
989#define RT5645_ADC_OSR_32 (0x2)
990#define RT5645_ADC_OSR_16 (0x3)
991
992/* ADC/DAC Clock Control 2 (0x74) */
993#define RT5645_DAC_L_OSR_MASK (0x3 << 14)
994#define RT5645_DAC_L_OSR_SFT 14
995#define RT5645_DAC_L_OSR_128 (0x0 << 14)
996#define RT5645_DAC_L_OSR_64 (0x1 << 14)
997#define RT5645_DAC_L_OSR_32 (0x2 << 14)
998#define RT5645_DAC_L_OSR_16 (0x3 << 14)
999#define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1000#define RT5645_ADC_R_OSR_SFT 12
1001#define RT5645_ADC_R_OSR_128 (0x0 << 12)
1002#define RT5645_ADC_R_OSR_64 (0x1 << 12)
1003#define RT5645_ADC_R_OSR_32 (0x2 << 12)
1004#define RT5645_ADC_R_OSR_16 (0x3 << 12)
1005#define RT5645_DAHPF_EN (0x1 << 11)
1006#define RT5645_DAHPF_EN_SFT 11
1007#define RT5645_ADHPF_EN (0x1 << 10)
1008#define RT5645_ADHPF_EN_SFT 10
1009
1010/* Digital Microphone Control (0x75) */
1011#define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1012#define RT5645_DMIC_1_EN_SFT 15
1013#define RT5645_DMIC_1_DIS (0x0 << 15)
1014#define RT5645_DMIC_1_EN (0x1 << 15)
1015#define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1016#define RT5645_DMIC_2_EN_SFT 14
1017#define RT5645_DMIC_2_DIS (0x0 << 14)
1018#define RT5645_DMIC_2_EN (0x1 << 14)
1019#define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1020#define RT5645_DMIC_1L_LH_SFT 13
1021#define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1022#define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1023#define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1024#define RT5645_DMIC_1R_LH_SFT 12
1025#define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1026#define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1027#define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1028#define RT5645_DMIC_2_DP_SFT 10
1029#define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1030#define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1031#define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1032#define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1033#define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1034#define RT5645_DMIC_2L_LH_SFT 9
1035#define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)
1036#define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1037#define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1038#define RT5645_DMIC_2R_LH_SFT 8
1039#define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1040#define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1041#define RT5645_DMIC_CLK_MASK (0x7 << 5)
1042#define RT5645_DMIC_CLK_SFT 5
1043#define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1044#define RT5645_DMIC_3_EN_SFT 4
1045#define RT5645_DMIC_3_DIS (0x0 << 4)
1046#define RT5645_DMIC_3_EN (0x1 << 4)
1047#define RT5645_DMIC_1_DP_MASK (0x3 << 0)
1048#define RT5645_DMIC_1_DP_SFT 0
1049#define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)
1050#define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1051#define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)
1052
1053/* TDM Control 1 (0x77) */
1054#define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1055#define RT5645_IF1_ADC_IN_SFT 8
1056
1057/* Global Clock Control (0x80) */
1058#define RT5645_SCLK_SRC_MASK (0x3 << 14)
1059#define RT5645_SCLK_SRC_SFT 14
1060#define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1061#define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1062#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
1063#define RT5645_PLL1_SRC_MASK (0x3 << 12)
1064#define RT5645_PLL1_SRC_SFT 12
1065#define RT5645_PLL1_SRC_MCLK (0x0 << 12)
1066#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12)
1067#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12)
1068#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12)
1069#define RT5645_PLL1_PD_MASK (0x1 << 3)
1070#define RT5645_PLL1_PD_SFT 3
1071#define RT5645_PLL1_PD_1 (0x0 << 3)
1072#define RT5645_PLL1_PD_2 (0x1 << 3)
1073
1074#define RT5645_PLL_INP_MAX 40000000
1075#define RT5645_PLL_INP_MIN 256000
1076/* PLL M/N/K Code Control 1 (0x81) */
1077#define RT5645_PLL_N_MAX 0x1ff
1078#define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)
1079#define RT5645_PLL_N_SFT 7
1080#define RT5645_PLL_K_MAX 0x1f
1081#define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)
1082#define RT5645_PLL_K_SFT 0
1083
1084/* PLL M/N/K Code Control 2 (0x82) */
1085#define RT5645_PLL_M_MAX 0xf
1086#define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1087#define RT5645_PLL_M_SFT 12
1088#define RT5645_PLL_M_BP (0x1 << 11)
1089#define RT5645_PLL_M_BP_SFT 11
1090
1091/* ASRC Control 1 (0x83) */
1092#define RT5645_STO_T_MASK (0x1 << 15)
1093#define RT5645_STO_T_SFT 15
1094#define RT5645_STO_T_SCLK (0x0 << 15)
1095#define RT5645_STO_T_LRCK1 (0x1 << 15)
1096#define RT5645_M1_T_MASK (0x1 << 14)
1097#define RT5645_M1_T_SFT 14
1098#define RT5645_M1_T_I2S2 (0x0 << 14)
1099#define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1100#define RT5645_I2S2_F_MASK (0x1 << 12)
1101#define RT5645_I2S2_F_SFT 12
1102#define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1103#define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1104#define RT5645_DMIC_1_M_MASK (0x1 << 9)
1105#define RT5645_DMIC_1_M_SFT 9
1106#define RT5645_DMIC_1_M_NOR (0x0 << 9)
1107#define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1108#define RT5645_DMIC_2_M_MASK (0x1 << 8)
1109#define RT5645_DMIC_2_M_SFT 8
1110#define RT5645_DMIC_2_M_NOR (0x0 << 8)
1111#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1112
1113/* ASRC Control 2 (0x84) */
1114#define RT5645_MDA_L_M_MASK (0x1 << 15)
1115#define RT5645_MDA_L_M_SFT 15
1116#define RT5645_MDA_L_M_NOR (0x0 << 15)
1117#define RT5645_MDA_L_M_ASYN (0x1 << 15)
1118#define RT5645_MDA_R_M_MASK (0x1 << 14)
1119#define RT5645_MDA_R_M_SFT 14
1120#define RT5645_MDA_R_M_NOR (0x0 << 14)
1121#define RT5645_MDA_R_M_ASYN (0x1 << 14)
1122#define RT5645_MAD_L_M_MASK (0x1 << 13)
1123#define RT5645_MAD_L_M_SFT 13
1124#define RT5645_MAD_L_M_NOR (0x0 << 13)
1125#define RT5645_MAD_L_M_ASYN (0x1 << 13)
1126#define RT5645_MAD_R_M_MASK (0x1 << 12)
1127#define RT5645_MAD_R_M_SFT 12
1128#define RT5645_MAD_R_M_NOR (0x0 << 12)
1129#define RT5645_MAD_R_M_ASYN (0x1 << 12)
1130#define RT5645_ADC_M_MASK (0x1 << 11)
1131#define RT5645_ADC_M_SFT 11
1132#define RT5645_ADC_M_NOR (0x0 << 11)
1133#define RT5645_ADC_M_ASYN (0x1 << 11)
1134#define RT5645_STO_DAC_M_MASK (0x1 << 5)
1135#define RT5645_STO_DAC_M_SFT 5
1136#define RT5645_STO_DAC_M_NOR (0x0 << 5)
1137#define RT5645_STO_DAC_M_ASYN (0x1 << 5)
1138#define RT5645_I2S1_R_D_MASK (0x1 << 4)
1139#define RT5645_I2S1_R_D_SFT 4
1140#define RT5645_I2S1_R_D_DIS (0x0 << 4)
1141#define RT5645_I2S1_R_D_EN (0x1 << 4)
1142#define RT5645_I2S2_R_D_MASK (0x1 << 3)
1143#define RT5645_I2S2_R_D_SFT 3
1144#define RT5645_I2S2_R_D_DIS (0x0 << 3)
1145#define RT5645_I2S2_R_D_EN (0x1 << 3)
1146#define RT5645_PRE_SCLK_MASK (0x3)
1147#define RT5645_PRE_SCLK_SFT 0
1148#define RT5645_PRE_SCLK_512 (0x0)
1149#define RT5645_PRE_SCLK_1024 (0x1)
1150#define RT5645_PRE_SCLK_2048 (0x2)
1151
1152/* ASRC Control 3 (0x85) */
1153#define RT5645_I2S1_RATE_MASK (0xf << 12)
1154#define RT5645_I2S1_RATE_SFT 12
1155#define RT5645_I2S2_RATE_MASK (0xf << 8)
1156#define RT5645_I2S2_RATE_SFT 8
1157
1158/* ASRC Control 4 (0x89) */
1159#define RT5645_I2S1_PD_MASK (0x7 << 12)
1160#define RT5645_I2S1_PD_SFT 12
1161#define RT5645_I2S2_PD_MASK (0x7 << 8)
1162#define RT5645_I2S2_PD_SFT 8
1163
1164/* HPOUT Over Current Detection (0x8b) */
1165#define RT5645_HP_OVCD_MASK (0x1 << 10)
1166#define RT5645_HP_OVCD_SFT 10
1167#define RT5645_HP_OVCD_DIS (0x0 << 10)
1168#define RT5645_HP_OVCD_EN (0x1 << 10)
1169#define RT5645_HP_OC_TH_MASK (0x3 << 8)
1170#define RT5645_HP_OC_TH_SFT 8
1171#define RT5645_HP_OC_TH_90 (0x0 << 8)
1172#define RT5645_HP_OC_TH_105 (0x1 << 8)
1173#define RT5645_HP_OC_TH_120 (0x2 << 8)
1174#define RT5645_HP_OC_TH_135 (0x3 << 8)
1175
1176/* Class D Over Current Control (0x8c) */
1177#define RT5645_CLSD_OC_MASK (0x1 << 9)
1178#define RT5645_CLSD_OC_SFT 9
1179#define RT5645_CLSD_OC_PU (0x0 << 9)
1180#define RT5645_CLSD_OC_PD (0x1 << 9)
1181#define RT5645_AUTO_PD_MASK (0x1 << 8)
1182#define RT5645_AUTO_PD_SFT 8
1183#define RT5645_AUTO_PD_DIS (0x0 << 8)
1184#define RT5645_AUTO_PD_EN (0x1 << 8)
1185#define RT5645_CLSD_OC_TH_MASK (0x3f)
1186#define RT5645_CLSD_OC_TH_SFT 0
1187
1188/* Class D Output Control (0x8d) */
1189#define RT5645_CLSD_RATIO_MASK (0xf << 12)
1190#define RT5645_CLSD_RATIO_SFT 12
1191#define RT5645_CLSD_OM_MASK (0x1 << 11)
1192#define RT5645_CLSD_OM_SFT 11
1193#define RT5645_CLSD_OM_MONO (0x0 << 11)
1194#define RT5645_CLSD_OM_STO (0x1 << 11)
1195#define RT5645_CLSD_SCH_MASK (0x1 << 10)
1196#define RT5645_CLSD_SCH_SFT 10
1197#define RT5645_CLSD_SCH_L (0x0 << 10)
1198#define RT5645_CLSD_SCH_S (0x1 << 10)
1199
1200/* Depop Mode Control 1 (0x8e) */
1201#define RT5645_SMT_TRIG_MASK (0x1 << 15)
1202#define RT5645_SMT_TRIG_SFT 15
1203#define RT5645_SMT_TRIG_DIS (0x0 << 15)
1204#define RT5645_SMT_TRIG_EN (0x1 << 15)
1205#define RT5645_HP_L_SMT_MASK (0x1 << 9)
1206#define RT5645_HP_L_SMT_SFT 9
1207#define RT5645_HP_L_SMT_DIS (0x0 << 9)
1208#define RT5645_HP_L_SMT_EN (0x1 << 9)
1209#define RT5645_HP_R_SMT_MASK (0x1 << 8)
1210#define RT5645_HP_R_SMT_SFT 8
1211#define RT5645_HP_R_SMT_DIS (0x0 << 8)
1212#define RT5645_HP_R_SMT_EN (0x1 << 8)
1213#define RT5645_HP_CD_PD_MASK (0x1 << 7)
1214#define RT5645_HP_CD_PD_SFT 7
1215#define RT5645_HP_CD_PD_DIS (0x0 << 7)
1216#define RT5645_HP_CD_PD_EN (0x1 << 7)
1217#define RT5645_RSTN_MASK (0x1 << 6)
1218#define RT5645_RSTN_SFT 6
1219#define RT5645_RSTN_DIS (0x0 << 6)
1220#define RT5645_RSTN_EN (0x1 << 6)
1221#define RT5645_RSTP_MASK (0x1 << 5)
1222#define RT5645_RSTP_SFT 5
1223#define RT5645_RSTP_DIS (0x0 << 5)
1224#define RT5645_RSTP_EN (0x1 << 5)
1225#define RT5645_HP_CO_MASK (0x1 << 4)
1226#define RT5645_HP_CO_SFT 4
1227#define RT5645_HP_CO_DIS (0x0 << 4)
1228#define RT5645_HP_CO_EN (0x1 << 4)
1229#define RT5645_HP_CP_MASK (0x1 << 3)
1230#define RT5645_HP_CP_SFT 3
1231#define RT5645_HP_CP_PD (0x0 << 3)
1232#define RT5645_HP_CP_PU (0x1 << 3)
1233#define RT5645_HP_SG_MASK (0x1 << 2)
1234#define RT5645_HP_SG_SFT 2
1235#define RT5645_HP_SG_DIS (0x0 << 2)
1236#define RT5645_HP_SG_EN (0x1 << 2)
1237#define RT5645_HP_DP_MASK (0x1 << 1)
1238#define RT5645_HP_DP_SFT 1
1239#define RT5645_HP_DP_PD (0x0 << 1)
1240#define RT5645_HP_DP_PU (0x1 << 1)
1241#define RT5645_HP_CB_MASK (0x1)
1242#define RT5645_HP_CB_SFT 0
1243#define RT5645_HP_CB_PD (0x0)
1244#define RT5645_HP_CB_PU (0x1)
1245
1246/* Depop Mode Control 2 (0x8f) */
1247#define RT5645_DEPOP_MASK (0x1 << 13)
1248#define RT5645_DEPOP_SFT 13
1249#define RT5645_DEPOP_AUTO (0x0 << 13)
1250#define RT5645_DEPOP_MAN (0x1 << 13)
1251#define RT5645_RAMP_MASK (0x1 << 12)
1252#define RT5645_RAMP_SFT 12
1253#define RT5645_RAMP_DIS (0x0 << 12)
1254#define RT5645_RAMP_EN (0x1 << 12)
1255#define RT5645_BPS_MASK (0x1 << 11)
1256#define RT5645_BPS_SFT 11
1257#define RT5645_BPS_DIS (0x0 << 11)
1258#define RT5645_BPS_EN (0x1 << 11)
1259#define RT5645_FAST_UPDN_MASK (0x1 << 10)
1260#define RT5645_FAST_UPDN_SFT 10
1261#define RT5645_FAST_UPDN_DIS (0x0 << 10)
1262#define RT5645_FAST_UPDN_EN (0x1 << 10)
1263#define RT5645_MRES_MASK (0x3 << 8)
1264#define RT5645_MRES_SFT 8
1265#define RT5645_MRES_15MO (0x0 << 8)
1266#define RT5645_MRES_25MO (0x1 << 8)
1267#define RT5645_MRES_35MO (0x2 << 8)
1268#define RT5645_MRES_45MO (0x3 << 8)
1269#define RT5645_VLO_MASK (0x1 << 7)
1270#define RT5645_VLO_SFT 7
1271#define RT5645_VLO_3V (0x0 << 7)
1272#define RT5645_VLO_32V (0x1 << 7)
1273#define RT5645_DIG_DP_MASK (0x1 << 6)
1274#define RT5645_DIG_DP_SFT 6
1275#define RT5645_DIG_DP_DIS (0x0 << 6)
1276#define RT5645_DIG_DP_EN (0x1 << 6)
1277#define RT5645_DP_TH_MASK (0x3 << 4)
1278#define RT5645_DP_TH_SFT 4
1279
1280/* Depop Mode Control 3 (0x90) */
1281#define RT5645_CP_SYS_MASK (0x7 << 12)
1282#define RT5645_CP_SYS_SFT 12
1283#define RT5645_CP_FQ1_MASK (0x7 << 8)
1284#define RT5645_CP_FQ1_SFT 8
1285#define RT5645_CP_FQ2_MASK (0x7 << 4)
1286#define RT5645_CP_FQ2_SFT 4
1287#define RT5645_CP_FQ3_MASK (0x7)
1288#define RT5645_CP_FQ3_SFT 0
1289#define RT5645_CP_FQ_1_5_KHZ 0
1290#define RT5645_CP_FQ_3_KHZ 1
1291#define RT5645_CP_FQ_6_KHZ 2
1292#define RT5645_CP_FQ_12_KHZ 3
1293#define RT5645_CP_FQ_24_KHZ 4
1294#define RT5645_CP_FQ_48_KHZ 5
1295#define RT5645_CP_FQ_96_KHZ 6
1296#define RT5645_CP_FQ_192_KHZ 7
1297
1298/* PV detection and SPK gain control (0x92) */
1299#define RT5645_PVDD_DET_MASK (0x1 << 15)
1300#define RT5645_PVDD_DET_SFT 15
1301#define RT5645_PVDD_DET_DIS (0x0 << 15)
1302#define RT5645_PVDD_DET_EN (0x1 << 15)
1303#define RT5645_SPK_AG_MASK (0x1 << 14)
1304#define RT5645_SPK_AG_SFT 14
1305#define RT5645_SPK_AG_DIS (0x0 << 14)
1306#define RT5645_SPK_AG_EN (0x1 << 14)
1307
1308/* Micbias Control (0x93) */
1309#define RT5645_MIC1_BS_MASK (0x1 << 15)
1310#define RT5645_MIC1_BS_SFT 15
1311#define RT5645_MIC1_BS_9AV (0x0 << 15)
1312#define RT5645_MIC1_BS_75AV (0x1 << 15)
1313#define RT5645_MIC2_BS_MASK (0x1 << 14)
1314#define RT5645_MIC2_BS_SFT 14
1315#define RT5645_MIC2_BS_9AV (0x0 << 14)
1316#define RT5645_MIC2_BS_75AV (0x1 << 14)
1317#define RT5645_MIC1_CLK_MASK (0x1 << 13)
1318#define RT5645_MIC1_CLK_SFT 13
1319#define RT5645_MIC1_CLK_DIS (0x0 << 13)
1320#define RT5645_MIC1_CLK_EN (0x1 << 13)
1321#define RT5645_MIC2_CLK_MASK (0x1 << 12)
1322#define RT5645_MIC2_CLK_SFT 12
1323#define RT5645_MIC2_CLK_DIS (0x0 << 12)
1324#define RT5645_MIC2_CLK_EN (0x1 << 12)
1325#define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1326#define RT5645_MIC1_OVCD_SFT 11
1327#define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1328#define RT5645_MIC1_OVCD_EN (0x1 << 11)
1329#define RT5645_MIC1_OVTH_MASK (0x3 << 9)
1330#define RT5645_MIC1_OVTH_SFT 9
1331#define RT5645_MIC1_OVTH_600UA (0x0 << 9)
1332#define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1333#define RT5645_MIC1_OVTH_2000UA (0x2 << 9)
1334#define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1335#define RT5645_MIC2_OVCD_SFT 8
1336#define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1337#define RT5645_MIC2_OVCD_EN (0x1 << 8)
1338#define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1339#define RT5645_MIC2_OVTH_SFT 6
1340#define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1341#define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1342#define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1343#define RT5645_PWR_MB_MASK (0x1 << 5)
1344#define RT5645_PWR_MB_SFT 5
1345#define RT5645_PWR_MB_PD (0x0 << 5)
1346#define RT5645_PWR_MB_PU (0x1 << 5)
1347#define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1348#define RT5645_PWR_CLK25M_SFT 4
1349#define RT5645_PWR_CLK25M_PD (0x0 << 4)
1350#define RT5645_PWR_CLK25M_PU (0x1 << 4)
1351
1352/* VAD Control 4 (0x9d) */
1353#define RT5645_VAD_SEL_MASK (0x3 << 8)
1354#define RT5645_VAD_SEL_SFT 8
1355
1356/* EQ Control 1 (0xb0) */
1357#define RT5645_EQ_SRC_MASK (0x1 << 15)
1358#define RT5645_EQ_SRC_SFT 15
1359#define RT5645_EQ_SRC_DAC (0x0 << 15)
1360#define RT5645_EQ_SRC_ADC (0x1 << 15)
1361#define RT5645_EQ_UPD (0x1 << 14)
1362#define RT5645_EQ_UPD_BIT 14
1363#define RT5645_EQ_CD_MASK (0x1 << 13)
1364#define RT5645_EQ_CD_SFT 13
1365#define RT5645_EQ_CD_DIS (0x0 << 13)
1366#define RT5645_EQ_CD_EN (0x1 << 13)
1367#define RT5645_EQ_DITH_MASK (0x3 << 8)
1368#define RT5645_EQ_DITH_SFT 8
1369#define RT5645_EQ_DITH_NOR (0x0 << 8)
1370#define RT5645_EQ_DITH_LSB (0x1 << 8)
1371#define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1372#define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1373
1374/* EQ Control 2 (0xb1) */
1375#define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1376#define RT5645_EQ_HPF1_M_SFT 8
1377#define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1378#define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1379#define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1380#define RT5645_EQ_LPF1_M_SFT 7
1381#define RT5645_EQ_LPF1_M_LO (0x0 << 7)
1382#define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1383#define RT5645_EQ_HPF2_MASK (0x1 << 6)
1384#define RT5645_EQ_HPF2_SFT 6
1385#define RT5645_EQ_HPF2_DIS (0x0 << 6)
1386#define RT5645_EQ_HPF2_EN (0x1 << 6)
1387#define RT5645_EQ_HPF1_MASK (0x1 << 5)
1388#define RT5645_EQ_HPF1_SFT 5
1389#define RT5645_EQ_HPF1_DIS (0x0 << 5)
1390#define RT5645_EQ_HPF1_EN (0x1 << 5)
1391#define RT5645_EQ_BPF4_MASK (0x1 << 4)
1392#define RT5645_EQ_BPF4_SFT 4
1393#define RT5645_EQ_BPF4_DIS (0x0 << 4)
1394#define RT5645_EQ_BPF4_EN (0x1 << 4)
1395#define RT5645_EQ_BPF3_MASK (0x1 << 3)
1396#define RT5645_EQ_BPF3_SFT 3
1397#define RT5645_EQ_BPF3_DIS (0x0 << 3)
1398#define RT5645_EQ_BPF3_EN (0x1 << 3)
1399#define RT5645_EQ_BPF2_MASK (0x1 << 2)
1400#define RT5645_EQ_BPF2_SFT 2
1401#define RT5645_EQ_BPF2_DIS (0x0 << 2)
1402#define RT5645_EQ_BPF2_EN (0x1 << 2)
1403#define RT5645_EQ_BPF1_MASK (0x1 << 1)
1404#define RT5645_EQ_BPF1_SFT 1
1405#define RT5645_EQ_BPF1_DIS (0x0 << 1)
1406#define RT5645_EQ_BPF1_EN (0x1 << 1)
1407#define RT5645_EQ_LPF_MASK (0x1)
1408#define RT5645_EQ_LPF_SFT 0
1409#define RT5645_EQ_LPF_DIS (0x0)
1410#define RT5645_EQ_LPF_EN (0x1)
1411#define RT5645_EQ_CTRL_MASK (0x7f)
1412
1413/* Memory Test (0xb2) */
1414#define RT5645_MT_MASK (0x1 << 15)
1415#define RT5645_MT_SFT 15
1416#define RT5645_MT_DIS (0x0 << 15)
1417#define RT5645_MT_EN (0x1 << 15)
1418
1419/* DRC/AGC Control 1 (0xb4) */
1420#define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1421#define RT5645_DRC_AGC_P_SFT 15
1422#define RT5645_DRC_AGC_P_DAC (0x0 << 15)
1423#define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1424#define RT5645_DRC_AGC_MASK (0x1 << 14)
1425#define RT5645_DRC_AGC_SFT 14
1426#define RT5645_DRC_AGC_DIS (0x0 << 14)
1427#define RT5645_DRC_AGC_EN (0x1 << 14)
1428#define RT5645_DRC_AGC_UPD (0x1 << 13)
1429#define RT5645_DRC_AGC_UPD_BIT 13
1430#define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1431#define RT5645_DRC_AGC_AR_SFT 8
1432#define RT5645_DRC_AGC_R_MASK (0x7 << 5)
1433#define RT5645_DRC_AGC_R_SFT 5
1434#define RT5645_DRC_AGC_R_48K (0x1 << 5)
1435#define RT5645_DRC_AGC_R_96K (0x2 << 5)
1436#define RT5645_DRC_AGC_R_192K (0x3 << 5)
1437#define RT5645_DRC_AGC_R_441K (0x5 << 5)
1438#define RT5645_DRC_AGC_R_882K (0x6 << 5)
1439#define RT5645_DRC_AGC_R_1764K (0x7 << 5)
1440#define RT5645_DRC_AGC_RC_MASK (0x1f)
1441#define RT5645_DRC_AGC_RC_SFT 0
1442
1443/* DRC/AGC Control 2 (0xb5) */
1444#define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1445#define RT5645_DRC_AGC_POB_SFT 8
1446#define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1447#define RT5645_DRC_AGC_CP_SFT 7
1448#define RT5645_DRC_AGC_CP_DIS (0x0 << 7)
1449#define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1450#define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)
1451#define RT5645_DRC_AGC_CPR_SFT 5
1452#define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)
1453#define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1454#define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)
1455#define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)
1456#define RT5645_DRC_AGC_PRB_MASK (0x1f)
1457#define RT5645_DRC_AGC_PRB_SFT 0
1458
1459/* DRC/AGC Control 3 (0xb6) */
1460#define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1461#define RT5645_DRC_AGC_NGB_SFT 12
1462#define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)
1463#define RT5645_DRC_AGC_TAR_SFT 7
1464#define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1465#define RT5645_DRC_AGC_NG_SFT 6
1466#define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1467#define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1468#define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1469#define RT5645_DRC_AGC_NGH_SFT 5
1470#define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)
1471#define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1472#define RT5645_DRC_AGC_NGT_MASK (0x1f)
1473#define RT5645_DRC_AGC_NGT_SFT 0
1474
1475/* ANC Control 1 (0xb8) */
1476#define RT5645_ANC_M_MASK (0x1 << 15)
1477#define RT5645_ANC_M_SFT 15
1478#define RT5645_ANC_M_NOR (0x0 << 15)
1479#define RT5645_ANC_M_REV (0x1 << 15)
1480#define RT5645_ANC_MASK (0x1 << 14)
1481#define RT5645_ANC_SFT 14
1482#define RT5645_ANC_DIS (0x0 << 14)
1483#define RT5645_ANC_EN (0x1 << 14)
1484#define RT5645_ANC_MD_MASK (0x3 << 12)
1485#define RT5645_ANC_MD_SFT 12
1486#define RT5645_ANC_MD_DIS (0x0 << 12)
1487#define RT5645_ANC_MD_67MS (0x1 << 12)
1488#define RT5645_ANC_MD_267MS (0x2 << 12)
1489#define RT5645_ANC_MD_1067MS (0x3 << 12)
1490#define RT5645_ANC_SN_MASK (0x1 << 11)
1491#define RT5645_ANC_SN_SFT 11
1492#define RT5645_ANC_SN_DIS (0x0 << 11)
1493#define RT5645_ANC_SN_EN (0x1 << 11)
1494#define RT5645_ANC_CLK_MASK (0x1 << 10)
1495#define RT5645_ANC_CLK_SFT 10
1496#define RT5645_ANC_CLK_ANC (0x0 << 10)
1497#define RT5645_ANC_CLK_REG (0x1 << 10)
1498#define RT5645_ANC_ZCD_MASK (0x3 << 8)
1499#define RT5645_ANC_ZCD_SFT 8
1500#define RT5645_ANC_ZCD_DIS (0x0 << 8)
1501#define RT5645_ANC_ZCD_T1 (0x1 << 8)
1502#define RT5645_ANC_ZCD_T2 (0x2 << 8)
1503#define RT5645_ANC_ZCD_WT (0x3 << 8)
1504#define RT5645_ANC_CS_MASK (0x1 << 7)
1505#define RT5645_ANC_CS_SFT 7
1506#define RT5645_ANC_CS_DIS (0x0 << 7)
1507#define RT5645_ANC_CS_EN (0x1 << 7)
1508#define RT5645_ANC_SW_MASK (0x1 << 6)
1509#define RT5645_ANC_SW_SFT 6
1510#define RT5645_ANC_SW_NOR (0x0 << 6)
1511#define RT5645_ANC_SW_AUTO (0x1 << 6)
1512#define RT5645_ANC_CO_L_MASK (0x3f)
1513#define RT5645_ANC_CO_L_SFT 0
1514
1515/* ANC Control 2 (0xb6) */
1516#define RT5645_ANC_FG_R_MASK (0xf << 12)
1517#define RT5645_ANC_FG_R_SFT 12
1518#define RT5645_ANC_FG_L_MASK (0xf << 8)
1519#define RT5645_ANC_FG_L_SFT 8
1520#define RT5645_ANC_CG_R_MASK (0xf << 4)
1521#define RT5645_ANC_CG_R_SFT 4
1522#define RT5645_ANC_CG_L_MASK (0xf)
1523#define RT5645_ANC_CG_L_SFT 0
1524
1525/* ANC Control 3 (0xb6) */
1526#define RT5645_ANC_CD_MASK (0x1 << 6)
1527#define RT5645_ANC_CD_SFT 6
1528#define RT5645_ANC_CD_BOTH (0x0 << 6)
1529#define RT5645_ANC_CD_IND (0x1 << 6)
1530#define RT5645_ANC_CO_R_MASK (0x3f)
1531#define RT5645_ANC_CO_R_SFT 0
1532
1533/* Jack Detect Control (0xbb) */
1534#define RT5645_JD_MASK (0x7 << 13)
1535#define RT5645_JD_SFT 13
1536#define RT5645_JD_DIS (0x0 << 13)
1537#define RT5645_JD_GPIO1 (0x1 << 13)
1538#define RT5645_JD_JD1_IN4P (0x2 << 13)
1539#define RT5645_JD_JD2_IN4N (0x3 << 13)
1540#define RT5645_JD_GPIO2 (0x4 << 13)
1541#define RT5645_JD_GPIO3 (0x5 << 13)
1542#define RT5645_JD_GPIO4 (0x6 << 13)
1543#define RT5645_JD_HP_MASK (0x1 << 11)
1544#define RT5645_JD_HP_SFT 11
1545#define RT5645_JD_HP_DIS (0x0 << 11)
1546#define RT5645_JD_HP_EN (0x1 << 11)
1547#define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1548#define RT5645_JD_HP_TRG_SFT 10
1549#define RT5645_JD_HP_TRG_LO (0x0 << 10)
1550#define RT5645_JD_HP_TRG_HI (0x1 << 10)
1551#define RT5645_JD_SPL_MASK (0x1 << 9)
1552#define RT5645_JD_SPL_SFT 9
1553#define RT5645_JD_SPL_DIS (0x0 << 9)
1554#define RT5645_JD_SPL_EN (0x1 << 9)
1555#define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1556#define RT5645_JD_SPL_TRG_SFT 8
1557#define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1558#define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1559#define RT5645_JD_SPR_MASK (0x1 << 7)
1560#define RT5645_JD_SPR_SFT 7
1561#define RT5645_JD_SPR_DIS (0x0 << 7)
1562#define RT5645_JD_SPR_EN (0x1 << 7)
1563#define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1564#define RT5645_JD_SPR_TRG_SFT 6
1565#define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1566#define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1567#define RT5645_JD_MO_MASK (0x1 << 5)
1568#define RT5645_JD_MO_SFT 5
1569#define RT5645_JD_MO_DIS (0x0 << 5)
1570#define RT5645_JD_MO_EN (0x1 << 5)
1571#define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1572#define RT5645_JD_MO_TRG_SFT 4
1573#define RT5645_JD_MO_TRG_LO (0x0 << 4)
1574#define RT5645_JD_MO_TRG_HI (0x1 << 4)
1575#define RT5645_JD_LO_MASK (0x1 << 3)
1576#define RT5645_JD_LO_SFT 3
1577#define RT5645_JD_LO_DIS (0x0 << 3)
1578#define RT5645_JD_LO_EN (0x1 << 3)
1579#define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1580#define RT5645_JD_LO_TRG_SFT 2
1581#define RT5645_JD_LO_TRG_LO (0x0 << 2)
1582#define RT5645_JD_LO_TRG_HI (0x1 << 2)
1583#define RT5645_JD1_IN4P_MASK (0x1 << 1)
1584#define RT5645_JD1_IN4P_SFT 1
1585#define RT5645_JD1_IN4P_DIS (0x0 << 1)
1586#define RT5645_JD1_IN4P_EN (0x1 << 1)
1587#define RT5645_JD2_IN4N_MASK (0x1)
1588#define RT5645_JD2_IN4N_SFT 0
1589#define RT5645_JD2_IN4N_DIS (0x0)
1590#define RT5645_JD2_IN4N_EN (0x1)
1591
1592/* Jack detect for ANC (0xbc) */
1593#define RT5645_ANC_DET_MASK (0x3 << 4)
1594#define RT5645_ANC_DET_SFT 4
1595#define RT5645_ANC_DET_DIS (0x0 << 4)
1596#define RT5645_ANC_DET_MB1 (0x1 << 4)
1597#define RT5645_ANC_DET_MB2 (0x2 << 4)
1598#define RT5645_ANC_DET_JD (0x3 << 4)
1599#define RT5645_AD_TRG_MASK (0x1 << 3)
1600#define RT5645_AD_TRG_SFT 3
1601#define RT5645_AD_TRG_LO (0x0 << 3)
1602#define RT5645_AD_TRG_HI (0x1 << 3)
1603#define RT5645_ANCM_DET_MASK (0x3 << 4)
1604#define RT5645_ANCM_DET_SFT 4
1605#define RT5645_ANCM_DET_DIS (0x0 << 4)
1606#define RT5645_ANCM_DET_MB1 (0x1 << 4)
1607#define RT5645_ANCM_DET_MB2 (0x2 << 4)
1608#define RT5645_ANCM_DET_JD (0x3 << 4)
1609#define RT5645_AMD_TRG_MASK (0x1 << 3)
1610#define RT5645_AMD_TRG_SFT 3
1611#define RT5645_AMD_TRG_LO (0x0 << 3)
1612#define RT5645_AMD_TRG_HI (0x1 << 3)
1613
1614/* IRQ Control 1 (0xbd) */
1615#define RT5645_IRQ_JD_MASK (0x1 << 15)
1616#define RT5645_IRQ_JD_SFT 15
1617#define RT5645_IRQ_JD_BP (0x0 << 15)
1618#define RT5645_IRQ_JD_NOR (0x1 << 15)
1619#define RT5645_IRQ_OT_MASK (0x1 << 14)
1620#define RT5645_IRQ_OT_SFT 14
1621#define RT5645_IRQ_OT_BP (0x0 << 14)
1622#define RT5645_IRQ_OT_NOR (0x1 << 14)
1623#define RT5645_JD_STKY_MASK (0x1 << 13)
1624#define RT5645_JD_STKY_SFT 13
1625#define RT5645_JD_STKY_DIS (0x0 << 13)
1626#define RT5645_JD_STKY_EN (0x1 << 13)
1627#define RT5645_OT_STKY_MASK (0x1 << 12)
1628#define RT5645_OT_STKY_SFT 12
1629#define RT5645_OT_STKY_DIS (0x0 << 12)
1630#define RT5645_OT_STKY_EN (0x1 << 12)
1631#define RT5645_JD_P_MASK (0x1 << 11)
1632#define RT5645_JD_P_SFT 11
1633#define RT5645_JD_P_NOR (0x0 << 11)
1634#define RT5645_JD_P_INV (0x1 << 11)
1635#define RT5645_OT_P_MASK (0x1 << 10)
1636#define RT5645_OT_P_SFT 10
1637#define RT5645_OT_P_NOR (0x0 << 10)
1638#define RT5645_OT_P_INV (0x1 << 10)
1639
1640/* IRQ Control 2 (0xbe) */
1641#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1642#define RT5645_IRQ_MB1_OC_SFT 15
1643#define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
1644#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1645#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1646#define RT5645_IRQ_MB2_OC_SFT 14
1647#define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1648#define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1649#define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1650#define RT5645_MB1_OC_STKY_SFT 13
1651#define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1652#define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1653#define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1654#define RT5645_MB2_OC_STKY_SFT 12
1655#define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1656#define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1657#define RT5645_MB1_OC_P_MASK (0x1 << 7)
1658#define RT5645_MB1_OC_P_SFT 7
1659#define RT5645_MB1_OC_P_NOR (0x0 << 7)
1660#define RT5645_MB1_OC_P_INV (0x1 << 7)
1661#define RT5645_MB2_OC_P_MASK (0x1 << 6)
1662#define RT5645_MB2_OC_P_SFT 6
1663#define RT5645_MB2_OC_P_NOR (0x0 << 6)
1664#define RT5645_MB2_OC_P_INV (0x1 << 6)
1665#define RT5645_MB1_OC_CLR (0x1 << 3)
1666#define RT5645_MB1_OC_CLR_SFT 3
1667#define RT5645_MB2_OC_CLR (0x1 << 2)
1668#define RT5645_MB2_OC_CLR_SFT 2
1669
1670/* GPIO Control 1 (0xc0) */
1671#define RT5645_GP1_PIN_MASK (0x1 << 15)
1672#define RT5645_GP1_PIN_SFT 15
1673#define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
1674#define RT5645_GP1_PIN_IRQ (0x1 << 15)
1675#define RT5645_GP2_PIN_MASK (0x1 << 14)
1676#define RT5645_GP2_PIN_SFT 14
1677#define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1678#define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1679#define RT5645_GP3_PIN_MASK (0x3 << 12)
1680#define RT5645_GP3_PIN_SFT 12
1681#define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1682#define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1683#define RT5645_GP3_PIN_IRQ (0x2 << 12)
1684#define RT5645_GP4_PIN_MASK (0x1 << 11)
1685#define RT5645_GP4_PIN_SFT 11
1686#define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1687#define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1688#define RT5645_DP_SIG_MASK (0x1 << 10)
1689#define RT5645_DP_SIG_SFT 10
1690#define RT5645_DP_SIG_TEST (0x0 << 10)
1691#define RT5645_DP_SIG_AP (0x1 << 10)
1692#define RT5645_GPIO_M_MASK (0x1 << 9)
1693#define RT5645_GPIO_M_SFT 9
1694#define RT5645_GPIO_M_FLT (0x0 << 9)
1695#define RT5645_GPIO_M_PH (0x1 << 9)
1696#define RT5645_I2S2_SEL (0x1 << 8)
1697#define RT5645_I2S2_SEL_SFT 8
1698#define RT5645_GP5_PIN_MASK (0x1 << 7)
1699#define RT5645_GP5_PIN_SFT 7
1700#define RT5645_GP5_PIN_GPIO5 (0x0 << 7)
1701#define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1702#define RT5645_GP6_PIN_MASK (0x1 << 6)
1703#define RT5645_GP6_PIN_SFT 6
1704#define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1705#define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1706#define RT5645_GP8_PIN_MASK (0x1 << 3)
1707#define RT5645_GP8_PIN_SFT 3
1708#define RT5645_GP8_PIN_GPIO8 (0x0 << 3)
1709#define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1710#define RT5645_GP12_PIN_MASK (0x1 << 2)
1711#define RT5645_GP12_PIN_SFT 2
1712#define RT5645_GP12_PIN_GPIO12 (0x0 << 2)
1713#define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1714#define RT5645_GP11_PIN_MASK (0x1 << 1)
1715#define RT5645_GP11_PIN_SFT 1
1716#define RT5645_GP11_PIN_GPIO11 (0x0 << 1)
1717#define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1718#define RT5645_GP10_PIN_MASK (0x1)
1719#define RT5645_GP10_PIN_SFT 0
1720#define RT5645_GP10_PIN_GPIO10 (0x0)
1721#define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1722
1723/* GPIO Control 3 (0xc2) */
1724#define RT5645_GP4_PF_MASK (0x1 << 11)
1725#define RT5645_GP4_PF_SFT 11
1726#define RT5645_GP4_PF_IN (0x0 << 11)
1727#define RT5645_GP4_PF_OUT (0x1 << 11)
1728#define RT5645_GP4_OUT_MASK (0x1 << 10)
1729#define RT5645_GP4_OUT_SFT 10
1730#define RT5645_GP4_OUT_LO (0x0 << 10)
1731#define RT5645_GP4_OUT_HI (0x1 << 10)
1732#define RT5645_GP4_P_MASK (0x1 << 9)
1733#define RT5645_GP4_P_SFT 9
1734#define RT5645_GP4_P_NOR (0x0 << 9)
1735#define RT5645_GP4_P_INV (0x1 << 9)
1736#define RT5645_GP3_PF_MASK (0x1 << 8)
1737#define RT5645_GP3_PF_SFT 8
1738#define RT5645_GP3_PF_IN (0x0 << 8)
1739#define RT5645_GP3_PF_OUT (0x1 << 8)
1740#define RT5645_GP3_OUT_MASK (0x1 << 7)
1741#define RT5645_GP3_OUT_SFT 7
1742#define RT5645_GP3_OUT_LO (0x0 << 7)
1743#define RT5645_GP3_OUT_HI (0x1 << 7)
1744#define RT5645_GP3_P_MASK (0x1 << 6)
1745#define RT5645_GP3_P_SFT 6
1746#define RT5645_GP3_P_NOR (0x0 << 6)
1747#define RT5645_GP3_P_INV (0x1 << 6)
1748#define RT5645_GP2_PF_MASK (0x1 << 5)
1749#define RT5645_GP2_PF_SFT 5
1750#define RT5645_GP2_PF_IN (0x0 << 5)
1751#define RT5645_GP2_PF_OUT (0x1 << 5)
1752#define RT5645_GP2_OUT_MASK (0x1 << 4)
1753#define RT5645_GP2_OUT_SFT 4
1754#define RT5645_GP2_OUT_LO (0x0 << 4)
1755#define RT5645_GP2_OUT_HI (0x1 << 4)
1756#define RT5645_GP2_P_MASK (0x1 << 3)
1757#define RT5645_GP2_P_SFT 3
1758#define RT5645_GP2_P_NOR (0x0 << 3)
1759#define RT5645_GP2_P_INV (0x1 << 3)
1760#define RT5645_GP1_PF_MASK (0x1 << 2)
1761#define RT5645_GP1_PF_SFT 2
1762#define RT5645_GP1_PF_IN (0x0 << 2)
1763#define RT5645_GP1_PF_OUT (0x1 << 2)
1764#define RT5645_GP1_OUT_MASK (0x1 << 1)
1765#define RT5645_GP1_OUT_SFT 1
1766#define RT5645_GP1_OUT_LO (0x0 << 1)
1767#define RT5645_GP1_OUT_HI (0x1 << 1)
1768#define RT5645_GP1_P_MASK (0x1)
1769#define RT5645_GP1_P_SFT 0
1770#define RT5645_GP1_P_NOR (0x0)
1771#define RT5645_GP1_P_INV (0x1)
1772
1773/* Programmable Register Array Control 1 (0xc8) */
1774#define RT5645_REG_SEQ_MASK (0xf << 12)
1775#define RT5645_REG_SEQ_SFT 12
1776#define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1777#define RT5645_SEQ1_ST_SFT 11
1778#define RT5645_SEQ1_ST_RUN (0x0 << 11)
1779#define RT5645_SEQ1_ST_FIN (0x1 << 11)
1780#define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1781#define RT5645_SEQ2_ST_SFT 10
1782#define RT5645_SEQ2_ST_RUN (0x0 << 10)
1783#define RT5645_SEQ2_ST_FIN (0x1 << 10)
1784#define RT5645_REG_LV_MASK (0x1 << 9)
1785#define RT5645_REG_LV_SFT 9
1786#define RT5645_REG_LV_MX (0x0 << 9)
1787#define RT5645_REG_LV_PR (0x1 << 9)
1788#define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1789#define RT5645_SEQ_2_PT_BIT 8
1790#define RT5645_REG_IDX_MASK (0xff)
1791#define RT5645_REG_IDX_SFT 0
1792
1793/* Programmable Register Array Control 2 (0xc9) */
1794#define RT5645_REG_DAT_MASK (0xffff)
1795#define RT5645_REG_DAT_SFT 0
1796
1797/* Programmable Register Array Control 3 (0xca) */
1798#define RT5645_SEQ_DLY_MASK (0xff << 8)
1799#define RT5645_SEQ_DLY_SFT 8
1800#define RT5645_PROG_MASK (0x1 << 7)
1801#define RT5645_PROG_SFT 7
1802#define RT5645_PROG_DIS (0x0 << 7)
1803#define RT5645_PROG_EN (0x1 << 7)
1804#define RT5645_SEQ1_PT_RUN (0x1 << 6)
1805#define RT5645_SEQ1_PT_RUN_BIT 6
1806#define RT5645_SEQ2_PT_RUN (0x1 << 5)
1807#define RT5645_SEQ2_PT_RUN_BIT 5
1808
1809/* Programmable Register Array Control 4 (0xcb) */
1810#define RT5645_SEQ1_START_MASK (0xf << 8)
1811#define RT5645_SEQ1_START_SFT 8
1812#define RT5645_SEQ1_END_MASK (0xf)
1813#define RT5645_SEQ1_END_SFT 0
1814
1815/* Programmable Register Array Control 5 (0xcc) */
1816#define RT5645_SEQ2_START_MASK (0xf << 8)
1817#define RT5645_SEQ2_START_SFT 8
1818#define RT5645_SEQ2_END_MASK (0xf)
1819#define RT5645_SEQ2_END_SFT 0
1820
1821/* Scramble Function (0xcd) */
1822#define RT5645_SCB_KEY_MASK (0xff)
1823#define RT5645_SCB_KEY_SFT 0
1824
1825/* Scramble Control (0xce) */
1826#define RT5645_SCB_SWAP_MASK (0x1 << 15)
1827#define RT5645_SCB_SWAP_SFT 15
1828#define RT5645_SCB_SWAP_DIS (0x0 << 15)
1829#define RT5645_SCB_SWAP_EN (0x1 << 15)
1830#define RT5645_SCB_MASK (0x1 << 14)
1831#define RT5645_SCB_SFT 14
1832#define RT5645_SCB_DIS (0x0 << 14)
1833#define RT5645_SCB_EN (0x1 << 14)
1834
1835/* Baseback Control (0xcf) */
1836#define RT5645_BB_MASK (0x1 << 15)
1837#define RT5645_BB_SFT 15
1838#define RT5645_BB_DIS (0x0 << 15)
1839#define RT5645_BB_EN (0x1 << 15)
1840#define RT5645_BB_CT_MASK (0x7 << 12)
1841#define RT5645_BB_CT_SFT 12
1842#define RT5645_BB_CT_A (0x0 << 12)
1843#define RT5645_BB_CT_B (0x1 << 12)
1844#define RT5645_BB_CT_C (0x2 << 12)
1845#define RT5645_BB_CT_D (0x3 << 12)
1846#define RT5645_M_BB_L_MASK (0x1 << 9)
1847#define RT5645_M_BB_L_SFT 9
1848#define RT5645_M_BB_R_MASK (0x1 << 8)
1849#define RT5645_M_BB_R_SFT 8
1850#define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1851#define RT5645_M_BB_HPF_L_SFT 7
1852#define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1853#define RT5645_M_BB_HPF_R_SFT 6
1854#define RT5645_G_BB_BST_MASK (0x3f)
1855#define RT5645_G_BB_BST_SFT 0
1856
1857/* MP3 Plus Control 1 (0xd0) */
1858#define RT5645_M_MP3_L_MASK (0x1 << 15)
1859#define RT5645_M_MP3_L_SFT 15
1860#define RT5645_M_MP3_R_MASK (0x1 << 14)
1861#define RT5645_M_MP3_R_SFT 14
1862#define RT5645_M_MP3_MASK (0x1 << 13)
1863#define RT5645_M_MP3_SFT 13
1864#define RT5645_M_MP3_DIS (0x0 << 13)
1865#define RT5645_M_MP3_EN (0x1 << 13)
1866#define RT5645_EG_MP3_MASK (0x1f << 8)
1867#define RT5645_EG_MP3_SFT 8
1868#define RT5645_MP3_HLP_MASK (0x1 << 7)
1869#define RT5645_MP3_HLP_SFT 7
1870#define RT5645_MP3_HLP_DIS (0x0 << 7)
1871#define RT5645_MP3_HLP_EN (0x1 << 7)
1872#define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1873#define RT5645_M_MP3_ORG_L_SFT 6
1874#define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1875#define RT5645_M_MP3_ORG_R_SFT 5
1876
1877/* MP3 Plus Control 2 (0xd1) */
1878#define RT5645_MP3_WT_MASK (0x1 << 13)
1879#define RT5645_MP3_WT_SFT 13
1880#define RT5645_MP3_WT_1_4 (0x0 << 13)
1881#define RT5645_MP3_WT_1_2 (0x1 << 13)
1882#define RT5645_OG_MP3_MASK (0x1f << 8)
1883#define RT5645_OG_MP3_SFT 8
1884#define RT5645_HG_MP3_MASK (0x3f)
1885#define RT5645_HG_MP3_SFT 0
1886
1887/* 3D HP Control 1 (0xd2) */
1888#define RT5645_3D_CF_MASK (0x1 << 15)
1889#define RT5645_3D_CF_SFT 15
1890#define RT5645_3D_CF_DIS (0x0 << 15)
1891#define RT5645_3D_CF_EN (0x1 << 15)
1892#define RT5645_3D_HP_MASK (0x1 << 14)
1893#define RT5645_3D_HP_SFT 14
1894#define RT5645_3D_HP_DIS (0x0 << 14)
1895#define RT5645_3D_HP_EN (0x1 << 14)
1896#define RT5645_3D_BT_MASK (0x1 << 13)
1897#define RT5645_3D_BT_SFT 13
1898#define RT5645_3D_BT_DIS (0x0 << 13)
1899#define RT5645_3D_BT_EN (0x1 << 13)
1900#define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1901#define RT5645_3D_1F_MIX_SFT 11
1902#define RT5645_3D_HP_M_MASK (0x1 << 10)
1903#define RT5645_3D_HP_M_SFT 10
1904#define RT5645_3D_HP_M_SUR (0x0 << 10)
1905#define RT5645_3D_HP_M_FRO (0x1 << 10)
1906#define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1907#define RT5645_M_3D_HRTF_SFT 9
1908#define RT5645_M_3D_D2H_MASK (0x1 << 8)
1909#define RT5645_M_3D_D2H_SFT 8
1910#define RT5645_M_3D_D2R_MASK (0x1 << 7)
1911#define RT5645_M_3D_D2R_SFT 7
1912#define RT5645_M_3D_REVB_MASK (0x1 << 6)
1913#define RT5645_M_3D_REVB_SFT 6
1914
1915/* Adjustable high pass filter control 1 (0xd3) */
1916#define RT5645_2ND_HPF_MASK (0x1 << 15)
1917#define RT5645_2ND_HPF_SFT 15
1918#define RT5645_2ND_HPF_DIS (0x0 << 15)
1919#define RT5645_2ND_HPF_EN (0x1 << 15)
1920#define RT5645_HPF_CF_L_MASK (0x7 << 12)
1921#define RT5645_HPF_CF_L_SFT 12
1922#define RT5645_1ST_HPF_MASK (0x1 << 11)
1923#define RT5645_1ST_HPF_SFT 11
1924#define RT5645_1ST_HPF_DIS (0x0 << 11)
1925#define RT5645_1ST_HPF_EN (0x1 << 11)
1926#define RT5645_HPF_CF_R_MASK (0x7 << 8)
1927#define RT5645_HPF_CF_R_SFT 8
1928#define RT5645_ZD_T_MASK (0x3 << 6)
1929#define RT5645_ZD_T_SFT 6
1930#define RT5645_ZD_F_MASK (0x3 << 4)
1931#define RT5645_ZD_F_SFT 4
1932#define RT5645_ZD_F_IM (0x0 << 4)
1933#define RT5645_ZD_F_ZC_IM (0x1 << 4)
1934#define RT5645_ZD_F_ZC_IOD (0x2 << 4)
1935#define RT5645_ZD_F_UN (0x3 << 4)
1936
1937/* HP calibration control and Amp detection (0xd6) */
1938#define RT5645_SI_DAC_MASK (0x1 << 11)
1939#define RT5645_SI_DAC_SFT 11
1940#define RT5645_SI_DAC_AUTO (0x0 << 11)
1941#define RT5645_SI_DAC_TEST (0x1 << 11)
1942#define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943#define RT5645_DC_CAL_M_SFT 10
1944#define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945#define RT5645_DC_CAL_M_NOR (0x1 << 10)
1946#define RT5645_DC_CAL_MASK (0x1 << 9)
1947#define RT5645_DC_CAL_SFT 9
1948#define RT5645_DC_CAL_DIS (0x0 << 9)
1949#define RT5645_DC_CAL_EN (0x1 << 9)
1950#define RT5645_HPD_RCV_MASK (0x7 << 6)
1951#define RT5645_HPD_RCV_SFT 6
1952#define RT5645_HPD_PS_MASK (0x1 << 5)
1953#define RT5645_HPD_PS_SFT 5
1954#define RT5645_HPD_PS_DIS (0x0 << 5)
1955#define RT5645_HPD_PS_EN (0x1 << 5)
1956#define RT5645_CAL_M_MASK (0x1 << 4)
1957#define RT5645_CAL_M_SFT 4
1958#define RT5645_CAL_M_DEP (0x0 << 4)
1959#define RT5645_CAL_M_CAL (0x1 << 4)
1960#define RT5645_CAL_MASK (0x1 << 3)
1961#define RT5645_CAL_SFT 3
1962#define RT5645_CAL_DIS (0x0 << 3)
1963#define RT5645_CAL_EN (0x1 << 3)
1964#define RT5645_CAL_TEST_MASK (0x1 << 2)
1965#define RT5645_CAL_TEST_SFT 2
1966#define RT5645_CAL_TEST_DIS (0x0 << 2)
1967#define RT5645_CAL_TEST_EN (0x1 << 2)
1968#define RT5645_CAL_P_MASK (0x3)
1969#define RT5645_CAL_P_SFT 0
1970#define RT5645_CAL_P_NONE (0x0)
1971#define RT5645_CAL_P_CAL (0x1)
1972#define RT5645_CAL_P_DAC_CAL (0x2)
1973
1974/* Soft volume and zero cross control 1 (0xd9) */
1975#define RT5645_SV_MASK (0x1 << 15)
1976#define RT5645_SV_SFT 15
1977#define RT5645_SV_DIS (0x0 << 15)
1978#define RT5645_SV_EN (0x1 << 15)
1979#define RT5645_SPO_SV_MASK (0x1 << 14)
1980#define RT5645_SPO_SV_SFT 14
1981#define RT5645_SPO_SV_DIS (0x0 << 14)
1982#define RT5645_SPO_SV_EN (0x1 << 14)
1983#define RT5645_OUT_SV_MASK (0x1 << 13)
1984#define RT5645_OUT_SV_SFT 13
1985#define RT5645_OUT_SV_DIS (0x0 << 13)
1986#define RT5645_OUT_SV_EN (0x1 << 13)
1987#define RT5645_HP_SV_MASK (0x1 << 12)
1988#define RT5645_HP_SV_SFT 12
1989#define RT5645_HP_SV_DIS (0x0 << 12)
1990#define RT5645_HP_SV_EN (0x1 << 12)
1991#define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992#define RT5645_ZCD_DIG_SFT 11
1993#define RT5645_ZCD_DIG_DIS (0x0 << 11)
1994#define RT5645_ZCD_DIG_EN (0x1 << 11)
1995#define RT5645_ZCD_MASK (0x1 << 10)
1996#define RT5645_ZCD_SFT 10
1997#define RT5645_ZCD_PD (0x0 << 10)
1998#define RT5645_ZCD_PU (0x1 << 10)
1999#define RT5645_M_ZCD_MASK (0x3f << 4)
2000#define RT5645_M_ZCD_SFT 4
2001#define RT5645_M_ZCD_RM_L (0x1 << 9)
2002#define RT5645_M_ZCD_RM_R (0x1 << 8)
2003#define RT5645_M_ZCD_SM_L (0x1 << 7)
2004#define RT5645_M_ZCD_SM_R (0x1 << 6)
2005#define RT5645_M_ZCD_OM_L (0x1 << 5)
2006#define RT5645_M_ZCD_OM_R (0x1 << 4)
2007#define RT5645_SV_DLY_MASK (0xf)
2008#define RT5645_SV_DLY_SFT 0
2009
2010/* Soft volume and zero cross control 2 (0xda) */
2011#define RT5645_ZCD_HP_MASK (0x1 << 15)
2012#define RT5645_ZCD_HP_SFT 15
2013#define RT5645_ZCD_HP_DIS (0x0 << 15)
2014#define RT5645_ZCD_HP_EN (0x1 << 15)
2015
2016
2017/* Codec Private Register definition */
2018/* 3D Speaker Control (0x63) */
2019#define RT5645_3D_SPK_MASK (0x1 << 15)
2020#define RT5645_3D_SPK_SFT 15
2021#define RT5645_3D_SPK_DIS (0x0 << 15)
2022#define RT5645_3D_SPK_EN (0x1 << 15)
2023#define RT5645_3D_SPK_M_MASK (0x3 << 13)
2024#define RT5645_3D_SPK_M_SFT 13
2025#define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2026#define RT5645_3D_SPK_CG_SFT 8
2027#define RT5645_3D_SPK_SG_MASK (0x1f)
2028#define RT5645_3D_SPK_SG_SFT 0
2029
2030/* Wind Noise Detection Control 1 (0x6c) */
2031#define RT5645_WND_MASK (0x1 << 15)
2032#define RT5645_WND_SFT 15
2033#define RT5645_WND_DIS (0x0 << 15)
2034#define RT5645_WND_EN (0x1 << 15)
2035
2036/* Wind Noise Detection Control 2 (0x6d) */
2037#define RT5645_WND_FC_NW_MASK (0x3f << 10)
2038#define RT5645_WND_FC_NW_SFT 10
2039#define RT5645_WND_FC_WK_MASK (0x3f << 4)
2040#define RT5645_WND_FC_WK_SFT 4
2041
2042/* Wind Noise Detection Control 3 (0x6e) */
2043#define RT5645_HPF_FC_MASK (0x3f << 6)
2044#define RT5645_HPF_FC_SFT 6
2045#define RT5645_WND_FC_ST_MASK (0x3f)
2046#define RT5645_WND_FC_ST_SFT 0
2047
2048/* Wind Noise Detection Control 4 (0x6f) */
2049#define RT5645_WND_TH_LO_MASK (0x3ff)
2050#define RT5645_WND_TH_LO_SFT 0
2051
2052/* Wind Noise Detection Control 5 (0x70) */
2053#define RT5645_WND_TH_HI_MASK (0x3ff)
2054#define RT5645_WND_TH_HI_SFT 0
2055
2056/* Wind Noise Detection Control 8 (0x73) */
2057#define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2058#define RT5645_WND_WIND_SFT 13
2059#define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2060#define RT5645_WND_STRONG_SFT 12
2061enum {
2062 RT5645_NO_WIND,
2063 RT5645_BREEZE,
2064 RT5645_STORM,
2065};
2066
2067/* Dipole Speaker Interface (0x75) */
2068#define RT5645_DP_ATT_MASK (0x3 << 14)
2069#define RT5645_DP_ATT_SFT 14
2070#define RT5645_DP_SPK_MASK (0x1 << 10)
2071#define RT5645_DP_SPK_SFT 10
2072#define RT5645_DP_SPK_DIS (0x0 << 10)
2073#define RT5645_DP_SPK_EN (0x1 << 10)
2074
2075/* EQ Pre Volume Control (0xb3) */
2076#define RT5645_EQ_PRE_VOL_MASK (0xffff)
2077#define RT5645_EQ_PRE_VOL_SFT 0
2078
2079/* EQ Post Volume Control (0xb4) */
2080#define RT5645_EQ_PST_VOL_MASK (0xffff)
2081#define RT5645_EQ_PST_VOL_SFT 0
2082
2083/* Jack Detect Control 3 (0xf8) */
2084#define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2085#define RT5645_JD_CBJ_EN (0x1 << 7)
2086#define RT5645_JD_CBJ_POL (0x1 << 6)
2087#define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
2088#define RT5645_JD_TRI_CBJ_SEL_SFT (3)
2089#define RT5645_JD_TRI_HPO_SEL_MASK (0x7)
2090#define RT5645_JD_TRI_HPO_SEL_SFT (0)
2091#define RT5645_JD_F_GPIO_JD1 (0x0)
2092#define RT5645_JD_F_JD1_1 (0x1)
2093#define RT5645_JD_F_JD1_2 (0x2)
2094#define RT5645_JD_F_JD2 (0x3)
2095#define RT5645_JD_F_JD3 (0x4)
2096#define RT5645_JD_F_GPIO_JD2 (0x5)
2097#define RT5645_JD_F_MX0B_12 (0x6)
2098
2099/* Digital Misc Control (0xfa) */
2100#define RT5645_RST_DSP (0x1 << 13)
2101#define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2102#define RT5645_IF1_ADC1_IN1_SFT 12
2103#define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2104#define RT5645_IF1_ADC1_IN2_SFT 11
2105#define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2106#define RT5645_IF1_ADC2_IN1_SFT 10
2107#define RT5645_DIG_GATE_CTRL 0x1
2108
2109/* General Control2 (0xfb) */
2110#define RT5645_RXDC_SRC_MASK (0x1 << 7)
2111#define RT5645_RXDC_SRC_STO (0x0 << 7)
2112#define RT5645_RXDC_SRC_MONO (0x1 << 7)
2113#define RT5645_RXDC_SRC_SFT (7)
2114#define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2115#define RT5645_RXDP2_SEL_IF2 (0x0 << 3)
2116#define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2117#define RT5645_RXDP2_SEL_SFT (3)
2118
2119
2120/* Vendor ID (0xfd) */
2121#define RT5645_VER_C 0x2
2122#define RT5645_VER_D 0x3
2123
2124
2125/* Volume Rescale */
2126#define RT5645_VOL_RSCL_MAX 0x27
2127#define RT5645_VOL_RSCL_RANGE 0x1F
2128/* Debug String Length */
2129#define RT5645_REG_DISP_LEN 23
2130
2131
2132/* System Clock Source */
2133enum {
2134 RT5645_SCLK_S_MCLK,
2135 RT5645_SCLK_S_PLL1,
2136 RT5645_SCLK_S_RCCLK,
2137};
2138
2139/* PLL1 Source */
2140enum {
2141 RT5645_PLL1_S_MCLK,
2142 RT5645_PLL1_S_BCLK1,
2143 RT5645_PLL1_S_BCLK2,
2144};
2145
2146enum {
2147 RT5645_AIF1,
2148 RT5645_AIF2,
2149 RT5645_AIFS,
2150};
2151
2152enum {
2153 RT5645_DMIC_DATA_IN2P,
2154 RT5645_DMIC_DATA_GPIO6,
2155 RT5645_DMIC_DATA_GPIO10,
2156 RT5645_DMIC_DATA_GPIO12,
2157};
2158
2159enum {
2160 RT5645_DMIC_DATA_IN2N,
2161 RT5645_DMIC_DATA_GPIO5,
2162 RT5645_DMIC_DATA_GPIO11,
2163};
2164
2165struct rt5645_pll_code {
2166 bool m_bp; /* Indicates bypass m code or not. */
2167 int m_code;
2168 int n_code;
2169 int k_code;
2170};
2171
2172struct rt5645_priv {
2173 struct snd_soc_codec *codec;
2174 struct rt5645_platform_data pdata;
2175 struct regmap *regmap;
2176
2177 int sysclk;
2178 int sysclk_src;
2179 int lrck[RT5645_AIFS];
2180 int bclk[RT5645_AIFS];
2181 int master[RT5645_AIFS];
2182
2183 int pll_src;
2184 int pll_in;
2185 int pll_out;
2186};
2187
2188#endif /* __RT5645_H__ */
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