Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...

13 files changed, 1034 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 1f5c42254798..75b07cf5eed0 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -233,6 +233,8 @@
 #define GCC_PCIE_CLKREF_CLK                                     216
 #define GCC_RX2_USB2_CLKREF_CLK                                 217
 #define GCC_RX1_USB2_CLKREF_CLK                                 218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK                      219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK                      220
 
 #define GCC_SYSTEM_NOC_BCR                                      0
 #define GCC_CONFIG_NOC_BCR                                      1
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 000000000000..4e8ae3dee590
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2                 0
+#define R8A77995_CLK_ZG                 1
+#define R8A77995_CLK_ZTR                2
+#define R8A77995_CLK_ZT                 3
+#define R8A77995_CLK_ZX                 4
+#define R8A77995_CLK_S0D1               5
+#define R8A77995_CLK_S1D1               6
+#define R8A77995_CLK_S1D2               7
+#define R8A77995_CLK_S1D4               8
+#define R8A77995_CLK_S2D1               9
+#define R8A77995_CLK_S2D2               10
+#define R8A77995_CLK_S2D4               11
+#define R8A77995_CLK_S3D1               12
+#define R8A77995_CLK_S3D2               13
+#define R8A77995_CLK_S3D4               14
+#define R8A77995_CLK_S1D4C              15
+#define R8A77995_CLK_S3D1C              16
+#define R8A77995_CLK_S3D2C              17
+#define R8A77995_CLK_S3D4C              18
+#define R8A77995_CLK_LB                 19
+#define R8A77995_CLK_CL                 20
+#define R8A77995_CLK_ZB3                21
+#define R8A77995_CLK_ZB3D2              22
+#define R8A77995_CLK_CR                 23
+#define R8A77995_CLK_CRD2               24
+#define R8A77995_CLK_SD0H               25
+#define R8A77995_CLK_SD0                26
+#define R8A77995_CLK_SSP2               27
+#define R8A77995_CLK_SSP1               28
+#define R8A77995_CLK_RPC                29
+#define R8A77995_CLK_RPCD2              30
+#define R8A77995_CLK_ZA2                31
+#define R8A77995_CLK_ZA8                32
+#define R8A77995_CLK_Z2D                33
+#define R8A77995_CLK_CANFD              34
+#define R8A77995_CLK_MSO                35
+#define R8A77995_CLK_R                  36
+#define R8A77995_CLK_OSC                37
+#define R8A77995_CLK_LV0                38
+#define R8A77995_CLK_LV1                39
+#define R8A77995_CLK_CP                 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 56f841c22801..55655ab0a4c4 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -49,6 +49,7 @@
 #define SCLK_EMMC_DRV           117
 #define SCLK_SDMMC_SAMPLE       118
 #define SCLK_SDIO_SAMPLE        119
+#define SCLK_SDIO_SRC           120
 #define SCLK_EMMC_SAMPLE        121
 #define SCLK_VOP                122
 #define SCLK_HDMI_HDCP          123
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index f269d833e41a..d8d0e0456dc2 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -67,9 +67,9 @@
 #define SCLK_SPI                        108
 #define SCLK_SARADC                     109
 #define SCLK_TSADC                      110
-#define SCLK_MACPHY_PRE                 111
-#define SCLK_MACPHY                     112
-#define SCLK_MACPHY_RX                  113
+#define SCLK_MAC_PRE                    111
+#define SCLK_MAC                        112
+#define SCLK_MAC_RX                     113
 #define SCLK_MAC_REF                    114
 #define SCLK_MAC_REFOUT                 115
 #define SCLK_DSP_PFM                    116
@@ -110,6 +110,7 @@
 #define ACLK_CIF2                       207
 #define ACLK_CIF3                       208
 #define ACLK_PERI                       209
+#define ACLK_GMAC                       210
 
 /* pclk gates */
 #define PCLK_GPIO1                      256
@@ -141,6 +142,7 @@
 #define PCLK_EFUSE0                     282
 #define PCLK_EFUSE1                     283
 #define PCLK_WDT                        284
+#define PCLK_GMAC                       285
 
 /* hclk gates */
 #define HCLK_I2S0_8CH                   320
diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 000000000000..6637272b3242
--- /dev/null
+++ b/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,165 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 000000000000..c5a53f38d654
--- /dev/null
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC                1
+#define CLK_CPU                 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG             26
+#define CLK_AHB_EHCI0           27
+#define CLK_AHB_OHCI0           28
+#define CLK_AHB_EHCI1           29
+#define CLK_AHB_OHCI1           30
+#define CLK_AHB_SS              31
+#define CLK_AHB_DMA             32
+#define CLK_AHB_BIST            33
+#define CLK_AHB_MMC0            34
+#define CLK_AHB_MMC1            35
+#define CLK_AHB_MMC2            36
+#define CLK_AHB_MMC3            37
+#define CLK_AHB_MS              38
+#define CLK_AHB_NAND            39
+#define CLK_AHB_SDRAM           40
+#define CLK_AHB_ACE             41
+#define CLK_AHB_EMAC            42
+#define CLK_AHB_TS              43
+#define CLK_AHB_SPI0            44
+#define CLK_AHB_SPI1            45
+#define CLK_AHB_SPI2            46
+#define CLK_AHB_SPI3            47
+#define CLK_AHB_PATA            48
+#define CLK_AHB_SATA            49
+#define CLK_AHB_GPS             50
+#define CLK_AHB_HSTIMER         51
+#define CLK_AHB_VE              52
+#define CLK_AHB_TVD             53
+#define CLK_AHB_TVE0            54
+#define CLK_AHB_TVE1            55
+#define CLK_AHB_LCD0            56
+#define CLK_AHB_LCD1            57
+#define CLK_AHB_CSI0            58
+#define CLK_AHB_CSI1            59
+#define CLK_AHB_HDMI0           60
+#define CLK_AHB_HDMI1           61
+#define CLK_AHB_DE_BE0          62
+#define CLK_AHB_DE_BE1          63
+#define CLK_AHB_DE_FE0          64
+#define CLK_AHB_DE_FE1          65
+#define CLK_AHB_GMAC            66
+#define CLK_AHB_MP              67
+#define CLK_AHB_GPU             68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC          69
+#define CLK_APB0_SPDIF          70
+#define CLK_APB0_I2S0           71
+#define CLK_APB0_AC97           72
+#define CLK_APB0_I2S1           73
+#define CLK_APB0_PIO            74
+#define CLK_APB0_IR0            75
+#define CLK_APB0_IR1            76
+#define CLK_APB0_I2S2           77
+#define CLK_APB0_KEYPAD         78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0           79
+#define CLK_APB1_I2C1           80
+#define CLK_APB1_I2C2           81
+#define CLK_APB1_I2C3           82
+#define CLK_APB1_CAN            83
+#define CLK_APB1_SCR            84
+#define CLK_APB1_PS20           85
+#define CLK_APB1_PS21           86
+#define CLK_APB1_I2C4           87
+#define CLK_APB1_UART0          88
+#define CLK_APB1_UART1          89
+#define CLK_APB1_UART2          90
+#define CLK_APB1_UART3          91
+#define CLK_APB1_UART4          92
+#define CLK_APB1_UART5          93
+#define CLK_APB1_UART6          94
+#define CLK_APB1_UART7          95
+
+/* IP clocks */
+#define CLK_NAND                96
+#define CLK_MS                  97
+#define CLK_MMC0                98
+#define CLK_MMC0_OUTPUT         99
+#define CLK_MMC0_SAMPLE         100
+#define CLK_MMC1                101
+#define CLK_MMC1_OUTPUT         102
+#define CLK_MMC1_SAMPLE         103
+#define CLK_MMC2                104
+#define CLK_MMC2_OUTPUT         105
+#define CLK_MMC2_SAMPLE         106
+#define CLK_MMC3                107
+#define CLK_MMC3_OUTPUT         108
+#define CLK_MMC3_SAMPLE         109
+#define CLK_TS                  110
+#define CLK_SS                  111
+#define CLK_SPI0                112
+#define CLK_SPI1                113
+#define CLK_SPI2                114
+#define CLK_PATA                115
+#define CLK_IR0                 116
+#define CLK_IR1                 117
+#define CLK_I2S0                118
+#define CLK_AC97                119
+#define CLK_SPDIF               120
+#define CLK_KEYPAD              121
+#define CLK_SATA                122
+#define CLK_USB_OHCI0           123
+#define CLK_USB_OHCI1           124
+#define CLK_USB_PHY             125
+#define CLK_GPS                 126
+#define CLK_SPI3                127
+#define CLK_I2S1                128
+#define CLK_I2S2                129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE             130
+#define CLK_DRAM_CSI0           131
+#define CLK_DRAM_CSI1           132
+#define CLK_DRAM_TS             133
+#define CLK_DRAM_TVD            134
+#define CLK_DRAM_TVE0           135
+#define CLK_DRAM_TVE1           136
+#define CLK_DRAM_OUT            137
+#define CLK_DRAM_DE_FE1         138
+#define CLK_DRAM_DE_FE0         139
+#define CLK_DRAM_DE_BE0         140
+#define CLK_DRAM_DE_BE1         141
+#define CLK_DRAM_MP             142
+#define CLK_DRAM_ACE            143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0              144
+#define CLK_DE_BE1              145
+#define CLK_DE_FE0              146
+#define CLK_DE_FE1              147
+#define CLK_DE_MP               148
+#define CLK_TCON0_CH0           149
+#define CLK_TCON1_CH0           150
+#define CLK_CSI_SCLK            151
+#define CLK_TVD_SCLK2           152
+#define CLK_TVD                 153
+#define CLK_TCON0_CH1_SCLK2     154
+#define CLK_TCON0_CH1           155
+#define CLK_TCON1_CH1_SCLK2     156
+#define CLK_TCON1_CH1           157
+#define CLK_CSI0                158
+#define CLK_CSI1                159
+#define CLK_CODEC               160
+#define CLK_VE                  161
+#define CLK_AVS                 162
+#define CLK_ACE                 163
+#define CLK_HDMI                164
+#define CLK_GPU                 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 000000000000..045a5178da0c
--- /dev/null
+++ b/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS                166
+#define CLK_HDMI1_SLOW          167
+#define CLK_HDMI1               168
+#define CLK_OUT_A               169
+#define CLK_OUT_B               170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 000000000000..4fa5f69fc297
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU                 24
+
+#define CLK_BUS_MIPI_DSI        29
+#define CLK_BUS_CE              30
+#define CLK_BUS_DMA             31
+#define CLK_BUS_MMC0            32
+#define CLK_BUS_MMC1            33
+#define CLK_BUS_MMC2            34
+#define CLK_BUS_MMC3            35
+#define CLK_BUS_NAND            36
+#define CLK_BUS_DRAM            37
+#define CLK_BUS_EMAC            38
+#define CLK_BUS_TS              39
+#define CLK_BUS_HSTIMER         40
+#define CLK_BUS_SPI0            41
+#define CLK_BUS_SPI1            42
+#define CLK_BUS_SPI2            43
+#define CLK_BUS_SPI3            44
+#define CLK_BUS_SATA            45
+#define CLK_BUS_OTG             46
+#define CLK_BUS_EHCI0           47
+#define CLK_BUS_EHCI1           48
+#define CLK_BUS_EHCI2           49
+#define CLK_BUS_OHCI0           50
+#define CLK_BUS_OHCI1           51
+#define CLK_BUS_OHCI2           52
+#define CLK_BUS_VE              53
+#define CLK_BUS_MP              54
+#define CLK_BUS_DEINTERLACE     55
+#define CLK_BUS_CSI0            56
+#define CLK_BUS_CSI1            57
+#define CLK_BUS_HDMI1           58
+#define CLK_BUS_HDMI0           59
+#define CLK_BUS_DE              60
+#define CLK_BUS_TVE0            61
+#define CLK_BUS_TVE1            62
+#define CLK_BUS_TVE_TOP         63
+#define CLK_BUS_GMAC            64
+#define CLK_BUS_GPU             65
+#define CLK_BUS_TVD0            66
+#define CLK_BUS_TVD1            67
+#define CLK_BUS_TVD2            68
+#define CLK_BUS_TVD3            69
+#define CLK_BUS_TVD_TOP         70
+#define CLK_BUS_TCON_LCD0       71
+#define CLK_BUS_TCON_LCD1       72
+#define CLK_BUS_TCON_TV0        73
+#define CLK_BUS_TCON_TV1        74
+#define CLK_BUS_TCON_TOP        75
+#define CLK_BUS_CODEC           76
+#define CLK_BUS_SPDIF           77
+#define CLK_BUS_AC97            78
+#define CLK_BUS_PIO             79
+#define CLK_BUS_IR0             80
+#define CLK_BUS_IR1             81
+#define CLK_BUS_THS             82
+#define CLK_BUS_KEYPAD          83
+#define CLK_BUS_I2S0            84
+#define CLK_BUS_I2S1            85
+#define CLK_BUS_I2S2            86
+#define CLK_BUS_I2C0            87
+#define CLK_BUS_I2C1            88
+#define CLK_BUS_I2C2            89
+#define CLK_BUS_I2C3            90
+#define CLK_BUS_CAN             91
+#define CLK_BUS_SCR             92
+#define CLK_BUS_PS20            93
+#define CLK_BUS_PS21            94
+#define CLK_BUS_I2C4            95
+#define CLK_BUS_UART0           96
+#define CLK_BUS_UART1           97
+#define CLK_BUS_UART2           98
+#define CLK_BUS_UART3           99
+#define CLK_BUS_UART4           100
+#define CLK_BUS_UART5           101
+#define CLK_BUS_UART6           102
+#define CLK_BUS_UART7           103
+#define CLK_BUS_DBG             104
+
+#define CLK_THS                 105
+#define CLK_NAND                106
+#define CLK_MMC0                107
+#define CLK_MMC1                108
+#define CLK_MMC2                109
+#define CLK_MMC3                110
+#define CLK_TS                  111
+#define CLK_CE                  112
+#define CLK_SPI0                113
+#define CLK_SPI1                114
+#define CLK_SPI2                115
+#define CLK_SPI3                116
+#define CLK_I2S0                117
+#define CLK_I2S1                118
+#define CLK_I2S2                119
+#define CLK_AC97                120
+#define CLK_SPDIF               121
+#define CLK_KEYPAD              122
+#define CLK_SATA                123
+#define CLK_USB_PHY0            124
+#define CLK_USB_PHY1            125
+#define CLK_USB_PHY2            126
+#define CLK_USB_OHCI0           127
+#define CLK_USB_OHCI1           128
+#define CLK_USB_OHCI2           129
+#define CLK_IR0                 130
+#define CLK_IR1                 131
+
+#define CLK_DRAM_VE             133
+#define CLK_DRAM_CSI0           134
+#define CLK_DRAM_CSI1           135
+#define CLK_DRAM_TS             136
+#define CLK_DRAM_TVD            137
+#define CLK_DRAM_MP             138
+#define CLK_DRAM_DEINTERLACE    139
+#define CLK_DE                  140
+#define CLK_MP                  141
+#define CLK_TCON_LCD0           142
+#define CLK_TCON_LCD1           143
+#define CLK_TCON_TV0            144
+#define CLK_TCON_TV1            145
+#define CLK_DEINTERLACE         146
+#define CLK_CSI1_MCLK           147
+#define CLK_CSI_SCLK            148
+#define CLK_CSI0_MCLK           149
+#define CLK_VE                  150
+#define CLK_CODEC               151
+#define CLK_AVS                 152
+#define CLK_HDMI                153
+#define CLK_HDMI_SLOW           154
+
+#define CLK_DSI_DPHY            156
+#define CLK_TVE0                157
+#define CLK_TVE1                158
+#define CLK_TVD0                159
+#define CLK_TVD1                160
+#define CLK_TVD2                161
+#define CLK_TVD3                162
+#define CLK_GPU                 163
+#define CLK_OUTA                164
+#define CLK_OUTB                165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h
new file mode 100644
index 000000000000..461a8e04453a
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32h7-rcc.h
@@ -0,0 +1,136 @@
+/*
+ * This header provides constants for the STM32H7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
+#define _DT_BINDINGS_MFD_STM32H7_RCC_H
+
+/* AHB3 */
+#define STM32H7_RCC_AHB3_MDMA           0
+#define STM32H7_RCC_AHB3_DMA2D          4
+#define STM32H7_RCC_AHB3_JPGDEC         5
+#define STM32H7_RCC_AHB3_FMC            12
+#define STM32H7_RCC_AHB3_QUADSPI        14
+#define STM32H7_RCC_AHB3_SDMMC1         16
+#define STM32H7_RCC_AHB3_CPU            31
+
+#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
+
+/* AHB1 */
+#define STM32H7_RCC_AHB1_DMA1           0
+#define STM32H7_RCC_AHB1_DMA2           1
+#define STM32H7_RCC_AHB1_ADC12          5
+#define STM32H7_RCC_AHB1_ART            14
+#define STM32H7_RCC_AHB1_ETH1MAC        15
+#define STM32H7_RCC_AHB1_USB1OTG        25
+#define STM32H7_RCC_AHB1_USB2OTG        27
+
+#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
+
+/* AHB2 */
+#define STM32H7_RCC_AHB2_CAMITF         0
+#define STM32H7_RCC_AHB2_CRYPT          4
+#define STM32H7_RCC_AHB2_HASH           5
+#define STM32H7_RCC_AHB2_RNG            6
+#define STM32H7_RCC_AHB2_SDMMC2         9
+
+#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
+
+/* AHB4 */
+#define STM32H7_RCC_AHB4_GPIOA          0
+#define STM32H7_RCC_AHB4_GPIOB          1
+#define STM32H7_RCC_AHB4_GPIOC          2
+#define STM32H7_RCC_AHB4_GPIOD          3
+#define STM32H7_RCC_AHB4_GPIOE          4
+#define STM32H7_RCC_AHB4_GPIOF          5
+#define STM32H7_RCC_AHB4_GPIOG          6
+#define STM32H7_RCC_AHB4_GPIOH          7
+#define STM32H7_RCC_AHB4_GPIOI          8
+#define STM32H7_RCC_AHB4_GPIOJ          9
+#define STM32H7_RCC_AHB4_GPIOK          10
+#define STM32H7_RCC_AHB4_CRC            19
+#define STM32H7_RCC_AHB4_BDMA           21
+#define STM32H7_RCC_AHB4_ADC3           24
+#define STM32H7_RCC_AHB4_HSEM           25
+
+#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
+
+/* APB3 */
+#define STM32H7_RCC_APB3_LTDC           3
+#define STM32H7_RCC_APB3_DSI            4
+
+#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
+
+/* APB1L */
+#define STM32H7_RCC_APB1L_TIM2          0
+#define STM32H7_RCC_APB1L_TIM3          1
+#define STM32H7_RCC_APB1L_TIM4          2
+#define STM32H7_RCC_APB1L_TIM5          3
+#define STM32H7_RCC_APB1L_TIM6          4
+#define STM32H7_RCC_APB1L_TIM7          5
+#define STM32H7_RCC_APB1L_TIM12         6
+#define STM32H7_RCC_APB1L_TIM13         7
+#define STM32H7_RCC_APB1L_TIM14         8
+#define STM32H7_RCC_APB1L_LPTIM1        9
+#define STM32H7_RCC_APB1L_SPI2          14
+#define STM32H7_RCC_APB1L_SPI3          15
+#define STM32H7_RCC_APB1L_SPDIF_RX      16
+#define STM32H7_RCC_APB1L_USART2        17
+#define STM32H7_RCC_APB1L_USART3        18
+#define STM32H7_RCC_APB1L_UART4         19
+#define STM32H7_RCC_APB1L_UART5         20
+#define STM32H7_RCC_APB1L_I2C1          21
+#define STM32H7_RCC_APB1L_I2C2          22
+#define STM32H7_RCC_APB1L_I2C3          23
+#define STM32H7_RCC_APB1L_HDMICEC       27
+#define STM32H7_RCC_APB1L_DAC12         29
+#define STM32H7_RCC_APB1L_USART7        30
+#define STM32H7_RCC_APB1L_USART8        31
+
+#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
+
+/* APB1H */
+#define STM32H7_RCC_APB1H_CRS           1
+#define STM32H7_RCC_APB1H_SWP           2
+#define STM32H7_RCC_APB1H_OPAMP         4
+#define STM32H7_RCC_APB1H_MDIOS         5
+#define STM32H7_RCC_APB1H_FDCAN         8
+
+#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
+
+/* APB2 */
+#define STM32H7_RCC_APB2_TIM1           0
+#define STM32H7_RCC_APB2_TIM8           1
+#define STM32H7_RCC_APB2_USART1         4
+#define STM32H7_RCC_APB2_USART6         5
+#define STM32H7_RCC_APB2_SPI1           12
+#define STM32H7_RCC_APB2_SPI4           13
+#define STM32H7_RCC_APB2_TIM15          16
+#define STM32H7_RCC_APB2_TIM16          17
+#define STM32H7_RCC_APB2_TIM17          18
+#define STM32H7_RCC_APB2_SPI5           20
+#define STM32H7_RCC_APB2_SAI1           22
+#define STM32H7_RCC_APB2_SAI2           23
+#define STM32H7_RCC_APB2_SAI3           24
+#define STM32H7_RCC_APB2_DFSDM1         28
+#define STM32H7_RCC_APB2_HRTIM          29
+
+#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
+
+/* APB4 */
+#define STM32H7_RCC_APB4_SYSCFG         1
+#define STM32H7_RCC_APB4_LPUART1        3
+#define STM32H7_RCC_APB4_SPI6           5
+#define STM32H7_RCC_APB4_I2C4           7
+#define STM32H7_RCC_APB4_LPTIM2         9
+#define STM32H7_RCC_APB4_LPTIM3         10
+#define STM32H7_RCC_APB4_LPTIM4         11
+#define STM32H7_RCC_APB4_LPTIM5         12
+#define STM32H7_RCC_APB4_COMP12         14
+#define STM32H7_RCC_APB4_VREF           15
+#define STM32H7_RCC_APB4_SAI4           21
+#define STM32H7_RCC_APB4_TMPSENS        26
+
+#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
+
+#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h
new file mode 100644
index 000000000000..5f4480bedc8a
--- /dev/null
+++ b/include/dt-bindings/reset/sun4i-a10-ccu.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
+#define _DT_BINDINGS_RST_SUN4I_A10_H
+
+#define RST_USB_PHY0            1
+#define RST_USB_PHY1            2
+#define RST_USB_PHY2            3
+#define RST_GPS                 4
+#define RST_DE_BE0              5
+#define RST_DE_BE1              6
+#define RST_DE_FE0              7
+#define RST_DE_FE1              8
+#define RST_DE_MP               9
+#define RST_TVE0                10
+#define RST_TCON0               11
+#define RST_TVE1                12
+#define RST_TCON1               13
+#define RST_CSI0                14
+#define RST_CSI1                15
+#define RST_VE                  16
+#define RST_ACE                 17
+#define RST_LVDS                18
+#define RST_GPU                 19
+#define RST_HDMI_H              20
+#define RST_HDMI_SYS            21
+#define RST_HDMI_AUDIO_DMA      22
+
+#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h
new file mode 100644
index 000000000000..c5ebcf6672e4
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r40-ccu.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
+#define _DT_BINDINGS_RST_SUN8I_R40_H_
+
+#define RST_USB_PHY0            0
+#define RST_USB_PHY1            1
+#define RST_USB_PHY2            2
+
+#define RST_DRAM                3
+#define RST_MBUS                4
+
+#define RST_BUS_MIPI_DSI        5
+#define RST_BUS_CE              6
+#define RST_BUS_DMA             7
+#define RST_BUS_MMC0            8
+#define RST_BUS_MMC1            9
+#define RST_BUS_MMC2            10
+#define RST_BUS_MMC3            11
+#define RST_BUS_NAND            12
+#define RST_BUS_DRAM            13
+#define RST_BUS_EMAC            14
+#define RST_BUS_TS              15
+#define RST_BUS_HSTIMER         16
+#define RST_BUS_SPI0            17
+#define RST_BUS_SPI1            18
+#define RST_BUS_SPI2            19
+#define RST_BUS_SPI3            20
+#define RST_BUS_SATA            21
+#define RST_BUS_OTG             22
+#define RST_BUS_EHCI0           23
+#define RST_BUS_EHCI1           24
+#define RST_BUS_EHCI2           25
+#define RST_BUS_OHCI0           26
+#define RST_BUS_OHCI1           27
+#define RST_BUS_OHCI2           28
+#define RST_BUS_VE              29
+#define RST_BUS_MP              30
+#define RST_BUS_DEINTERLACE     31
+#define RST_BUS_CSI0            32
+#define RST_BUS_CSI1            33
+#define RST_BUS_HDMI0           34
+#define RST_BUS_HDMI1           35
+#define RST_BUS_DE              36
+#define RST_BUS_TVE0            37
+#define RST_BUS_TVE1            38
+#define RST_BUS_TVE_TOP         39
+#define RST_BUS_GMAC            40
+#define RST_BUS_GPU             41
+#define RST_BUS_TVD0            42
+#define RST_BUS_TVD1            43
+#define RST_BUS_TVD2            44
+#define RST_BUS_TVD3            45
+#define RST_BUS_TVD_TOP         46
+#define RST_BUS_TCON_LCD0       47
+#define RST_BUS_TCON_LCD1       48
+#define RST_BUS_TCON_TV0        49
+#define RST_BUS_TCON_TV1        50
+#define RST_BUS_TCON_TOP        51
+#define RST_BUS_DBG             52
+#define RST_BUS_LVDS            53
+#define RST_BUS_CODEC           54
+#define RST_BUS_SPDIF           55
+#define RST_BUS_AC97            56
+#define RST_BUS_IR0             57
+#define RST_BUS_IR1             58
+#define RST_BUS_THS             59
+#define RST_BUS_KEYPAD          60
+#define RST_BUS_I2S0            61
+#define RST_BUS_I2S1            62
+#define RST_BUS_I2S2            63
+#define RST_BUS_I2C0            64
+#define RST_BUS_I2C1            65
+#define RST_BUS_I2C2            66
+#define RST_BUS_I2C3            67
+#define RST_BUS_CAN             68
+#define RST_BUS_SCR             69
+#define RST_BUS_PS20            70
+#define RST_BUS_PS21            71
+#define RST_BUS_I2C4            72
+#define RST_BUS_UART0           73
+#define RST_BUS_UART1           74
+#define RST_BUS_UART2           75
+#define RST_BUS_UART3           76
+#define RST_BUS_UART4           77
+#define RST_BUS_UART5           78
+#define RST_BUS_UART6           79
+#define RST_BUS_UART7           80
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..5100ec1b5d55 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -343,6 +343,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
                 u8 clk_gate_flags, spinlock_t *lock);
 void clk_unregister_gate(struct clk *clk);
 void clk_hw_unregister_gate(struct clk_hw *hw);
+int clk_gate_is_enabled(struct clk_hw *hw);
 
 struct clk_div_table {
         unsigned int    val;
@@ -565,6 +566,9 @@ struct clk_fractional_divider {
         u8              nwidth;
         u32             nmask;
         u8              flags;
+        void            (*approximation)(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *parent_rate,
+                                unsigned long *m, unsigned long *n);
         spinlock_t      *lock;
 };
 
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413bbbedf..6aca5ce8a99a 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -185,4 +185,29 @@
 #define         AT91_PMC_PCR_EN                 (0x1  <<  28)                           /* Enable */
 #define         AT91_PMC_PCR_GCKEN              (0x1  <<  29)                           /* GCK Enable */
 
+#define AT91_PMC_AUDIO_PLL0     0x14c
+#define         AT91_PMC_AUDIO_PLL_PLLEN        (1  <<  0)
+#define         AT91_PMC_AUDIO_PLL_PADEN        (1  <<  1)
+#define         AT91_PMC_AUDIO_PLL_PMCEN        (1  <<  2)
+#define         AT91_PMC_AUDIO_PLL_RESETN       (1  <<  3)
+#define         AT91_PMC_AUDIO_PLL_ND_OFFSET    8
+#define         AT91_PMC_AUDIO_PLL_ND_MASK      (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_ND(n)        ((n)  << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
+#define         AT91_PMC_AUDIO_PLL_QDPMC_MASK   (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPMC(n)     ((n)  << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+
+#define AT91_PMC_AUDIO_PLL1     0x150
+#define         AT91_PMC_AUDIO_PLL_FRACR_MASK           0x3fffff
+#define         AT91_PMC_AUDIO_PLL_QDPAD_OFFSET         24
+#define         AT91_PMC_AUDIO_PLL_QDPAD_MASK           (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD(n)             ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET     AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK       (0x3  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV(n)         ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET  26
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX     0x1f
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK    (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n)      ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+
 #endif