Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...

142 files changed, 9354 insertions, 1101 deletions

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index faa6d8ac5834..786dc39ca904 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,gxbb-aoclkc"
-- reg: physical base address of the clock controller and length of memory
-       mapped region.
+- compatible: value should be different for each SoC family as :
+        - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
+        - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
+        - GXM (S912) : "amlogic,meson-gxm-aoclkc"
+        followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
 
@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
 preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
 used in device tree sources.
 
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
 Example: AO Clock controller node:
 
-        clkc_AO: clock-controller@040 {
-                compatible = "amlogic,gxbb-aoclkc";
-                reg = <0x0 0x040 0x0 0x4>;
+ao_sysctrl: sys-ctrl@0 {
+        compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+        reg =  <0x0 0x0 0x0 0x100>;
+
+        clkc_AO: clock-controller {
+                compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
                 #clock-cells = <1>;
                 #reset-cells = <1>;
         };
+};
 
 Example: UART controller node that consumes the clock and reset generated
   by the clock controller:
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index 5f3ad65daf69..51c259a92d02 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -81,6 +81,16 @@ Required properties:
         "atmel,sama5d2-clk-generated":
                 at91 generated clock
 
+        "atmel,sama5d2-clk-audio-pll-frac":
+                at91 audio fractional pll
+
+        "atmel,sama5d2-clk-audio-pll-pad":
+                at91 audio pll CLK_AUDIO output pin
+
+        "atmel,sama5d2-clk-audio-pll-pmc"
+                at91 audio pll output on AUDIOPLLCLK that feeds the PMC
+                and can be used by peripheral clock or generic clock
+
 Required properties for SCKC node:
 - reg : defines the IO memory reserved for the SCKC.
 - #size-cells : shall be 0 (reg is used to encode clk id).
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 53d7e50ed875..05a245c9df08 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -1,24 +1,32 @@
-Binding for IDT VersaClock5 programmable i2c clock generator.
+Binding for IDT VersaClock 5,6 programmable i2c clock generators.
 
-The IDT VersaClock5 are programmable i2c clock generators providing
-from 3 to 12 output clocks.
+The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
+generators providing from 3 to 12 output clocks.
 
 ==I2C device node==
 
 Required properties:
-- compatible:   shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
-                "idt,5p49v5935".
+- compatible:   shall be one of
+                "idt,5p49v5923"
+                "idt,5p49v5925"
+                "idt,5p49v5933"
+                "idt,5p49v5935"
+                "idt,5p49v6901"
 - reg:          i2c device address, shall be 0x68 or 0x6a.
 - #clock-cells: from common clock binding; shall be set to 1.
 - clocks:       from common clock binding; list of parent clock handles,
-                - 5p49v5923: (required) either or both of XTAL or CLKIN
+                - 5p49v5923 and
+                  5p49v5925 and
+                  5p49v6901: (required) either or both of XTAL or CLKIN
                                         reference clock.
                 - 5p49v5933 and
                 - 5p49v5935: (optional) property not present (internal
                                         Xtal used) or CLKIN reference
                                         clock.
 - clock-names:  from common clock binding; clock input names, can be
-                - 5p49v5923: (required) either or both of "xin", "clkin".
+                - 5p49v5923 and
+                  5p49v5925 and
+                  5p49v6901: (required) either or both of "xin", "clkin".
                 - 5p49v5933 and
                 - 5p49v5935: (optional) property not present or "clkin".
 
@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
         1 -- OUT1
         2 -- OUT4
 
+5P49V5925 and
 5P49V5935:
         0 -- OUT0_SEL_I2CB
         1 -- OUT1
@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
         3 -- OUT3
         4 -- OUT4
 
+5P49V6901:
+        0 -- OUT0_SEL_I2CB
+        1 -- OUT1
+        2 -- OUT2
+        3 -- OUT3
+        4 -- OUT4
+
 ==Example==
 
 /* 25MHz reference crystal */
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 707a686d8d3e..316e13686568 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
       - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
 
   - reg: Base address and length of the memory resource used by the CPG/MSSR
     block
@@ -30,7 +31,7 @@ Required Properties:
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
       - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
-                 r8a7795, r8a7796)
+                 r8a7795, r8a7796, r8a77995)
       - "extalr" (r8a7795, r8a7796)
       - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
 
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
new file mode 100644
index 000000000000..e96e085271c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -0,0 +1,55 @@
+* Renesas R-Car USB 2.0 clock selector
+
+This file provides information on what the device node for the R-Car USB 2.0
+clock selector.
+
+If you connect an external clock to the USB_EXTAL pin only, you should set
+the clock rate to "usb_extal" node only.
+If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
+is not needed because this is default setting. (Of course, you can set the
+clock rates to both "usb_extal" and "usb_xtal" nodes.
+
+Case 1: An external clock connects to R-Car SoC
+        +----------+   +--- R-Car ---------------------+
+        |External  |---|USB_EXTAL ---> all usb channels|
+        |clock     |   |USB_XTAL                       |
+        +----------+   +-------------------------------+
+In this case, we need this driver with "usb_extal" clock.
+
+Case 2: An oscillator connects to R-Car SoC
+        +----------+   +--- R-Car ---------------------+
+        |Oscillator|---|USB_EXTAL -+-> all usb channels|
+        |          |---|USB_XTAL --+                   |
+        +----------+   +-------------------------------+
+In this case, we don't need this selector.
+
+Required properties:
+- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
+              an R8A7795 SoC.
+              "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
+              an R8A7796 SoC.
+              "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
+              compatible device.
+
+              When compatible with the generic version, nodes must list the
+              SoC-specific version corresponding to the platform first
+              followed by the generic version.
+
+- reg: offset and length of the USB 2.0 clock selector register block.
+- clocks: A list of phandles and specifier pairs.
+- clock-names: Name of the clocks.
+ - The functional clock must be "ehci_ohci"
+ - The USB_EXTAL clock pin must be "usb_extal"
+ - The USB_XTAL clock pin must be "usb_xtal"
+- #clock-cells: Must be 0
+
+Example (R-Car H3):
+
+        usb2_clksel: clock-controller@e6590630 {
+                compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
+                             "renesas,rcar-gen3-usb2-clock-sel";
+                reg = <0 0xe6590630 0 0x02>;
+                clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
+                clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+                #clock-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
index 455a9a00a623..6f8744fd301b 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
@@ -1,12 +1,14 @@
-* Rockchip RK3128 Clock and Reset Unit
+* Rockchip RK3126/RK3128 Clock and Reset Unit
 
-The RK3128 clock controller generates and supplies clock to various
+The RK3126/RK3128 clock controller generates and supplies clock to various
 controllers within the SoC and also implements a reset controller for SoC
 peripherals.
 
 Required Properties:
 
-- compatible: should be "rockchip,rk3128-cru"
+- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
+  "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
+  "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - #clock-cells: should be 1.
diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
new file mode 100644
index 000000000000..c56c7553c730
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the HSDK Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-<name>-pll-clock"
+  "snps,hsdk-core-pll-clock"
+  "snps,hsdk-gp-pll-clock"
+  "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+        input_clk: input-clk {
+                clock-frequency = <33333333>;
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        cpu_clk: cpu-clk@0 {
+                compatible = "snps,hsdk-core-pll-clock";
+                reg = <0x00 0x10>;
+                #clock-cells = <0>;
+                clocks = <&input_clk>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
new file mode 100644
index 000000000000..11fe4876612c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the AXS10X Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-<name>-pll-clock"
+  "snps,axs10x-arc-pll-clock"
+  "snps,axs10x-pgu-pll-clock"
+- reg: should always contain 2 pairs address - length: first for PLL config
+registers and second for corresponding LOCK CGU register.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+        input-clk: input-clk {
+                clock-frequency = <33333333>;
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+        };
+
+        core-clk: core-clk@80 {
+                compatible = "snps,axs10x-arc-pll-clock";
+                reg = <0x80 0x10>, <0x100 0x10>;
+                #clock-cells = <0>;
+                clocks = <&input-clk>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt
new file mode 100644
index 000000000000..a135504c7d57
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt
@@ -0,0 +1,71 @@
+STMicroelectronics STM32H7 Reset and Clock Controller
+=====================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please refer to clock-bindings.txt for common clock controller binding usage.
+Please also refer to reset.txt for common reset controller binding usage.
+
+Required properties:
+- compatible: Should be:
+  "st,stm32h743-rcc"
+
+- reg: should be register base and length as documented in the
+  datasheet
+
+- #reset-cells: 1, see below
+
+- #clock-cells : from common clock binding; shall be set to 1
+
+- clocks: External oscillator clock phandle
+  - high speed external clock signal (HSE)
+  - low speed external clock signal (LSE)
+  - external I2S clock (I2S_CKIN)
+
+Optional properties:
+- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
+  write protection (RTC clock).
+
+Example:
+
+        rcc: reset-clock-controller@58024400 {
+                compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+                reg = <0x58024400 0x400>;
+                #reset-cells = <1>;
+                #clock-cells = <2>;
+                clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
+
+                st,syscfg = <&pwrcfg>;
+};
+
+The peripheral clock consumer should specify the desired clock by
+having the clock ID in its "clocks" phandle cell.
+
+Example:
+
+                timer5: timer@40000c00 {
+                        compatible = "st,stm32-timer";
+                        reg = <0x40000c00 0x400>;
+                        interrupts = <50>;
+                        clocks = <&rcc TIM5_CK>;
+                };
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example, for CRC reset:
+  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
+
+Example:
+
+        timer2 {
+                resets  = <&rcc STM32H7_APB1L_RESET(TIM2)>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index df9fad58facd..7eda08eb8a1e 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
 
 Required properties :
 - compatible: must contain one of the following compatibles:
+                - "allwinner,sun4i-a10-ccu"
+                - "allwinner,sun5i-a10s-ccu"
+                - "allwinner,sun5i-a13-ccu"
                 - "allwinner,sun6i-a31-ccu"
+                - "allwinner,sun7i-a20-ccu"
                 - "allwinner,sun8i-a23-ccu"
                 - "allwinner,sun8i-a33-ccu"
                 - "allwinner,sun8i-a83t-ccu"
                 - "allwinner,sun8i-a83t-r-ccu"
                 - "allwinner,sun8i-h3-ccu"
                 - "allwinner,sun8i-h3-r-ccu"
++               - "allwinner,sun8i-r40-ccu"
                 - "allwinner,sun8i-v3s-ccu"
                 - "allwinner,sun9i-a80-ccu"
                 - "allwinner,sun50i-a64-ccu"
                 - "allwinner,sun50i-a64-r-ccu"
                 - "allwinner,sun50i-h5-ccu"
+                - "nextthing,gr8-ccu"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
index 812163060fa3..7b5f602765fe 100644
--- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -6,7 +6,6 @@ System clock
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-clock" - for sLD3 SoC.
     "socionext,uniphier-ld4-clock"  - for LD4 SoC.
     "socionext,uniphier-pro4-clock" - for Pro4 SoC.
     "socionext,uniphier-sld8-clock" - for sLD8 SoC.
@@ -14,6 +13,7 @@ Required properties:
     "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
     "socionext,uniphier-ld11-clock" - for LD11 SoC.
     "socionext,uniphier-ld20-clock" - for LD20 SoC.
+    "socionext,uniphier-pxs3-clock" - for PXs3 SoC
 - #clock-cells: should be 1.
 
 Example:
@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
     "socionext,uniphier-ld4-mio-clock"  - for LD4 SoC.
     "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
     "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
@@ -56,6 +55,7 @@ Required properties:
     "socionext,uniphier-pxs2-sd-clock"  - for PXs2/LD6b SoC.
     "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
     "socionext,uniphier-ld20-sd-clock"  - for LD20 SoC.
+    "socionext,uniphier-pxs3-sd-clock"  - for PXs3 SoC
 - #clock-cells: should be 1.
 
 Example:
@@ -82,11 +82,9 @@ Provided clocks:
  8: USB2 ch0 host
  9: USB2 ch1 host
 10: USB2 ch2 host
-11: USB2 ch3 host
 12: USB2 ch0 PHY
 13: USB2 ch1 PHY
 14: USB2 ch2 PHY
-15: USB2 ch3 PHY
 
 
 Peripheral clock
@@ -94,7 +92,6 @@ Peripheral clock
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
     "socionext,uniphier-ld4-peri-clock"  - for LD4 SoC.
     "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
     "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
@@ -102,6 +99,7 @@ Required properties:
     "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
     "socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
     "socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
+    "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
 - #clock-cells: should be 1.
 
 Example:
diff --git a/Documentation/devicetree/bindings/sound/atmel-classd.txt b/Documentation/devicetree/bindings/sound/atmel-classd.txt
index 549e701cb7a1..898551076382 100644
--- a/Documentation/devicetree/bindings/sound/atmel-classd.txt
+++ b/Documentation/devicetree/bindings/sound/atmel-classd.txt
@@ -13,13 +13,11 @@ Required properties:
         Must be "tx".
 - clock-names
         Tuple listing input clock names.
-        Required elements: "pclk", "gclk" and "aclk".
+        Required elements: "pclk" and "gclk".
 - clocks
         Please refer to clock-bindings.txt.
 - assigned-clocks
         Should be <&classd_gclk>.
-- assigned-clock-parents
-        Should be <&audio_pll_pmc>.
 
 Optional properties:
 - pinctrl-names, pinctrl-0
@@ -45,10 +43,9 @@ classd: classd@fc048000 {
                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
                         | AT91_XDMAC_DT_PERID(47))>;
                 dma-names = "tx";
-                clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
-                clock-names = "pclk", "gclk", "aclk";
+                clocks = <&classd_clk>, <&classd_gclk>;
+                clock-names = "pclk", "gclk";
                 assigned-clocks = <&classd_gclk>;
-                assigned-clock-parents = <&audio_pll_pmc>;
 
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_classd_default>;
diff --git a/MAINTAINERS b/MAINTAINERS
index 048586a2a9be..7be4129ec951 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12842,6 +12842,18 @@ F:	drivers/clocksource/arc_timer.c
 F:      drivers/tty/serial/arc_uart.c
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
 
+SYNOPSYS ARC HSDK SDP pll clock driver
+M:      Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:      Supported
+F:      drivers/clk/clk-hsdk-pll.c
+F:      Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
+
+SYNOPSYS ARC SDP clock driver
+M:      Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:      Supported
+F:      drivers/clk/axs10x/*
+F:      Documentation/devicetree/bindings/clock/snps,pll-clock.txt
+
 SYNOPSYS ARC SDP platform support
 M:      Alexey Brodkin <abrodkin@synopsys.com>
 S:      Supported
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 195da38cb9a2..6d870421a7a6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -26,6 +26,7 @@ config SOC_SAMA5D2
         select HAVE_AT91_USB_CLK
         select HAVE_AT91_H32MX
         select HAVE_AT91_GENERATED_CLK
+        select HAVE_AT91_AUDIO_PLL
         select PINCTRL_AT91PIO4
         help
           Select this if ou are using one of Atmel's SAMA5D2 family SoC.
@@ -125,6 +126,9 @@ config HAVE_AT91_H32MX
 config HAVE_AT91_GENERATED_CLK
         bool
 
+config HAVE_AT91_AUDIO_PLL
+        bool
+
 config SOC_SAM_V4_V5
         bool
 
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 68ca2d9fcd73..1c4e1aa6767e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -31,6 +31,13 @@ config COMMON_CLK_WM831X
 
 source "drivers/clk/versatile/Kconfig"
 
+config CLK_HSDK
+        bool "PLL Driver for HSDK platform"
+        depends on OF || COMPILE_TEST
+        ---help---
+          This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
+          control.
+
 config COMMON_CLK_MAX77686
         tristate "Clock driver for Maxim 77620/77686/77802 MFD"
         depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
@@ -39,10 +46,10 @@ config COMMON_CLK_MAX77686
           clock.
 
 config COMMON_CLK_RK808
-        tristate "Clock driver for RK808/RK818"
+        tristate "Clock driver for RK805/RK808/RK818"
         depends on MFD_RK808
         ---help---
-          This driver supports RK808 and RK818 crystal oscillator clock. These
+          This driver supports RK805, RK808 and RK818 crystal oscillator clock. These
           multi-function devices have two fixed-rate oscillators,
           clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
           by control register.
@@ -210,14 +217,14 @@ config COMMON_CLK_OXNAS
           Support for the OXNAS SoC Family clocks.
 
 config COMMON_CLK_VC5
-        tristate "Clock driver for IDT VersaClock5 devices"
+        tristate "Clock driver for IDT VersaClock 5,6 devices"
         depends on I2C
         depends on OF
         select REGMAP_I2C
         help
         ---help---
-          This driver supports the IDT VersaClock5 programmable clock
-          generator.
+          This driver supports the IDT VersaClock 5 and VersaClock 6
+          programmable clock generators.
 
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cd376b3fb47a..c99f363826f0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,8 +27,8 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o
 obj-$(CONFIG_ARCH_EFM32)                += clk-efm32gg.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)         += clk-gemini.o
 obj-$(CONFIG_ARCH_HIGHBANK)             += clk-highbank.o
+obj-$(CONFIG_CLK_HSDK)                  += clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)       += clk-max77686.o
-obj-$(CONFIG_ARCH_MB86S7X)              += clk-mb86s7x.o
 obj-$(CONFIG_ARCH_MOXART)               += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)              += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)               += clk-nspire.o
@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI514)          += clk-si514.o
 obj-$(CONFIG_COMMON_CLK_SI570)          += clk-si570.o
 obj-$(CONFIG_ARCH_STM32)                += clk-stm32f4.o
+obj-$(CONFIG_ARCH_STM32)                += clk-stm32h7.o
 obj-$(CONFIG_ARCH_TANGO)                += clk-tango4.o
 obj-$(CONFIG_CLK_TWL6040)               += clk-twl6040.o
 obj-$(CONFIG_ARCH_U300)                 += clk-u300.o
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 13e67bd35cff..c68947b65a4c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -6,6 +6,7 @@ obj-y += pmc.o sckc.o
 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
 obj-y += clk-system.o clk-peripheral.o clk-programmable.o
 
+obj-$(CONFIG_HAVE_AT91_AUDIO_PLL)       += clk-audio-pll.o
 obj-$(CONFIG_HAVE_AT91_UTMI)            += clk-utmi.o
 obj-$(CONFIG_HAVE_AT91_USB_CLK)         += clk-usb.o
 obj-$(CONFIG_HAVE_AT91_SMD)             += clk-smd.o
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
new file mode 100644
index 000000000000..da7bafcfbe70
--- /dev/null
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -0,0 +1,536 @@
+/*
+ *  Copyright (C) 2016 Atmel Corporation,
+ *                     Songjun Wu <songjun.wu@atmel.com>,
+ *                     Nicolas Ferre <nicolas.ferre@atmel.com>
+ *  Copyright (C) 2017 Free Electrons,
+ *                     Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
+ * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
+ * its own parent. PMC and PAD can then divide the FRAC rate to best match the
+ * asked rate.
+ *
+ * Traits of FRAC clock:
+ * enable - clk_enable writes nd, fracr parameters and enables PLL
+ * rate - rate is adjustable.
+ *        clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
+ * parent - fixed parent.  No clk_set_parent support
+ *
+ * Traits of PMC clock:
+ * enable - clk_enable writes qdpmc, and enables PMC output
+ * rate - rate is adjustable.
+ *        clk->rate = parent->rate / (qdpmc + 1)
+ * parent - fixed parent.  No clk_set_parent support
+ *
+ * Traits of PAD clock:
+ * enable - clk_enable writes divisors and enables PAD output
+ * rate - rate is adjustable.
+ *        clk->rate = parent->rate / (qdaudio * div))
+ * parent - fixed parent.  No clk_set_parent support
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/at91_pmc.h>
+#include <linux/of.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#define AUDIO_PLL_DIV_FRAC      BIT(22)
+#define AUDIO_PLL_ND_MAX        (AT91_PMC_AUDIO_PLL_ND_MASK >> \
+                                        AT91_PMC_AUDIO_PLL_ND_OFFSET)
+
+#define AUDIO_PLL_QDPAD(qd, div)        ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
+                                          AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
+                                         (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
+                                          AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
+
+#define AUDIO_PLL_QDPMC_MAX             (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
+                                                AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+
+#define AUDIO_PLL_FOUT_MIN      620000000UL
+#define AUDIO_PLL_FOUT_MAX      700000000UL
+
+struct clk_audio_frac {
+        struct clk_hw hw;
+        struct regmap *regmap;
+        u32 fracr;
+        u8 nd;
+};
+
+struct clk_audio_pad {
+        struct clk_hw hw;
+        struct regmap *regmap;
+        u8 qdaudio;
+        u8 div;
+};
+
+struct clk_audio_pmc {
+        struct clk_hw hw;
+        struct regmap *regmap;
+        u8 qdpmc;
+};
+
+#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
+#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
+#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
+
+static int clk_audio_pll_frac_enable(struct clk_hw *hw)
+{
+        struct clk_audio_frac *frac = to_clk_audio_frac(hw);
+
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_RESETN, 0);
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_RESETN,
+                           AT91_PMC_AUDIO_PLL_RESETN);
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
+                           AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
+
+        /*
+         * reset and enable have to be done in 2 separated writes
+         * for AT91_PMC_AUDIO_PLL0
+         */
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PLLEN |
+                           AT91_PMC_AUDIO_PLL_ND_MASK,
+                           AT91_PMC_AUDIO_PLL_PLLEN |
+                           AT91_PMC_AUDIO_PLL_ND(frac->nd));
+
+        return 0;
+}
+
+static int clk_audio_pll_pad_enable(struct clk_hw *hw)
+{
+        struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
+
+        regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
+                           AT91_PMC_AUDIO_PLL_QDPAD_MASK,
+                           AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
+        regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
+
+        return 0;
+}
+
+static int clk_audio_pll_pmc_enable(struct clk_hw *hw)
+{
+        struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
+
+        regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PMCEN |
+                           AT91_PMC_AUDIO_PLL_QDPMC_MASK,
+                           AT91_PMC_AUDIO_PLL_PMCEN |
+                           AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
+        return 0;
+}
+
+static void clk_audio_pll_frac_disable(struct clk_hw *hw)
+{
+        struct clk_audio_frac *frac = to_clk_audio_frac(hw);
+
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PLLEN, 0);
+        /* do it in 2 separated writes */
+        regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_RESETN, 0);
+}
+
+static void clk_audio_pll_pad_disable(struct clk_hw *hw)
+{
+        struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
+
+        regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PADEN, 0);
+}
+
+static void clk_audio_pll_pmc_disable(struct clk_hw *hw)
+{
+        struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
+
+        regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
+                           AT91_PMC_AUDIO_PLL_PMCEN, 0);
+}
+
+static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
+                                        unsigned long nd, unsigned long fracr)
+{
+        unsigned long long fr = (unsigned long long)parent_rate * fracr;
+
+        pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
+
+        fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
+
+        pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
+
+        return parent_rate * (nd + 1) + fr;
+}
+
+static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw,
+                                                    unsigned long parent_rate)
+{
+        struct clk_audio_frac *frac = to_clk_audio_frac(hw);
+        unsigned long fout;
+
+        fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
+
+        pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
+                 fout, frac->nd, (unsigned long)frac->fracr);
+
+        return fout;
+}
+
+static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
+                                                   unsigned long parent_rate)
+{
+        struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
+        unsigned long apad_rate = 0;
+
+        if (apad_ck->qdaudio && apad_ck->div)
+                apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
+
+        pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
+                 __func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
+
+        return apad_rate;
+}
+
+static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
+                                                   unsigned long parent_rate)
+{
+        struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
+        unsigned long apmc_rate = 0;
+
+        apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
+
+        pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
+                 apmc_rate, apmc_ck->qdpmc);
+
+        return apmc_rate;
+}
+
+static int clk_audio_pll_frac_compute_frac(unsigned long rate,
+                                           unsigned long parent_rate,
+                                           unsigned long *nd,
+                                           unsigned long *fracr)
+{
+        unsigned long long tmp, rem;
+
+        if (!rate)
+                return -EINVAL;
+
+        tmp = rate;
+        rem = do_div(tmp, parent_rate);
+        if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
+                return -EINVAL;
+
+        *nd = tmp - 1;
+
+        tmp = rem * AUDIO_PLL_DIV_FRAC;
+        tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
+        if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
+                return -EINVAL;
+
+        /* we can cast here as we verified the bounds just above */
+        *fracr = (unsigned long)tmp;
+
+        return 0;
+}
+
+static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
+                                             struct clk_rate_request *req)
+{
+        unsigned long fracr, nd;
+        int ret;
+
+        pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+                 req->rate, req->best_parent_rate);
+
+        req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX);
+
+        req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN);
+        req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX);
+
+        ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate,
+                                              &nd, &fracr);
+        if (ret)
+                return ret;
+
+        req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr);
+
+        req->best_parent_hw = clk_hw_get_parent(hw);
+
+        pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
+                 __func__, req->rate, nd, fracr);
+
+        return 0;
+}
+
+static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *parent_rate)
+{
+        struct clk_hw *pclk = clk_hw_get_parent(hw);
+        long best_rate = -EINVAL;
+        unsigned long best_parent_rate;
+        unsigned long tmp_qd;
+        u32 div;
+        long tmp_rate;
+        int tmp_diff;
+        int best_diff = -1;
+
+        pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+                 rate, *parent_rate);
+
+        /*
+         * Rate divisor is actually made of two different divisors, multiplied
+         * between themselves before dividing the rate.
+         * tmp_qd goes from 1 to 31 and div is either 2 or 3.
+         * In order to avoid testing twice the rate divisor (e.g. divisor 12 can
+         * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
+         * for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
+         * We cannot inverse it (condition div is 3 and tmp_qd is even) or we
+         * would miss some rate divisor that aren't reachable with div being 2
+         * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
+         * tmp_qd is even so we skip it because we think div 2 could make this
+         * rate divisor which isn't possible since tmp_qd has to be <= 31).
+         */
+        for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
+                for (div = 2; div <= 3; div++) {
+                        if (div == 2 && tmp_qd % 3 == 0)
+                                continue;
+
+                        best_parent_rate = clk_hw_round_rate(pclk,
+                                                        rate * tmp_qd * div);
+                        tmp_rate = best_parent_rate / (div * tmp_qd);
+                        tmp_diff = abs(rate - tmp_rate);
+
+                        if (best_diff < 0 || best_diff > tmp_diff) {
+                                *parent_rate = best_parent_rate;
+                                best_rate = tmp_rate;
+                                best_diff = tmp_diff;
+                        }
+                }
+
+        pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
+                 __func__, best_rate, best_parent_rate);
+
+        return best_rate;
+}
+
+static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *parent_rate)
+{
+        struct clk_hw *pclk = clk_hw_get_parent(hw);
+        long best_rate = -EINVAL;
+        unsigned long best_parent_rate = 0;
+        u32 tmp_qd = 0, div;
+        long tmp_rate;
+        int tmp_diff;
+        int best_diff = -1;
+
+        pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+                 rate, *parent_rate);
+
+        for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
+                best_parent_rate = clk_round_rate(pclk->clk, rate * div);
+                tmp_rate = best_parent_rate / div;
+                tmp_diff = abs(rate - tmp_rate);
+
+                if (best_diff < 0 || best_diff > tmp_diff) {
+                        *parent_rate = best_parent_rate;
+                        best_rate = tmp_rate;
+                        best_diff = tmp_diff;
+                        tmp_qd = div;
+                }
+        }
+
+        pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
+                 __func__, best_rate, *parent_rate, tmp_qd - 1);
+
+        return best_rate;
+}
+
+static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long parent_rate)
+{
+        struct clk_audio_frac *frac = to_clk_audio_frac(hw);
+        unsigned long fracr, nd;
+        int ret;
+
+        pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
+                 parent_rate);
+
+        if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
+                return -EINVAL;
+
+        ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
+        if (ret)
+                return ret;
+
+        frac->nd = nd;
+        frac->fracr = fracr;
+
+        return 0;
+}
+
+static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
+                                      unsigned long parent_rate)
+{
+        struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
+        u8 tmp_div;
+
+        pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+                 rate, parent_rate);
+
+        if (!rate)
+                return -EINVAL;
+
+        tmp_div = parent_rate / rate;
+        if (tmp_div % 3 == 0) {
+                apad_ck->qdaudio = tmp_div / 3;
+                apad_ck->div = 3;
+        } else {
+                apad_ck->qdaudio = tmp_div / 2;
+                apad_ck->div = 2;
+        }
+
+        return 0;
+}
+
+static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                      unsigned long parent_rate)
+{
+        struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
+
+        if (!rate)
+                return -EINVAL;
+
+        pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+                 rate, parent_rate);
+
+        apmc_ck->qdpmc = parent_rate / rate - 1;
+
+        return 0;
+}
+
+static const struct clk_ops audio_pll_frac_ops = {
+        .enable = clk_audio_pll_frac_enable,
+        .disable = clk_audio_pll_frac_disable,
+        .recalc_rate = clk_audio_pll_frac_recalc_rate,
+        .determine_rate = clk_audio_pll_frac_determine_rate,
+        .set_rate = clk_audio_pll_frac_set_rate,
+};
+
+static const struct clk_ops audio_pll_pad_ops = {
+        .enable = clk_audio_pll_pad_enable,
+        .disable = clk_audio_pll_pad_disable,
+        .recalc_rate = clk_audio_pll_pad_recalc_rate,
+        .round_rate = clk_audio_pll_pad_round_rate,
+        .set_rate = clk_audio_pll_pad_set_rate,
+};
+
+static const struct clk_ops audio_pll_pmc_ops = {
+        .enable = clk_audio_pll_pmc_enable,
+        .disable = clk_audio_pll_pmc_disable,
+        .recalc_rate = clk_audio_pll_pmc_recalc_rate,
+        .round_rate = clk_audio_pll_pmc_round_rate,
+        .set_rate = clk_audio_pll_pmc_set_rate,
+};
+
+static int of_sama5d2_clk_audio_pll_setup(struct device_node *np,
+                                          struct clk_init_data *init,
+                                          struct clk_hw *hw,
+                                          struct regmap **clk_audio_regmap)
+{
+        struct regmap *regmap;
+        const char *parent_names[1];
+        int ret;
+
+        regmap = syscon_node_to_regmap(of_get_parent(np));
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        init->name = np->name;
+        of_clk_parent_fill(np, parent_names, 1);
+        init->parent_names = parent_names;
+        init->num_parents = 1;
+
+        hw->init = init;
+        *clk_audio_regmap = regmap;
+
+        ret = clk_hw_register(NULL, hw);
+        if (ret)
+                return ret;
+
+        return of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+}
+
+static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
+{
+        struct clk_audio_frac *frac_ck;
+        struct clk_init_data init = {};
+
+        frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
+        if (!frac_ck)
+                return;
+
+        init.ops = &audio_pll_frac_ops;
+        init.flags = CLK_SET_RATE_GATE;
+
+        if (of_sama5d2_clk_audio_pll_setup(np, &init, &frac_ck->hw,
+                                           &frac_ck->regmap))
+                kfree(frac_ck);
+}
+
+static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
+{
+        struct clk_audio_pad *apad_ck;
+        struct clk_init_data init = {};
+
+        apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
+        if (!apad_ck)
+                return;
+
+        init.ops = &audio_pll_pad_ops;
+        init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+                CLK_SET_RATE_PARENT;
+
+        if (of_sama5d2_clk_audio_pll_setup(np, &init, &apad_ck->hw,
+                                           &apad_ck->regmap))
+                kfree(apad_ck);
+}
+
+static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
+{
+        struct clk_audio_pad *apmc_ck;
+        struct clk_init_data init = {};
+
+        apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
+        if (!apmc_ck)
+                return;
+
+        init.ops = &audio_pll_pmc_ops;
+        init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+                CLK_SET_RATE_PARENT;
+
+        if (of_sama5d2_clk_audio_pll_setup(np, &init, &apmc_ck->hw,
+                                           &apmc_ck->regmap))
+                kfree(apmc_ck);
+}
+
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
+               "atmel,sama5d2-clk-audio-pll-frac",
+               of_sama5d2_clk_audio_pll_frac_setup);
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
+               "atmel,sama5d2-clk-audio-pll-pad",
+               of_sama5d2_clk_audio_pll_pad_setup);
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
+               "atmel,sama5d2-clk-audio-pll-pmc",
+               of_sama5d2_clk_audio_pll_pmc_setup);
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index f0b7ae904ce2..33481368740e 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -26,6 +26,13 @@
 #define GENERATED_SOURCE_MAX    6
 #define GENERATED_MAX_DIV       255
 
+#define GCK_ID_SSC0             43
+#define GCK_ID_SSC1             44
+#define GCK_ID_I2S0             54
+#define GCK_ID_I2S1             55
+#define GCK_ID_CLASSD           59
+#define GCK_INDEX_DT_AUDIO_PLL  5
+
 struct clk_generated {
         struct clk_hw hw;
         struct regmap *regmap;
@@ -34,6 +41,7 @@ struct clk_generated {
         u32 id;
         u32 gckdiv;
         u8 parent_id;
+        bool audio_pll_allowed;
 };
 
 #define to_clk_generated(hw) \
@@ -99,21 +107,41 @@ clk_generated_recalc_rate(struct clk_hw *hw,
         return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
 }
 
+static void clk_generated_best_diff(struct clk_rate_request *req,
+                                    struct clk_hw *parent,
+                                    unsigned long parent_rate, u32 div,
+                                    int *best_diff, long *best_rate)
+{
+        unsigned long tmp_rate;
+        int tmp_diff;
+
+        if (!div)
+                tmp_rate = parent_rate;
+        else
+                tmp_rate = parent_rate / div;
+        tmp_diff = abs(req->rate - tmp_rate);
+
+        if (*best_diff < 0 || *best_diff > tmp_diff) {
+                *best_rate = tmp_rate;
+                *best_diff = tmp_diff;
+                req->best_parent_rate = parent_rate;
+                req->best_parent_hw = parent;
+        }
+}
+
 static int clk_generated_determine_rate(struct clk_hw *hw,
                                         struct clk_rate_request *req)
 {
         struct clk_generated *gck = to_clk_generated(hw);
         struct clk_hw *parent = NULL;
+        struct clk_rate_request req_parent = *req;
         long best_rate = -EINVAL;
-        unsigned long tmp_rate, min_rate;
+        unsigned long min_rate, parent_rate;
         int best_diff = -1;
-        int tmp_diff;
         int i;
+        u32 div;
 
-        for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
-                u32 div;
-                unsigned long parent_rate;
-
+        for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
                 parent = clk_hw_get_parent_by_index(hw, i);
                 if (!parent)
                         continue;
@@ -124,25 +152,43 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
                     (gck->range.max && min_rate > gck->range.max))
                         continue;
 
-                for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
-                        tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
-                        tmp_diff = abs(req->rate - tmp_rate);
+                div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
 
-                        if (best_diff < 0 || best_diff > tmp_diff) {
-                                best_rate = tmp_rate;
-                                best_diff = tmp_diff;
-                                req->best_parent_rate = parent_rate;
-                                req->best_parent_hw = parent;
-                        }
+                clk_generated_best_diff(req, parent, parent_rate, div,
+                                        &best_diff, &best_rate);
 
-                        if (!best_diff || tmp_rate < req->rate)
-                                break;
-                }
+                if (!best_diff)
+                        break;
+        }
+
+        /*
+         * The audio_pll rate can be modified, unlike the five others clocks
+         * that should never be altered.
+         * The audio_pll can technically be used by multiple consumers. However,
+         * with the rate locking, the first consumer to enable to clock will be
+         * the one definitely setting the rate of the clock.
+         * Since audio IPs are most likely to request the same rate, we enforce
+         * that the only clks able to modify gck rate are those of audio IPs.
+         */
+
+        if (!gck->audio_pll_allowed)
+                goto end;
+
+        parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
+        if (!parent)
+                goto end;
+
+        for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
+                req_parent.rate = req->rate * div;
+                __clk_determine_rate(parent, &req_parent);
+                clk_generated_best_diff(req, parent, req_parent.rate, div,
+                                        &best_diff, &best_rate);
 
                 if (!best_diff)
                         break;
         }
 
+end:
         pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
                  __func__, best_rate,
                  __clk_get_name((req->best_parent_hw)->clk),
@@ -252,7 +298,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
         init.ops = &generated_ops;
         init.parent_names = parent_names;
         init.num_parents = num_parents;
-        init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+        init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+                CLK_SET_RATE_PARENT;
 
         gck->id = id;
         gck->hw.init = &init;
@@ -284,6 +331,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
         struct device_node *gcknp;
         struct clk_range range = CLK_RANGE(0, 0);
         struct regmap *regmap;
+        struct clk_generated *gck;
 
         num_parents = of_clk_get_parent_count(np);
         if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
@@ -315,6 +363,21 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
                 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
                                                   parent_names, num_parents,
                                                   id, &range);
+
+                gck = to_clk_generated(hw);
+
+                if (of_device_is_compatible(np,
+                                            "atmel,sama5d2-clk-generated")) {
+                        if (gck->id == GCK_ID_SSC0 || gck->id == GCK_ID_SSC1 ||
+                            gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
+                            gck->id == GCK_ID_CLASSD)
+                                gck->audio_pll_allowed = true;
+                        else
+                                gck->audio_pll_allowed = false;
+                } else {
+                        gck->audio_pll_allowed = false;
+                }
+
                 if (IS_ERR(hw))
                         continue;
 
diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile
index 01996b871b06..d747deafbf1e 100644
--- a/drivers/clk/axs10x/Makefile
+++ b/drivers/clk/axs10x/Makefile
@@ -1 +1,2 @@
 obj-y += i2s_pll_clock.o
+obj-y += pll_clock.o
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
new file mode 100644
index 000000000000..25d8c240ddfb
--- /dev/null
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -0,0 +1,346 @@
+/*
+ * Synopsys AXS10X SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+
+/* PLL registers addresses */
+#define PLL_REG_IDIV    0x0
+#define PLL_REG_FBDIV   0x4
+#define PLL_REG_ODIV    0x8
+
+/*
+ * Bit fields of the PLL IDIV/FBDIV/ODIV registers:
+ *  ________________________________________________________________________
+ * |31                15|    14    |   13   |  12  |11         6|5         0|
+ * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
+ * |____________________|__________|________|______|____________|___________|
+ *
+ * Following macros determine the way of access to these registers
+ * They should be set up only using the macros.
+ * reg should be an u32 variable.
+ */
+
+#define PLL_REG_GET_LOW(reg)                    \
+        (((reg) & (0x3F << 0)) >> 0)
+#define PLL_REG_GET_HIGH(reg)                   \
+        (((reg) & (0x3F << 6)) >> 6)
+#define PLL_REG_GET_EDGE(reg)                   \
+        (((reg) & (BIT(12))) ? 1 : 0)
+#define PLL_REG_GET_BYPASS(reg)                 \
+        (((reg) & (BIT(13))) ? 1 : 0)
+#define PLL_REG_GET_NOUPD(reg)                  \
+        (((reg) & (BIT(14))) ? 1 : 0)
+#define PLL_REG_GET_PAD(reg)                    \
+        (((reg) & (0x1FFFF << 15)) >> 15)
+
+#define PLL_REG_SET_LOW(reg, value)             \
+        { reg |= (((value) & 0x3F) << 0); }
+#define PLL_REG_SET_HIGH(reg, value)            \
+        { reg |= (((value) & 0x3F) << 6); }
+#define PLL_REG_SET_EDGE(reg, value)            \
+        { reg |= (((value) & 0x01) << 12); }
+#define PLL_REG_SET_BYPASS(reg, value)          \
+        { reg |= (((value) & 0x01) << 13); }
+#define PLL_REG_SET_NOUPD(reg, value)           \
+        { reg |= (((value) & 0x01) << 14); }
+#define PLL_REG_SET_PAD(reg, value)             \
+        { reg |= (((value) & 0x1FFFF) << 15); }
+
+#define PLL_LOCK        BIT(0)
+#define PLL_ERROR       BIT(1)
+#define PLL_MAX_LOCK_TIME 100 /* 100 us */
+
+struct axs10x_pll_cfg {
+        u32 rate;
+        u32 idiv;
+        u32 fbdiv;
+        u32 odiv;
+};
+
+static const struct axs10x_pll_cfg arc_pll_cfg[] = {
+        { 33333333,  1, 1,  1 },
+        { 50000000,  1, 30, 20 },
+        { 75000000,  2, 45, 10 },
+        { 90000000,  2, 54, 10 },
+        { 100000000, 1, 30, 10 },
+        { 125000000, 2, 45, 6 },
+        {}
+};
+
+static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
+        { 25200000, 1, 84, 90 },
+        { 50000000, 1, 100, 54 },
+        { 74250000, 1, 44, 16 },
+        {}
+};
+
+struct axs10x_pll_clk {
+        struct clk_hw hw;
+        void __iomem *base;
+        void __iomem *lock;
+        const struct axs10x_pll_cfg *pll_cfg;
+        struct device *dev;
+};
+
+static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
+                                    u32 val)
+{
+        iowrite32(val, clk->base + reg);
+}
+
+static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
+{
+        return ioread32(clk->base + reg);
+}
+
+static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
+{
+        return container_of(hw, struct axs10x_pll_clk, hw);
+}
+
+static inline u32 axs10x_div_get_value(u32 reg)
+{
+        if (PLL_REG_GET_BYPASS(reg))
+                return 1;
+
+        return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
+}
+
+static inline u32 axs10x_encode_div(unsigned int id, int upd)
+{
+        u32 div = 0;
+
+        PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
+        PLL_REG_SET_HIGH(div, id >> 1);
+        PLL_REG_SET_EDGE(div, id % 2);
+        PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
+        PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
+
+        return div;
+}
+
+static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
+                                            unsigned long parent_rate)
+{
+        u64 rate;
+        u32 idiv, fbdiv, odiv;
+        struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
+
+        idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
+        fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
+        odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
+
+        rate = (u64)parent_rate * fbdiv;
+        do_div(rate, idiv * odiv);
+
+        return rate;
+}
+
+static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                  unsigned long *prate)
+{
+        int i;
+        long best_rate;
+        struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
+        const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
+
+        if (pll_cfg[0].rate == 0)
+                return -EINVAL;
+
+        best_rate = pll_cfg[0].rate;
+
+        for (i = 1; pll_cfg[i].rate != 0; i++) {
+                if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
+                        best_rate = pll_cfg[i].rate;
+        }
+
+        return best_rate;
+}
+
+static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+        int i;
+        struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
+        const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
+
+        for (i = 0; pll_cfg[i].rate != 0; i++) {
+                if (pll_cfg[i].rate == rate) {
+                        axs10x_pll_write(clk, PLL_REG_IDIV,
+                                         axs10x_encode_div(pll_cfg[i].idiv, 0));
+                        axs10x_pll_write(clk, PLL_REG_FBDIV,
+                                         axs10x_encode_div(pll_cfg[i].fbdiv, 0));
+                        axs10x_pll_write(clk, PLL_REG_ODIV,
+                                         axs10x_encode_div(pll_cfg[i].odiv, 1));
+
+                        /*
+                         * Wait until CGU relocks and check error status.
+                         * If after timeout CGU is unlocked yet return error
+                         */
+                        udelay(PLL_MAX_LOCK_TIME);
+                        if (!(ioread32(clk->lock) & PLL_LOCK))
+                                return -ETIMEDOUT;
+
+                        if (ioread32(clk->lock) & PLL_ERROR)
+                                return -EINVAL;
+
+                        return 0;
+                }
+        }
+
+        dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
+                        parent_rate);
+        return -EINVAL;
+}
+
+static const struct clk_ops axs10x_pll_ops = {
+        .recalc_rate = axs10x_pll_recalc_rate,
+        .round_rate = axs10x_pll_round_rate,
+        .set_rate = axs10x_pll_set_rate,
+};
+
+static int axs10x_pll_clk_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        const char *parent_name;
+        struct axs10x_pll_clk *pll_clk;
+        struct resource *mem;
+        struct clk_init_data init = { };
+        int ret;
+
+        pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
+        if (!pll_clk)
+                return -ENOMEM;
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pll_clk->base = devm_ioremap_resource(dev, mem);
+        if (IS_ERR(pll_clk->base))
+                return PTR_ERR(pll_clk->base);
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        pll_clk->lock = devm_ioremap_resource(dev, mem);
+        if (IS_ERR(pll_clk->lock))
+                return PTR_ERR(pll_clk->lock);
+
+        init.name = dev->of_node->name;
+        init.ops = &axs10x_pll_ops;
+        parent_name = of_clk_get_parent_name(dev->of_node, 0);
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+        pll_clk->hw.init = &init;
+        pll_clk->dev = dev;
+        pll_clk->pll_cfg = of_device_get_match_data(dev);
+
+        if (!pll_clk->pll_cfg) {
+                dev_err(dev, "No OF match data provided\n");
+                return -EINVAL;
+        }
+
+        ret = devm_clk_hw_register(dev, &pll_clk->hw);
+        if (ret) {
+                dev_err(dev, "failed to register %s clock\n", init.name);
+                return ret;
+        }
+
+        return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
+                        &pll_clk->hw);
+}
+
+static int axs10x_pll_clk_remove(struct platform_device *pdev)
+{
+        of_clk_del_provider(pdev->dev.of_node);
+        return 0;
+}
+
+static void __init of_axs10x_pll_clk_setup(struct device_node *node)
+{
+        const char *parent_name;
+        struct axs10x_pll_clk *pll_clk;
+        struct clk_init_data init = { };
+        int ret;
+
+        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+        if (!pll_clk)
+                return;
+
+        pll_clk->base = of_iomap(node, 0);
+        if (!pll_clk->base) {
+                pr_err("failed to map pll div registers\n");
+                goto err_free_pll_clk;
+        }
+
+        pll_clk->lock = of_iomap(node, 1);
+        if (!pll_clk->lock) {
+                pr_err("failed to map pll lock register\n");
+                goto err_unmap_base;
+        }
+
+        init.name = node->name;
+        init.ops = &axs10x_pll_ops;
+        parent_name = of_clk_get_parent_name(node, 0);
+        init.parent_names = &parent_name;
+        init.num_parents = parent_name ? 1 : 0;
+        pll_clk->hw.init = &init;
+        pll_clk->pll_cfg = arc_pll_cfg;
+
+        ret = clk_hw_register(NULL, &pll_clk->hw);
+        if (ret) {
+                pr_err("failed to register %s clock\n", node->name);
+                goto err_unmap_lock;
+        }
+
+        ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
+        if (ret) {
+                pr_err("failed to add hw provider for %s clock\n", node->name);
+                goto err_unregister_clk;
+        }
+
+        return;
+
+err_unregister_clk:
+        clk_hw_unregister(&pll_clk->hw);
+err_unmap_lock:
+        iounmap(pll_clk->lock);
+err_unmap_base:
+        iounmap(pll_clk->base);
+err_free_pll_clk:
+        kfree(pll_clk);
+}
+CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
+               of_axs10x_pll_clk_setup);
+
+static const struct of_device_id axs10x_pll_clk_id[] = {
+        { .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
+        { }
+};
+MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
+
+static struct platform_driver axs10x_pll_clk_driver = {
+        .driver = {
+                .name = "axs10x-pll-clock",
+                .of_match_table = axs10x_pll_clk_id,
+        },
+        .probe = axs10x_pll_clk_probe,
+        .remove = axs10x_pll_clk_remove,
+};
+builtin_platform_driver(axs10x_pll_clk_driver);
+
+MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
+MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index 1d99292e2039..e7331ace0337 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -679,8 +679,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
                 if (!IS_ERR(hws[n]))
                         continue;
 
-                pr_err("%s: Unable to register leaf clock %d\n",
-                       np->full_name, n);
+                pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
                 goto bg2_fail;
         }
 
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 3b784b593afd..67c270b143f7 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -304,14 +304,14 @@ static void __init berlin2q_clock_setup(struct device_node *np)
 
         gbase = of_iomap(parent_np, 0);
         if (!gbase) {
-                pr_err("%s: Unable to map global base\n", np->full_name);
+                pr_err("%pOF: Unable to map global base\n", np);
                 return;
         }
 
         /* BG2Q CPU PLL is not part of global registers */
         cpupll_base = of_iomap(parent_np, 1);
         if (!cpupll_base) {
-                pr_err("%s: Unable to map cpupll base\n", np->full_name);
+                pr_err("%pOF: Unable to map cpupll base\n", np);
                 iounmap(gbase);
                 return;
         }
@@ -376,8 +376,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
                 if (!IS_ERR(hws[n]))
                         continue;
 
-                pr_err("%s: Unable to register leaf clock %d\n",
-                       np->full_name, n);
+                pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
                 goto bg2q_fail;
         }
 
diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c
index ea8568536193..bf0582cbbf38 100644
--- a/drivers/clk/clk-asm9260.c
+++ b/drivers/clk/clk-asm9260.c
@@ -338,8 +338,8 @@ static void __init asm9260_acc_init(struct device_node *np)
                 if (!IS_ERR(hws[n]))
                         continue;
 
-                pr_err("%s: Unable to register leaf clock %d\n",
-                                np->full_name, n);
+                pr_err("%pOF: Unable to register leaf clock %d\n",
+                                np, n);
                 goto fail;
         }
 
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 7ec36722f8ab..49819b546134 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -23,8 +23,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
         num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
                                                  "#clock-cells");
         if (num_parents == -EINVAL)
-                pr_err("clk: invalid value of clock-parents property at %s\n",
-                       node->full_name);
+                pr_err("clk: invalid value of clock-parents property at %pOF\n",
+                       node);
 
         for (index = 0; index < num_parents; index++) {
                 rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
@@ -41,8 +41,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
                 pclk = of_clk_get_from_provider(&clkspec);
                 if (IS_ERR(pclk)) {
                         if (PTR_ERR(pclk) != -EPROBE_DEFER)
-                                pr_warn("clk: couldn't get parent clock %d for %s\n",
-                                        index, node->full_name);
+                                pr_warn("clk: couldn't get parent clock %d for %pOF\n",
+                                        index, node);
                         return PTR_ERR(pclk);
                 }
 
@@ -57,8 +57,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
                 clk = of_clk_get_from_provider(&clkspec);
                 if (IS_ERR(clk)) {
                         if (PTR_ERR(clk) != -EPROBE_DEFER)
-                                pr_warn("clk: couldn't get assigned clock %d for %s\n",
-                                        index, node->full_name);
+                                pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
+                                        index, node);
                         rc = PTR_ERR(clk);
                         goto err;
                 }
@@ -102,8 +102,8 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
                         clk = of_clk_get_from_provider(&clkspec);
                         if (IS_ERR(clk)) {
                                 if (PTR_ERR(clk) != -EPROBE_DEFER)
-                                        pr_warn("clk: couldn't get clock %d for %s\n",
-                                                index, node->full_name);
+                                        pr_warn("clk: couldn't get clock %d for %pOF\n",
+                                                index, node);
                                 return PTR_ERR(clk);
                         }
 
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index c54baede4d68..e8ea81c30f0c 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -343,6 +343,15 @@ static int cs2000_set_rate(struct clk_hw *hw,
         return __cs2000_set_rate(priv, ch, rate, parent_rate);
 }
 
+static int cs2000_set_saved_rate(struct cs2000_priv *priv)
+{
+        int ch = 0; /* it uses ch0 only at this point */
+
+        return __cs2000_set_rate(priv, ch,
+                                 priv->saved_rate,
+                                 priv->saved_parent_rate);
+}
+
 static int cs2000_enable(struct clk_hw *hw)
 {
         struct cs2000_priv *priv = hw_to_priv(hw);
@@ -535,11 +544,8 @@ probe_err:
 static int cs2000_resume(struct device *dev)
 {
         struct cs2000_priv *priv = dev_get_drvdata(dev);
-        int ch = 0; /* it uses ch0 only at this point */
 
-        return __cs2000_set_rate(priv, ch,
-                                 priv->saved_rate,
-                                 priv->saved_parent_rate);
+        return cs2000_set_saved_rate(priv);
 }
 
 static const struct dev_pm_ops cs2000_pm_ops = {
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 9bb472cccca6..4ed516cb7276 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long parent_rate)
 {
         struct clk_divider *divider = to_clk_divider(hw);
-        unsigned int value;
+        int value;
         unsigned long flags = 0;
         u32 val;
 
         value = divider_get_val(rate, parent_rate, divider->table,
                                 divider->width, divider->flags);
+        if (value < 0)
+                return value;
 
         if (divider->lock)
                 spin_lock_irqsave(divider->lock, flags);
@@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
                 val = clk_readl(divider->reg);
                 val &= ~(div_mask(divider->width) << divider->shift);
         }
-        val |= value << divider->shift;
+        val |= (u32)value << divider->shift;
         clk_writel(val, divider->reg);
 
         if (divider->lock)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index aab904618eb6..fdf625fb10fa 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
         return ret;
 }
 
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
-                              unsigned long *parent_rate)
+static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *parent_rate,
+                                         unsigned long *m, unsigned long *n)
 {
         struct clk_fractional_divider *fd = to_clk_fd(hw);
         unsigned long scale;
-        unsigned long m, n;
-        u64 ret;
-
-        if (!rate || rate >= *parent_rate)
-                return *parent_rate;
 
         /*
          * Get rate closer to *parent_rate to guarantee there is no overflow
@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 
         rational_best_approximation(rate, *parent_rate,
                         GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
-                        &m, &n);
+                        m, n);
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *parent_rate)
+{
+        struct clk_fractional_divider *fd = to_clk_fd(hw);
+        unsigned long m, n;
+        u64 ret;
+
+        if (!rate || rate >= *parent_rate)
+                return *parent_rate;
+
+        if (fd->approximation)
+                fd->approximation(hw, rate, parent_rate, &m, &n);
+        else
+                clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
 
         ret = (u64)*parent_rate * m;
         do_div(ret, n);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 4e0c054a787c..dd82485e09a1 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -86,7 +86,7 @@ static void clk_gate_disable(struct clk_hw *hw)
         clk_gate_endisable(hw, 0);
 }
 
-static int clk_gate_is_enabled(struct clk_hw *hw)
+int clk_gate_is_enabled(struct clk_hw *hw)
 {
         u32 reg;
         struct clk_gate *gate = to_clk_gate(hw);
@@ -101,6 +101,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 
         return reg ? 1 : 0;
 }
+EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
 
 const struct clk_ops clk_gate_ops = {
         .enable = clk_gate_enable,
diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c
index b4cf2f699a21..f940e5af845b 100644
--- a/drivers/clk/clk-gemini.c
+++ b/drivers/clk/clk-gemini.c
@@ -37,7 +37,6 @@ static DEFINE_SPINLOCK(gemini_clk_lock);
 
 #define GEMINI_GLOBAL_MISC_CONTROL      0x30
 #define PCI_CLK_66MHZ                   BIT(18)
-#define PCI_CLK_OE                      BIT(17)
 
 #define GEMINI_GLOBAL_CLOCK_CONTROL     0x34
 #define PCI_CLKRUN_EN                   BIT(16)
@@ -159,9 +158,6 @@ static int gemini_pci_enable(struct clk_hw *hw)
 
         regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
                            0, PCI_CLKRUN_EN);
-        regmap_update_bits(pciclk->map,
-                           GEMINI_GLOBAL_MISC_CONTROL,
-                           0, PCI_CLK_OE);
         return 0;
 }
 
@@ -169,9 +165,6 @@ static void gemini_pci_disable(struct clk_hw *hw)
 {
         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 
-        regmap_update_bits(pciclk->map,
-                           GEMINI_GLOBAL_MISC_CONTROL,
-                           PCI_CLK_OE, 0);
         regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
                            PCI_CLKRUN_EN, 0);
 }
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
new file mode 100644
index 000000000000..bbf237173b37
--- /dev/null
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -0,0 +1,431 @@
+/*
+ * Synopsys HSDK SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define CGU_PLL_CTRL    0x000 /* ARC PLL control register */
+#define CGU_PLL_STATUS  0x004 /* ARC PLL status register */
+#define CGU_PLL_FMEAS   0x008 /* ARC PLL frequency measurement register */
+#define CGU_PLL_MON     0x00C /* ARC PLL monitor register */
+
+#define CGU_PLL_CTRL_ODIV_SHIFT         2
+#define CGU_PLL_CTRL_IDIV_SHIFT         4
+#define CGU_PLL_CTRL_FBDIV_SHIFT        9
+#define CGU_PLL_CTRL_BAND_SHIFT         20
+
+#define CGU_PLL_CTRL_ODIV_MASK          GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
+#define CGU_PLL_CTRL_IDIV_MASK          GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
+#define CGU_PLL_CTRL_FBDIV_MASK         GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
+
+#define CGU_PLL_CTRL_PD                 BIT(0)
+#define CGU_PLL_CTRL_BYPASS             BIT(1)
+
+#define CGU_PLL_STATUS_LOCK             BIT(0)
+#define CGU_PLL_STATUS_ERR              BIT(1)
+
+#define HSDK_PLL_MAX_LOCK_TIME          100 /* 100 us */
+
+#define CGU_PLL_SOURCE_MAX              1
+
+#define CORE_IF_CLK_THRESHOLD_HZ        500000000
+#define CREG_CORE_IF_CLK_DIV_1          0x0
+#define CREG_CORE_IF_CLK_DIV_2          0x1
+
+struct hsdk_pll_cfg {
+        u32 rate;
+        u32 idiv;
+        u32 fbdiv;
+        u32 odiv;
+        u32 band;
+};
+
+static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
+        { 100000000,  0, 11, 3, 0 },
+        { 133000000,  0, 15, 3, 0 },
+        { 200000000,  1, 47, 3, 0 },
+        { 233000000,  1, 27, 2, 0 },
+        { 300000000,  1, 35, 2, 0 },
+        { 333000000,  1, 39, 2, 0 },
+        { 400000000,  1, 47, 2, 0 },
+        { 500000000,  0, 14, 1, 0 },
+        { 600000000,  0, 17, 1, 0 },
+        { 700000000,  0, 20, 1, 0 },
+        { 800000000,  0, 23, 1, 0 },
+        { 900000000,  1, 26, 0, 0 },
+        { 1000000000, 1, 29, 0, 0 },
+        { 1100000000, 1, 32, 0, 0 },
+        { 1200000000, 1, 35, 0, 0 },
+        { 1300000000, 1, 38, 0, 0 },
+        { 1400000000, 1, 41, 0, 0 },
+        { 1500000000, 1, 44, 0, 0 },
+        { 1600000000, 1, 47, 0, 0 },
+        {}
+};
+
+static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
+        { 297000000,  0, 21, 2, 0 },
+        { 540000000,  0, 19, 1, 0 },
+        { 594000000,  0, 21, 1, 0 },
+        {}
+};
+
+struct hsdk_pll_clk {
+        struct clk_hw hw;
+        void __iomem *regs;
+        void __iomem *spec_regs;
+        const struct hsdk_pll_devdata *pll_devdata;
+        struct device *dev;
+};
+
+struct hsdk_pll_devdata {
+        const struct hsdk_pll_cfg *pll_cfg;
+        int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
+                           const struct hsdk_pll_cfg *cfg);
+};
+
+static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
+                                     const struct hsdk_pll_cfg *);
+static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
+                                     const struct hsdk_pll_cfg *);
+
+static const struct hsdk_pll_devdata core_pll_devdata = {
+        .pll_cfg = asdt_pll_cfg,
+        .update_rate = hsdk_pll_core_update_rate,
+};
+
+static const struct hsdk_pll_devdata sdt_pll_devdata = {
+        .pll_cfg = asdt_pll_cfg,
+        .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static const struct hsdk_pll_devdata hdmi_pll_devdata = {
+        .pll_cfg = hdmi_pll_cfg,
+        .update_rate = hsdk_pll_comm_update_rate,
+};
+
+static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
+{
+        iowrite32(val, clk->regs + reg);
+}
+
+static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
+{
+        return ioread32(clk->regs + reg);
+}
+
+static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
+                                    const struct hsdk_pll_cfg *cfg)
+{
+        u32 val = 0;
+
+        /* Powerdown and Bypass bits should be cleared */
+        val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+        val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+        val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+        val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+
+        dev_dbg(clk->dev, "write configurarion: %#x\n", val);
+
+        hsdk_pll_write(clk, CGU_PLL_CTRL, val);
+}
+
+static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
+{
+        return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
+}
+
+static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
+{
+        return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
+}
+
+static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
+{
+        return container_of(hw, struct hsdk_pll_clk, hw);
+}
+
+static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
+                                          unsigned long parent_rate)
+{
+        u32 val;
+        u64 rate;
+        u32 idiv, fbdiv, odiv;
+        struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
+
+        val = hsdk_pll_read(clk, CGU_PLL_CTRL);
+
+        dev_dbg(clk->dev, "current configurarion: %#x\n", val);
+
+        /* Check if PLL is disabled */
+        if (val & CGU_PLL_CTRL_PD)
+                return 0;
+
+        /* Check if PLL is bypassed */
+        if (val & CGU_PLL_CTRL_BYPASS)
+                return parent_rate;
+
+        /* input divider = reg.idiv + 1 */
+        idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
+        /* fb divider = 2*(reg.fbdiv + 1) */
+        fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
+        /* output divider = 2^(reg.odiv) */
+        odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
+
+        rate = (u64)parent_rate * fbdiv;
+        do_div(rate, idiv * odiv);
+
+        return rate;
+}
+
+static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        int i;
+        unsigned long best_rate;
+        struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
+        const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+        if (pll_cfg[0].rate == 0)
+                return -EINVAL;
+
+        best_rate = pll_cfg[0].rate;
+
+        for (i = 1; pll_cfg[i].rate != 0; i++) {
+                if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
+                        best_rate = pll_cfg[i].rate;
+        }
+
+        dev_dbg(clk->dev, "chosen best rate: %lu\n", best_rate);
+
+        return best_rate;
+}
+
+static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
+                                     unsigned long rate,
+                                     const struct hsdk_pll_cfg *cfg)
+{
+        hsdk_pll_set_cfg(clk, cfg);
+
+        /*
+         * Wait until CGU relocks and check error status.
+         * If after timeout CGU is unlocked yet return error.
+         */
+        udelay(HSDK_PLL_MAX_LOCK_TIME);
+        if (!hsdk_pll_is_locked(clk))
+                return -ETIMEDOUT;
+
+        if (hsdk_pll_is_err(clk))
+                return -EINVAL;
+
+        return 0;
+}
+
+static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
+                                     unsigned long rate,
+                                     const struct hsdk_pll_cfg *cfg)
+{
+        /*
+         * When core clock exceeds 500MHz, the divider for the interface
+         * clock must be programmed to div-by-2.
+         */
+        if (rate > CORE_IF_CLK_THRESHOLD_HZ)
+                iowrite32(CREG_CORE_IF_CLK_DIV_2, clk->spec_regs);
+
+        hsdk_pll_set_cfg(clk, cfg);
+
+        /*
+         * Wait until CGU relocks and check error status.
+         * If after timeout CGU is unlocked yet return error.
+         */
+        udelay(HSDK_PLL_MAX_LOCK_TIME);
+        if (!hsdk_pll_is_locked(clk))
+                return -ETIMEDOUT;
+
+        if (hsdk_pll_is_err(clk))
+                return -EINVAL;
+
+        /*
+         * Program divider to div-by-1 if we succesfuly set core clock below
+         * 500MHz threshold.
+         */
+        if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
+                iowrite32(CREG_CORE_IF_CLK_DIV_1, clk->spec_regs);
+
+        return 0;
+}
+
+static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                             unsigned long parent_rate)
+{
+        int i;
+        struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
+        const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+
+        for (i = 0; pll_cfg[i].rate != 0; i++) {
+                if (pll_cfg[i].rate == rate) {
+                        return clk->pll_devdata->update_rate(clk, rate,
+                                                             &pll_cfg[i]);
+                }
+        }
+
+        dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
+                        parent_rate);
+
+        return -EINVAL;
+}
+
+static const struct clk_ops hsdk_pll_ops = {
+        .recalc_rate = hsdk_pll_recalc_rate,
+        .round_rate = hsdk_pll_round_rate,
+        .set_rate = hsdk_pll_set_rate,
+};
+
+static int hsdk_pll_clk_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct resource *mem;
+        const char *parent_name;
+        unsigned int num_parents;
+        struct hsdk_pll_clk *pll_clk;
+        struct clk_init_data init = { };
+        struct device *dev = &pdev->dev;
+
+        pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
+        if (!pll_clk)
+                return -ENOMEM;
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pll_clk->regs = devm_ioremap_resource(dev, mem);
+        if (IS_ERR(pll_clk->regs))
+                return PTR_ERR(pll_clk->regs);
+
+        init.name = dev->of_node->name;
+        init.ops = &hsdk_pll_ops;
+        parent_name = of_clk_get_parent_name(dev->of_node, 0);
+        init.parent_names = &parent_name;
+        num_parents = of_clk_get_parent_count(dev->of_node);
+        if (num_parents == 0 || num_parents > CGU_PLL_SOURCE_MAX) {
+                dev_err(dev, "wrong clock parents number: %u\n", num_parents);
+                return -EINVAL;
+        }
+        init.num_parents = num_parents;
+
+        pll_clk->hw.init = &init;
+        pll_clk->dev = dev;
+        pll_clk->pll_devdata = of_device_get_match_data(dev);
+
+        if (!pll_clk->pll_devdata) {
+                dev_err(dev, "No OF match data provided\n");
+                return -EINVAL;
+        }
+
+        ret = devm_clk_hw_register(dev, &pll_clk->hw);
+        if (ret) {
+                dev_err(dev, "failed to register %s clock\n", init.name);
+                return ret;
+        }
+
+        return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
+                        &pll_clk->hw);
+}
+
+static int hsdk_pll_clk_remove(struct platform_device *pdev)
+{
+        of_clk_del_provider(pdev->dev.of_node);
+        return 0;
+}
+
+static void __init of_hsdk_pll_clk_setup(struct device_node *node)
+{
+        int ret;
+        const char *parent_name;
+        unsigned int num_parents;
+        struct hsdk_pll_clk *pll_clk;
+        struct clk_init_data init = { };
+
+        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+        if (!pll_clk)
+                return;
+
+        pll_clk->regs = of_iomap(node, 0);
+        if (!pll_clk->regs) {
+                pr_err("failed to map pll registers\n");
+                goto err_free_pll_clk;
+        }
+
+        pll_clk->spec_regs = of_iomap(node, 1);
+        if (!pll_clk->spec_regs) {
+                pr_err("failed to map pll registers\n");
+                goto err_unmap_comm_regs;
+        }
+
+        init.name = node->name;
+        init.ops = &hsdk_pll_ops;
+        parent_name = of_clk_get_parent_name(node, 0);
+        init.parent_names = &parent_name;
+        num_parents = of_clk_get_parent_count(node);
+        if (num_parents > CGU_PLL_SOURCE_MAX) {
+                pr_err("too much clock parents: %u\n", num_parents);
+                goto err_unmap_spec_regs;
+        }
+        init.num_parents = num_parents;
+
+        pll_clk->hw.init = &init;
+        pll_clk->pll_devdata = &core_pll_devdata;
+
+        ret = clk_hw_register(NULL, &pll_clk->hw);
+        if (ret) {
+                pr_err("failed to register %s clock\n", node->name);
+                goto err_unmap_spec_regs;
+        }
+
+        ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
+        if (ret) {
+                pr_err("failed to add hw provider for %s clock\n", node->name);
+                goto err_unmap_spec_regs;
+        }
+
+        return;
+
+err_unmap_spec_regs:
+        iounmap(pll_clk->spec_regs);
+err_unmap_comm_regs:
+        iounmap(pll_clk->regs);
+err_free_pll_clk:
+        kfree(pll_clk);
+}
+
+/* Core PLL needed early for ARC cpus timers */
+CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
+of_hsdk_pll_clk_setup);
+
+static const struct of_device_id hsdk_pll_clk_id[] = {
+        { .compatible = "snps,hsdk-gp-pll-clock", .data = &sdt_pll_devdata},
+        { .compatible = "snps,hsdk-hdmi-pll-clock", .data = &hdmi_pll_devdata},
+        { }
+};
+
+static struct platform_driver hsdk_pll_clk_driver = {
+        .driver = {
+                .name = "hsdk-gp-pll-clock",
+                .of_match_table = hsdk_pll_clk_id,
+        },
+        .probe = hsdk_pll_clk_probe,
+        .remove = hsdk_pll_clk_remove,
+};
+builtin_platform_driver(hsdk_pll_clk_driver);
diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
deleted file mode 100644
index 2a83a3ff1d09..000000000000
--- a/drivers/clk/clk-mb86s7x.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
- * Copyright (C) 2015 Linaro Ltd.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clkdev.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/cpu.h>
-#include <linux/clk-provider.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/topology.h>
-#include <linux/mailbox_client.h>
-#include <linux/platform_device.h>
-
-#include <soc/mb86s7x/scb_mhu.h>
-
-#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
-#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
-
-struct mb86s7x_peri_clk {
-        u32 payload_size;
-        u32 cntrlr;
-        u32 domain;
-        u32 port;
-        u32 en;
-        u64 frequency;
-} __packed __aligned(4);
-
-struct hack_rate {
-        unsigned clk_id;
-        unsigned long rate;
-        int gated;
-};
-
-struct crg_clk {
-        struct clk_hw hw;
-        u8 cntrlr, domain, port;
-};
-
-static int crg_gate_control(struct clk_hw *hw, int en)
-{
-        struct crg_clk *crgclk = to_crg_clk(hw);
-        struct mb86s7x_peri_clk cmd;
-        int ret;
-
-        cmd.payload_size = sizeof(cmd);
-        cmd.cntrlr = crgclk->cntrlr;
-        cmd.domain = crgclk->domain;
-        cmd.port = crgclk->port;
-        cmd.en = en;
-
-        /* Port is UngatedCLK */
-        if (cmd.port == 8)
-                return en ? 0 : -EINVAL;
-
-        pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
-                 __func__, __LINE__, cmd.cntrlr,
-                 cmd.domain, cmd.port, cmd.en);
-
-        ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
-                                  &cmd, sizeof(cmd));
-        if (ret < 0) {
-                pr_err("%s:%d failed!\n", __func__, __LINE__);
-                return ret;
-        }
-
-        pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
-                 __func__, __LINE__, cmd.cntrlr,
-                 cmd.domain, cmd.port, cmd.en);
-
-        /* If the request was rejected */
-        if (cmd.en != en)
-                ret = -EINVAL;
-        else
-                ret = 0;
-
-        return ret;
-}
-
-static int crg_port_prepare(struct clk_hw *hw)
-{
-        return crg_gate_control(hw, 1);
-}
-
-static void crg_port_unprepare(struct clk_hw *hw)
-{
-        crg_gate_control(hw, 0);
-}
-
-static int
-crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
-{
-        struct crg_clk *crgclk = to_crg_clk(hw);
-        struct mb86s7x_peri_clk cmd;
-        int code, ret;
-
-        cmd.payload_size = sizeof(cmd);
-        cmd.cntrlr = crgclk->cntrlr;
-        cmd.domain = crgclk->domain;
-        cmd.port = crgclk->port;
-        cmd.frequency = *rate;
-
-        if (set) {
-                code = CMD_PERI_CLOCK_RATE_SET_REQ;
-                pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
-                         __func__, __LINE__, cmd.cntrlr,
-                         cmd.domain, cmd.port, cmd.frequency);
-        } else {
-                code = CMD_PERI_CLOCK_RATE_GET_REQ;
-                pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
-                         __func__, __LINE__, cmd.cntrlr,
-                         cmd.domain, cmd.port);
-        }
-
-        ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
-        if (ret < 0) {
-                pr_err("%s:%d failed!\n", __func__, __LINE__);
-                return ret;
-        }
-
-        if (set)
-                pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
-                         __func__, __LINE__, cmd.cntrlr,
-                         cmd.domain, cmd.port, cmd.frequency);
-        else
-                pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
-                         __func__, __LINE__, cmd.cntrlr,
-                         cmd.domain, cmd.port, cmd.frequency);
-
-        *rate = cmd.frequency;
-        return 0;
-}
-
-static unsigned long
-crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-{
-        unsigned long rate;
-
-        crg_rate_control(hw, 0, &rate);
-
-        return rate;
-}
-
-static long
-crg_port_round_rate(struct clk_hw *hw,
-                    unsigned long rate, unsigned long *pr)
-{
-        return rate;
-}
-
-static int
-crg_port_set_rate(struct clk_hw *hw,
-                  unsigned long rate, unsigned long parent_rate)
-{
-        return crg_rate_control(hw, 1, &rate);
-}
-
-const struct clk_ops crg_port_ops = {
-        .prepare = crg_port_prepare,
-        .unprepare = crg_port_unprepare,
-        .recalc_rate = crg_port_recalc_rate,
-        .round_rate = crg_port_round_rate,
-        .set_rate = crg_port_set_rate,
-};
-
-struct mb86s70_crg11 {
-        struct mutex lock; /* protects CLK populating and searching */
-};
-
-static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
-{
-        struct mb86s70_crg11 *crg11 = data;
-        struct clk_init_data init;
-        u32 cntrlr, domain, port;
-        struct crg_clk *crgclk;
-        struct clk *clk;
-        char clkp[20];
-
-        if (clkspec->args_count != 3)
-                return ERR_PTR(-EINVAL);
-
-        cntrlr = clkspec->args[0];
-        domain = clkspec->args[1];
-        port = clkspec->args[2];
-
-        if (port > 7)
-                snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
-        else
-                snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
-
-        mutex_lock(&crg11->lock);
-
-        clk = __clk_lookup(clkp);
-        if (clk) {
-                mutex_unlock(&crg11->lock);
-                return clk;
-        }
-
-        crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
-        if (!crgclk) {
-                mutex_unlock(&crg11->lock);
-                return ERR_PTR(-ENOMEM);
-        }
-
-        init.name = clkp;
-        init.num_parents = 0;
-        init.ops = &crg_port_ops;
-        init.flags = 0;
-        crgclk->hw.init = &init;
-        crgclk->cntrlr = cntrlr;
-        crgclk->domain = domain;
-        crgclk->port = port;
-        clk = clk_register(NULL, &crgclk->hw);
-        if (IS_ERR(clk))
-                pr_err("%s:%d Error!\n", __func__, __LINE__);
-        else
-                pr_debug("Registered %s\n", clkp);
-
-        clk_register_clkdev(clk, clkp, NULL);
-        mutex_unlock(&crg11->lock);
-        return clk;
-}
-
-static void __init crg_port_init(struct device_node *node)
-{
-        struct mb86s70_crg11 *crg11;
-
-        crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
-        if (!crg11)
-                return;
-
-        mutex_init(&crg11->lock);
-
-        of_clk_add_provider(node, crg11_get, crg11);
-}
-CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
-
-struct cl_clk {
-        struct clk_hw hw;
-        int cluster;
-};
-
-struct mb86s7x_cpu_freq {
-        u32 payload_size;
-        u32 cluster_class;
-        u32 cluster_id;
-        u32 cpu_id;
-        u64 frequency;
-};
-
-static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
-{
-        struct cl_clk *clc = to_clc_clk(hw);
-        struct mb86s7x_cpu_freq cmd;
-        int code, ret;
-
-        cmd.payload_size = sizeof(cmd);
-        cmd.cluster_class = 0;
-        cmd.cluster_id = clc->cluster;
-        cmd.cpu_id = 0;
-        cmd.frequency = *rate;
-
-        if (get)
-                code = CMD_CPU_CLOCK_RATE_GET_REQ;
-        else
-                code = CMD_CPU_CLOCK_RATE_SET_REQ;
-
-        pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
-                 __func__, __LINE__, cmd.cluster_class,
-                 cmd.cluster_id, cmd.cpu_id, cmd.frequency);
-
-        ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
-        if (ret < 0) {
-                pr_err("%s:%d failed!\n", __func__, __LINE__);
-                return;
-        }
-
-        pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
-                 __func__, __LINE__, cmd.cluster_class,
-                 cmd.cluster_id, cmd.cpu_id, cmd.frequency);
-
-        *rate = cmd.frequency;
-}
-
-static unsigned long
-clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
-{
-        unsigned long rate;
-
-        mhu_cluster_rate(hw, &rate, 1);
-        return rate;
-}
-
-static long
-clc_round_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *unused)
-{
-        return rate;
-}
-
-static int
-clc_set_rate(struct clk_hw *hw, unsigned long rate,
-             unsigned long unused)
-{
-        unsigned long res = rate;
-
-        mhu_cluster_rate(hw, &res, 0);
-
-        return (res == rate) ? 0 : -EINVAL;
-}
-
-static struct clk_ops clk_clc_ops = {
-        .recalc_rate = clc_recalc_rate,
-        .round_rate = clc_round_rate,
-        .set_rate = clc_set_rate,
-};
-
-static struct clk_hw *mb86s7x_clclk_register(struct device *cpu_dev)
-{
-        struct clk_init_data init;
-        struct cl_clk *clc;
-        int ret;
-
-        clc = kzalloc(sizeof(*clc), GFP_KERNEL);
-        if (!clc)
-                return ERR_PTR(-ENOMEM);
-
-        clc->hw.init = &init;
-        clc->cluster = topology_physical_package_id(cpu_dev->id);
-
-        init.name = dev_name(cpu_dev);
-        init.ops = &clk_clc_ops;
-        init.flags = CLK_GET_RATE_NOCACHE;
-        init.num_parents = 0;
-
-        ret = devm_clk_hw_register(cpu_dev, &clc->hw);
-        if (ret)
-                return ERR_PTR(ret);
-        return &clc->hw;
-}
-
-static int mb86s7x_clclk_of_init(void)
-{
-        int cpu, ret = -ENODEV;
-        struct device_node *np;
-        struct clk_hw *hw;
-
-        np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
-        if (!np || !of_device_is_available(np))
-                goto exit;
-
-        for_each_possible_cpu(cpu) {
-                struct device *cpu_dev = get_cpu_device(cpu);
-
-                if (!cpu_dev) {
-                        pr_err("failed to get cpu%d device\n", cpu);
-                        continue;
-                }
-
-                hw = mb86s7x_clclk_register(cpu_dev);
-                if (IS_ERR(hw)) {
-                        pr_err("failed to register cpu%d clock\n", cpu);
-                        continue;
-                }
-                if (clk_hw_register_clkdev(hw, NULL, dev_name(cpu_dev))) {
-                        pr_err("failed to register cpu%d clock lookup\n", cpu);
-                        continue;
-                }
-                pr_debug("registered clk for %s\n", dev_name(cpu_dev));
-        }
-        ret = 0;
-
-        platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
-exit:
-        of_node_put(np);
-        return ret;
-}
-module_init(mb86s7x_clclk_of_init);
diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c
index b86dac851116..58428d0043fd 100644
--- a/drivers/clk/clk-moxart.c
+++ b/drivers/clk/clk-moxart.c
@@ -18,7 +18,7 @@
 
 static void __init moxart_of_pll_clk_init(struct device_node *node)
 {
-        static void __iomem *base;
+        void __iomem *base;
         struct clk_hw *hw;
         struct clk *ref_clk;
         unsigned int mul;
@@ -30,7 +30,7 @@ static void __init moxart_of_pll_clk_init(struct device_node *node)
 
         base = of_iomap(node, 0);
         if (!base) {
-                pr_err("%s: of_iomap failed\n", node->full_name);
+                pr_err("%pOF: of_iomap failed\n", node);
                 return;
         }
 
@@ -39,13 +39,13 @@ static void __init moxart_of_pll_clk_init(struct device_node *node)
 
         ref_clk = of_clk_get(node, 0);
         if (IS_ERR(ref_clk)) {
-                pr_err("%s: of_clk_get failed\n", node->full_name);
+                pr_err("%pOF: of_clk_get failed\n", node);
                 return;
         }
 
         hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
         if (IS_ERR(hw)) {
-                pr_err("%s: failed to register clock\n", node->full_name);
+                pr_err("%pOF: failed to register clock\n", node);
                 return;
         }
 
@@ -57,7 +57,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
 
 static void __init moxart_of_apb_clk_init(struct device_node *node)
 {
-        static void __iomem *base;
+        void __iomem *base;
         struct clk_hw *hw;
         struct clk *pll_clk;
         unsigned int div, val;
@@ -70,7 +70,7 @@ static void __init moxart_of_apb_clk_init(struct device_node *node)
 
         base = of_iomap(node, 0);
         if (!base) {
-                pr_err("%s: of_iomap failed\n", node->full_name);
+                pr_err("%pOF: of_iomap failed\n", node);
                 return;
         }
 
@@ -83,13 +83,13 @@ static void __init moxart_of_apb_clk_init(struct device_node *node)
 
         pll_clk = of_clk_get(node, 0);
         if (IS_ERR(pll_clk)) {
-                pr_err("%s: of_clk_get failed\n", node->full_name);
+                pr_err("%pOF: of_clk_get failed\n", node);
                 return;
         }
 
         hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
         if (IS_ERR(hw)) {
-                pr_err("%s: failed to register clock\n", node->full_name);
+                pr_err("%pOF: failed to register clock\n", node);
                 return;
         }
 
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index f3931e38fac0..b0ea753b8709 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/fsl/guts.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -537,6 +538,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
                 .flags = CG_PLL_8BIT,
         },
         {
+                .compat = "fsl,ls1088a-clockgen",
+                .cmux_groups = {
+                        &clockgen2_cmux_cga12
+                },
+                .cmux_to_group = {
+                        0, 0, -1
+                },
+                .pll_mask = 0x07,
+                .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+        },
+        {
                 .compat = "fsl,ls1012a-clockgen",
                 .cmux_groups = {
                         &ls1012a_cmux
@@ -1113,6 +1125,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 
         for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
                 struct clk *clk;
+                int ret;
 
                 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
                          "cg-pll%d-div%d", idx, i + 1);
@@ -1126,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
                 }
 
                 pll->div[i].clk = clk;
+                ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
+                if (ret != 0)
+                        pr_err("%s: %s: register to lookup table failed %ld\n",
+                               __func__, pll->div[i].name, PTR_ERR(clk));
+
         }
 }
 
@@ -1348,8 +1366,7 @@ static void __init clockgen_init(struct device_node *np)
         }
 
         if (i == ARRAY_SIZE(chipinfo)) {
-                pr_err("%s: unknown clockgen node %s\n", __func__,
-                       np->full_name);
+                pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
                 goto err;
         }
         clockgen.info = chipinfo[i];
@@ -1362,8 +1379,8 @@ static void __init clockgen_init(struct device_node *np)
                 if (guts) {
                         clockgen.guts = of_iomap(guts, 0);
                         if (!clockgen.guts) {
-                                pr_err("%s: Couldn't map %s regs\n", __func__,
-                                       guts->full_name);
+                                pr_err("%s: Couldn't map %pOF regs\n", __func__,
+                                       guts);
                         }
                 }
 
@@ -1398,6 +1415,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
 
 /* Legacy nodes */
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 2492442eea77..20d90769cced 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -519,6 +519,11 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                 SI5351_CLK_INTEGER_MODE,
                 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
 
+        /* Do a pll soft reset on the affected pll */
+        si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
+                         hwdata->num == 0 ? SI5351_PLL_RESET_A :
+                                            SI5351_PLL_RESET_B);
+
         dev_dbg(&hwdata->drvdata->client->dev,
                 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
                 __func__, clk_hw_get_name(hw),
@@ -1091,13 +1096,6 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
         si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
                         SI5351_CLK_POWERDOWN, 0);
 
-        /*
-         * Do a pll soft reset on both plls, needed in some cases to get
-         * all outputs running.
-         */
-        si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
-                         SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
-
         dev_dbg(&hwdata->drvdata->client->dev,
                 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
                 __func__, clk_hw_get_name(hw), (1 << rdiv),
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 68e2a4e499f1..96c6b6bc8f0e 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1541,8 +1541,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
                     base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
 
                 if (IS_ERR(clks[idx])) {
-                        pr_err("%s: Unable to register leaf clock %s\n",
-                               np->full_name, gd->name);
+                        pr_err("%pOF: Unable to register leaf clock %s\n",
+                               np, gd->name);
                         goto fail;
                 }
         }
diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
new file mode 100644
index 000000000000..a94c3f56c590
--- /dev/null
+++ b/drivers/clk/clk-stm32h7.c
@@ -0,0 +1,1410 @@
+/*
+ * Copyright (C) Gabriel Fernandez 2017
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/stm32h7-clks.h>
+
+/* Reset Clock Control Registers */
+#define RCC_CR          0x00
+#define RCC_CFGR        0x10
+#define RCC_D1CFGR      0x18
+#define RCC_D2CFGR      0x1C
+#define RCC_D3CFGR      0x20
+#define RCC_PLLCKSELR   0x28
+#define RCC_PLLCFGR     0x2C
+#define RCC_PLL1DIVR    0x30
+#define RCC_PLL1FRACR   0x34
+#define RCC_PLL2DIVR    0x38
+#define RCC_PLL2FRACR   0x3C
+#define RCC_PLL3DIVR    0x40
+#define RCC_PLL3FRACR   0x44
+#define RCC_D1CCIPR     0x4C
+#define RCC_D2CCIP1R    0x50
+#define RCC_D2CCIP2R    0x54
+#define RCC_D3CCIPR     0x58
+#define RCC_BDCR        0x70
+#define RCC_CSR         0x74
+#define RCC_AHB3ENR     0xD4
+#define RCC_AHB1ENR     0xD8
+#define RCC_AHB2ENR     0xDC
+#define RCC_AHB4ENR     0xE0
+#define RCC_APB3ENR     0xE4
+#define RCC_APB1LENR    0xE8
+#define RCC_APB1HENR    0xEC
+#define RCC_APB2ENR     0xF0
+#define RCC_APB4ENR     0xF4
+
+static DEFINE_SPINLOCK(stm32rcc_lock);
+
+static void __iomem *base;
+static struct clk_hw **hws;
+
+/* System clock parent */
+static const char * const sys_src[] = {
+        "hsi_ck", "csi_ck", "hse_ck", "pll1_p" };
+
+static const char * const tracein_src[] = {
+        "hsi_ck", "csi_ck", "hse_ck", "pll1_r" };
+
+static const char * const per_src[] = {
+        "hsi_ker", "csi_ker", "hse_ck", "disabled" };
+
+static const char * const pll_src[] = {
+        "hsi_ck", "csi_ck", "hse_ck", "no clock" };
+
+static const char * const sdmmc_src[] = { "pll1_q", "pll2_r" };
+
+static const char * const dsi_src[] = { "ck_dsi_phy", "pll2_q" };
+
+static const char * const qspi_src[] = {
+        "hclk", "pll1_q", "pll2_r", "per_ck" };
+
+static const char * const fmc_src[] = {
+        "hclk", "pll1_q", "pll2_r", "per_ck" };
+
+/* Kernel clock parent */
+static const char * const swp_src[] = { "pclk1", "hsi_ker" };
+
+static const char * const fdcan_src[] = { "hse_ck", "pll1_q", "pll2_q" };
+
+static const char * const dfsdm1_src[] = { "pclk2", "sys_ck" };
+
+static const char * const spdifrx_src[] = {
+        "pll1_q", "pll2_r", "pll3_r", "hsi_ker" };
+
+static const char *spi_src1[5] = {
+        "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
+
+static const char * const spi_src2[] = {
+        "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
+
+static const char * const spi_src3[] = {
+        "pclk4", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
+
+static const char * const lptim_src1[] = {
+        "pclk1", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
+
+static const char * const lptim_src2[] = {
+        "pclk4", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
+
+static const char * const cec_src[] = {"lse_ck", "lsi_ck", "csi_ker_div122" };
+
+static const char * const usbotg_src[] = {"pll1_q", "pll3_q", "rc48_ck" };
+
+/* i2c 1,2,3 src */
+static const char * const i2c_src1[] = {
+        "pclk1", "pll3_r", "hsi_ker", "csi_ker" };
+
+static const char * const i2c_src2[] = {
+        "pclk4", "pll3_r", "hsi_ker", "csi_ker" };
+
+static const char * const rng_src[] = {
+        "rc48_ck", "pll1_q", "lse_ck", "lsi_ck" };
+
+/* usart 1,6 src */
+static const char * const usart_src1[] = {
+        "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
+
+/* usart 2,3,4,5,7,8 src */
+static const char * const usart_src2[] = {
+        "pclk1", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
+
+static const char *sai_src[5] = {
+        "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
+
+static const char * const adc_src[] = { "pll2_p", "pll3_r", "per_ck" };
+
+/* lptim 2,3,4,5 src */
+static const char * const lpuart1_src[] = {
+        "pclk3", "pll2_q", "pll3_q", "csi_ker", "lse_ck" };
+
+static const char * const hrtim_src[] = { "tim2_ker", "d1cpre" };
+
+/* RTC clock parent */
+static const char * const rtc_src[] = { "off", "lse_ck", "lsi_ck", "hse_1M" };
+
+/* Micro-controller output clock parent */
+static const char * const mco_src1[] = {
+        "hsi_ck", "lse_ck", "hse_ck", "pll1_q", "rc48_ck" };
+
+static const char * const mco_src2[] = {
+        "sys_ck", "pll2_p", "hse_ck", "pll1_p", "csi_ck", "lsi_ck" };
+
+/* LCD clock */
+static const char * const ltdc_src[] = {"pll3_r"};
+
+/* Gate clock with ready bit and backup domain management */
+struct stm32_ready_gate {
+        struct  clk_gate gate;
+        u8      bit_rdy;
+};
+
+#define to_ready_gate_clk(_rgate) container_of(_rgate, struct stm32_ready_gate,\
+                gate)
+
+#define RGATE_TIMEOUT 10000
+
+static int ready_gate_clk_enable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = to_clk_gate(hw);
+        struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
+        int bit_status;
+        unsigned int timeout = RGATE_TIMEOUT;
+
+        if (clk_gate_ops.is_enabled(hw))
+                return 0;
+
+        clk_gate_ops.enable(hw);
+
+        /* We can't use readl_poll_timeout() because we can blocked if
+         * someone enables this clock before clocksource changes.
+         * Only jiffies counter is available. Jiffies are incremented by
+         * interruptions and enable op does not allow to be interrupted.
+         */
+        do {
+                bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy));
+
+                if (bit_status)
+                        udelay(100);
+
+        } while (bit_status && --timeout);
+
+        return bit_status;
+}
+
+static void ready_gate_clk_disable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = to_clk_gate(hw);
+        struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
+        int bit_status;
+        unsigned int timeout = RGATE_TIMEOUT;
+
+        if (!clk_gate_ops.is_enabled(hw))
+                return;
+
+        clk_gate_ops.disable(hw);
+
+        do {
+                bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy));
+
+                if (bit_status)
+                        udelay(100);
+
+        } while (bit_status && --timeout);
+}
+
+static const struct clk_ops ready_gate_clk_ops = {
+        .enable         = ready_gate_clk_enable,
+        .disable        = ready_gate_clk_disable,
+        .is_enabled     = clk_gate_is_enabled,
+};
+
+static struct clk_hw *clk_register_ready_gate(struct device *dev,
+                const char *name, const char *parent_name,
+                void __iomem *reg, u8 bit_idx, u8 bit_rdy,
+                unsigned long flags, spinlock_t *lock)
+{
+        struct stm32_ready_gate *rgate;
+        struct clk_init_data init = { NULL };
+        struct clk_hw *hw;
+        int ret;
+
+        rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
+        if (!rgate)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &ready_gate_clk_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        rgate->bit_rdy = bit_rdy;
+        rgate->gate.lock = lock;
+        rgate->gate.reg = reg;
+        rgate->gate.bit_idx = bit_idx;
+        rgate->gate.hw.init = &init;
+
+        hw = &rgate->gate.hw;
+        ret = clk_hw_register(dev, hw);
+        if (ret) {
+                kfree(rgate);
+                hw = ERR_PTR(ret);
+        }
+
+        return hw;
+}
+
+struct gate_cfg {
+        u32 offset;
+        u8  bit_idx;
+};
+
+struct muxdiv_cfg {
+        u32 offset;
+        u8 shift;
+        u8 width;
+};
+
+struct composite_clk_cfg {
+        struct gate_cfg *gate;
+        struct muxdiv_cfg *mux;
+        struct muxdiv_cfg *div;
+        const char *name;
+        const char * const *parent_name;
+        int num_parents;
+        u32 flags;
+};
+
+struct composite_clk_gcfg_t {
+        u8 flags;
+        const struct clk_ops *ops;
+};
+
+/*
+ * General config definition of a composite clock (only clock diviser for rate)
+ */
+struct composite_clk_gcfg {
+        struct composite_clk_gcfg_t *mux;
+        struct composite_clk_gcfg_t *div;
+        struct composite_clk_gcfg_t *gate;
+};
+
+#define M_CFG_MUX(_mux_ops, _mux_flags)\
+        .mux = &(struct composite_clk_gcfg_t) { _mux_flags, _mux_ops}
+
+#define M_CFG_DIV(_rate_ops, _rate_flags)\
+        .div = &(struct composite_clk_gcfg_t) {_rate_flags, _rate_ops}
+
+#define M_CFG_GATE(_gate_ops, _gate_flags)\
+        .gate = &(struct composite_clk_gcfg_t) { _gate_flags, _gate_ops}
+
+static struct clk_mux *_get_cmux(void __iomem *reg, u8 shift, u8 width,
+                u32 flags, spinlock_t *lock)
+{
+        struct clk_mux *mux;
+
+        mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+        if (!mux)
+                return ERR_PTR(-ENOMEM);
+
+        mux->reg        = reg;
+        mux->shift      = shift;
+        mux->mask       = (1 << width) - 1;
+        mux->flags      = flags;
+        mux->lock       = lock;
+
+        return mux;
+}
+
+static struct clk_divider *_get_cdiv(void __iomem *reg, u8 shift, u8 width,
+                u32 flags, spinlock_t *lock)
+{
+        struct clk_divider *div;
+
+        div = kzalloc(sizeof(*div), GFP_KERNEL);
+
+        if (!div)
+                return ERR_PTR(-ENOMEM);
+
+        div->reg   = reg;
+        div->shift = shift;
+        div->width = width;
+        div->flags = flags;
+        div->lock  = lock;
+
+        return div;
+}
+
+static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags,
+                spinlock_t *lock)
+{
+        struct clk_gate *gate;
+
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+        if (!gate)
+                return ERR_PTR(-ENOMEM);
+
+        gate->reg       = reg;
+        gate->bit_idx   = bit_idx;
+        gate->flags     = flags;
+        gate->lock      = lock;
+
+        return gate;
+}
+
+struct composite_cfg {
+        struct clk_hw *mux_hw;
+        struct clk_hw *div_hw;
+        struct clk_hw *gate_hw;
+
+        const struct clk_ops *mux_ops;
+        const struct clk_ops *div_ops;
+        const struct clk_ops *gate_ops;
+};
+
+static void get_cfg_composite_div(const struct composite_clk_gcfg *gcfg,
+                const struct composite_clk_cfg *cfg,
+                struct composite_cfg *composite, spinlock_t *lock)
+{
+        struct clk_mux     *mux = NULL;
+        struct clk_divider *div = NULL;
+        struct clk_gate    *gate = NULL;
+        const struct clk_ops *mux_ops, *div_ops, *gate_ops;
+        struct clk_hw *mux_hw;
+        struct clk_hw *div_hw;
+        struct clk_hw *gate_hw;
+
+        mux_ops = div_ops = gate_ops = NULL;
+        mux_hw = div_hw = gate_hw = NULL;
+
+        if (gcfg->mux && gcfg->mux) {
+                mux = _get_cmux(base + cfg->mux->offset,
+                                cfg->mux->shift,
+                                cfg->mux->width,
+                                gcfg->mux->flags, lock);
+
+                if (!IS_ERR(mux)) {
+                        mux_hw = &mux->hw;
+                        mux_ops = gcfg->mux->ops ?
+                                  gcfg->mux->ops : &clk_mux_ops;
+                }
+        }
+
+        if (gcfg->div && cfg->div) {
+                div = _get_cdiv(base + cfg->div->offset,
+                                cfg->div->shift,
+                                cfg->div->width,
+                                gcfg->div->flags, lock);
+
+                if (!IS_ERR(div)) {
+                        div_hw = &div->hw;
+                        div_ops = gcfg->div->ops ?
+                                  gcfg->div->ops : &clk_divider_ops;
+                }
+        }
+
+        if (gcfg->gate && gcfg->gate) {
+                gate = _get_cgate(base + cfg->gate->offset,
+                                cfg->gate->bit_idx,
+                                gcfg->gate->flags, lock);
+
+                if (!IS_ERR(gate)) {
+                        gate_hw = &gate->hw;
+                        gate_ops = gcfg->gate->ops ?
+                                   gcfg->gate->ops : &clk_gate_ops;
+                }
+        }
+
+        composite->mux_hw = mux_hw;
+        composite->mux_ops = mux_ops;
+
+        composite->div_hw = div_hw;
+        composite->div_ops = div_ops;
+
+        composite->gate_hw = gate_hw;
+        composite->gate_ops = gate_ops;
+}
+
+/* Kernel Timer */
+struct timer_ker {
+        u8 dppre_shift;
+        struct clk_hw hw;
+        spinlock_t *lock;
+};
+
+#define to_timer_ker(_hw) container_of(_hw, struct timer_ker, hw)
+
+static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct timer_ker *clk_elem = to_timer_ker(hw);
+        u32 timpre;
+        u32 dppre_shift = clk_elem->dppre_shift;
+        u32 prescaler;
+        u32 mul;
+
+        timpre = (readl(base + RCC_CFGR) >> 15) & 0x01;
+
+        prescaler = (readl(base + RCC_D2CFGR) >> dppre_shift) & 0x03;
+
+        mul = 2;
+
+        if (prescaler < 4)
+                mul = 1;
+
+        else if (timpre && prescaler > 4)
+                mul = 4;
+
+        return parent_rate * mul;
+}
+
+static const struct clk_ops timer_ker_ops = {
+        .recalc_rate = timer_ker_recalc_rate,
+};
+
+static struct clk_hw *clk_register_stm32_timer_ker(struct device *dev,
+                const char *name, const char *parent_name,
+                unsigned long flags,
+                u8 dppre_shift,
+                spinlock_t *lock)
+{
+        struct timer_ker *element;
+        struct clk_init_data init;
+        struct clk_hw *hw;
+        int err;
+
+        element = kzalloc(sizeof(*element), GFP_KERNEL);
+        if (!element)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &timer_ker_ops;
+        init.flags = flags;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        element->hw.init = &init;
+        element->lock = lock;
+        element->dppre_shift = dppre_shift;
+
+        hw = &element->hw;
+        err = clk_hw_register(dev, hw);
+
+        if (err) {
+                kfree(element);
+                return ERR_PTR(err);
+        }
+
+        return hw;
+}
+
+static const struct clk_div_table d1cpre_div_table[] = {
+        { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
+        { 4, 1 }, { 5, 1 }, { 6, 1 }, { 7, 1},
+        { 8, 2 }, { 9, 4 }, { 10, 8 }, { 11, 16 },
+        { 12, 64 }, { 13, 128 }, { 14, 256 },
+        { 15, 512 },
+        { 0 },
+};
+
+static const struct clk_div_table ppre_div_table[] = {
+        { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
+        { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
+        { 0 },
+};
+
+static void register_core_and_bus_clocks(void)
+{
+        /* CORE AND BUS */
+        hws[SYS_D1CPRE] = clk_hw_register_divider_table(NULL, "d1cpre",
+                        "sys_ck", CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 8, 4, 0,
+                        d1cpre_div_table, &stm32rcc_lock);
+
+        hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",
+                        CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 0, 4, 0,
+                        d1cpre_div_table, &stm32rcc_lock);
+
+        /* D1 DOMAIN */
+        /* * CPU Systick */
+        hws[CPU_SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick",
+                        "d1cpre", 0, 1, 8);
+
+        /* * APB3 peripheral */
+        hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0,
+                        base + RCC_D1CFGR, 4, 3, 0,
+                        ppre_div_table, &stm32rcc_lock);
+
+        /* D2 DOMAIN */
+        /* * APB1 peripheral */
+        hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0,
+                        base + RCC_D2CFGR, 4, 3, 0,
+                        ppre_div_table, &stm32rcc_lock);
+
+        /* Timers prescaler clocks */
+        clk_register_stm32_timer_ker(NULL, "tim1_ker", "pclk1", 0,
+                        4, &stm32rcc_lock);
+
+        /* * APB2 peripheral */
+        hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0,
+                        base + RCC_D2CFGR, 8, 3, 0, ppre_div_table,
+                        &stm32rcc_lock);
+
+        clk_register_stm32_timer_ker(NULL, "tim2_ker", "pclk2", 0, 8,
+                        &stm32rcc_lock);
+
+        /* D3 DOMAIN */
+        /* * APB4 peripheral */
+        hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0,
+                        base + RCC_D3CFGR, 4, 3, 0,
+                        ppre_div_table, &stm32rcc_lock);
+}
+
+/* MUX clock configuration */
+struct stm32_mux_clk {
+        const char *name;
+        const char * const *parents;
+        u8 num_parents;
+        u32 offset;
+        u8 shift;
+        u8 width;
+        u32 flags;
+};
+
+#define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\
+{\
+        .name           = _name,\
+        .parents        = _parents,\
+        .num_parents    = ARRAY_SIZE(_parents),\
+        .offset         = _mux_offset,\
+        .shift          = _mux_shift,\
+        .width          = _mux_width,\
+        .flags          = _flags,\
+}
+
+#define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\
+        M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
+
+static const struct stm32_mux_clk stm32_mclk[] __initconst = {
+        M_MCLOC("per_ck",       per_src,        RCC_D1CCIPR,    28, 3),
+        M_MCLOC("pllsrc",       pll_src,        RCC_PLLCKSELR,   0, 3),
+        M_MCLOC("sys_ck",       sys_src,        RCC_CFGR,        0, 3),
+        M_MCLOC("tracein_ck",   tracein_src,    RCC_CFGR,        0, 3),
+};
+
+/* Oscillary clock configuration */
+struct stm32_osc_clk {
+        const char *name;
+        const char *parent;
+        u32 gate_offset;
+        u8 bit_idx;
+        u8 bit_rdy;
+        u32 flags;
+};
+
+#define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\
+{\
+        .name           = _name,\
+        .parent         = _parent,\
+        .gate_offset    = _gate_offset,\
+        .bit_idx        = _bit_idx,\
+        .bit_rdy        = _bit_rdy,\
+        .flags          = _flags,\
+}
+
+#define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\
+        OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0)
+
+static const struct stm32_osc_clk stm32_oclk[] __initconst = {
+        OSC_CLKF("hsi_ck",  "hsidiv",   RCC_CR,   0,  2, CLK_IGNORE_UNUSED),
+        OSC_CLKF("hsi_ker", "hsidiv",   RCC_CR,   1,  2, CLK_IGNORE_UNUSED),
+        OSC_CLKF("csi_ck",  "clk-csi",  RCC_CR,   7,  8, CLK_IGNORE_UNUSED),
+        OSC_CLKF("csi_ker", "clk-csi",  RCC_CR,   9,  8, CLK_IGNORE_UNUSED),
+        OSC_CLKF("rc48_ck", "clk-rc48", RCC_CR,  12, 13, CLK_IGNORE_UNUSED),
+        OSC_CLKF("lsi_ck",  "clk-lsi",  RCC_CSR,  0,  1, CLK_IGNORE_UNUSED),
+};
+
+/* PLL configuration */
+struct st32h7_pll_cfg {
+        u8 bit_idx;
+        u32 offset_divr;
+        u8 bit_frac_en;
+        u32 offset_frac;
+        u8 divm;
+};
+
+struct stm32_pll_data {
+        const char *name;
+        const char *parent_name;
+        unsigned long flags;
+        const struct st32h7_pll_cfg *cfg;
+};
+
+static const struct st32h7_pll_cfg stm32h7_pll1 = {
+        .bit_idx = 24,
+        .offset_divr = RCC_PLL1DIVR,
+        .bit_frac_en = 0,
+        .offset_frac = RCC_PLL1FRACR,
+        .divm = 4,
+};
+
+static const struct st32h7_pll_cfg stm32h7_pll2 = {
+        .bit_idx = 26,
+        .offset_divr = RCC_PLL2DIVR,
+        .bit_frac_en = 4,
+        .offset_frac = RCC_PLL2FRACR,
+        .divm = 12,
+};
+
+static const struct st32h7_pll_cfg stm32h7_pll3 = {
+        .bit_idx = 28,
+        .offset_divr = RCC_PLL3DIVR,
+        .bit_frac_en = 8,
+        .offset_frac = RCC_PLL3FRACR,
+        .divm = 20,
+};
+
+static const struct stm32_pll_data stm32_pll[] = {
+        { "vco1", "pllsrc", CLK_IGNORE_UNUSED, &stm32h7_pll1 },
+        { "vco2", "pllsrc", 0, &stm32h7_pll2 },
+        { "vco3", "pllsrc", 0, &stm32h7_pll3 },
+};
+
+struct stm32_fractional_divider {
+        void __iomem    *mreg;
+        u8              mshift;
+        u8              mwidth;
+        u32             mmask;
+
+        void __iomem    *nreg;
+        u8              nshift;
+        u8              nwidth;
+
+        void __iomem    *freg_status;
+        u8              freg_bit;
+        void __iomem    *freg_value;
+        u8              fshift;
+        u8              fwidth;
+
+        u8              flags;
+        struct clk_hw   hw;
+        spinlock_t      *lock;
+};
+
+struct stm32_pll_obj {
+        spinlock_t *lock;
+        struct stm32_fractional_divider div;
+        struct stm32_ready_gate rgate;
+        struct clk_hw hw;
+};
+
+#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
+
+static int pll_is_enabled(struct clk_hw *hw)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
+
+        __clk_hw_set_clk(_hw, hw);
+
+        return ready_gate_clk_ops.is_enabled(_hw);
+}
+
+static int pll_enable(struct clk_hw *hw)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
+
+        __clk_hw_set_clk(_hw, hw);
+
+        return ready_gate_clk_ops.enable(_hw);
+}
+
+static void pll_disable(struct clk_hw *hw)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
+
+        __clk_hw_set_clk(_hw, hw);
+
+        ready_gate_clk_ops.disable(_hw);
+}
+
+static int pll_frac_is_enabled(struct clk_hw *hw)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct stm32_fractional_divider *fd = &clk_elem->div;
+
+        return (readl(fd->freg_status) >> fd->freg_bit) & 0x01;
+}
+
+static unsigned long pll_read_frac(struct clk_hw *hw)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct stm32_fractional_divider *fd = &clk_elem->div;
+
+        return (readl(fd->freg_value) >> fd->fshift) &
+                GENMASK(fd->fwidth - 1, 0);
+}
+
+static unsigned long pll_fd_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct stm32_pll_obj *clk_elem = to_pll(hw);
+        struct stm32_fractional_divider *fd = &clk_elem->div;
+        unsigned long m, n;
+        u32 val, mask;
+        u64 rate, rate1 = 0;
+
+        val = readl(fd->mreg);
+        mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
+        m = (val & mask) >> fd->mshift;
+
+        val = readl(fd->nreg);
+        mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
+        n = ((val & mask) >> fd->nshift) + 1;
+
+        if (!n || !m)
+                return parent_rate;
+
+        rate = (u64)parent_rate * n;
+        do_div(rate, m);
+
+        if (pll_frac_is_enabled(hw)) {
+                val = pll_read_frac(hw);
+                rate1 = (u64)parent_rate * (u64)val;
+                do_div(rate1, (m * 8191));
+        }
+
+        return rate + rate1;
+}
+
+static const struct clk_ops pll_ops = {
+        .enable         = pll_enable,
+        .disable        = pll_disable,
+        .is_enabled     = pll_is_enabled,
+        .recalc_rate    = pll_fd_recalc_rate,
+};
+
+static struct clk_hw *clk_register_stm32_pll(struct device *dev,
+                const char *name,
+                const char *parent,
+                unsigned long flags,
+                const struct st32h7_pll_cfg *cfg,
+                spinlock_t *lock)
+{
+        struct stm32_pll_obj *pll;
+        struct clk_init_data init = { NULL };
+        struct clk_hw *hw;
+        int ret;
+        struct stm32_fractional_divider *div = NULL;
+        struct stm32_ready_gate *rgate;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &pll_ops;
+        init.flags = flags;
+        init.parent_names = &parent;
+        init.num_parents = 1;
+        pll->hw.init = &init;
+
+        hw = &pll->hw;
+        rgate = &pll->rgate;
+
+        rgate->bit_rdy = cfg->bit_idx + 1;
+        rgate->gate.lock = lock;
+        rgate->gate.reg = base + RCC_CR;
+        rgate->gate.bit_idx = cfg->bit_idx;
+
+        div = &pll->div;
+        div->flags = 0;
+        div->mreg = base + RCC_PLLCKSELR;
+        div->mshift = cfg->divm;
+        div->mwidth = 6;
+        div->nreg = base +  cfg->offset_divr;
+        div->nshift = 0;
+        div->nwidth = 9;
+
+        div->freg_status = base + RCC_PLLCFGR;
+        div->freg_bit = cfg->bit_frac_en;
+        div->freg_value = base +  cfg->offset_frac;
+        div->fshift = 3;
+        div->fwidth = 13;
+
+        div->lock = lock;
+
+        ret = clk_hw_register(dev, hw);
+        if (ret) {
+                kfree(pll);
+                hw = ERR_PTR(ret);
+        }
+
+        return hw;
+}
+
+/* ODF CLOCKS */
+static unsigned long odf_divider_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return clk_divider_ops.recalc_rate(hw, parent_rate);
+}
+
+static long odf_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *prate)
+{
+        return clk_divider_ops.round_rate(hw, rate, prate);
+}
+
+static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_hw *hwp;
+        int pll_status;
+        int ret;
+
+        hwp = clk_hw_get_parent(hw);
+
+        pll_status = pll_is_enabled(hwp);
+
+        if (pll_status)
+                pll_disable(hwp);
+
+        ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+        if (pll_status)
+                pll_enable(hwp);
+
+        return ret;
+}
+
+static const struct clk_ops odf_divider_ops = {
+        .recalc_rate    = odf_divider_recalc_rate,
+        .round_rate     = odf_divider_round_rate,
+        .set_rate       = odf_divider_set_rate,
+};
+
+static int odf_gate_enable(struct clk_hw *hw)
+{
+        struct clk_hw *hwp;
+        int pll_status;
+        int ret;
+
+        if (clk_gate_ops.is_enabled(hw))
+                return 0;
+
+        hwp = clk_hw_get_parent(hw);
+
+        pll_status = pll_is_enabled(hwp);
+
+        if (pll_status)
+                pll_disable(hwp);
+
+        ret = clk_gate_ops.enable(hw);
+
+        if (pll_status)
+                pll_enable(hwp);
+
+        return ret;
+}
+
+static void odf_gate_disable(struct clk_hw *hw)
+{
+        struct clk_hw *hwp;
+        int pll_status;
+
+        if (!clk_gate_ops.is_enabled(hw))
+                return;
+
+        hwp = clk_hw_get_parent(hw);
+
+        pll_status = pll_is_enabled(hwp);
+
+        if (pll_status)
+                pll_disable(hwp);
+
+        clk_gate_ops.disable(hw);
+
+        if (pll_status)
+                pll_enable(hwp);
+}
+
+static const struct clk_ops odf_gate_ops = {
+        .enable         = odf_gate_enable,
+        .disable        = odf_gate_disable,
+        .is_enabled     = clk_gate_is_enabled,
+};
+
+static struct composite_clk_gcfg odf_clk_gcfg = {
+        M_CFG_DIV(&odf_divider_ops, 0),
+        M_CFG_GATE(&odf_gate_ops, 0),
+};
+
+#define M_ODF_F(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
+                _rate_shift, _rate_width, _flags)\
+{\
+        .mux = NULL,\
+        .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
+        .gate = &(struct gate_cfg) {_gate_offset, _bit_idx },\
+        .name = _name,\
+        .parent_name = &(const char *) {_parent},\
+        .num_parents = 1,\
+        .flags = _flags,\
+}
+
+#define M_ODF(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
+                _rate_shift, _rate_width)\
+M_ODF_F(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
+                _rate_shift, _rate_width, 0)\
+
+static const struct composite_clk_cfg stm32_odf[3][3] = {
+        {
+                M_ODF_F("pll1_p", "vco1", RCC_PLLCFGR, 16, RCC_PLL1DIVR,  9, 7,
+                                CLK_IGNORE_UNUSED),
+                M_ODF_F("pll1_q", "vco1", RCC_PLLCFGR, 17, RCC_PLL1DIVR, 16, 7,
+                                CLK_IGNORE_UNUSED),
+                M_ODF_F("pll1_r", "vco1", RCC_PLLCFGR, 18, RCC_PLL1DIVR, 24, 7,
+                                CLK_IGNORE_UNUSED),
+        },
+
+        {
+                M_ODF("pll2_p", "vco2", RCC_PLLCFGR, 19, RCC_PLL2DIVR,  9, 7),
+                M_ODF("pll2_q", "vco2", RCC_PLLCFGR, 20, RCC_PLL2DIVR, 16, 7),
+                M_ODF("pll2_r", "vco2", RCC_PLLCFGR, 21, RCC_PLL2DIVR, 24, 7),
+        },
+        {
+                M_ODF("pll3_p", "vco3", RCC_PLLCFGR, 22, RCC_PLL3DIVR,  9, 7),
+                M_ODF("pll3_q", "vco3", RCC_PLLCFGR, 23, RCC_PLL3DIVR, 16, 7),
+                M_ODF("pll3_r", "vco3", RCC_PLLCFGR, 24, RCC_PLL3DIVR, 24, 7),
+        }
+};
+
+/* PERIF CLOCKS */
+struct pclk_t {
+        u32 gate_offset;
+        u8 bit_idx;
+        const char *name;
+        const char *parent;
+        u32 flags;
+};
+
+#define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\
+{\
+        .gate_offset    = _gate_offset,\
+        .bit_idx        = _bit_idx,\
+        .name           = _name,\
+        .parent         = _parent,\
+        .flags          = _flags,\
+}
+
+#define PER_CLK(_gate_offset, _bit_idx, _name, _parent)\
+        PER_CLKF(_gate_offset, _bit_idx, _name, _parent, 0)
+
+static const struct pclk_t pclk[] = {
+        PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 28, "dtcm1", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 8, "flitf", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 5, "jpgdec", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 4, "dma2d", "hclk"),
+        PER_CLK(RCC_AHB3ENR, 0, "mdma", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 28, "usb2ulpi", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 26, "usb1ulpi", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 17, "eth1rx", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 16, "eth1tx", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 15, "eth1mac", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 14, "art", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 1, "dma2", "hclk"),
+        PER_CLK(RCC_AHB1ENR, 0, "dma1", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 31, "d2sram3", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 30, "d2sram2", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 29, "d2sram1", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 5, "hash", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 4, "crypt", "hclk"),
+        PER_CLK(RCC_AHB2ENR, 0, "camitf", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 28, "bkpram", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 25, "hsem", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 21, "bdma", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 19, "crc", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 10, "gpiok", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 9, "gpioj", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 8, "gpioi", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 7, "gpioh", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 6, "gpiog", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 5, "gpiof", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 4, "gpioe", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 3, "gpiod", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 2, "gpioc", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 1, "gpiob", "hclk"),
+        PER_CLK(RCC_AHB4ENR, 0, "gpioa", "hclk"),
+        PER_CLK(RCC_APB3ENR, 6, "wwdg1", "pclk3"),
+        PER_CLK(RCC_APB1LENR, 29, "dac12", "pclk1"),
+        PER_CLK(RCC_APB1LENR, 11, "wwdg2", "pclk1"),
+        PER_CLK(RCC_APB1LENR, 8, "tim14", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 7, "tim13", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 6, "tim12", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 5, "tim7", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 4, "tim6", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 3, "tim5", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 2, "tim4", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 1, "tim3", "tim1_ker"),
+        PER_CLK(RCC_APB1LENR, 0, "tim2", "tim1_ker"),
+        PER_CLK(RCC_APB1HENR, 5, "mdios", "pclk1"),
+        PER_CLK(RCC_APB1HENR, 4, "opamp", "pclk1"),
+        PER_CLK(RCC_APB1HENR, 1, "crs", "pclk1"),
+        PER_CLK(RCC_APB2ENR, 18, "tim17", "tim2_ker"),
+        PER_CLK(RCC_APB2ENR, 17, "tim16", "tim2_ker"),
+        PER_CLK(RCC_APB2ENR, 16, "tim15", "tim2_ker"),
+        PER_CLK(RCC_APB2ENR, 1, "tim8", "tim2_ker"),
+        PER_CLK(RCC_APB2ENR, 0, "tim1", "tim2_ker"),
+        PER_CLK(RCC_APB4ENR, 26, "tmpsens", "pclk4"),
+        PER_CLK(RCC_APB4ENR, 16, "rtcapb", "pclk4"),
+        PER_CLK(RCC_APB4ENR, 15, "vref", "pclk4"),
+        PER_CLK(RCC_APB4ENR, 14, "comp12", "pclk4"),
+        PER_CLK(RCC_APB4ENR, 1, "syscfg", "pclk4"),
+};
+
+/* KERNEL CLOCKS */
+#define KER_CLKF(_gate_offset, _bit_idx,\
+                _mux_offset, _mux_shift, _mux_width,\
+                _name, _parent_name,\
+                _flags) \
+{ \
+        .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
+        .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
+        .name = _name, \
+        .parent_name = _parent_name, \
+        .num_parents = ARRAY_SIZE(_parent_name),\
+        .flags = _flags,\
+}
+
+#define KER_CLK(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
+                _name, _parent_name) \
+KER_CLKF(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
+                _name, _parent_name, 0)\
+
+#define KER_CLKF_NOMUX(_gate_offset, _bit_idx,\
+                _name, _parent_name,\
+                _flags) \
+{ \
+        .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
+        .mux = NULL,\
+        .name = _name, \
+        .parent_name = _parent_name, \
+        .num_parents = 1,\
+        .flags = _flags,\
+}
+
+static const struct composite_clk_cfg kclk[] = {
+        KER_CLK(RCC_AHB3ENR,  16, RCC_D1CCIPR,  16, 1, "sdmmc1", sdmmc_src),
+        KER_CLKF(RCC_AHB3ENR, 14, RCC_D1CCIPR,   4, 2, "quadspi", qspi_src,
+                        CLK_IGNORE_UNUSED),
+        KER_CLKF(RCC_AHB3ENR, 12, RCC_D1CCIPR,   0, 2, "fmc", fmc_src,
+                        CLK_IGNORE_UNUSED),
+        KER_CLK(RCC_AHB1ENR,  27, RCC_D2CCIP2R, 20, 2, "usb2otg", usbotg_src),
+        KER_CLK(RCC_AHB1ENR,  25, RCC_D2CCIP2R, 20, 2, "usb1otg", usbotg_src),
+        KER_CLK(RCC_AHB1ENR,   5, RCC_D3CCIPR,  16, 2, "adc12", adc_src),
+        KER_CLK(RCC_AHB2ENR,   9, RCC_D1CCIPR,  16, 1, "sdmmc2", sdmmc_src),
+        KER_CLK(RCC_AHB2ENR,   6, RCC_D2CCIP2R,  8, 2, "rng", rng_src),
+        KER_CLK(RCC_AHB4ENR,  24, RCC_D3CCIPR,  16, 2, "adc3", adc_src),
+        KER_CLKF(RCC_APB3ENR,   4, RCC_D1CCIPR,  8, 1, "dsi", dsi_src,
+                        CLK_SET_RATE_PARENT),
+        KER_CLKF_NOMUX(RCC_APB3ENR, 3, "ltdc", ltdc_src, CLK_SET_RATE_PARENT),
+        KER_CLK(RCC_APB1LENR, 31, RCC_D2CCIP2R,  0, 3, "usart8", usart_src2),
+        KER_CLK(RCC_APB1LENR, 30, RCC_D2CCIP2R,  0, 3, "usart7", usart_src2),
+        KER_CLK(RCC_APB1LENR, 27, RCC_D2CCIP2R, 22, 2, "hdmicec", cec_src),
+        KER_CLK(RCC_APB1LENR, 23, RCC_D2CCIP2R, 12, 2, "i2c3", i2c_src1),
+        KER_CLK(RCC_APB1LENR, 22, RCC_D2CCIP2R, 12, 2, "i2c2", i2c_src1),
+        KER_CLK(RCC_APB1LENR, 21, RCC_D2CCIP2R, 12, 2, "i2c1", i2c_src1),
+        KER_CLK(RCC_APB1LENR, 20, RCC_D2CCIP2R,  0, 3, "uart5", usart_src2),
+        KER_CLK(RCC_APB1LENR, 19, RCC_D2CCIP2R,  0, 3, "uart4", usart_src2),
+        KER_CLK(RCC_APB1LENR, 18, RCC_D2CCIP2R,  0, 3, "usart3", usart_src2),
+        KER_CLK(RCC_APB1LENR, 17, RCC_D2CCIP2R,  0, 3, "usart2", usart_src2),
+        KER_CLK(RCC_APB1LENR, 16, RCC_D2CCIP1R, 20, 2, "spdifrx", spdifrx_src),
+        KER_CLK(RCC_APB1LENR, 15, RCC_D2CCIP1R, 16, 3, "spi3", spi_src1),
+        KER_CLK(RCC_APB1LENR, 14, RCC_D2CCIP1R, 16, 3, "spi2", spi_src1),
+        KER_CLK(RCC_APB1LENR,  9, RCC_D2CCIP2R, 28, 3, "lptim1", lptim_src1),
+        KER_CLK(RCC_APB1HENR,  8, RCC_D2CCIP1R, 28, 2, "fdcan", fdcan_src),
+        KER_CLK(RCC_APB1HENR,  2, RCC_D2CCIP1R, 31, 1, "swp", swp_src),
+        KER_CLK(RCC_APB2ENR,  29, RCC_CFGR,     14, 1, "hrtim", hrtim_src),
+        KER_CLK(RCC_APB2ENR,  28, RCC_D2CCIP1R, 24, 1, "dfsdm1", dfsdm1_src),
+        KER_CLKF(RCC_APB2ENR,  24, RCC_D2CCIP1R,  6, 3, "sai3", sai_src,
+                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
+        KER_CLKF(RCC_APB2ENR,  23, RCC_D2CCIP1R,  6, 3, "sai2", sai_src,
+                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
+        KER_CLKF(RCC_APB2ENR,  22, RCC_D2CCIP1R,  0, 3, "sai1", sai_src,
+                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
+        KER_CLK(RCC_APB2ENR,  20, RCC_D2CCIP1R, 16, 3, "spi5", spi_src2),
+        KER_CLK(RCC_APB2ENR,  13, RCC_D2CCIP1R, 16, 3, "spi4", spi_src2),
+        KER_CLK(RCC_APB2ENR,  12, RCC_D2CCIP1R, 16, 3, "spi1", spi_src1),
+        KER_CLK(RCC_APB2ENR,   5, RCC_D2CCIP2R,  3, 3, "usart6", usart_src1),
+        KER_CLK(RCC_APB2ENR,   4, RCC_D2CCIP2R,  3, 3, "usart1", usart_src1),
+        KER_CLK(RCC_APB4ENR,  21, RCC_D3CCIPR,  24, 3, "sai4b", sai_src),
+        KER_CLK(RCC_APB4ENR,  21, RCC_D3CCIPR,  21, 3, "sai4a", sai_src),
+        KER_CLK(RCC_APB4ENR,  12, RCC_D3CCIPR,  13, 3, "lptim5", lptim_src2),
+        KER_CLK(RCC_APB4ENR,  11, RCC_D3CCIPR,  13, 3, "lptim4", lptim_src2),
+        KER_CLK(RCC_APB4ENR,  10, RCC_D3CCIPR,  13, 3, "lptim3", lptim_src2),
+        KER_CLK(RCC_APB4ENR,   9, RCC_D3CCIPR,  10, 3, "lptim2", lptim_src2),
+        KER_CLK(RCC_APB4ENR,   7, RCC_D3CCIPR,   8, 2, "i2c4", i2c_src2),
+        KER_CLK(RCC_APB4ENR,   5, RCC_D3CCIPR,  28, 3, "spi6", spi_src3),
+        KER_CLK(RCC_APB4ENR,   3, RCC_D3CCIPR,   0, 3, "lpuart1", lpuart1_src),
+};
+
+static struct composite_clk_gcfg kernel_clk_cfg = {
+        M_CFG_MUX(NULL, 0),
+        M_CFG_GATE(NULL, 0),
+};
+
+/* RTC clock */
+/*
+ * RTC & LSE registers are protected against parasitic write access.
+ * PWR_CR_DBP bit must be set to enable write access to RTC registers.
+ */
+/* STM32_PWR_CR */
+#define PWR_CR                          0x00
+/* STM32_PWR_CR bit field */
+#define PWR_CR_DBP                      BIT(8)
+
+static struct composite_clk_gcfg rtc_clk_cfg = {
+        M_CFG_MUX(NULL, 0),
+        M_CFG_GATE(NULL, 0),
+};
+
+static const struct composite_clk_cfg rtc_clk =
+        KER_CLK(RCC_BDCR, 15, RCC_BDCR, 8, 2, "rtc_ck", rtc_src);
+
+/* Micro-controller output clock */
+static struct composite_clk_gcfg mco_clk_cfg = {
+        M_CFG_MUX(NULL, 0),
+        M_CFG_DIV(NULL, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
+};
+
+#define M_MCO_F(_name, _parents, _mux_offset,  _mux_shift, _mux_width,\
+                _rate_offset, _rate_shift, _rate_width,\
+                _flags)\
+{\
+        .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
+        .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
+        .gate = NULL,\
+        .name = _name,\
+        .parent_name = _parents,\
+        .num_parents = ARRAY_SIZE(_parents),\
+        .flags = _flags,\
+}
+
+static const struct composite_clk_cfg mco_clk[] = {
+        M_MCO_F("mco1", mco_src1, RCC_CFGR, 22, 4, RCC_CFGR, 18, 4, 0),
+        M_MCO_F("mco2", mco_src2, RCC_CFGR, 29, 3, RCC_CFGR, 25, 4, 0),
+};
+
+static void __init stm32h7_rcc_init(struct device_node *np)
+{
+        struct clk_hw_onecell_data *clk_data;
+        struct composite_cfg c_cfg;
+        int n;
+        const char *hse_clk, *lse_clk, *i2s_clk;
+        struct regmap *pdrm;
+
+        clk_data = kzalloc(sizeof(*clk_data) +
+                        sizeof(*clk_data->hws) * STM32H7_MAX_CLKS,
+                        GFP_KERNEL);
+        if (!clk_data)
+                return;
+
+        clk_data->num = STM32H7_MAX_CLKS;
+
+        hws = clk_data->hws;
+
+        for (n = 0; n < STM32H7_MAX_CLKS; n++)
+                hws[n] = ERR_PTR(-ENOENT);
+
+        /* get RCC base @ from DT */
+        base = of_iomap(np, 0);
+        if (!base) {
+                pr_err("%s: unable to map resource", np->name);
+                goto err_free_clks;
+        }
+
+        pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+        if (IS_ERR(pdrm))
+                pr_warn("%s: Unable to get syscfg\n", __func__);
+        else
+                /* In any case disable backup domain write protection
+                 * and will never be enabled.
+                 * Needed by LSE & RTC clocks.
+                 */
+                regmap_update_bits(pdrm, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
+
+        /* Put parent names from DT */
+        hse_clk = of_clk_get_parent_name(np, 0);
+        lse_clk = of_clk_get_parent_name(np, 1);
+        i2s_clk = of_clk_get_parent_name(np, 2);
+
+        sai_src[3] = i2s_clk;
+        spi_src1[3] = i2s_clk;
+
+        /* Register Internal oscillators */
+        clk_hw_register_fixed_rate(NULL, "clk-hsi", NULL, 0, 64000000);
+        clk_hw_register_fixed_rate(NULL, "clk-csi", NULL, 0, 4000000);
+        clk_hw_register_fixed_rate(NULL, "clk-lsi", NULL, 0, 32000);
+        clk_hw_register_fixed_rate(NULL, "clk-rc48", NULL, 0, 48000);
+
+        /* This clock is coming from outside. Frequencies unknown */
+        hws[CK_DSI_PHY] = clk_hw_register_fixed_rate(NULL, "ck_dsi_phy", NULL,
+                        0, 0);
+
+        hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
+                        base + RCC_CR, 3, 2, CLK_DIVIDER_POWER_OF_TWO,
+                        &stm32rcc_lock);
+
+        hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
+                        base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO,
+                        &stm32rcc_lock);
+
+        /* Mux system clocks */
+        for (n = 0; n < ARRAY_SIZE(stm32_mclk); n++)
+                hws[MCLK_BANK + n] = clk_hw_register_mux(NULL,
+                                stm32_mclk[n].name,
+                                stm32_mclk[n].parents,
+                                stm32_mclk[n].num_parents,
+                                stm32_mclk[n].flags,
+                                stm32_mclk[n].offset + base,
+                                stm32_mclk[n].shift,
+                                stm32_mclk[n].width,
+                                0,
+                                &stm32rcc_lock);
+
+        register_core_and_bus_clocks();
+
+        /* Oscillary clocks */
+        for (n = 0; n < ARRAY_SIZE(stm32_oclk); n++)
+                hws[OSC_BANK + n] = clk_register_ready_gate(NULL,
+                                stm32_oclk[n].name,
+                                stm32_oclk[n].parent,
+                                stm32_oclk[n].gate_offset + base,
+                                stm32_oclk[n].bit_idx,
+                                stm32_oclk[n].bit_rdy,
+                                stm32_oclk[n].flags,
+                                &stm32rcc_lock);
+
+        hws[HSE_CK] = clk_register_ready_gate(NULL,
+                                "hse_ck",
+                                hse_clk,
+                                RCC_CR + base,
+                                16, 17,
+                                0,
+                                &stm32rcc_lock);
+
+        hws[LSE_CK] = clk_register_ready_gate(NULL,
+                                "lse_ck",
+                                lse_clk,
+                                RCC_BDCR + base,
+                                0, 1,
+                                0,
+                                &stm32rcc_lock);
+
+        hws[CSI_KER_DIV122 + n] = clk_hw_register_fixed_factor(NULL,
+                        "csi_ker_div122", "csi_ker", 0, 1, 122);
+
+        /* PLLs */
+        for (n = 0; n < ARRAY_SIZE(stm32_pll); n++) {
+                int odf;
+
+                /* Register the VCO */
+                clk_register_stm32_pll(NULL, stm32_pll[n].name,
+                                stm32_pll[n].parent_name, stm32_pll[n].flags,
+                                stm32_pll[n].cfg,
+                                &stm32rcc_lock);
+
+                /* Register the 3 output dividers */
+                for (odf = 0; odf < 3; odf++) {
+                        int idx = n * 3 + odf;
+
+                        get_cfg_composite_div(&odf_clk_gcfg, &stm32_odf[n][odf],
+                                        &c_cfg, &stm32rcc_lock);
+
+                        hws[ODF_BANK + idx] = clk_hw_register_composite(NULL,
+                                        stm32_odf[n][odf].name,
+                                        stm32_odf[n][odf].parent_name,
+                                        stm32_odf[n][odf].num_parents,
+                                        c_cfg.mux_hw, c_cfg.mux_ops,
+                                        c_cfg.div_hw, c_cfg.div_ops,
+                                        c_cfg.gate_hw, c_cfg.gate_ops,
+                                        stm32_odf[n][odf].flags);
+                }
+        }
+
+        /* Peripheral clocks */
+        for (n = 0; n < ARRAY_SIZE(pclk); n++)
+                hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
+                                pclk[n].parent,
+                                pclk[n].flags, base + pclk[n].gate_offset,
+                                pclk[n].bit_idx, pclk[n].flags, &stm32rcc_lock);
+
+        /* Kernel clocks */
+        for (n = 0; n < ARRAY_SIZE(kclk); n++) {
+                get_cfg_composite_div(&kernel_clk_cfg, &kclk[n], &c_cfg,
+                                &stm32rcc_lock);
+
+                hws[KERN_BANK + n] = clk_hw_register_composite(NULL,
+                                kclk[n].name,
+                                kclk[n].parent_name,
+                                kclk[n].num_parents,
+                                c_cfg.mux_hw, c_cfg.mux_ops,
+                                c_cfg.div_hw, c_cfg.div_ops,
+                                c_cfg.gate_hw, c_cfg.gate_ops,
+                                kclk[n].flags);
+        }
+
+        /* RTC clock (default state is off) */
+        clk_hw_register_fixed_rate(NULL, "off", NULL, 0, 0);
+
+        get_cfg_composite_div(&rtc_clk_cfg, &rtc_clk, &c_cfg, &stm32rcc_lock);
+
+        hws[RTC_CK] = clk_hw_register_composite(NULL,
+                        rtc_clk.name,
+                        rtc_clk.parent_name,
+                        rtc_clk.num_parents,
+                        c_cfg.mux_hw, c_cfg.mux_ops,
+                        c_cfg.div_hw, c_cfg.div_ops,
+                        c_cfg.gate_hw, c_cfg.gate_ops,
+                        rtc_clk.flags);
+
+        /* Micro-controller clocks */
+        for (n = 0; n < ARRAY_SIZE(mco_clk); n++) {
+                get_cfg_composite_div(&mco_clk_cfg, &mco_clk[n], &c_cfg,
+                                &stm32rcc_lock);
+
+                hws[MCO_BANK + n] = clk_hw_register_composite(NULL,
+                                mco_clk[n].name,
+                                mco_clk[n].parent_name,
+                                mco_clk[n].num_parents,
+                                c_cfg.mux_hw, c_cfg.mux_ops,
+                                c_cfg.div_hw, c_cfg.div_ops,
+                                c_cfg.gate_hw, c_cfg.gate_ops,
+                                mco_clk[n].flags);
+        }
+
+        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+
+        return;
+
+err_free_clks:
+        kfree(clk_data);
+}
+
+/* The RCC node is a clock and reset controller, and these
+ * functionalities are supported by different drivers that
+ * matches the same compatible strings.
+ */
+CLK_OF_DECLARE_DRIVER(stm32h7_rcc, "st,stm32h743-rcc", stm32h7_rcc_init);
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index ea7d552a2f2b..decffb3826ec 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -57,6 +57,7 @@
 #define VC5_PRIM_SRC_SHDN                       0x10
 #define VC5_PRIM_SRC_SHDN_EN_XTAL               BIT(7)
 #define VC5_PRIM_SRC_SHDN_EN_CLKIN              BIT(6)
+#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ   BIT(3)
 #define VC5_PRIM_SRC_SHDN_SP                    BIT(1)
 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN           BIT(0)
 
@@ -122,12 +123,16 @@
 /* flags to describe chip features */
 /* chip has built-in oscilator */
 #define VC5_HAS_INTERNAL_XTAL   BIT(0)
+/* chip has PFD requency doubler */
+#define VC5_HAS_PFD_FREQ_DBL    BIT(1)
 
 /* Supported IDT VC5 models. */
 enum vc5_model {
         IDT_VC5_5P49V5923,
+        IDT_VC5_5P49V5925,
         IDT_VC5_5P49V5933,
         IDT_VC5_5P49V5935,
+        IDT_VC6_5P49V6901,
 };
 
 /* Structure to describe features of a particular VC5 model */
@@ -157,6 +162,8 @@ struct vc5_driver_data {
         struct clk              *pin_clkin;
         unsigned char           clk_mux_ins;
         struct clk_hw           clk_mux;
+        struct clk_hw           clk_mul;
+        struct clk_hw           clk_pfd;
         struct vc5_hw_data      clk_pll;
         struct vc5_hw_data      clk_fod[VC5_MAX_FOD_NUM];
         struct vc5_hw_data      clk_out[VC5_MAX_CLK_OUT_NUM];
@@ -166,6 +173,14 @@ static const char * const vc5_mux_names[] = {
         "mux"
 };
 
+static const char * const vc5_dbl_names[] = {
+        "dbl"
+};
+
+static const char * const vc5_pfd_names[] = {
+        "pfd"
+};
+
 static const char * const vc5_pll_names[] = {
         "pll"
 };
@@ -254,11 +269,64 @@ static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
         return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
 }
 
-static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw,
+static const struct clk_ops vc5_mux_ops = {
+        .set_parent     = vc5_mux_set_parent,
+        .get_parent     = vc5_mux_get_parent,
+};
+
+static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
                                          unsigned long parent_rate)
 {
         struct vc5_driver_data *vc5 =
-                container_of(hw, struct vc5_driver_data, clk_mux);
+                container_of(hw, struct vc5_driver_data, clk_mul);
+        unsigned int premul;
+
+        regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
+        if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
+                parent_rate *= 2;
+
+        return parent_rate;
+}
+
+static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate)
+{
+        if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
+                return rate;
+        else
+                return -EINVAL;
+}
+
+static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+        struct vc5_driver_data *vc5 =
+                container_of(hw, struct vc5_driver_data, clk_mul);
+        u32 mask;
+
+        if ((parent_rate * 2) == rate)
+                mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
+        else
+                mask = 0;
+
+        regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
+                           VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
+                           mask);
+
+        return 0;
+}
+
+static const struct clk_ops vc5_dbl_ops = {
+        .recalc_rate    = vc5_dbl_recalc_rate,
+        .round_rate     = vc5_dbl_round_rate,
+        .set_rate       = vc5_dbl_set_rate,
+};
+
+static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct vc5_driver_data *vc5 =
+                container_of(hw, struct vc5_driver_data, clk_pfd);
         unsigned int prediv, div;
 
         regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
@@ -276,7 +344,7 @@ static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw,
                 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
 }
 
-static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate,
+static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
                                unsigned long *parent_rate)
 {
         unsigned long idiv;
@@ -296,11 +364,11 @@ static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate,
         return *parent_rate / idiv;
 }
 
-static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate,
+static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
                             unsigned long parent_rate)
 {
         struct vc5_driver_data *vc5 =
-                container_of(hw, struct vc5_driver_data, clk_mux);
+                container_of(hw, struct vc5_driver_data, clk_pfd);
         unsigned long idiv;
         u8 div;
 
@@ -328,12 +396,10 @@ static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
-static const struct clk_ops vc5_mux_ops = {
-        .set_parent     = vc5_mux_set_parent,
-        .get_parent     = vc5_mux_get_parent,
-        .recalc_rate    = vc5_mux_recalc_rate,
-        .round_rate     = vc5_mux_round_rate,
-        .set_rate       = vc5_mux_set_rate,
+static const struct clk_ops vc5_pfd_ops = {
+        .recalc_rate    = vc5_pfd_recalc_rate,
+        .round_rate     = vc5_pfd_round_rate,
+        .set_rate       = vc5_pfd_set_rate,
 };
 
 /*
@@ -426,6 +492,10 @@ static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
         div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
                   (od_frc[2] << 6) | (od_frc[3] >> 2);
 
+        /* Avoid division by zero if the output is not configured. */
+        if (div_int == 0 && div_frc == 0)
+                return 0;
+
         /* The PLL divider has 12 integer bits and 30 fractional bits */
         return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
 }
@@ -503,6 +573,25 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
 {
         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
         struct vc5_driver_data *vc5 = hwdata->vc5;
+        const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
+                        VC5_OUT_DIV_CONTROL_SEL_EXT |
+                        VC5_OUT_DIV_CONTROL_EN_FOD;
+        unsigned int src;
+        int ret;
+
+        /*
+         * If the input mux is disabled, enable it first and
+         * select source from matching FOD.
+         */
+        regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
+        if ((src & mask) == 0) {
+                src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
+                ret = regmap_update_bits(vc5->regmap,
+                                         VC5_OUT_DIV_CONTROL(hwdata->num),
+                                         mask | VC5_OUT_DIV_CONTROL_RESET, src);
+                if (ret)
+                        return ret;
+        }
 
         /* Enable the clock buffer */
         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
@@ -516,7 +605,7 @@ static void vc5_clk_out_unprepare(struct clk_hw *hw)
         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
         struct vc5_driver_data *vc5 = hwdata->vc5;
 
-        /* Enable the clock buffer */
+        /* Disable the clock buffer */
         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
 }
@@ -537,6 +626,9 @@ static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
         regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
         src &= mask;
 
+        if (src == 0)   /* Input mux set to DISABLED */
+                return 0;
+
         if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
                 return 0;
 
@@ -595,7 +687,9 @@ static int vc5_map_index_to_output(const enum vc5_model model,
         case IDT_VC5_5P49V5933:
                 return (n == 0) ? 0 : 3;
         case IDT_VC5_5P49V5923:
+        case IDT_VC5_5P49V5925:
         case IDT_VC5_5P49V5935:
+        case IDT_VC6_5P49V6901:
         default:
                 return n;
         }
@@ -672,12 +766,46 @@ static int vc5_probe(struct i2c_client *client,
                 goto err_clk;
         }
 
+        if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
+                /* Register frequency doubler */
+                memset(&init, 0, sizeof(init));
+                init.name = vc5_dbl_names[0];
+                init.ops = &vc5_dbl_ops;
+                init.flags = CLK_SET_RATE_PARENT;
+                init.parent_names = vc5_mux_names;
+                init.num_parents = 1;
+                vc5->clk_mul.init = &init;
+                ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
+                if (ret) {
+                        dev_err(&client->dev, "unable to register %s\n",
+                                init.name);
+                        goto err_clk;
+                }
+        }
+
+        /* Register PFD */
+        memset(&init, 0, sizeof(init));
+        init.name = vc5_pfd_names[0];
+        init.ops = &vc5_pfd_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
+                init.parent_names = vc5_dbl_names;
+        else
+                init.parent_names = vc5_mux_names;
+        init.num_parents = 1;
+        vc5->clk_pfd.init = &init;
+        ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
+        if (ret) {
+                dev_err(&client->dev, "unable to register %s\n", init.name);
+                goto err_clk;
+        }
+
         /* Register PLL */
         memset(&init, 0, sizeof(init));
         init.name = vc5_pll_names[0];
         init.ops = &vc5_pll_ops;
         init.flags = CLK_SET_RATE_PARENT;
-        init.parent_names = vc5_mux_names;
+        init.parent_names = vc5_pfd_names;
         init.num_parents = 1;
         vc5->clk_pll.num = 0;
         vc5->clk_pll.vc5 = vc5;
@@ -785,6 +913,13 @@ static const struct vc5_chip_info idt_5p49v5923_info = {
         .flags = 0,
 };
 
+static const struct vc5_chip_info idt_5p49v5925_info = {
+        .model = IDT_VC5_5P49V5925,
+        .clk_fod_cnt = 4,
+        .clk_out_cnt = 5,
+        .flags = 0,
+};
+
 static const struct vc5_chip_info idt_5p49v5933_info = {
         .model = IDT_VC5_5P49V5933,
         .clk_fod_cnt = 2,
@@ -799,18 +934,29 @@ static const struct vc5_chip_info idt_5p49v5935_info = {
         .flags = VC5_HAS_INTERNAL_XTAL,
 };
 
+static const struct vc5_chip_info idt_5p49v6901_info = {
+        .model = IDT_VC6_5P49V6901,
+        .clk_fod_cnt = 4,
+        .clk_out_cnt = 5,
+        .flags = VC5_HAS_PFD_FREQ_DBL,
+};
+
 static const struct i2c_device_id vc5_id[] = {
         { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
+        { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
         { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
         { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
+        { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
         { }
 };
 MODULE_DEVICE_TABLE(i2c, vc5_id);
 
 static const struct of_device_id clk_vc5_of_match[] = {
         { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
+        { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
         { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
         { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
+        { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
         { },
 };
 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index bc37030e38ba..4c75821a3933 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -192,7 +192,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
 
         reg = of_iomap(np, 0);
         if (reg == NULL) {
-                pr_err("Unable to map CSR register for %s\n", np->full_name);
+                pr_err("Unable to map CSR register for %pOF\n", np);
                 return;
         }
         of_property_read_string(np, "clock-output-names", &clk_name);
@@ -409,12 +409,12 @@ static void xgene_pmdclk_init(struct device_node *np)
         /* Parse the DTS register for resource */
         rc = of_address_to_resource(np, 0, &res);
         if (rc != 0) {
-                pr_err("no DTS register for %s\n", np->full_name);
+                pr_err("no DTS register for %pOF\n", np);
                 return;
         }
         csr_reg = of_iomap(np, 0);
         if (!csr_reg) {
-                pr_err("Unable to map resource for %s\n", np->full_name);
+                pr_err("Unable to map resource for %pOF\n", np);
                 return;
         }
         of_property_read_string(np, "clock-output-names", &clk_name);
@@ -703,16 +703,14 @@ static void __init xgene_devclk_init(struct device_node *np)
                 rc = of_address_to_resource(np, i, &res);
                 if (rc != 0) {
                         if (i == 0) {
-                                pr_err("no DTS register for %s\n",
-                                        np->full_name);
+                                pr_err("no DTS register for %pOF\n", np);
                                 return;
                         }
                         break;
                 }
                 map_res = of_iomap(np, i);
                 if (map_res == NULL) {
-                        pr_err("Unable to map resource %d for %s\n",
-                                i, np->full_name);
+                        pr_err("Unable to map resource %d for %pOF\n", i, np);
                         goto err;
                 }
                 if (strcmp(res.name, "div-reg") == 0)
@@ -747,8 +745,7 @@ static void __init xgene_devclk_init(struct device_node *np)
         pr_debug("Add %s clock\n", clk_name);
         rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
         if (rc != 0)
-                pr_err("%s: could register provider clk %s\n", __func__,
-                        np->full_name);
+                pr_err("%s: could register provider clk %pOF\n", __func__, np);
 
         return;
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index fc58c52a26b4..c8d83acda006 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3132,7 +3132,7 @@ int of_clk_add_provider(struct device_node *np,
         mutex_lock(&of_clk_mutex);
         list_add(&cp->link, &of_clk_providers);
         mutex_unlock(&of_clk_mutex);
-        pr_debug("Added clock from %s\n", np->full_name);
+        pr_debug("Added clock from %pOF\n", np);
 
         ret = of_clk_set_defaults(np, true);
         if (ret < 0)
@@ -3167,7 +3167,7 @@ int of_clk_add_hw_provider(struct device_node *np,
         mutex_lock(&of_clk_mutex);
         list_add(&cp->link, &of_clk_providers);
         mutex_unlock(&of_clk_mutex);
-        pr_debug("Added clk_hw provider from %s\n", np->full_name);
+        pr_debug("Added clk_hw provider from %pOF\n", np);
 
         ret = of_clk_set_defaults(np, true);
         if (ret < 0)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index bb8a77a5985f..6b2f29df3f70 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -77,8 +77,8 @@ static struct clk *__of_clk_get_by_name(struct device_node *np,
                         break;
                 } else if (name && index >= 0) {
                         if (PTR_ERR(clk) != -EPROBE_DEFER)
-                                pr_err("ERROR: could not get clock %s:%s(%i)\n",
-                                        np->full_name, name ? name : "", index);
+                                pr_err("ERROR: could not get clock %pOF:%s(%i)\n",
+                                        np, name ? name : "", index);
                         return clk;
                 }
 
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index 4181b6808545..e786d717f75d 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -55,9 +55,9 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
 };
 
 static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
-        { HI6220_WDT0_PCLK,   "wdt0_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
-        { HI6220_WDT1_PCLK,   "wdt1_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
-        { HI6220_WDT2_PCLK,   "wdt2_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
+        { HI6220_WDT0_PCLK,   "wdt0_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
+        { HI6220_WDT1_PCLK,   "wdt1_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
+        { HI6220_WDT2_PCLK,   "wdt2_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
         { HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
         { HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
         { HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c
index 1e3c9ea5f9dc..7bcaf270db11 100644
--- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -416,10 +416,10 @@ static void __init mx51_clocks_init(struct device_node *np)
 
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
-        clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
-                                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
-        clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
-                                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
+        clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT);
         clk[IMX5_CLK_TVE_EXT_SEL]       = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
                                                 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
         clk[IMX5_CLK_TVE_SEL]           = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 5fd4ddac1bf1..9642cdf0fb88 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -71,7 +71,7 @@ static const char *pll5_bypass_sels[]	= { "pll5", "pll5_bypass_src", };
 static const char *pll6_bypass_sels[]   = { "pll6", "pll6_bypass_src", };
 static const char *pll7_bypass_sels[]   = { "pll7", "pll7_bypass_src", };
 
-static struct clk_div_table clk_enet_ref_table[] = {
+static const struct clk_div_table clk_enet_ref_table[] = {
         { .val = 0, .div = 20, },
         { .val = 1, .div = 10, },
         { .val = 2, .div = 5, },
@@ -79,14 +79,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
         { }
 };
 
-static struct clk_div_table post_div_table[] = {
+static const struct clk_div_table post_div_table[] = {
         { .val = 2, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 0, .div = 4, },
         { }
 };
 
-static struct clk_div_table video_div_table[] = {
+static const struct clk_div_table video_div_table[] = {
         { .val = 0, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 2, .div = 1, },
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index b5c96de41ccf..e6d389e333d7 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -105,7 +105,7 @@ static int const clks_init_on[] __initconst = {
         IMX6SX_CLK_EPIT2,
 };
 
-static struct clk_div_table clk_enet_ref_table[] = {
+static const struct clk_div_table clk_enet_ref_table[] = {
         { .val = 0, .div = 20, },
         { .val = 1, .div = 10, },
         { .val = 2, .div = 5, },
@@ -113,14 +113,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
         { }
 };
 
-static struct clk_div_table post_div_table[] = {
+static const struct clk_div_table post_div_table[] = {
         { .val = 2, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 0, .div = 4, },
         { }
 };
 
-static struct clk_div_table video_div_table[] = {
+static const struct clk_div_table video_div_table[] = {
         { .val = 0, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 2, .div = 1, },
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index b4e0dff3c8c2..5e8c18afce9a 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -78,7 +78,7 @@ static int const clks_init_on[] __initconst = {
         IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
 };
 
-static struct clk_div_table clk_enet_ref_table[] = {
+static const struct clk_div_table clk_enet_ref_table[] = {
         { .val = 0, .div = 20, },
         { .val = 1, .div = 10, },
         { .val = 2, .div = 5, },
@@ -86,14 +86,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
         { }
 };
 
-static struct clk_div_table post_div_table[] = {
+static const struct clk_div_table post_div_table[] = {
         { .val = 2, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 0, .div = 4, },
         { }
 };
 
-static struct clk_div_table video_div_table[] = {
+static const struct clk_div_table video_div_table[] = {
         { .val = 0, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 2, .div = 1, },
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 3da121826b1b..2305699db467 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -27,7 +27,7 @@ static u32 share_count_sai2;
 static u32 share_count_sai3;
 static u32 share_count_nand;
 
-static struct clk_div_table test_div_table[] = {
+static const struct clk_div_table test_div_table[] = {
         { .val = 3, .div = 1, },
         { .val = 2, .div = 1, },
         { .val = 1, .div = 2, },
@@ -35,7 +35,7 @@ static struct clk_div_table test_div_table[] = {
         { }
 };
 
-static struct clk_div_table post_div_table[] = {
+static const struct clk_div_table post_div_table[] = {
         { .val = 3, .div = 4, },
         { .val = 2, .div = 1, },
         { .val = 1, .div = 2, },
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 59b1863deb88..6dae54325a91 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -102,7 +102,7 @@ static const char *ftm_ext_sels[]	= {"sirc_128k", "sxosc", "fxosc_half", "audio_
 static const char *ftm_fix_sels[]       = { "sxosc", "ipg_bus", };
 
 
-static struct clk_div_table pll4_audio_div_table[] = {
+static const struct clk_div_table pll4_audio_div_table[] = {
         { .val = 0, .div = 1 },
         { .val = 1, .div = 2 },
         { .val = 2, .div = 6 },
diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
index edd8e6918050..16e56772d280 100644
--- a/drivers/clk/mediatek/clk-cpumux.c
+++ b/drivers/clk/mediatek/clk-cpumux.c
@@ -27,7 +27,6 @@ static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
 static u8 clk_cpumux_get_parent(struct clk_hw *hw)
 {
         struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
-        int num_parents = clk_hw_get_num_parents(hw);
         unsigned int val;
 
         regmap_read(mux->regmap, mux->reg, &val);
@@ -35,9 +34,6 @@ static u8 clk_cpumux_get_parent(struct clk_hw *hw)
         val >>= mux->shift;
         val &= mux->mask;
 
-        if (val >= num_parents)
-                return -EINVAL;
-
         return val;
 }
 
@@ -98,7 +94,7 @@ int __init mtk_clk_register_cpumuxes(struct device_node *node,
 
         regmap = syscon_node_to_regmap(node);
         if (IS_ERR(regmap)) {
-                pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
+                pr_err("Cannot find regmap for %pOF: %ld\n", node,
                        PTR_ERR(regmap));
                 return PTR_ERR(regmap);
         }
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 0541df78141c..9c0ae4278a94 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -114,7 +114,7 @@ int mtk_clk_register_gates(struct device_node *node,
 
         regmap = syscon_node_to_regmap(node);
         if (IS_ERR(regmap)) {
-                pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
+                pr_err("Cannot find regmap for %pOF: %ld\n", node,
                                 PTR_ERR(regmap));
                 return PTR_ERR(regmap);
         }
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 309049d41f1b..d3551d5efef2 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -72,7 +72,7 @@ void mtk_register_reset_controller(struct device_node *np,
 
         regmap = syscon_node_to_regmap(np);
         if (IS_ERR(regmap)) {
-                pr_err("Cannot find regmap for %s: %ld\n", np->full_name,
+                pr_err("Cannot find regmap for %pOF: %ld\n", np,
                                 PTR_ERR(regmap));
                 return;
         }
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 5588f75a8414..d2d0174a6eca 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
 config COMMON_CLK_MESON8B
         bool
         depends on COMMON_CLK_AMLOGIC
+        select RESET_CONTROLLER
         help
           Support for the clock controller on AmLogic S802 (Meson8),
           S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 83b6d9d65aa1..b139d41b25da 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
-obj-$(CONFIG_COMMON_CLK_GXBB)    += gxbb.o gxbb-aoclk.o
+obj-$(CONFIG_COMMON_CLK_GXBB)    += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
diff --git a/drivers/clk/meson/gxbb-aoclk-32k.c b/drivers/clk/meson/gxbb-aoclk-32k.c
new file mode 100644
index 000000000000..491634dbc985
--- /dev/null
+++ b/drivers/clk/meson/gxbb-aoclk-32k.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include "gxbb-aoclk.h"
+
+/*
+ * The AO Domain embeds a dual/divider to generate a more precise
+ * 32,768KHz clock for low-power suspend mode and CEC.
+ *                      ______   ______
+ *                     |      | |      |
+ *         ______      | Div1 |-| Cnt1 |       ______
+ *        |      |    /|______| |______|\     |      |
+ * Xtal-->| Gate |---|  ______   ______  X-X--| Gate |-->
+ *        |______| |  \|      | |      |/  |  |______|
+ *                 |   | Div2 |-| Cnt2 |   |
+ *                 |   |______| |______|   |
+ *                 |_______________________|
+ *
+ * The dividing can be switched to single or dual, with a counter
+ * for each divider to set when the switching is done.
+ * The entire dividing mechanism can be also bypassed.
+ */
+
+#define CLK_CNTL0_N1_MASK       GENMASK(11, 0)
+#define CLK_CNTL0_N2_MASK       GENMASK(23, 12)
+#define CLK_CNTL0_DUALDIV_EN    BIT(28)
+#define CLK_CNTL0_OUT_GATE_EN   BIT(30)
+#define CLK_CNTL0_IN_GATE_EN    BIT(31)
+
+#define CLK_CNTL1_M1_MASK       GENMASK(11, 0)
+#define CLK_CNTL1_M2_MASK       GENMASK(23, 12)
+#define CLK_CNTL1_BYPASS_EN     BIT(24)
+#define CLK_CNTL1_SELECT_OSC    BIT(27)
+
+#define PWR_CNTL_ALT_32K_SEL    GENMASK(13, 10)
+
+struct cec_32k_freq_table {
+        unsigned long parent_rate;
+        unsigned long target_rate;
+        bool dualdiv;
+        unsigned int n1;
+        unsigned int n2;
+        unsigned int m1;
+        unsigned int m2;
+};
+
+static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
+        [0] = {
+                .parent_rate = 24000000,
+                .target_rate = 32768,
+                .dualdiv = true,
+                .n1 = 733,
+                .n2 = 732,
+                .m1 = 8,
+                .m2 = 11,
+        },
+};
+
+/*
+ * If CLK_CNTL0_DUALDIV_EN == 0
+ *  - will use N1 divider only
+ * If CLK_CNTL0_DUALDIV_EN == 1
+ *  - hold M1 cycles of N1 divider then changes to N2
+ *  - hold M2 cycles of N2 divider then changes to N1
+ * Then we can get more accurate division.
+ */
+static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
+                                               unsigned long parent_rate)
+{
+        struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
+        unsigned long n1;
+        u32 reg0, reg1;
+
+        regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, &reg0);
+        regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, &reg1);
+
+        if (reg1 & CLK_CNTL1_BYPASS_EN)
+                return parent_rate;
+
+        if (reg0 & CLK_CNTL0_DUALDIV_EN) {
+                unsigned long n2, m1, m2, f1, f2, p1, p2;
+
+                n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
+                n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
+
+                m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
+                m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
+
+                f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
+                f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
+
+                p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
+                p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
+
+                return DIV_ROUND_UP(100000000, p1 + p2);
+        }
+
+        n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
+
+        return DIV_ROUND_CLOSEST(parent_rate, n1);
+}
+
+static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
+                                                          unsigned long prate)
+{
+        int i;
+
+        for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
+                if (aoclk_cec_32k_table[i].parent_rate == prate &&
+                    aoclk_cec_32k_table[i].target_rate == rate)
+                        return &aoclk_cec_32k_table[i];
+
+        return NULL;
+}
+
+static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
+                                     unsigned long *prate)
+{
+        const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
+                                                                  *prate);
+
+        /* If invalid return first one */
+        if (!freq)
+                return aoclk_cec_32k_table[0].target_rate;
+
+        return freq->target_rate;
+}
+
+/*
+ * From the Amlogic init procedure, the IN and OUT gates needs to be handled
+ * in the init procedure to avoid any glitches.
+ */
+
+static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
+                                  unsigned long parent_rate)
+{
+        const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
+                                                                  parent_rate);
+        struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
+        u32 reg = 0;
+
+        if (!freq)
+                return -EINVAL;
+
+        /* Disable clock */
+        regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
+                           CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
+
+        reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
+        if (freq->dualdiv)
+                reg |= CLK_CNTL0_DUALDIV_EN |
+                       FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
+
+        regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
+
+        reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
+        if (freq->dualdiv)
+                reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
+
+        regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
+
+        /* Enable clock */
+        regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
+                           CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
+
+        udelay(200);
+
+        regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
+                           CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
+
+        regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
+                           CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
+
+        /* Select 32k from XTAL */
+        regmap_update_bits(cec_32k->regmap,
+                          AO_RTI_PWR_CNTL_REG0,
+                          PWR_CNTL_ALT_32K_SEL,
+                          FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
+
+        return 0;
+}
+
+const struct clk_ops meson_aoclk_cec_32k_ops = {
+        .recalc_rate = aoclk_cec_32k_recalc_rate,
+        .round_rate = aoclk_cec_32k_round_rate,
+        .set_rate = aoclk_cec_32k_set_rate,
+};
diff --git a/drivers/clk/meson/gxbb-aoclk-regmap.c b/drivers/clk/meson/gxbb-aoclk-regmap.c
new file mode 100644
index 000000000000..2515fbfa0467
--- /dev/null
+++ b/drivers/clk/meson/gxbb-aoclk-regmap.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/bitfield.h>
+#include <linux/regmap.h>
+#include "gxbb-aoclk.h"
+
+static int aoclk_gate_regmap_enable(struct clk_hw *hw)
+{
+        struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
+
+        return regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
+                                  BIT(gate->bit_idx), BIT(gate->bit_idx));
+}
+
+static void aoclk_gate_regmap_disable(struct clk_hw *hw)
+{
+        struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
+
+        regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
+                           BIT(gate->bit_idx), 0);
+}
+
+static int aoclk_gate_regmap_is_enabled(struct clk_hw *hw)
+{
+        struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
+        unsigned int val;
+        int ret;
+
+        ret = regmap_read(gate->regmap, AO_RTI_GEN_CNTL_REG0, &val);
+        if (ret)
+                return ret;
+
+        return (val & BIT(gate->bit_idx)) != 0;
+}
+
+const struct clk_ops meson_aoclk_gate_regmap_ops = {
+        .enable = aoclk_gate_regmap_enable,
+        .disable = aoclk_gate_regmap_disable,
+        .is_enabled = aoclk_gate_regmap_is_enabled,
+};
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index b45c5fba7e35..6c161e0a8e59 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -56,16 +56,20 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <dt-bindings/clock/gxbb-aoclkc.h>
 #include <dt-bindings/reset/gxbb-aoclkc.h>
+#include "gxbb-aoclk.h"
 
 static DEFINE_SPINLOCK(gxbb_aoclk_lock);
 
 struct gxbb_aoclk_reset_controller {
         struct reset_controller_dev reset;
         unsigned int *data;
-        void __iomem *base;
+        struct regmap *regmap;
 };
 
 static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
@@ -74,9 +78,8 @@ static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
         struct gxbb_aoclk_reset_controller *reset =
                 container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
 
-        writel(BIT(reset->data[id]), reset->base);
-
-        return 0;
+        return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
+                            BIT(reset->data[id]));
 }
 
 static const struct reset_control_ops gxbb_aoclk_reset_ops = {
@@ -84,13 +87,12 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = {
 };
 
 #define GXBB_AO_GATE(_name, _bit)                                       \
-static struct clk_gate _name##_ao = {                                   \
-        .reg = (void __iomem *)0,                                       \
+static struct aoclk_gate_regmap _name##_ao = {                          \
         .bit_idx = (_bit),                                              \
         .lock = &gxbb_aoclk_lock,                                       \
         .hw.init = &(struct clk_init_data) {                            \
                 .name = #_name "_ao",                                   \
-                .ops = &clk_gate_ops,                                   \
+                .ops = &meson_aoclk_gate_regmap_ops,                    \
                 .parent_names = (const char *[]){ "clk81" },            \
                 .num_parents = 1,                                       \
                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),     \
@@ -104,6 +106,17 @@ GXBB_AO_GATE(uart1, 3);
 GXBB_AO_GATE(uart2, 5);
 GXBB_AO_GATE(ir_blaster, 6);
 
+static struct aoclk_cec_32k cec_32k_ao = {
+        .lock = &gxbb_aoclk_lock,
+        .hw.init = &(struct clk_init_data) {
+                .name = "cec_32k_ao",
+                .ops = &meson_aoclk_cec_32k_ops,
+                .parent_names = (const char *[]){ "xtal" },
+                .num_parents = 1,
+                .flags = CLK_IGNORE_UNUSED,
+        },
+};
+
 static unsigned int gxbb_aoclk_reset[] = {
         [RESET_AO_REMOTE] = 16,
         [RESET_AO_I2C_MASTER] = 18,
@@ -113,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = {
         [RESET_AO_IR_BLASTER] = 23,
 };
 
-static struct clk_gate *gxbb_aoclk_gate[] = {
+static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
         [CLKID_AO_REMOTE] = &remote_ao,
         [CLKID_AO_I2C_MASTER] = &i2c_master_ao,
         [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
@@ -130,30 +143,30 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
                 [CLKID_AO_UART1] = &uart1_ao.hw,
                 [CLKID_AO_UART2] = &uart2_ao.hw,
                 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
+                [CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
         },
-        .num = ARRAY_SIZE(gxbb_aoclk_gate),
+        .num = 7,
 };
 
 static int gxbb_aoclkc_probe(struct platform_device *pdev)
 {
-        struct resource *res;
-        void __iomem *base;
-        int ret, clkid;
-        struct device *dev = &pdev->dev;
         struct gxbb_aoclk_reset_controller *rstc;
+        struct device *dev = &pdev->dev;
+        struct regmap *regmap;
+        int ret, clkid;
 
         rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
         if (!rstc)
                 return -ENOMEM;
 
-        /* Generic clocks */
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        base = devm_ioremap_resource(dev, res);
-        if (IS_ERR(base))
-                return PTR_ERR(base);
+        regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+        if (IS_ERR(regmap)) {
+                dev_err(dev, "failed to get regmap\n");
+                return -ENODEV;
+        }
 
         /* Reset Controller */
-        rstc->base = base;
+        rstc->regmap = regmap;
         rstc->data = gxbb_aoclk_reset;
         rstc->reset.ops = &gxbb_aoclk_reset_ops;
         rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
@@ -161,10 +174,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
         ret = devm_reset_controller_register(dev, &rstc->reset);
 
         /*
-         * Populate base address and register all clks
+         * Populate regmap and register all clks
          */
-        for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
-                gxbb_aoclk_gate[clkid]->reg = base;
+        for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
+                gxbb_aoclk_gate[clkid]->regmap = regmap;
 
                 ret = devm_clk_hw_register(dev,
                                         gxbb_aoclk_onecell_data.hws[clkid]);
@@ -172,12 +185,18 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
                         return ret;
         }
 
+        /* Specific clocks */
+        cec_32k_ao.regmap = regmap;
+        ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
+        if (ret)
+                return ret;
+
         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
                         &gxbb_aoclk_onecell_data);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-        { .compatible = "amlogic,gxbb-aoclkc" },
+        { .compatible = "amlogic,meson-gx-aoclkc" },
         { }
 };
 
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
new file mode 100644
index 000000000000..e8604c8f7eee
--- /dev/null
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GXBB_AOCLKC_H
+#define __GXBB_AOCLKC_H
+
+/* AO Configuration Clock registers offsets */
+#define AO_RTI_PWR_CNTL_REG1    0x0c
+#define AO_RTI_PWR_CNTL_REG0    0x10
+#define AO_RTI_GEN_CNTL_REG0    0x40
+#define AO_OSCIN_CNTL           0x58
+#define AO_CRT_CLK_CNTL1        0x68
+#define AO_RTC_ALT_CLK_CNTL0    0x94
+#define AO_RTC_ALT_CLK_CNTL1    0x98
+
+struct aoclk_gate_regmap {
+        struct clk_hw hw;
+        unsigned bit_idx;
+        struct regmap *regmap;
+        spinlock_t *lock;
+};
+
+#define to_aoclk_gate_regmap(_hw) \
+        container_of(_hw, struct aoclk_gate_regmap, hw)
+
+extern const struct clk_ops meson_aoclk_gate_regmap_ops;
+
+struct aoclk_cec_32k {
+        struct clk_hw hw;
+        struct regmap *regmap;
+        spinlock_t *lock;
+};
+
+#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
+
+extern const struct clk_ops meson_aoclk_cec_32k_ops;
+
+#endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 964489b39f6a..b2d1e8ed7152 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -850,13 +850,14 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
                 .shift   = 0,
                 .width   = 8,
         },
+        .flags = CLK_DIVIDER_ROUND_CLOSEST,
         .lock = &clk_lock,
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk_div",
                 .ops = &meson_clk_audio_divider_ops,
                 .parent_names = (const char *[]){ "cts_amclk_sel" },
                 .num_parents = 1,
-                .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -880,7 +881,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
         /* Default parent unknown (register reset value: 0) */
         .table = (u32[]){ 1, 2, 3 },
         .lock = &clk_lock,
-                .hw.init = &(struct clk_init_data){
+        .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_sel",
                 .ops = &clk_mux_ops,
                 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
@@ -894,12 +895,13 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
         .shift = 16,
         .width = 8,
         .lock = &clk_lock,
-        .hw.init = &(struct clk_init_data){
+        .flags = CLK_DIVIDER_ROUND_CLOSEST,
+        .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_div",
                 .ops = &clk_divider_ops,
                 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
                 .num_parents = 1,
-                .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -979,6 +981,156 @@ static struct clk_mux gxbb_32k_clk_sel = {
         },
 };
 
+static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
+        "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
+
+        /*
+         * Following these parent clocks, we should also have had mpll2, mpll3
+         * and gp0_pll but these clocks are too precious to be used here. All
+         * the necessary rates for MMC and NAND operation can be acheived using
+         * xtal or fclk_div clocks
+         */
+};
+
+/* SDIO clock */
+static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .mask = 0x7,
+        .shift = 9,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_a_clk0_sel",
+                .ops = &clk_mux_ops,
+                .parent_names = gxbb_sd_emmc_clk0_parent_names,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .shift = 0,
+        .width = 7,
+        .lock = &clk_lock,
+        .flags = CLK_DIVIDER_ROUND_CLOSEST,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_a_clk0_div",
+                .ops = &clk_divider_ops,
+                .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_gate gxbb_sd_emmc_a_clk0 = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .bit_idx = 7,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sd_emmc_a_clk0",
+                .ops = &clk_gate_ops,
+                .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
+                .num_parents = 1,
+
+                /*
+                 * FIXME:
+                 * We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
+                 * instead of this clock. CCF would gate this on boot, killing
+                 * the mmc controller. Please remove this flag once DT properly
+                 * point to this clock instead of xtal
+                 *
+                 * Same goes for emmc B and C clocks
+                 */
+                .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+        },
+};
+
+/* SDcard clock */
+static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .mask = 0x7,
+        .shift = 25,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_b_clk0_sel",
+                .ops = &clk_mux_ops,
+                .parent_names = gxbb_sd_emmc_clk0_parent_names,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .shift = 16,
+        .width = 7,
+        .lock = &clk_lock,
+        .flags = CLK_DIVIDER_ROUND_CLOSEST,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_b_clk0_div",
+                .ops = &clk_divider_ops,
+                .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_gate gxbb_sd_emmc_b_clk0 = {
+        .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
+        .bit_idx = 23,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sd_emmc_b_clk0",
+                .ops = &clk_gate_ops,
+                .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+        },
+};
+
+/* EMMC/NAND clock */
+static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
+        .reg = (void *)HHI_NAND_CLK_CNTL,
+        .mask = 0x7,
+        .shift = 9,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_c_clk0_sel",
+                .ops = &clk_mux_ops,
+                .parent_names = gxbb_sd_emmc_clk0_parent_names,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
+        .reg = (void *)HHI_NAND_CLK_CNTL,
+        .shift = 0,
+        .width = 7,
+        .lock = &clk_lock,
+        .flags = CLK_DIVIDER_ROUND_CLOSEST,
+        .hw.init = &(struct clk_init_data) {
+                .name = "sd_emmc_c_clk0_div",
+                .ops = &clk_divider_ops,
+                .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_gate gxbb_sd_emmc_c_clk0 = {
+        .reg = (void *)HHI_NAND_CLK_CNTL,
+        .bit_idx = 7,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sd_emmc_c_clk0",
+                .ops = &clk_gate_ops,
+                .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+        },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1188,6 +1340,15 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
+                [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
+                [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
+                [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
+                [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
+                [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
+                [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
+                [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
+                [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
+                [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
                 [NR_CLKS]                   = NULL,
         },
         .num = NR_CLKS,
@@ -1311,6 +1472,15 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
+                [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
+                [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
+                [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
+                [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
+                [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
+                [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
+                [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
+                [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
+                [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
                 [NR_CLKS]                   = NULL,
         },
         .num = NR_CLKS,
@@ -1427,6 +1597,9 @@ static struct clk_gate *const gxbb_clk_gates[] = {
         &gxbb_cts_amclk,
         &gxbb_cts_mclk_i958,
         &gxbb_32k_clk,
+        &gxbb_sd_emmc_a_clk0,
+        &gxbb_sd_emmc_b_clk0,
+        &gxbb_sd_emmc_c_clk0,
 };
 
 static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1439,6 +1612,9 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
         &gxbb_cts_mclk_i958_sel,
         &gxbb_cts_i958,
         &gxbb_32k_clk_sel,
+        &gxbb_sd_emmc_a_clk0_sel,
+        &gxbb_sd_emmc_b_clk0_sel,
+        &gxbb_sd_emmc_c_clk0_sel,
 };
 
 static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1448,6 +1624,9 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
         &gxbb_mali_1_div,
         &gxbb_cts_mclk_i958_div,
         &gxbb_32k_clk_div,
+        &gxbb_sd_emmc_a_clk0_div,
+        &gxbb_sd_emmc_b_clk0_div,
+        &gxbb_sd_emmc_c_clk0_div,
 };
 
 static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index cb60a516ca82..20ab7190d328 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -25,6 +25,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 
 #include "clkc.h"
@@ -32,6 +34,13 @@
 
 static DEFINE_SPINLOCK(clk_lock);
 
+static void __iomem *clk_base;
+
+struct meson8b_clk_reset {
+        struct reset_controller_dev reset;
+        void __iomem *base;
+};
+
 static const struct pll_rate_table sys_pll_rate_table[] = {
         PLL_RATE(312000000, 52, 1, 2),
         PLL_RATE(336000000, 56, 1, 2),
@@ -696,20 +705,114 @@ static struct clk_divider *const meson8b_clk_dividers[] = {
         &meson8b_mpeg_clk_div,
 };
 
+static const struct meson8b_clk_reset_line {
+        u32 reg;
+        u8 bit_idx;
+} meson8b_clk_reset_bits[] = {
+        [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
+        },
+        [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
+        },
+        [CLKC_RESET_SCU_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
+        },
+        [CLKC_RESET_CPU3_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
+        },
+        [CLKC_RESET_CPU2_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
+        },
+        [CLKC_RESET_CPU1_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
+        },
+        [CLKC_RESET_CPU0_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
+        },
+        [CLKC_RESET_A5_GLOBAL_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
+        },
+        [CLKC_RESET_A5_AXI_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
+        },
+        [CLKC_RESET_A5_ABP_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
+        },
+        [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
+                .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
+        },
+        [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
+                .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
+        },
+        [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
+                .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
+        },
+        [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
+                .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
+        },
+        [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
+                .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
+        },
+        [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
+                .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
+        },
+};
+
+static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
+                                    unsigned long id, bool assert)
+{
+        struct meson8b_clk_reset *meson8b_clk_reset =
+                container_of(rcdev, struct meson8b_clk_reset, reset);
+        unsigned long flags;
+        const struct meson8b_clk_reset_line *reset;
+        u32 val;
+
+        if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
+                return -EINVAL;
+
+        reset = &meson8b_clk_reset_bits[id];
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        val = readl(meson8b_clk_reset->base + reset->reg);
+        if (assert)
+                val |= BIT(reset->bit_idx);
+        else
+                val &= ~BIT(reset->bit_idx);
+        writel(val, meson8b_clk_reset->base + reset->reg);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+
+static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
+                                     unsigned long id)
+{
+        return meson8b_clk_reset_update(rcdev, id, true);
+}
+
+static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
+                                       unsigned long id)
+{
+        return meson8b_clk_reset_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson8b_clk_reset_ops = {
+        .assert = meson8b_clk_reset_assert,
+        .deassert = meson8b_clk_reset_deassert,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
-        void __iomem *clk_base;
         int ret, clkid, i;
         struct clk_hw *parent_hw;
         struct clk *parent_clk;
         struct device *dev = &pdev->dev;
 
-        /*  Generic clocks and PLLs */
-        clk_base = of_iomap(dev->of_node, 1);
-        if (!clk_base) {
-                pr_err("%s: Unable to map clk base\n", __func__);
+        if (!clk_base)
                 return -ENXIO;
-        }
 
         /* Populate base address for PLLs */
         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
@@ -749,7 +852,7 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
                 /* FIXME convert to devm_clk_register */
                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
                 if (ret)
-                        goto iounmap;
+                        return ret;
         }
 
         /*
@@ -772,15 +875,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
         if (ret) {
                 pr_err("%s: failed to register clock notifier for cpu_clk\n",
                                 __func__);
-                goto iounmap;
+                return ret;
         }
 
         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
                         &meson8b_hw_onecell_data);
-
-iounmap:
-        iounmap(clk_base);
-        return ret;
 }
 
 static const struct of_device_id meson8b_clkc_match_table[] = {
@@ -799,3 +898,39 @@ static struct platform_driver meson8b_driver = {
 };
 
 builtin_platform_driver(meson8b_driver);
+
+static void __init meson8b_clkc_reset_init(struct device_node *np)
+{
+        struct meson8b_clk_reset *rstc;
+        int ret;
+
+        /* Generic clocks, PLLs and some of the reset-bits */
+        clk_base = of_iomap(np, 1);
+        if (!clk_base) {
+                pr_err("%s: Unable to map clk base\n", __func__);
+                return;
+        }
+
+        rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+        if (!rstc)
+                return;
+
+        /* Reset Controller */
+        rstc->base = clk_base;
+        rstc->reset.ops = &meson8b_clk_reset_ops;
+        rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
+        rstc->reset.of_node = np;
+        ret = reset_controller_register(&rstc->reset);
+        if (ret) {
+                pr_err("%s: Failed to register clkc reset controller: %d\n",
+                       __func__, ret);
+                return;
+        }
+}
+
+CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
+                      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
+                      meson8b_clkc_reset_init);
+CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
+                      meson8b_clkc_reset_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index c139bb3273ca..2eaf8a52e7dd 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -37,6 +37,9 @@
 #define HHI_GCLK_AO                     0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1           0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL               0x174 /* 0x5d offset in data sheet */
+#define HHI_VID_CLK_CNTL                0x17c /* 0x5f offset in data sheet */
+#define HHI_VID_DIVIDER_CNTL            0x198 /* 0x66 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0           0x19c /* 0x67 offset in data sheet */
 #define HHI_MPLL_CNTL                   0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL                0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL                0x320 /* 0xc8 offset in data sheet */
@@ -68,7 +71,11 @@
 
 #define CLK_NR_CLKS             96
 
-/* include the CLKIDs that have been made part of the stable DT binding */
+/*
+ * include the CLKID and RESETID that have
+ * been made part of the stable DT binding
+ */
 #include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 
 #endif /* __MESON8B_H */
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c
index 61893fe73251..089927e4cda2 100644
--- a/drivers/clk/mmp/clk.c
+++ b/drivers/clk/mmp/clk.c
@@ -9,7 +9,7 @@
 void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
                 int nr_clks)
 {
-        static struct clk **clk_table;
+        struct clk **clk_table;
 
         clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
         if (!clk_table)
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 5b98ff9076f3..7b359afd620e 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -885,7 +885,7 @@ static const struct clk_ops clk_usb_i2c_ops = {
         .recalc_rate = clk_usb_i2c_recalc_rate,
 };
 
-static int clk_gate_enable(struct clk_hw *hw)
+static int lpc32xx_clk_gate_enable(struct clk_hw *hw)
 {
         struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
         u32 mask = BIT(clk->bit_idx);
@@ -894,7 +894,7 @@ static int clk_gate_enable(struct clk_hw *hw)
         return regmap_update_bits(clk_regmap, clk->reg, mask, val);
 }
 
-static void clk_gate_disable(struct clk_hw *hw)
+static void lpc32xx_clk_gate_disable(struct clk_hw *hw)
 {
         struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
         u32 mask = BIT(clk->bit_idx);
@@ -903,7 +903,7 @@ static void clk_gate_disable(struct clk_hw *hw)
         regmap_update_bits(clk_regmap, clk->reg, mask, val);
 }
 
-static int clk_gate_is_enabled(struct clk_hw *hw)
+static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw)
 {
         struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
         u32 val;
@@ -916,9 +916,9 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 }
 
 static const struct clk_ops lpc32xx_clk_gate_ops = {
-        .enable = clk_gate_enable,
-        .disable = clk_gate_disable,
-        .is_enabled = clk_gate_is_enabled,
+        .enable = lpc32xx_clk_gate_enable,
+        .disable = lpc32xx_clk_gate_disable,
+        .is_enabled = lpc32xx_clk_gate_is_enabled,
 };
 
 #define div_mask(width) ((1 << (width)) - 1)
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index d990fe44aef3..cc03d5508627 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -412,8 +412,6 @@ static const struct clk_ops clk_smd_rpm_ops = {
 static const struct clk_ops clk_smd_rpm_branch_ops = {
         .prepare        = clk_smd_rpm_prepare,
         .unprepare      = clk_smd_rpm_unprepare,
-        .round_rate     = clk_smd_rpm_round_rate,
-        .recalc_rate    = clk_smd_rpm_recalc_rate,
 };
 
 /* msm8916 */
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 2cfe7000fc60..3410ee68d4bc 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1176,7 +1176,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
                 .parent_names = gcc_xo_gpll0_bimc,
                 .num_parents = 3,
                 .flags = CLK_GET_RATE_NOCACHE,
-                .ops = &clk_rcg2_shared_ops,
+                .ops = &clk_rcg2_ops,
         },
 };
 
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 8abc200d4fd3..7ddec886fcd3 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -2730,6 +2730,32 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
         },
 };
 
+static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
+        .halt_reg = 0x7d010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x7d010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "hlos1_vote_lpass_core_smmu_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
+        .halt_reg = 0x7d014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x7d014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "hlos1_vote_lpass_adsp_smmu_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
 static struct clk_branch gcc_ufs_rx_cfg_clk = {
         .halt_reg = 0x75014,
         .clkr = {
@@ -3307,6 +3333,8 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
+        [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
+        [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 78d1df9112ba..acbb38151ba1 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -15,6 +15,7 @@ config CLK_RENESAS
         select CLK_R8A7794 if ARCH_R8A7794
         select CLK_R8A7795 if ARCH_R8A7795
         select CLK_R8A7796 if ARCH_R8A7796
+        select CLK_R8A77995 if ARCH_R8A77995
         select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -34,94 +35,103 @@ config CLK_EMEV2
         bool "Emma Mobile EV2 clock support" if COMPILE_TEST
 
 config CLK_RZA1
-        bool
+        bool "RZ/A1H clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
 
 config CLK_R8A73A4
-        bool
+        bool "R-Mobile APE6 clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
         select CLK_RENESAS_DIV6
 
 config CLK_R8A7740
-        bool
+        bool "R-Mobile A1 clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
         select CLK_RENESAS_DIV6
 
 config CLK_R8A7743
-        bool
+        bool "RZ/G1M clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2_CPG
 
 config CLK_R8A7745
-        bool
+        bool "RZ/G1E clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2_CPG
 
 config CLK_R8A7778
-        bool
+        bool "R-Car M1A clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
 
 config CLK_R8A7779
-        bool
+        bool "R-Car H1 clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
 
 config CLK_R8A7790
-        bool
+        bool "R-Car H2 clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
         select CLK_RCAR_GEN2_CPG
         select CLK_RENESAS_DIV6
 
 config CLK_R8A7791
-        bool
+        bool "R-Car M2-W/N clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
         select CLK_RCAR_GEN2_CPG
         select CLK_RENESAS_DIV6
 
 config CLK_R8A7792
-        bool
+        bool "R-Car V2H clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
         select CLK_RCAR_GEN2_CPG
 
 config CLK_R8A7794
-        bool
+        bool "R-Car E2 clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
         select CLK_RCAR_GEN2_CPG
         select CLK_RENESAS_DIV6
 
 config CLK_R8A7795
-        bool
+        bool "R-Car H3 clock support" if COMPILE_TEST
         select CLK_RCAR_GEN3_CPG
 
 config CLK_R8A7796
-        bool
+        bool "R-Car M3-W clock support" if COMPILE_TEST
+        select CLK_RCAR_GEN3_CPG
+
+config CLK_R8A77995
+        bool "R-Car D3 clock support" if COMPILE_TEST
         select CLK_RCAR_GEN3_CPG
 
 config CLK_SH73A0
-        bool
+        bool "SH-Mobile AG5 clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
         select CLK_RENESAS_DIV6
 
 
 # Family
 config CLK_RCAR_GEN2
-        bool
+        bool "R-Car Gen2 legacy clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
         select CLK_RENESAS_DIV6
 
 config CLK_RCAR_GEN2_CPG
-        bool
+        bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSSR
 
 config CLK_RCAR_GEN3_CPG
-        bool
+        bool "R-Car Gen3 CPG clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSSR
 
+config CLK_RCAR_USB2_CLOCK_SEL
+        bool "Renesas R-Car USB2 clock selector support"
+        depends on ARCH_RENESAS || COMPILE_TEST
+        help
+          This is a driver for R-Car USB2 clock selector
 
 # Generic
 config CLK_RENESAS_CPG_MSSR
-        bool
+        bool "CPG/MSSR clock support" if COMPILE_TEST
         select CLK_RENESAS_DIV6
 
 config CLK_RENESAS_CPG_MSTP
-        bool
+        bool "MSTP clock support" if COMPILE_TEST
 
 config CLK_RENESAS_DIV6
         bool "DIV6 clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 02d04124371f..9bda3ec5b199 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -13,12 +13,14 @@ obj-$(CONFIG_CLK_R8A7792)		+= r8a7792-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7794)               += r8a7794-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7795)               += r8a7795-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7796)               += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77995)              += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_SH73A0)                += clk-sh73a0.o
 
 # Family
 obj-$(CONFIG_CLK_RCAR_GEN2)             += clk-rcar-gen2.o
 obj-$(CONFIG_CLK_RCAR_GEN2_CPG)         += rcar-gen2-cpg.o
 obj-$(CONFIG_CLK_RCAR_GEN3_CPG)         += rcar-gen3-cpg.o
+obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)   += rcar-usb2-clock-sel.o
 
 # Generic
 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)      += renesas-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 0627860233cb..3e0040c0ac87 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -29,6 +29,9 @@
  * @hw: handle between common and hardware-specific interfaces
  * @reg: IO-remapped register
  * @div: divisor value (1-64)
+ * @src_shift: Shift to access the register bits to select the parent clock
+ * @src_width: Number of register bits to select the parent clock (may be 0)
+ * @parents: Array to map from valid parent clocks indices to hardware indices
  */
 struct div6_clock {
         struct clk_hw hw;
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index f1617dd044cb..500a9e4e03c4 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -335,7 +335,7 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
         u32 ncells;
 
         if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
-                pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+                pr_warn("%pOF lacks #power-domain-cells\n", np);
                 return;
         }
 
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 51a2479ed5d7..0b2e56d0d94b 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -407,8 +407,7 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 
         if (rcar_rst_read_mode_pins(&cpg_mode)) {
                 /* Backward-compatibility with old DT */
-                pr_warn("%s: failed to obtain mode pins from RST\n",
-                        np->full_name);
+                pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
                 cpg_mode = rcar_gen2_read_mode_pins();
         }
 
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index a832b9b6f7b0..7f85bbf20bf7 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -118,6 +118,13 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
         DEF_MOD("vin1",                  810,   R8A7792_CLK_ZG),
         DEF_MOD("vin0",                  811,   R8A7792_CLK_ZG),
         DEF_MOD("etheravb",              812,   R8A7792_CLK_HP),
+        DEF_MOD("imr-lx3",               821,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-1",            822,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-0",            823,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-5",            825,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-4",            826,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-3",            827,   R8A7792_CLK_ZG),
+        DEF_MOD("imr-lsx3-2",            828,   R8A7792_CLK_ZG),
         DEF_MOD("gyro-adc",              901,   R8A7792_CLK_P),
         DEF_MOD("gpio7",                 904,   R8A7792_CLK_CP),
         DEF_MOD("gpio6",                 905,   R8A7792_CLK_CP),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index c091a8e024b8..762b2f8824f1 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -305,23 +305,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
                                          (((md) & BIT(17)) >> 17))
 
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
-        /* EXTAL div    PLL1 mult       PLL3 mult */
-        { 1,            192,            192,    },
-        { 1,            192,            128,    },
-        { 0, /* Prohibited setting */           },
-        { 1,            192,            192,    },
-        { 1,            160,            160,    },
-        { 1,            160,            106,    },
-        { 0, /* Prohibited setting */           },
-        { 1,            160,            160,    },
-        { 1,            128,            128,    },
-        { 1,            128,            84,     },
-        { 0, /* Prohibited setting */           },
-        { 1,            128,            128,    },
-        { 2,            192,            192,    },
-        { 2,            192,            128,    },
-        { 0, /* Prohibited setting */           },
-        { 2,            192,            192,    },
+        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
+        { 1,            192,    1,      192,    1,      },
+        { 1,            192,    1,      128,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            192,    1,      192,    1,      },
+        { 1,            160,    1,      160,    1,      },
+        { 1,            160,    1,      106,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            160,    1,      160,    1,      },
+        { 1,            128,    1,      128,    1,      },
+        { 1,            128,    1,      84,     1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            128,    1,      128,    1,      },
+        { 2,            192,    1,      192,    1,      },
+        { 2,            192,    1,      128,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 2,            192,    1,      192,    1,      },
 };
 
 static const struct soc_device_attribute r8a7795es1[] __initconst = {
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index acc6d0f153e1..e5e7fb212288 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -138,6 +138,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
         DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
         DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
+        DEF_MOD("usb3-if0",              328,   R8A7796_CLK_S3D1),
         DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
         DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
         DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
@@ -277,23 +278,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
                                          (((md) & BIT(17)) >> 17))
 
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
-        /* EXTAL div    PLL1 mult       PLL3 mult */
-        { 1,            192,            192,    },
-        { 1,            192,            128,    },
-        { 0, /* Prohibited setting */           },
-        { 1,            192,            192,    },
-        { 1,            160,            160,    },
-        { 1,            160,            106,    },
-        { 0, /* Prohibited setting */           },
-        { 1,            160,            160,    },
-        { 1,            128,            128,    },
-        { 1,            128,            84,     },
-        { 0, /* Prohibited setting */           },
-        { 1,            128,            128,    },
-        { 2,            192,            192,    },
-        { 2,            192,            128,    },
-        { 0, /* Prohibited setting */           },
-        { 2,            192,            192,    },
+        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
+        { 1,            192,    1,      192,    1,      },
+        { 1,            192,    1,      128,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            192,    1,      192,    1,      },
+        { 1,            160,    1,      160,    1,      },
+        { 1,            160,    1,      106,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            160,    1,      160,    1,      },
+        { 1,            128,    1,      128,    1,      },
+        { 1,            128,    1,      84,     1,      },
+        { 0, /* Prohibited setting */                   },
+        { 1,            128,    1,      128,    1,      },
+        { 2,            192,    1,      192,    1,      },
+        { 2,            192,    1,      128,    1,      },
+        { 0, /* Prohibited setting */                   },
+        { 2,            192,    1,      192,    1,      },
 };
 
 static int __init r8a7796_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
new file mode 100644
index 000000000000..e594cf8ee63b
--- /dev/null
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -0,0 +1,236 @@
+/*
+ * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+        /* Core Clock Outputs exported to DT */
+        LAST_DT_CORE_CLK = R8A77995_CLK_CP,
+
+        /* External Input Clocks */
+        CLK_EXTAL,
+
+        /* Internal Core Clocks */
+        CLK_MAIN,
+        CLK_PLL0,
+        CLK_PLL1,
+        CLK_PLL3,
+        CLK_PLL0D2,
+        CLK_PLL0D3,
+        CLK_PLL0D5,
+        CLK_PLL1D2,
+        CLK_PE,
+        CLK_S0,
+        CLK_S1,
+        CLK_S2,
+        CLK_S3,
+        CLK_SDSRC,
+        CLK_SSPSRC,
+
+        /* Module Clocks */
+        MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
+        /* External Clock Inputs */
+        DEF_INPUT("extal",     CLK_EXTAL),
+
+        /* Internal Core Clocks */
+        DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
+        DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
+        DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
+
+        DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       4, 250),
+        DEF_FIXED(".pll0d2",   CLK_PLL0D2,         CLK_PLL0,       2, 1),
+        DEF_FIXED(".pll0d3",   CLK_PLL0D3,         CLK_PLL0,       3, 1),
+        DEF_FIXED(".pll0d5",   CLK_PLL0D5,         CLK_PLL0,       5, 1),
+        DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
+        DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D3,     4, 1),
+        DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
+        DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
+        DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
+        DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
+        DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
+
+        /* Core Clock Outputs */
+        DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
+        DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
+        DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
+        DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),
+        DEF_FIXED("s0d1",      R8A77995_CLK_S0D1,  CLK_S0,         1, 1),
+        DEF_FIXED("s1d1",      R8A77995_CLK_S1D1,  CLK_S1,         1, 1),
+        DEF_FIXED("s1d2",      R8A77995_CLK_S1D2,  CLK_S1,         2, 1),
+        DEF_FIXED("s1d4",      R8A77995_CLK_S1D4,  CLK_S1,         4, 1),
+        DEF_FIXED("s2d1",      R8A77995_CLK_S2D1,  CLK_S2,         1, 1),
+        DEF_FIXED("s2d2",      R8A77995_CLK_S2D2,  CLK_S2,         2, 1),
+        DEF_FIXED("s2d4",      R8A77995_CLK_S2D4,  CLK_S2,         4, 1),
+        DEF_FIXED("s3d1",      R8A77995_CLK_S3D1,  CLK_S3,         1, 1),
+        DEF_FIXED("s3d2",      R8A77995_CLK_S3D2,  CLK_S3,         2, 1),
+        DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
+
+        DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
+        DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
+        DEF_FIXED("osc",       R8A77995_CLK_OSC,   CLK_EXTAL,    384, 1),
+        DEF_FIXED("r",         R8A77995_CLK_R,     CLK_EXTAL,   1536, 1),
+
+        DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+        DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+        DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+        DEF_GEN3_PE("s3d4c",   R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+        DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,   CLK_SDSRC,     0x268),
+
+        DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
+        DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
+        DEF_MOD("scif5",                 202,   R8A77995_CLK_S3D4C),
+        DEF_MOD("scif4",                 203,   R8A77995_CLK_S3D4C),
+        DEF_MOD("scif3",                 204,   R8A77995_CLK_S3D4C),
+        DEF_MOD("scif1",                 206,   R8A77995_CLK_S3D4C),
+        DEF_MOD("scif0",                 207,   R8A77995_CLK_S3D4C),
+        DEF_MOD("msiof3",                208,   R8A77995_CLK_MSO),
+        DEF_MOD("msiof2",                209,   R8A77995_CLK_MSO),
+        DEF_MOD("msiof1",                210,   R8A77995_CLK_MSO),
+        DEF_MOD("msiof0",                211,   R8A77995_CLK_MSO),
+        DEF_MOD("sys-dmac2",             217,   R8A77995_CLK_S3D1),
+        DEF_MOD("sys-dmac1",             218,   R8A77995_CLK_S3D1),
+        DEF_MOD("sys-dmac0",             219,   R8A77995_CLK_S3D1),
+        DEF_MOD("cmt3",                  300,   R8A77995_CLK_R),
+        DEF_MOD("cmt2",                  301,   R8A77995_CLK_R),
+        DEF_MOD("cmt1",                  302,   R8A77995_CLK_R),
+        DEF_MOD("cmt0",                  303,   R8A77995_CLK_R),
+        DEF_MOD("scif2",                 310,   R8A77995_CLK_S3D4C),
+        DEF_MOD("emmc0",                 312,   R8A77995_CLK_SD0),
+        DEF_MOD("usb-dmac0",             330,   R8A77995_CLK_S3D1),
+        DEF_MOD("usb-dmac1",             331,   R8A77995_CLK_S3D1),
+        DEF_MOD("rwdt",                  402,   R8A77995_CLK_R),
+        DEF_MOD("intc-ex",               407,   R8A77995_CLK_CP),
+        DEF_MOD("intc-ap",               408,   R8A77995_CLK_S3D1),
+        DEF_MOD("audmac0",               502,   R8A77995_CLK_S3D1),
+        DEF_MOD("hscif3",                517,   R8A77995_CLK_S3D1C),
+        DEF_MOD("hscif0",                520,   R8A77995_CLK_S3D1C),
+        DEF_MOD("thermal",               522,   R8A77995_CLK_CP),
+        DEF_MOD("pwm",                   523,   R8A77995_CLK_S3D4C),
+        DEF_MOD("fcpvd1",                602,   R8A77995_CLK_S1D2),
+        DEF_MOD("fcpvd0",                603,   R8A77995_CLK_S1D2),
+        DEF_MOD("fcpvbs",                607,   R8A77995_CLK_S0D1),
+        DEF_MOD("vspd1",                 622,   R8A77995_CLK_S1D2),
+        DEF_MOD("vspd0",                 623,   R8A77995_CLK_S1D2),
+        DEF_MOD("vspbs",                 627,   R8A77995_CLK_S0D1),
+        DEF_MOD("ehci0",                 703,   R8A77995_CLK_S3D2),
+        DEF_MOD("hsusb",                 704,   R8A77995_CLK_S3D2),
+        DEF_MOD("du1",                   723,   R8A77995_CLK_S2D1),
+        DEF_MOD("du0",                   724,   R8A77995_CLK_S2D1),
+        DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
+        DEF_MOD("vin7",                  804,   R8A77995_CLK_S1D2),
+        DEF_MOD("vin6",                  805,   R8A77995_CLK_S1D2),
+        DEF_MOD("vin5",                  806,   R8A77995_CLK_S1D2),
+        DEF_MOD("vin4",                  807,   R8A77995_CLK_S1D2),
+        DEF_MOD("etheravb",              812,   R8A77995_CLK_S3D2),
+        DEF_MOD("imr0",                  823,   R8A77995_CLK_S1D2),
+        DEF_MOD("gpio6",                 906,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio5",                 907,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio4",                 908,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio3",                 909,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio2",                 910,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio1",                 911,   R8A77995_CLK_S3D4),
+        DEF_MOD("gpio0",                 912,   R8A77995_CLK_S3D4),
+        DEF_MOD("can-fd",                914,   R8A77995_CLK_S3D2),
+        DEF_MOD("can-if1",               915,   R8A77995_CLK_S3D4),
+        DEF_MOD("can-if0",               916,   R8A77995_CLK_S3D4),
+        DEF_MOD("i2c3",                  928,   R8A77995_CLK_S3D2),
+        DEF_MOD("i2c2",                  929,   R8A77995_CLK_S3D2),
+        DEF_MOD("i2c1",                  930,   R8A77995_CLK_S3D2),
+        DEF_MOD("i2c0",                  931,   R8A77995_CLK_S3D2),
+        DEF_MOD("ssi-all",              1005,   R8A77995_CLK_S3D4),
+        DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
+        DEF_MOD("scu-all",              1017,   R8A77995_CLK_S3D4),
+        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
+        MOD_CLK_ID(408),        /* INTC-AP (GIC) */
+};
+
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD19         EXTAL (MHz)     PLL0            PLL1            PLL3
+ *--------------------------------------------------------------------
+ * 0            48 x 1          x250/4          x100/3          x100/3
+ * 1            48 x 1          x250/4          x100/3          x116/6
+ */
+#define CPG_PLL_CONFIG_INDEX(md)        (((md) & BIT(19)) >> 19)
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
+        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
+        { 1,            100,    3,      100,    3,      },
+        { 1,            100,    3,      116,    6,      },
+};
+
+static int __init r8a77995_cpg_mssr_init(struct device *dev)
+{
+        const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+        u32 cpg_mode;
+        int error;
+
+        error = rcar_rst_read_mode_pins(&cpg_mode);
+        if (error)
+                return error;
+
+        cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+        return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = {
+        /* Core Clocks */
+        .core_clks = r8a77995_core_clks,
+        .num_core_clks = ARRAY_SIZE(r8a77995_core_clks),
+        .last_dt_core_clk = LAST_DT_CORE_CLK,
+        .num_total_core_clks = MOD_CLK_BASE,
+
+        /* Module Clocks */
+        .mod_clks = r8a77995_mod_clks,
+        .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks),
+        .num_hw_mod_clks = 12 * 32,
+
+        /* Critical Module Clocks */
+        .crit_mod_clks = r8a77995_crit_mod_clks,
+        .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks),
+
+        /* Callbacks */
+        .init = r8a77995_cpg_mssr_init,
+        .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 3dee900522b7..951105816547 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -60,6 +60,7 @@ struct sd_clock {
         unsigned int div_num;
         unsigned int div_min;
         unsigned int div_max;
+        unsigned int cur_div_idx;
 };
 
 /* SDn divider
@@ -96,21 +97,10 @@ static const struct sd_div_table cpg_sd_div_table[] = {
 static int cpg_sd_clock_enable(struct clk_hw *hw)
 {
         struct sd_clock *clock = to_sd_clock(hw);
-        u32 val, sd_fc;
-        unsigned int i;
-
-        val = readl(clock->reg);
-
-        sd_fc = val & CPG_SD_FC_MASK;
-        for (i = 0; i < clock->div_num; i++)
-                if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
-                        break;
-
-        if (i >= clock->div_num)
-                return -EINVAL;
+        u32 val = readl(clock->reg);
 
         val &= ~(CPG_SD_STP_MASK);
-        val |= clock->div_table[i].val & CPG_SD_STP_MASK;
+        val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
 
         writel(val, clock->reg);
 
@@ -135,21 +125,9 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
                                                 unsigned long parent_rate)
 {
         struct sd_clock *clock = to_sd_clock(hw);
-        unsigned long rate = parent_rate;
-        u32 val, sd_fc;
-        unsigned int i;
 
-        val = readl(clock->reg);
-
-        sd_fc = val & CPG_SD_FC_MASK;
-        for (i = 0; i < clock->div_num; i++)
-                if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
-                        break;
-
-        if (i >= clock->div_num)
-                return -EINVAL;
-
-        return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
+        return DIV_ROUND_CLOSEST(parent_rate,
+                                 clock->div_table[clock->cur_div_idx].div);
 }
 
 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
@@ -190,6 +168,8 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
         if (i >= clock->div_num)
                 return -EINVAL;
 
+        clock->cur_div_idx = i;
+
         val = readl(clock->reg);
         val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
         val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
@@ -215,6 +195,7 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
         struct sd_clock *clock;
         struct clk *clk;
         unsigned int i;
+        u32 sd_fc;
 
         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
         if (!clock)
@@ -231,6 +212,18 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
         clock->div_table = cpg_sd_div_table;
         clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
 
+        sd_fc = readl(clock->reg) & CPG_SD_FC_MASK;
+        for (i = 0; i < clock->div_num; i++)
+                if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
+                        break;
+
+        if (WARN_ON(i >= clock->div_num)) {
+                kfree(clock);
+                return ERR_PTR(-EINVAL);
+        }
+
+        clock->cur_div_idx = i;
+
         clock->div_max = clock->div_table[0].div;
         clock->div_min = clock->div_max;
         for (i = 1; i < clock->div_num; i++) {
@@ -279,7 +272,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
         unsigned int div = 1;
         u32 value;
 
-        parent = clks[core->parent];
+        parent = clks[core->parent & 0xffff];   /* CLK_TYPE_PE uses high bits */
         if (IS_ERR(parent))
                 return ERR_CAST(parent);
 
@@ -303,6 +296,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 
         case CLK_TYPE_GEN3_PLL1:
                 mult = cpg_pll_config->pll1_mult;
+                div = cpg_pll_config->pll1_div;
                 break;
 
         case CLK_TYPE_GEN3_PLL2:
@@ -320,6 +314,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 
         case CLK_TYPE_GEN3_PLL3:
                 mult = cpg_pll_config->pll3_mult;
+                div = cpg_pll_config->pll3_div;
                 break;
 
         case CLK_TYPE_GEN3_PLL4:
@@ -360,6 +355,24 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
                         parent = clks[cpg_clk_extalr];
                 break;
 
+        case CLK_TYPE_GEN3_PE:
+                /*
+                 * Peripheral clock with a fixed divider, selectable between
+                 * clean and spread spectrum parents using MD12
+                 */
+                if (cpg_mode & BIT(12)) {
+                        /* Clean */
+                        div = core->div & 0xffff;
+                } else {
+                        /* SCCG */
+                        parent = clks[core->parent >> 16];
+                        if (IS_ERR(parent))
+                                return ERR_CAST(parent);
+                        div = core->div >> 16;
+                }
+                mult = 1;
+                break;
+
         default:
                 return ERR_PTR(-EINVAL);
         }
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 073be54b5d03..d756ef8b78eb 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -20,15 +20,24 @@ enum rcar_gen3_clk_types {
         CLK_TYPE_GEN3_PLL4,
         CLK_TYPE_GEN3_SD,
         CLK_TYPE_GEN3_R,
+        CLK_TYPE_GEN3_PE,
 };
 
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+                    _div_clean) \
+        DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,                  \
+                 (_parent_sscg) << 16 | (_parent_clean),        \
+                 .div = (_div_sscg) << 16 | (_div_clean))
+
 struct rcar_gen3_cpg_pll_config {
-        unsigned int extal_div;
-        unsigned int pll1_mult;
-        unsigned int pll3_mult;
+        u8 extal_div;
+        u8 pll1_mult;
+        u8 pll1_div;
+        u8 pll3_mult;
+        u8 pll3_div;
 };
 
 #define CPG_RCKCR       0x240
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
new file mode 100644
index 000000000000..6cd030a58964
--- /dev/null
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -0,0 +1,188 @@
+/*
+ * Renesas R-Car USB2.0 clock selector
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * Based on renesas-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#define USB20_CLKSET0           0x00
+#define CLKSET0_INTCLK_EN       BIT(11)
+#define CLKSET0_PRIVATE         BIT(0)
+#define CLKSET0_EXTAL_ONLY      (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
+
+struct usb2_clock_sel_priv {
+        void __iomem *base;
+        struct clk_hw hw;
+        bool extal;
+        bool xtal;
+};
+#define to_priv(_hw)    container_of(_hw, struct usb2_clock_sel_priv, hw)
+
+static void usb2_clock_sel_enable_extal_only(struct usb2_clock_sel_priv *priv)
+{
+        u16 val = readw(priv->base + USB20_CLKSET0);
+
+        pr_debug("%s: enter %d %d %x\n", __func__,
+                 priv->extal, priv->xtal, val);
+
+        if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY)
+                writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0);
+}
+
+static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
+{
+        if (priv->extal && !priv->xtal)
+                writew(CLKSET0_PRIVATE, priv->base + USB20_CLKSET0);
+}
+
+static int usb2_clock_sel_enable(struct clk_hw *hw)
+{
+        usb2_clock_sel_enable_extal_only(to_priv(hw));
+
+        return 0;
+}
+
+static void usb2_clock_sel_disable(struct clk_hw *hw)
+{
+        usb2_clock_sel_disable_extal_only(to_priv(hw));
+}
+
+/*
+ * This module seems a mux, but this driver assumes a gate because
+ * ehci/ohci platform drivers don't support clk_set_parent() for now.
+ * If this driver acts as a gate, ehci/ohci-platform drivers don't need
+ * any modification.
+ */
+static const struct clk_ops usb2_clock_sel_clock_ops = {
+        .enable = usb2_clock_sel_enable,
+        .disable = usb2_clock_sel_disable,
+};
+
+static const struct of_device_id rcar_usb2_clock_sel_match[] = {
+        { .compatible = "renesas,rcar-gen3-usb2-clock-sel" },
+        { }
+};
+
+static int rcar_usb2_clock_sel_suspend(struct device *dev)
+{
+        struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
+
+        usb2_clock_sel_disable_extal_only(priv);
+        pm_runtime_put(dev);
+
+        return 0;
+}
+
+static int rcar_usb2_clock_sel_resume(struct device *dev)
+{
+        struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
+
+        pm_runtime_get_sync(dev);
+        usb2_clock_sel_enable_extal_only(priv);
+
+        return 0;
+}
+
+static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct usb2_clock_sel_priv *priv = platform_get_drvdata(pdev);
+
+        of_clk_del_provider(dev->of_node);
+        clk_hw_unregister(&priv->hw);
+        pm_runtime_put(dev);
+        pm_runtime_disable(dev);
+
+        return 0;
+}
+
+static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct usb2_clock_sel_priv *priv;
+        struct resource *res;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        priv->base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(priv->base))
+                return PTR_ERR(priv->base);
+
+        pm_runtime_enable(dev);
+        pm_runtime_get_sync(dev);
+
+        clk = devm_clk_get(dev, "usb_extal");
+        if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
+                priv->extal = !!clk_get_rate(clk);
+                clk_disable_unprepare(clk);
+        }
+        clk = devm_clk_get(dev, "usb_xtal");
+        if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
+                priv->xtal = !!clk_get_rate(clk);
+                clk_disable_unprepare(clk);
+        }
+
+        if (!priv->extal && !priv->xtal) {
+                dev_err(dev, "This driver needs usb_extal or usb_xtal\n");
+                return -ENOENT;
+        }
+
+        platform_set_drvdata(pdev, priv);
+        dev_set_drvdata(dev, priv);
+
+        init.name = "rcar_usb2_clock_sel";
+        init.ops = &usb2_clock_sel_clock_ops;
+        init.flags = 0;
+        init.parent_names = NULL;
+        init.num_parents = 0;
+        priv->hw.init = &init;
+
+        clk = clk_register(NULL, &priv->hw);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        return of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
+}
+
+static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {
+        .suspend        = rcar_usb2_clock_sel_suspend,
+        .resume         = rcar_usb2_clock_sel_resume,
+};
+
+static struct platform_driver rcar_usb2_clock_sel_driver = {
+        .driver         = {
+                .name   = "rcar-usb2-clock-sel",
+                .of_match_table = rcar_usb2_clock_sel_match,
+                .pm     = &rcar_usb2_clock_sel_pm_ops,
+        },
+        .probe          = rcar_usb2_clock_sel_probe,
+        .remove         = rcar_usb2_clock_sel_remove,
+};
+builtin_platform_driver(rcar_usb2_clock_sel_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car USB2 clock selector Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 1f607c806f9b..e580a5e6346c 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -680,6 +680,12 @@ static const struct of_device_id cpg_mssr_match[] = {
                 .data = &r8a7796_cpg_mssr_info,
         },
 #endif
+#ifdef CONFIG_CLK_R8A77995
+        {
+                .compatible = "renesas,r8a77995-cpg-mssr",
+                .data = &r8a77995_cpg_mssr_info,
+        },
+#endif
         { /* sentinel */ }
 };
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 43d7c7f6832d..94b9071d1061 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -138,6 +138,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
 
 
     /*
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index e243f2eae68f..62d7854e4b87 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -201,7 +201,7 @@ static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
                         RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
 
-static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
+static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         /*
          * Clock-Architecture Diagram 1
          */
@@ -459,10 +459,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
                         RK2928_CLKGATE_CON(10), 15, GFLAGS),
 
-        COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
-                        RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
-                        RK2928_CLKGATE_CON(3), 15, GFLAGS),
-
         COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
                         RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
                         RK2928_CLKGATE_CON(1), 0, GFLAGS),
@@ -495,7 +491,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
         GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
         GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
-        GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
 
         GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
         GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
@@ -541,7 +536,6 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
         GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
 
-        GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
         GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
         GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
         GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
@@ -561,6 +555,21 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
 };
 
+static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
+        GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
+        GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
+        GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
+};
+
+static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
+        COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
+                        RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RK2928_CLKGATE_CON(3), 15, GFLAGS),
+
+        GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
+        GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
+};
+
 static const char *const rk3128_critical_clocks[] __initconst = {
         "aclk_cpu",
         "hclk_cpu",
@@ -570,7 +579,7 @@ static const char *const rk3128_critical_clocks[] __initconst = {
         "pclk_peri",
 };
 
-static void __init rk3128_clk_init(struct device_node *np)
+static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
 {
         struct rockchip_clk_provider *ctx;
         void __iomem *reg_base;
@@ -578,23 +587,21 @@ static void __init rk3128_clk_init(struct device_node *np)
         reg_base = of_iomap(np, 0);
         if (!reg_base) {
                 pr_err("%s: could not map cru region\n", __func__);
-                return;
+                return ERR_PTR(-ENOMEM);
         }
 
         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
         if (IS_ERR(ctx)) {
                 pr_err("%s: rockchip clk init failed\n", __func__);
                 iounmap(reg_base);
-                return;
+                return ERR_PTR(-ENOMEM);
         }
 
         rockchip_clk_register_plls(ctx, rk3128_pll_clks,
                                    ARRAY_SIZE(rk3128_pll_clks),
                                    RK3128_GRF_SOC_STATUS0);
-        rockchip_clk_register_branches(ctx, rk3128_clk_branches,
-                                  ARRAY_SIZE(rk3128_clk_branches));
-        rockchip_clk_protect_critical(rk3128_critical_clocks,
-                                      ARRAY_SIZE(rk3128_critical_clocks));
+        rockchip_clk_register_branches(ctx, common_clk_branches,
+                                  ARRAY_SIZE(common_clk_branches));
 
         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
@@ -606,6 +613,40 @@ static void __init rk3128_clk_init(struct device_node *np)
 
         rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
 
+        return ctx;
+}
+
+static void __init rk3126_clk_init(struct device_node *np)
+{
+        struct rockchip_clk_provider *ctx;
+
+        ctx = rk3128_common_clk_init(np);
+        if (IS_ERR(ctx))
+                return;
+
+        rockchip_clk_register_branches(ctx, rk3126_clk_branches,
+                                       ARRAY_SIZE(rk3126_clk_branches));
+        rockchip_clk_protect_critical(rk3128_critical_clocks,
+                                      ARRAY_SIZE(rk3128_critical_clocks));
+
+        rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
+
+static void __init rk3128_clk_init(struct device_node *np)
+{
+        struct rockchip_clk_provider *ctx;
+
+        ctx = rk3128_common_clk_init(np);
+        if (IS_ERR(ctx))
+                return;
+
+        rockchip_clk_register_branches(ctx, rk3128_clk_branches,
+                                       ARRAY_SIZE(rk3128_clk_branches));
+        rockchip_clk_protect_critical(rk3128_critical_clocks,
+                                      ARRAY_SIZE(rk3128_critical_clocks));
+
         rockchip_clk_of_add_provider(np, ctx);
 }
 
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index bb405d9044a3..11e7f2d1c054 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -391,7 +391,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
                         RK2928_CLKGATE_CON(2), 11, GFLAGS),
 
-        COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
+        COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
                         RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
                         RK2928_CLKGATE_CON(2), 13, GFLAGS),
         DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 7c05ab366348..089cb17925e5 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -93,9 +93,24 @@ static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
         }
 
 static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
-        RV1108_CPUCLK_RATE(816000000, 4),
-        RV1108_CPUCLK_RATE(600000000, 4),
-        RV1108_CPUCLK_RATE(312000000, 4),
+        RV1108_CPUCLK_RATE(1608000000, 7),
+        RV1108_CPUCLK_RATE(1512000000, 7),
+        RV1108_CPUCLK_RATE(1488000000, 5),
+        RV1108_CPUCLK_RATE(1416000000, 5),
+        RV1108_CPUCLK_RATE(1392000000, 5),
+        RV1108_CPUCLK_RATE(1296000000, 5),
+        RV1108_CPUCLK_RATE(1200000000, 5),
+        RV1108_CPUCLK_RATE(1104000000, 5),
+        RV1108_CPUCLK_RATE(1008000000, 5),
+        RV1108_CPUCLK_RATE(912000000, 5),
+        RV1108_CPUCLK_RATE(816000000, 3),
+        RV1108_CPUCLK_RATE(696000000, 3),
+        RV1108_CPUCLK_RATE(600000000, 3),
+        RV1108_CPUCLK_RATE(500000000, 3),
+        RV1108_CPUCLK_RATE(408000000, 1),
+        RV1108_CPUCLK_RATE(312000000, 1),
+        RV1108_CPUCLK_RATE(216000000, 1),
+        RV1108_CPUCLK_RATE(96000000, 1),
 };
 
 static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
@@ -105,7 +120,7 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
         .mux_core_alt = 1,
         .mux_core_main = 0,
         .mux_core_shift = 8,
-        .mux_core_mask = 0x1,
+        .mux_core_mask = 0x3,
 };
 
 PNAME(mux_pll_p)                = { "xin24m", "xin24m"};
@@ -114,30 +129,42 @@ PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
 PNAME(mux_usb480m_pre_p)        = { "usbphy", "xin24m" };
 PNAME(mux_hdmiphy_phy_p)        = { "hdmiphy", "xin24m" };
 PNAME(mux_dclk_hdmiphy_pre_p)   = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
-PNAME(mux_pll_src_4plls_p)      = { "dpll", "hdmiphy", "gpll", "usb480m" };
+PNAME(mux_pll_src_4plls_p)      = { "dpll", "gpll", "hdmiphy", "usb480m" };
 PNAME(mux_pll_src_3plls_p)      = { "apll", "gpll", "dpll" };
 PNAME(mux_pll_src_2plls_p)      = { "dpll", "gpll" };
 PNAME(mux_pll_src_apll_gpll_p)  = { "apll", "gpll" };
-PNAME(mux_aclk_peri_src_p)      = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" };
+PNAME(mux_aclk_peri_src_p)      = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
 PNAME(mux_aclk_bus_src_p)       = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
 PNAME(mux_mmc_src_p)            = { "dpll", "gpll", "xin24m", "usb480m" };
 PNAME(mux_pll_src_dpll_gpll_usb480m_p)  = { "dpll", "gpll", "usb480m" };
 PNAME(mux_uart0_p)              = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)              = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)              = { "uart2_src", "uart2_frac", "xin24m" };
-PNAME(mux_sclk_macphy_p)        = { "sclk_macphy_pre", "ext_gmac" };
+PNAME(mux_sclk_mac_p)           = { "sclk_mac_pre", "ext_gmac" };
 PNAME(mux_i2s0_pre_p)           = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_out_p)            = { "i2s0_pre", "xin12m" };
-PNAME(mux_i2s1_p)               = { "i2s1_src", "i2s1_frac", "xin12m" };
-PNAME(mux_i2s2_p)               = { "i2s2_src", "i2s2_frac", "xin12m" };
+PNAME(mux_i2s1_p)               = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
+PNAME(mux_i2s2_p)               = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
+PNAME(mux_wifi_src_p)           = { "gpll", "xin24m" };
+PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
+PNAME(mux_cifout_p)             = { "sclk_cifout_src", "xin24m" };
+PNAME(mux_sclk_cif0_src_p)      = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
+PNAME(mux_sclk_cif1_src_p)      = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
+PNAME(mux_sclk_cif2_src_p)      = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
+PNAME(mux_sclk_cif3_src_p)      = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
+PNAME(mux_dsp_src_p)            = { "dpll", "gpll", "apll", "usb480m" };
+PNAME(mux_dclk_hdmiphy_p)       = { "hdmiphy", "xin24m" };
+PNAME(mux_dclk_vop_p)           = { "dclk_hdmiphy", "dclk_vop_src" };
+PNAME(mux_hdmi_cec_src_p)               = { "dpll", "gpll", "xin24m" };
+PNAME(mux_cvbs_src_p)           = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
 
 static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
         [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
-                     RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates),
+                     RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
         [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
-                     RV1108_PLL_CON(11), 8, 31, 0, NULL),
+                     RV1108_PLL_CON(11), 8, 1, 0, NULL),
         [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
-                     RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates),
+                     RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
 };
 
 #define MFLAGS CLK_MUX_HIWORD_MASK
@@ -170,10 +197,10 @@ static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
                         RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
 
 static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
-        MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
-                        RV1108_MISC_CON, 13, 2, MFLAGS),
+        MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
+                        RV1108_MISC_CON, 13, 1, MFLAGS),
         MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
-                        RV1108_MISC_CON, 15, 2, MFLAGS),
+                        RV1108_MISC_CON, 15, 1, MFLAGS),
         /*
          * Clock-Architecture Diagram 2
          */
@@ -197,50 +224,212 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKGATE_CON(11), 1, GFLAGS),
 
         /* PD_RKVENC */
+        COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 8, GFLAGS),
+        FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
+                        RV1108_CLKGATE_CON(8), 10, GFLAGS),
+        COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 9, GFLAGS),
+        GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
+                        RV1108_CLKGATE_CON(19), 8, GFLAGS),
+        GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
+                        RV1108_CLKGATE_CON(19), 9, GFLAGS),
+        GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(19), 11, GFLAGS),
+        GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(19), 10, GFLAGS),
 
         /* PD_RKVDEC */
+        COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 2, GFLAGS),
+        FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
+                        RV1108_CLKGATE_CON(8), 10, GFLAGS),
+        COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 1, GFLAGS),
+
+        COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 0, GFLAGS),
+        COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(8), 3, GFLAGS),
+        GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
+                        RV1108_CLKGATE_CON(19), 0, GFLAGS),
+        GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
+                        RV1108_CLKGATE_CON(19), 1, GFLAGS),
+        GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
+                        RV1108_CLKGATE_CON(19), 2, GFLAGS),
+        GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
+                        RV1108_CLKGATE_CON(19), 3, GFLAGS),
+        GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(19), 4, GFLAGS),
+        GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(19), 5, GFLAGS),
+        GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(19), 6, GFLAGS),
 
         /* PD_PMU_wrapper */
         COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(8), 12, GFLAGS),
-        GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(10), 0, GFLAGS),
-        GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(10), 1, GFLAGS),
-        GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
                         RV1108_CLKGATE_CON(10), 2, GFLAGS),
-        GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(10), 3, GFLAGS),
-        GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(10), 4, GFLAGS),
-        GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
                         RV1108_CLKGATE_CON(10), 5, GFLAGS),
-        GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+        GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
                         RV1108_CLKGATE_CON(10), 6, GFLAGS),
-        COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(8), 15, GFLAGS),
-        COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(8), 14, GFLAGS),
         GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(8), 13, GFLAGS),
 
         /*
+         * Clock-Architecture Diagram 3
+         */
+        COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
+                        RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 8, GFLAGS),
+        COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
+                        RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
+                        RV1108_CLKGATE_CON(9), 11, GFLAGS),
+        COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
+                        RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
+        COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
+                        RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 12, GFLAGS),
+
+        GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 6, GFLAGS),
+        GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 14, GFLAGS),
+
+        GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(18), 10, GFLAGS),
+        GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 10, GFLAGS),
+        COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
+                        RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
+                        RV1108_CLKGATE_CON(7), 9, GFLAGS),
+        GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(17), 6, GFLAGS),
+        GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(17), 7, GFLAGS),
+        COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
+                        RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
+                        RV1108_CLKGATE_CON(7), 10, GFLAGS),
+        GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(17), 8, GFLAGS),
+        GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(17), 9, GFLAGS),
+        COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
+                        RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
+                        RV1108_CLKGATE_CON(7), 11, GFLAGS),
+        GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(17), 10, GFLAGS),
+        GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(17), 11, GFLAGS),
+        COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
+                        RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
+                        RV1108_CLKGATE_CON(7), 12, GFLAGS),
+        GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(7), 8, GFLAGS),
+
+        /* PD_DSP_wrapper */
+        COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
+                        RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 0, GFLAGS),
+        GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 0, GFLAGS),
+        GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 1, GFLAGS),
+        GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 2, GFLAGS),
+        GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 3, GFLAGS),
+        GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 13, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 1, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 2, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 3, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 4, GFLAGS),
+        GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 4, GFLAGS),
+        GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 5, GFLAGS),
+        GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 6, GFLAGS),
+        GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 7, GFLAGS),
+        GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 14, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 5, GFLAGS),
+        COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
+                        RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(9), 6, GFLAGS),
+        GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 8, GFLAGS),
+        GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 9, GFLAGS),
+        GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 10, GFLAGS),
+        GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 11, GFLAGS),
+        GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 12, GFLAGS),
+        GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(16), 15, GFLAGS),
+        GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(11), 8, GFLAGS),
+
+        /*
          * Clock-Architecture Diagram 4
          */
-        COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(6), 0, GFLAGS),
-        GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
+        GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
                         RV1108_CLKGATE_CON(17), 0, GFLAGS),
         COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
                         RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(7), 2, GFLAGS),
+        GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(17), 2, GFLAGS),
         COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
                         RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
                         RV1108_CLKGATE_CON(7), 3, GFLAGS),
+        GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(17), 3, GFLAGS),
+        COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
+                        RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(6), 1, GFLAGS),
+        GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(17), 1, GFLAGS),
 
         INVERTER(0, "pclk_vip", "ext_vip",
                         RV1108_CLKSEL_CON(31), 8, IFLAGS),
@@ -252,8 +441,63 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKGATE_CON(6), 5, GFLAGS),
         GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(6), 4, GFLAGS),
-        COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
-                        RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),
+        COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
+                        RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
+        COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
+                        RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
+        MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
+                        RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
+        MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
+                        RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
+        GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
+                        RV1108_CLKGATE_CON(18), 0, GFLAGS),
+        GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 1, GFLAGS),
+        GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
+                        RV1108_CLKGATE_CON(18), 2, GFLAGS),
+        GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 3, GFLAGS),
+
+        GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(18), 4, GFLAGS),
+        GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 5, GFLAGS),
+        COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(6), 6, GFLAGS),
+
+        COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
+                        RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(6), 7, GFLAGS),
+        FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
+
+        GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
+                        RV1108_CLKGATE_CON(6), 8, GFLAGS),
+
+        COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
+                        RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
+                        RV1108_CLKGATE_CON(6), 9, GFLAGS),
+        GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 8, GFLAGS),
+        GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 9, GFLAGS),
+
+        GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
+                        RV1108_CLKGATE_CON(18), 12, GFLAGS),
+        GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
+                        RV1108_CLKGATE_CON(18), 11, GFLAGS),
+        COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
+                        RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(6), 3, GFLAGS),
+
+        GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(9), 10, GFLAGS),
+        GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 9, GFLAGS),
+        GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 11, GFLAGS),
+        GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 12, GFLAGS),
 
         /*
          * Clock-Architecture Diagram 5
@@ -261,10 +505,11 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
 
         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 
-        COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
+
+        COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(2), 0, GFLAGS),
-        COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
+        COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
                         RV1108_CLKSEL_CON(8), 0,
                         RV1108_CLKGATE_CON(2), 1, GFLAGS,
                         &rv1108_i2s0_fracmux),
@@ -274,7 +519,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
                         RV1108_CLKGATE_CON(2), 3, GFLAGS),
 
-        COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
+        COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(2), 4, GFLAGS),
         COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
@@ -284,7 +529,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
         GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
                         RV1108_CLKGATE_CON(2), 6, GFLAGS),
 
-        COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
+        COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 8, GFLAGS),
         COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
@@ -303,32 +548,53 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKGATE_CON(1), 2, GFLAGS),
         COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
                         RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
-        COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0,
+        COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
                         RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(1), 4, GFLAGS),
-        COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0,
+        COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
                         RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
                         RV1108_CLKGATE_CON(1), 5, GFLAGS),
-        GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+        GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(1), 6, GFLAGS),
-        GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(1), 7, GFLAGS),
-        GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(1), 8, GFLAGS),
-        GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED,
+        GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
                         RV1108_CLKGATE_CON(1), 9, GFLAGS),
-        GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED,
+        GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(1), 10, GFLAGS),
-        GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(13), 4, GFLAGS),
 
-        COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+        GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 7, GFLAGS),
+        GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 8, GFLAGS),
+        GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 9, GFLAGS),
+
+        GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 10, GFLAGS),
+        GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 11, GFLAGS),
+        COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
+                        RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(2), 12, GFLAGS),
+
+        COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
+                        RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKGATE_CON(3), 0, GFLAGS),
+        GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(13), 5, GFLAGS),
+
+        COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 1, GFLAGS),
-        COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 3, GFLAGS),
-        COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 5, GFLAGS),
 
@@ -344,44 +610,58 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKSEL_CON(18), 0,
                         RV1108_CLKGATE_CON(3), 6, GFLAGS,
                         &rv1108_uart2_fracmux),
-        GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 10, GFLAGS),
-        GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 11, GFLAGS),
-        GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 12, GFLAGS),
 
-        COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
-                        RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS,
+        COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
+                        RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 7, GFLAGS),
-        COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
-                        RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS,
+        COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
+                        RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 8, GFLAGS),
-        COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
-                        RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS,
+        COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
+                        RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 9, GFLAGS),
-        GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 0, GFLAGS),
-        GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 1, GFLAGS),
-        GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 2, GFLAGS),
-        COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+        COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
                         RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
                         RV1108_CLKGATE_CON(3), 10, GFLAGS),
-        GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 6, GFLAGS),
-        GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 3, GFLAGS),
-        GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 7, GFLAGS),
-        GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 8, GFLAGS),
-        GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
                         RV1108_CLKGATE_CON(13), 9, GFLAGS),
 
         GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(14), 0, GFLAGS),
+        GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 12, GFLAGS),
+        GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(12), 13, GFLAGS),
+        GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(13), 13, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
+                        RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
+                        RV1108_CLKGATE_CON(3), 11, GFLAGS),
+        GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
+                        RV1108_CLKGATE_CON(13), 14, GFLAGS),
+        COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
+                        RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
+                        RV1108_CLKGATE_CON(3), 12, GFLAGS),
 
         GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
              RV1108_CLKGATE_CON(12), 2, GFLAGS),
@@ -397,18 +677,24 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
                         RV1108_CLKGATE_CON(0), 9, GFLAGS),
         GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(0), 10, GFLAGS),
-        COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+        COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                         RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
-                        DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+                        DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
+        FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
+        GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(10), 9, GFLAGS),
-        GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(12), 4, GFLAGS),
-        GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED,
+        GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(12), 5, GFLAGS),
-        GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED,
+        GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(12), 6, GFLAGS),
         GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(0), 11, GFLAGS),
+        GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 2, GFLAGS),
+        GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
+                        RV1108_CLKGATE_CON(14), 4, GFLAGS),
 
         /*
          * Clock-Architecture Diagram 6
@@ -418,23 +704,23 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
         COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
                         RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
                         RV1108_CLKGATE_CON(4), 5, GFLAGS),
-        GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
+        GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(15), 13, GFLAGS),
         COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
                         RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
                         RV1108_CLKGATE_CON(4), 4, GFLAGS),
-        GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
+        GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(15), 12, GFLAGS),
 
         GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(4), 1, GFLAGS),
         GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
                         RV1108_CLKGATE_CON(4), 2, GFLAGS),
-        COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED,
-                        RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS,
+        COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
+                        RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(15), 11, GFLAGS),
 
-        COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
+        COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
                         RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
                         RV1108_CLKGATE_CON(5), 0, GFLAGS),
 
@@ -454,23 +740,31 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
         GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
 
         COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
-                        RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS,
+                        RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
                         RV1108_CLKGATE_CON(5), 3, GFLAGS),
         GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
 
+        GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
+        GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
+        GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
+        GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
+        GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
+
         COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
-                        RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS,
+                        RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
                         RV1108_CLKGATE_CON(5), 4, GFLAGS),
         GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
 
-        COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,
-                        RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS,
+        COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
+                        RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
                         RV1108_CLKGATE_CON(4), 10, GFLAGS),
-        MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,
-                        RV1108_CLKSEL_CON(24), 8, 2, MFLAGS),
-        GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
-        GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
-        GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
+        MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
+                        RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
+        GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
+        GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
+        GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
+        GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
+        GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
 
         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
@@ -484,10 +778,16 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
 
 static const char *const rv1108_critical_clocks[] __initconst = {
         "aclk_core",
-        "aclk_bus_src_gpll",
+        "aclk_bus",
+        "hclk_bus",
+        "pclk_bus",
         "aclk_periph",
         "hclk_periph",
         "pclk_periph",
+        "nclk_ddrupctl",
+        "pclk_ddrmon",
+        "pclk_acodecphy",
+        "pclk_pmu",
 };
 
 static void __init rv1108_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fe1d393cf678..35dbd63c2f49 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -29,6 +29,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/reboot.h>
+#include <linux/rational.h>
 #include "clk.h"
 
 /**
@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
         return notifier_from_errno(ret);
 }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+static void rockchip_fractional_approximation(struct clk_hw *hw,
+                unsigned long rate, unsigned long *parent_rate,
+                unsigned long *m, unsigned long *n)
+{
+        struct clk_fractional_divider *fd = to_clk_fd(hw);
+        unsigned long p_rate, p_parent_rate;
+        struct clk_hw *p_parent;
+        unsigned long scale;
+
+        p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+        if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+                p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+                p_parent_rate = clk_hw_get_rate(p_parent);
+                *parent_rate = p_parent_rate;
+        }
+
+        /*
+         * Get rate closer to *parent_rate to guarantee there is no overflow
+         * for m and n. In the result it will be the nearest rate left shifted
+         * by (scale - fd->nwidth) bits.
+         */
+        scale = fls_long(*parent_rate / rate - 1);
+        if (scale > fd->nwidth)
+                rate <<= scale - fd->nwidth;
+
+        rational_best_approximation(rate, *parent_rate,
+                        GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
+                        m, n);
+}
+
 static struct clk *rockchip_clk_register_frac_branch(
                 struct rockchip_clk_provider *ctx, const char *name,
                 const char *const *parent_names, u8 num_parents,
@@ -210,6 +245,7 @@ static struct clk *rockchip_clk_register_frac_branch(
         div->nwidth = 16;
         div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
         div->lock = lock;
+        div->approximation = rockchip_fractional_approximation;
         div_ops = &clk_fractional_divider_ops;
 
         clk = clk_register_composite(NULL, name, parent_names, num_parents,
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 1fab56f396d4..b117783ed404 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -180,7 +180,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
         }
         clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
-                                CLK_SET_RATE_NO_REPARENT,
+                                CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
                                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 
         cdclk = devm_clk_get(&pdev->dev, "cdclk");
@@ -195,11 +195,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
                                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
 
         clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
-                                "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
-                                0, &lock);
+                                "mout_audss", CLK_SET_RATE_PARENT,
+                                reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
 
         clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
-                                "dout_aud_bus", "dout_srp", 0,
+                                "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
                                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
 
         clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9a6476aa7d81..25601967d1cd 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -537,8 +537,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 
         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
                         mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
-        MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
-                                                        SRC_TOP7, 20, 2),
+        MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
+                        SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
         MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 
@@ -547,8 +547,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
 
-        MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
-                                                        SRC_TOP9, 8, 1),
+        MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
+                        SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
                                                         SRC_TOP9, 16, 1),
         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -590,6 +590,8 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
                                 GATE_BUS_TOP, 24, 0, 0),
         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
                                 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
+        GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
+                        SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 };
 
 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
@@ -629,6 +631,11 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
                         "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
 };
 
+static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
+        GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
+                        SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
+};
+
 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
                         SRC_TOP7, 4, 1),
@@ -706,7 +713,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
-        MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
+        MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
+                        CLK_SET_RATE_PARENT, 0),
         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
@@ -1001,9 +1009,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
                         SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
 
-        GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
-                        SRC_MASK_TOP7, 20, 0, 0),
-
         /* sclk */
         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
@@ -1440,6 +1445,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
                                 ARRAY_SIZE(exynos5420_mux_clks));
                 samsung_clk_register_div(ctx, exynos5420_div_clks,
                                 ARRAY_SIZE(exynos5420_div_clks));
+                samsung_clk_register_gate(ctx, exynos5420_gate_clks,
+                                ARRAY_SIZE(exynos5420_gate_clks));
         } else {
                 samsung_clk_register_fixed_factor(
                                 ctx, exynos5800_fixed_factor_clks,
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928c35cd..6427d0ebe2de 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -11,6 +11,19 @@ config SUN50I_A64_CCU
         default ARM64 && ARCH_SUNXI
         depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUN4I_A10_CCU
+        bool "Support for the Allwinner A10/A20 CCU"
+        select SUNXI_CCU_DIV
+        select SUNXI_CCU_MULT
+        select SUNXI_CCU_NK
+        select SUNXI_CCU_NKM
+        select SUNXI_CCU_NM
+        select SUNXI_CCU_MP
+        select SUNXI_CCU_PHASE
+        default MACH_SUN4I
+        default MACH_SUN7I
+        depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
+
 config SUN5I_CCU
         bool "Support for the Allwinner sun5i family CCM"
         default MACH_SUN5I
@@ -48,6 +61,11 @@ config SUN8I_V3S_CCU
 config SUN8I_DE2_CCU
         bool "Support for the Allwinner SoCs DE2 CCU"
 
+config SUN8I_R40_CCU
+        bool "Support for the Allwinner R40 CCU"
+        default MACH_SUN8I
+        depends on MACH_SUN8I || COMPILE_TEST
+
 config SUN9I_A80_CCU
         bool "Support for the Allwinner A80 CCU"
         default MACH_SUN9I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 45a5910379a5..85a0633c1eac 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -20,6 +20,7 @@ lib-$(CONFIG_SUNXI_CCU)		+= ccu_mp.o
 
 # SoC support
 obj-$(CONFIG_SUN50I_A64_CCU)    += ccu-sun50i-a64.o
+obj-$(CONFIG_SUN4I_A10_CCU)     += ccu-sun4i-a10.o
 obj-$(CONFIG_SUN5I_CCU)         += ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)     += ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_A23_CCU)     += ccu-sun8i-a23.o
@@ -29,6 +30,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)     += ccu-sun8i-v3s.o
 obj-$(CONFIG_SUN8I_DE2_CCU)     += ccu-sun8i-de2.o
 obj-$(CONFIG_SUN8I_R_CCU)       += ccu-sun8i-r.o
+obj-$(CONFIG_SUN8I_R40_CCU)     += ccu-sun8i-r40.o
 obj-$(CONFIG_SUN9I_A80_CCU)     += ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)     += ccu-sun9i-a80-de.o
 obj-$(CONFIG_SUN9I_A80_CCU)     += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
new file mode 100644
index 000000000000..286b0049b7b6
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -0,0 +1,1456 @@
+/*
+ * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
+ * Copyright (c) 2017 Maxime Ripard.
+ * Copyright (c) 2017 Jonathan Liu.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun4i-a10.h"
+
+static struct ccu_nkmp pll_core_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .m              = _SUNXI_CCU_DIV(0, 2),
+        .p              = _SUNXI_CCU_DIV(16, 2),
+        .common         = {
+                .reg            = 0x000,
+                .hw.init        = CLK_HW_INIT("pll-core",
+                                              "hosc",
+                                              &ccu_nkmp_ops,
+                                              0),
+        },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names.
+ */
+#define SUN4I_PLL_AUDIO_REG     0x008
+static struct ccu_nm pll_audio_base_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
+        .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+        .common         = {
+                .reg            = 0x008,
+                .hw.init        = CLK_HW_INIT("pll-audio-base",
+                                              "hosc",
+                                              &ccu_nm_ops,
+                                              0),
+        },
+
+};
+
+static struct ccu_mult pll_video0_clk = {
+        .enable         = BIT(31),
+        .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+        .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
+                                          270000000, 297000000),
+        .common         = {
+                .reg            = 0x010,
+                .features       = (CCU_FEATURE_FRACTIONAL |
+                                   CCU_FEATURE_ALL_PREDIV),
+                .prediv         = 8,
+                .hw.init        = CLK_HW_INIT("pll-video0",
+                                              "hosc",
+                                              &ccu_mult_ops,
+                                              0),
+        },
+};
+
+static struct ccu_nkmp pll_ve_sun4i_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .m              = _SUNXI_CCU_DIV(0, 2),
+        .p              = _SUNXI_CCU_DIV(16, 2),
+        .common         = {
+                .reg            = 0x018,
+                .hw.init        = CLK_HW_INIT("pll-ve",
+                                              "hosc",
+                                              &ccu_nkmp_ops,
+                                              0),
+        },
+};
+
+static struct ccu_nk pll_ve_sun7i_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .common         = {
+                .reg            = 0x018,
+                .hw.init        = CLK_HW_INIT("pll-ve",
+                                              "hosc",
+                                              &ccu_nk_ops,
+                                              0),
+        },
+};
+
+static struct ccu_nk pll_ddr_base_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .common         = {
+                .reg            = 0x020,
+                .hw.init        = CLK_HW_INIT("pll-ddr-base",
+                                              "hosc",
+                                              &ccu_nk_ops,
+                                              0),
+        },
+};
+
+static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
+                   CLK_IS_CRITICAL);
+
+static struct ccu_div pll_ddr_other_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
+        .common         = {
+                .reg            = 0x020,
+                .hw.init        = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
+                                              &ccu_div_ops,
+                                              0),
+        },
+};
+
+static struct ccu_nk pll_periph_base_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .common         = {
+                .reg            = 0x028,
+                .hw.init        = CLK_HW_INIT("pll-periph-base",
+                                              "hosc",
+                                              &ccu_nk_ops,
+                                              0),
+        },
+};
+
+static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
+                        2, 1, CLK_SET_RATE_PARENT);
+
+/* Not documented on A10 */
+static struct ccu_div pll_periph_sata_clk = {
+        .enable         = BIT(14),
+        .div            = _SUNXI_CCU_DIV(0, 2),
+        .fixed_post_div = 6,
+        .common         = {
+                .reg            = 0x028,
+                .features       = CCU_FEATURE_FIXED_POSTDIV,
+                .hw.init        = CLK_HW_INIT("pll-periph-sata",
+                                              "pll-periph-base",
+                                              &ccu_div_ops, 0),
+        },
+};
+
+static struct ccu_mult pll_video1_clk = {
+        .enable         = BIT(31),
+        .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+        .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
+                                  270000000, 297000000),
+        .common         = {
+                .reg            = 0x030,
+                .features       = (CCU_FEATURE_FRACTIONAL |
+                                   CCU_FEATURE_ALL_PREDIV),
+                .prediv         = 8,
+                .hw.init        = CLK_HW_INIT("pll-video1",
+                                              "hosc",
+                                              &ccu_mult_ops,
+                                              0),
+        },
+};
+
+/* Not present on A10 */
+static struct ccu_nk pll_gpu_clk = {
+        .enable         = BIT(31),
+        .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .common         = {
+                .reg            = 0x040,
+                .hw.init        = CLK_HW_INIT("pll-gpu",
+                                              "hosc",
+                                              &ccu_nk_ops,
+                                              0),
+        },
+};
+
+static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
+
+static const char *const cpu_parents[] = { "osc32k", "hosc",
+                                           "pll-core", "pll-periph" };
+static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
+        { .index = 3, .div = 3, },
+};
+
+#define SUN4I_AHB_REG           0x054
+static struct ccu_mux cpu_clk = {
+        .mux            = {
+                .shift          = 16,
+                .width          = 2,
+                .fixed_predivs  = cpu_predivs,
+                .n_predivs      = ARRAY_SIZE(cpu_predivs),
+        },
+        .common         = {
+                .reg            = 0x054,
+                .features       = CCU_FEATURE_FIXED_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("cpu",
+                                                      cpu_parents,
+                                                      &ccu_mux_ops,
+                                                      CLK_IS_CRITICAL),
+        }
+};
+
+static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
+
+static struct ccu_div ahb_sun4i_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+        .common         = {
+                .reg            = 0x054,
+                .hw.init        = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
+        },
+};
+
+static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
+                                                 "pll-periph" };
+static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
+        { .index = 1, .div = 2, },
+        { /* Sentinel */ },
+};
+static struct ccu_div ahb_sun7i_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+        .mux            = {
+                .shift          = 6,
+                .width          = 2,
+                .fixed_predivs  = ahb_sun7i_predivs,
+                .n_predivs      = ARRAY_SIZE(ahb_sun7i_predivs),
+        },
+
+        .common         = {
+                .reg            = 0x054,
+                .hw.init        = CLK_HW_INIT_PARENTS("ahb",
+                                                      ahb_sun7i_parents,
+                                                      &ccu_div_ops,
+                                                      0),
+        },
+};
+
+static struct clk_div_table apb0_div_table[] = {
+        { .val = 0, .div = 2 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 4 },
+        { .val = 3, .div = 8 },
+        { /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
+                           0x054, 8, 2, apb0_div_table, 0);
+
+static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
+static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
+                             0, 5,      /* M */
+                             16, 2,     /* P */
+                             24, 2,     /* mux */
+                             0);
+
+/* Not present on A20 */
+static SUNXI_CCU_GATE(axi_dram_clk,     "axi-dram",     "ahb",
+                      0x05c, BIT(31), 0);
+
+static SUNXI_CCU_GATE(ahb_otg_clk,      "ahb-otg",      "ahb",
+                      0x060, BIT(0), 0);
+static SUNXI_CCU_GATE(ahb_ehci0_clk,    "ahb-ehci0",    "ahb",
+                      0x060, BIT(1), 0);
+static SUNXI_CCU_GATE(ahb_ohci0_clk,    "ahb-ohci0",    "ahb",
+                      0x060, BIT(2), 0);
+static SUNXI_CCU_GATE(ahb_ehci1_clk,    "ahb-ehci1",    "ahb",
+                      0x060, BIT(3), 0);
+static SUNXI_CCU_GATE(ahb_ohci1_clk,    "ahb-ohci1",    "ahb",
+                      0x060, BIT(4), 0);
+static SUNXI_CCU_GATE(ahb_ss_clk,       "ahb-ss",       "ahb",
+                      0x060, BIT(5), 0);
+static SUNXI_CCU_GATE(ahb_dma_clk,      "ahb-dma",      "ahb",
+                      0x060, BIT(6), 0);
+static SUNXI_CCU_GATE(ahb_bist_clk,     "ahb-bist",     "ahb",
+                      0x060, BIT(7), 0);
+static SUNXI_CCU_GATE(ahb_mmc0_clk,     "ahb-mmc0",     "ahb",
+                      0x060, BIT(8), 0);
+static SUNXI_CCU_GATE(ahb_mmc1_clk,     "ahb-mmc1",     "ahb",
+                      0x060, BIT(9), 0);
+static SUNXI_CCU_GATE(ahb_mmc2_clk,     "ahb-mmc2",     "ahb",
+                      0x060, BIT(10), 0);
+static SUNXI_CCU_GATE(ahb_mmc3_clk,     "ahb-mmc3",     "ahb",
+                      0x060, BIT(11), 0);
+static SUNXI_CCU_GATE(ahb_ms_clk,       "ahb-ms",       "ahb",
+                      0x060, BIT(12), 0);
+static SUNXI_CCU_GATE(ahb_nand_clk,     "ahb-nand",     "ahb",
+                      0x060, BIT(13), 0);
+static SUNXI_CCU_GATE(ahb_sdram_clk,    "ahb-sdram",    "ahb",
+                      0x060, BIT(14), CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE(ahb_ace_clk,      "ahb-ace",      "ahb",
+                      0x060, BIT(16), 0);
+static SUNXI_CCU_GATE(ahb_emac_clk,     "ahb-emac",     "ahb",
+                      0x060, BIT(17), 0);
+static SUNXI_CCU_GATE(ahb_ts_clk,       "ahb-ts",       "ahb",
+                      0x060, BIT(18), 0);
+static SUNXI_CCU_GATE(ahb_spi0_clk,     "ahb-spi0",     "ahb",
+                      0x060, BIT(20), 0);
+static SUNXI_CCU_GATE(ahb_spi1_clk,     "ahb-spi1",     "ahb",
+                      0x060, BIT(21), 0);
+static SUNXI_CCU_GATE(ahb_spi2_clk,     "ahb-spi2",     "ahb",
+                      0x060, BIT(22), 0);
+static SUNXI_CCU_GATE(ahb_spi3_clk,     "ahb-spi3",     "ahb",
+                      0x060, BIT(23), 0);
+static SUNXI_CCU_GATE(ahb_pata_clk,     "ahb-pata",     "ahb",
+                      0x060, BIT(24), 0);
+/* Not documented on A20 */
+static SUNXI_CCU_GATE(ahb_sata_clk,     "ahb-sata",     "ahb",
+                      0x060, BIT(25), 0);
+/* Not present on A20 */
+static SUNXI_CCU_GATE(ahb_gps_clk,      "ahb-gps",      "ahb",
+                      0x060, BIT(26), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(ahb_hstimer_clk,  "ahb-hstimer",  "ahb",
+                      0x060, BIT(28), 0);
+
+static SUNXI_CCU_GATE(ahb_ve_clk,       "ahb-ve",       "ahb",
+                      0x064, BIT(0), 0);
+static SUNXI_CCU_GATE(ahb_tvd_clk,      "ahb-tvd",      "ahb",
+                      0x064, BIT(1), 0);
+static SUNXI_CCU_GATE(ahb_tve0_clk,     "ahb-tve0",     "ahb",
+                      0x064, BIT(2), 0);
+static SUNXI_CCU_GATE(ahb_tve1_clk,     "ahb-tve1",     "ahb",
+                      0x064, BIT(3), 0);
+static SUNXI_CCU_GATE(ahb_lcd0_clk,     "ahb-lcd0",     "ahb",
+                      0x064, BIT(4), 0);
+static SUNXI_CCU_GATE(ahb_lcd1_clk,     "ahb-lcd1",     "ahb",
+                      0x064, BIT(5), 0);
+static SUNXI_CCU_GATE(ahb_csi0_clk,     "ahb-csi0",     "ahb",
+                      0x064, BIT(8), 0);
+static SUNXI_CCU_GATE(ahb_csi1_clk,     "ahb-csi1",     "ahb",
+                      0x064, BIT(9), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(ahb_hdmi1_clk,    "ahb-hdmi1",    "ahb",
+                      0x064, BIT(10), 0);
+static SUNXI_CCU_GATE(ahb_hdmi0_clk,    "ahb-hdmi0",    "ahb",
+                      0x064, BIT(11), 0);
+static SUNXI_CCU_GATE(ahb_de_be0_clk,   "ahb-de-be0",   "ahb",
+                      0x064, BIT(12), 0);
+static SUNXI_CCU_GATE(ahb_de_be1_clk,   "ahb-de-be1",   "ahb",
+                      0x064, BIT(13), 0);
+static SUNXI_CCU_GATE(ahb_de_fe0_clk,   "ahb-de-fe0",   "ahb",
+                      0x064, BIT(14), 0);
+static SUNXI_CCU_GATE(ahb_de_fe1_clk,   "ahb-de-fe1",   "ahb",
+                      0x064, BIT(15), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(ahb_gmac_clk,     "ahb-gmac",     "ahb",
+                      0x064, BIT(17), 0);
+static SUNXI_CCU_GATE(ahb_mp_clk,       "ahb-mp",       "ahb",
+                      0x064, BIT(18), 0);
+static SUNXI_CCU_GATE(ahb_gpu_clk,      "ahb-gpu",      "ahb",
+                      0x064, BIT(20), 0);
+
+static SUNXI_CCU_GATE(apb0_codec_clk,   "apb0-codec",   "apb0",
+                      0x068, BIT(0), 0);
+static SUNXI_CCU_GATE(apb0_spdif_clk,   "apb0-spdif",   "apb0",
+                      0x068, BIT(1), 0);
+static SUNXI_CCU_GATE(apb0_ac97_clk,    "apb0-ac97",    "apb0",
+                      0x068, BIT(2), 0);
+static SUNXI_CCU_GATE(apb0_i2s0_clk,    "apb0-i2s0",    "apb0",
+                      0x068, BIT(3), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(apb0_i2s1_clk,    "apb0-i2s1",    "apb0",
+                      0x068, BIT(4), 0);
+static SUNXI_CCU_GATE(apb0_pio_clk,     "apb0-pio",     "apb0",
+                      0x068, BIT(5), 0);
+static SUNXI_CCU_GATE(apb0_ir0_clk,     "apb0-ir0",     "apb0",
+                      0x068, BIT(6), 0);
+static SUNXI_CCU_GATE(apb0_ir1_clk,     "apb0-ir1",     "apb0",
+                      0x068, BIT(7), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(apb0_i2s2_clk,    "apb0-i2s2",    "apb0",
+                      0x068, BIT(8), 0);
+static SUNXI_CCU_GATE(apb0_keypad_clk,  "apb0-keypad",  "apb0",
+                      0x068, BIT(10), 0);
+
+static SUNXI_CCU_GATE(apb1_i2c0_clk,    "apb1-i2c0",    "apb1",
+                      0x06c, BIT(0), 0);
+static SUNXI_CCU_GATE(apb1_i2c1_clk,    "apb1-i2c1",    "apb1",
+                      0x06c, BIT(1), 0);
+static SUNXI_CCU_GATE(apb1_i2c2_clk,    "apb1-i2c2",    "apb1",
+                      0x06c, BIT(2), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(apb1_i2c3_clk,    "apb1-i2c3",    "apb1",
+                      0x06c, BIT(3), 0);
+static SUNXI_CCU_GATE(apb1_can_clk,     "apb1-can",     "apb1",
+                      0x06c, BIT(4), 0);
+static SUNXI_CCU_GATE(apb1_scr_clk,     "apb1-scr",     "apb1",
+                      0x06c, BIT(5), 0);
+static SUNXI_CCU_GATE(apb1_ps20_clk,    "apb1-ps20",    "apb1",
+                      0x06c, BIT(6), 0);
+static SUNXI_CCU_GATE(apb1_ps21_clk,    "apb1-ps21",    "apb1",
+                      0x06c, BIT(7), 0);
+/* Not present on A10 */
+static SUNXI_CCU_GATE(apb1_i2c4_clk,    "apb1-i2c4",    "apb1",
+                      0x06c, BIT(15), 0);
+static SUNXI_CCU_GATE(apb1_uart0_clk,   "apb1-uart0",   "apb1",
+                      0x06c, BIT(16), 0);
+static SUNXI_CCU_GATE(apb1_uart1_clk,   "apb1-uart1",   "apb1",
+                      0x06c, BIT(17), 0);
+static SUNXI_CCU_GATE(apb1_uart2_clk,   "apb1-uart2",   "apb1",
+                      0x06c, BIT(18), 0);
+static SUNXI_CCU_GATE(apb1_uart3_clk,   "apb1-uart3",   "apb1",
+                      0x06c, BIT(19), 0);
+static SUNXI_CCU_GATE(apb1_uart4_clk,   "apb1-uart4",   "apb1",
+                      0x06c, BIT(20), 0);
+static SUNXI_CCU_GATE(apb1_uart5_clk,   "apb1-uart5",   "apb1",
+                      0x06c, BIT(21), 0);
+static SUNXI_CCU_GATE(apb1_uart6_clk,   "apb1-uart6",   "apb1",
+                      0x06c, BIT(22), 0);
+static SUNXI_CCU_GATE(apb1_uart7_clk,   "apb1-uart7",   "apb1",
+                      0x06c, BIT(23), 0);
+
+static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
+                                                     "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* Undocumented on A10 */
+static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* MMC output and sample clocks are not present on A10 */
+static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
+                       0x088, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
+                       0x088, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* MMC output and sample clocks are not present on A10 */
+static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
+                       0x08c, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
+                       0x08c, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* MMC output and sample clocks are not present on A10 */
+static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
+                       0x090, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
+                       0x090, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* MMC output and sample clocks are not present on A10 */
+static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
+                       0x094, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
+                       0x094, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* Undocumented on A10 */
+static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* TODO: Check whether A10 actually supports osc32k as 4th parent? */
+static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
+                                                "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
+                                                "pll-ddr-other", "osc32k" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
+                                              "pll-audio-2x", "pll-audio" };
+static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
+                               0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
+                               0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+/* Undocumented on A10 */
+static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
+                               0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static const char *const keypad_parents[] = { "hosc", "losc"};
+static const u8 keypad_table[] = { 0, 2 };
+static struct ccu_mp keypad_clk = {
+        .enable         = BIT(31),
+        .m              = _SUNXI_CCU_DIV(0, 5),
+        .p              = _SUNXI_CCU_DIV(16, 2),
+        .mux            = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
+        .common         = {
+                .reg            = 0x0c4,
+                .hw.init        = CLK_HW_INIT_PARENTS("keypad",
+                                                      keypad_parents,
+                                                      &ccu_mp_ops,
+                                                      0),
+        },
+};
+
+/*
+ * SATA supports external clock as parent via BIT(24) and is probably an
+ * optional crystal or oscillator that can be connected to the
+ * SATA-CLKM / SATA-CLKP pins.
+ */
+static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
+static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
+                               0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
+
+
+static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "pll-periph",
+                      0x0cc, BIT(6), 0);
+static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "pll-periph",
+                      0x0cc, BIT(7), 0);
+static SUNXI_CCU_GATE(usb_phy_clk,      "usb-phy",      "pll-periph",
+                      0x0cc, BIT(8), 0);
+
+/* TODO: GPS CLK 0x0d0 */
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/* Not present on A10 */
+static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
+                               0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+/* Not present on A10 */
+static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
+                               0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "pll-ddr",
+                      0x100, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_csi0_clk,    "dram-csi0",    "pll-ddr",
+                      0x100, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_csi1_clk,    "dram-csi1",    "pll-ddr",
+                      0x100, BIT(2), 0);
+static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "pll-ddr",
+                      0x100, BIT(3), 0);
+static SUNXI_CCU_GATE(dram_tvd_clk,     "dram-tvd",     "pll-ddr",
+                      0x100, BIT(4), 0);
+static SUNXI_CCU_GATE(dram_tve0_clk,    "dram-tve0",    "pll-ddr",
+                      0x100, BIT(5), 0);
+static SUNXI_CCU_GATE(dram_tve1_clk,    "dram-tve1",    "pll-ddr",
+                      0x100, BIT(6), 0);
+
+/* Clock seems to be critical only on sun4i */
+static SUNXI_CCU_GATE(dram_out_clk,     "dram-out",     "pll-ddr",
+                      0x100, BIT(15), CLK_IS_CRITICAL);
+static SUNXI_CCU_GATE(dram_de_fe1_clk,  "dram-de-fe1",  "pll-ddr",
+                      0x100, BIT(24), 0);
+static SUNXI_CCU_GATE(dram_de_fe0_clk,  "dram-de-fe0",  "pll-ddr",
+                      0x100, BIT(25), 0);
+static SUNXI_CCU_GATE(dram_de_be0_clk,  "dram-de-be0",  "pll-ddr",
+                      0x100, BIT(26), 0);
+static SUNXI_CCU_GATE(dram_de_be1_clk,  "dram-de-be1",  "pll-ddr",
+                      0x100, BIT(27), 0);
+static SUNXI_CCU_GATE(dram_mp_clk,      "dram-mp",      "pll-ddr",
+                      0x100, BIT(28), 0);
+static SUNXI_CCU_GATE(dram_ace_clk,     "dram-ace",     "pll-ddr",
+                      0x100, BIT(29), 0);
+
+static const char *const de_parents[] = { "pll-video0", "pll-video1",
+                                           "pll-ddr-other" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
+                                 0x104, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
+                                 0x108, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
+                                 0x10c, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
+                                 0x110, 0, 4, 24, 2, BIT(31), 0);
+
+/* Undocumented on A10 */
+static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
+                                 0x114, 0, 4, 24, 2, BIT(31), 0);
+
+static const char *const disp_parents[] = { "pll-video0", "pll-video1",
+                                            "pll-video0-2x", "pll-video1-2x" };
+static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
+                               0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
+                               0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
+                                                "pll-ddr-other", "pll-periph" };
+
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
+                                 csi_sclk_parents,
+                                 0x120, 0, 4, 24, 2, BIT(31), 0);
+
+/* TVD clock setup for A10 */
+static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
+static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
+                               0x128, 24, 1, BIT(31), 0);
+
+/* TVD clock setup for A20 */
+static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
+                                  "tvd-sclk2", tvd_parents,
+                                  0x128,
+                                  0, 4,         /* M */
+                                  16, 4,        /* P */
+                                  8, 1,         /* mux */
+                                  BIT(15),      /* gate */
+                                  0);
+
+static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
+                             0x128, 0, 4, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
+                                 disp_parents,
+                                 0x12c, 0, 4, 24, 2, BIT(31),
+                                 CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
+                             "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
+                             0x12c, 11, 1, BIT(15),
+                             CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
+                                 disp_parents,
+                                 0x130, 0, 4, 24, 2, BIT(31),
+                                 CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
+                             "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
+                             0x130, 11, 1, BIT(15),
+                             CLK_SET_RATE_PARENT);
+
+static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
+                                           "pll-video0-2x", "pll-video1-2x"};
+static const u8 csi_table[] = { 0, 1, 2, 5, 6};
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
+                                       csi_parents, csi_table,
+                                       0x134, 0, 5, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
+                                       csi_parents, csi_table,
+                                       0x138, 0, 5, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
+
+static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
+                      0x140, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
+
+static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
+static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
+                                 0x148, 0, 4, 24, 1, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
+                                 0x150, 0, 4, 24, 2, BIT(31),
+                                 CLK_SET_RATE_PARENT);
+
+static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
+                                                 "pll-ddr-other",
+                                                 "pll-video1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
+                                 0x154, 0, 4, 24, 2, BIT(31),
+                                 CLK_SET_RATE_PARENT);
+
+static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
+                                                 "pll-ddr-other", "pll-video1",
+                                                 "pll-gpu" };
+static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
+                                       gpu_parents_sun7i, gpu_table_sun7i,
+                                       0x154, 0, 4, 24, 3, BIT(31),
+                                       CLK_SET_RATE_PARENT);
+
+static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
+                                                  "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
+                                  0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
+                                  0);
+static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
+                                                  "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
+                                  0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
+                                  CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
+
+static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
+static const u8 hdmi1_table[] = { 0, 1};
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
+                                       hdmi1_parents, hdmi1_table,
+                                       0x17c, 0, 4, 24, 2, BIT(31),
+                                       CLK_SET_RATE_PARENT);
+
+static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
+static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
+        { .index = 0, .div = 750, },
+};
+
+static struct ccu_mp out_a_clk = {
+        .enable         = BIT(31),
+        .m              = _SUNXI_CCU_DIV(8, 5),
+        .p              = _SUNXI_CCU_DIV(20, 2),
+        .mux            = {
+                .shift          = 24,
+                .width          = 2,
+                .fixed_predivs  = clk_out_predivs,
+                .n_predivs      = ARRAY_SIZE(clk_out_predivs),
+        },
+        .common         = {
+                .reg            = 0x1f0,
+                .features       = CCU_FEATURE_FIXED_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("out-a",
+                                                      out_parents,
+                                                      &ccu_mp_ops,
+                                                      0),
+        },
+};
+static struct ccu_mp out_b_clk = {
+        .enable         = BIT(31),
+        .m              = _SUNXI_CCU_DIV(8, 5),
+        .p              = _SUNXI_CCU_DIV(20, 2),
+        .mux            = {
+                .shift          = 24,
+                .width          = 2,
+                .fixed_predivs  = clk_out_predivs,
+                .n_predivs      = ARRAY_SIZE(clk_out_predivs),
+        },
+        .common         = {
+                .reg            = 0x1f4,
+                .features       = CCU_FEATURE_FIXED_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("out-b",
+                                                      out_parents,
+                                                      &ccu_mp_ops,
+                                                      0),
+        },
+};
+
+static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
+        &hosc_clk.common,
+        &pll_core_clk.common,
+        &pll_audio_base_clk.common,
+        &pll_video0_clk.common,
+        &pll_ve_sun4i_clk.common,
+        &pll_ve_sun7i_clk.common,
+        &pll_ddr_base_clk.common,
+        &pll_ddr_clk.common,
+        &pll_ddr_other_clk.common,
+        &pll_periph_base_clk.common,
+        &pll_periph_sata_clk.common,
+        &pll_video1_clk.common,
+        &pll_gpu_clk.common,
+        &cpu_clk.common,
+        &axi_clk.common,
+        &axi_dram_clk.common,
+        &ahb_sun4i_clk.common,
+        &ahb_sun7i_clk.common,
+        &apb0_clk.common,
+        &apb1_clk.common,
+        &ahb_otg_clk.common,
+        &ahb_ehci0_clk.common,
+        &ahb_ohci0_clk.common,
+        &ahb_ehci1_clk.common,
+        &ahb_ohci1_clk.common,
+        &ahb_ss_clk.common,
+        &ahb_dma_clk.common,
+        &ahb_bist_clk.common,
+        &ahb_mmc0_clk.common,
+        &ahb_mmc1_clk.common,
+        &ahb_mmc2_clk.common,
+        &ahb_mmc3_clk.common,
+        &ahb_ms_clk.common,
+        &ahb_nand_clk.common,
+        &ahb_sdram_clk.common,
+        &ahb_ace_clk.common,
+        &ahb_emac_clk.common,
+        &ahb_ts_clk.common,
+        &ahb_spi0_clk.common,
+        &ahb_spi1_clk.common,
+        &ahb_spi2_clk.common,
+        &ahb_spi3_clk.common,
+        &ahb_pata_clk.common,
+        &ahb_sata_clk.common,
+        &ahb_gps_clk.common,
+        &ahb_hstimer_clk.common,
+        &ahb_ve_clk.common,
+        &ahb_tvd_clk.common,
+        &ahb_tve0_clk.common,
+        &ahb_tve1_clk.common,
+        &ahb_lcd0_clk.common,
+        &ahb_lcd1_clk.common,
+        &ahb_csi0_clk.common,
+        &ahb_csi1_clk.common,
+        &ahb_hdmi1_clk.common,
+        &ahb_hdmi0_clk.common,
+        &ahb_de_be0_clk.common,
+        &ahb_de_be1_clk.common,
+        &ahb_de_fe0_clk.common,
+        &ahb_de_fe1_clk.common,
+        &ahb_gmac_clk.common,
+        &ahb_mp_clk.common,
+        &ahb_gpu_clk.common,
+        &apb0_codec_clk.common,
+        &apb0_spdif_clk.common,
+        &apb0_ac97_clk.common,
+        &apb0_i2s0_clk.common,
+        &apb0_i2s1_clk.common,
+        &apb0_pio_clk.common,
+        &apb0_ir0_clk.common,
+        &apb0_ir1_clk.common,
+        &apb0_i2s2_clk.common,
+        &apb0_keypad_clk.common,
+        &apb1_i2c0_clk.common,
+        &apb1_i2c1_clk.common,
+        &apb1_i2c2_clk.common,
+        &apb1_i2c3_clk.common,
+        &apb1_can_clk.common,
+        &apb1_scr_clk.common,
+        &apb1_ps20_clk.common,
+        &apb1_ps21_clk.common,
+        &apb1_i2c4_clk.common,
+        &apb1_uart0_clk.common,
+        &apb1_uart1_clk.common,
+        &apb1_uart2_clk.common,
+        &apb1_uart3_clk.common,
+        &apb1_uart4_clk.common,
+        &apb1_uart5_clk.common,
+        &apb1_uart6_clk.common,
+        &apb1_uart7_clk.common,
+        &nand_clk.common,
+        &ms_clk.common,
+        &mmc0_clk.common,
+        &mmc0_output_clk.common,
+        &mmc0_sample_clk.common,
+        &mmc1_clk.common,
+        &mmc1_output_clk.common,
+        &mmc1_sample_clk.common,
+        &mmc2_clk.common,
+        &mmc2_output_clk.common,
+        &mmc2_sample_clk.common,
+        &mmc3_clk.common,
+        &mmc3_output_clk.common,
+        &mmc3_sample_clk.common,
+        &ts_clk.common,
+        &ss_clk.common,
+        &spi0_clk.common,
+        &spi1_clk.common,
+        &spi2_clk.common,
+        &pata_clk.common,
+        &ir0_sun4i_clk.common,
+        &ir1_sun4i_clk.common,
+        &ir0_sun7i_clk.common,
+        &ir1_sun7i_clk.common,
+        &i2s0_clk.common,
+        &ac97_clk.common,
+        &spdif_clk.common,
+        &keypad_clk.common,
+        &sata_clk.common,
+        &usb_ohci0_clk.common,
+        &usb_ohci1_clk.common,
+        &usb_phy_clk.common,
+        &spi3_clk.common,
+        &i2s1_clk.common,
+        &i2s2_clk.common,
+        &dram_ve_clk.common,
+        &dram_csi0_clk.common,
+        &dram_csi1_clk.common,
+        &dram_ts_clk.common,
+        &dram_tvd_clk.common,
+        &dram_tve0_clk.common,
+        &dram_tve1_clk.common,
+        &dram_out_clk.common,
+        &dram_de_fe1_clk.common,
+        &dram_de_fe0_clk.common,
+        &dram_de_be0_clk.common,
+        &dram_de_be1_clk.common,
+        &dram_mp_clk.common,
+        &dram_ace_clk.common,
+        &de_be0_clk.common,
+        &de_be1_clk.common,
+        &de_fe0_clk.common,
+        &de_fe1_clk.common,
+        &de_mp_clk.common,
+        &tcon0_ch0_clk.common,
+        &tcon1_ch0_clk.common,
+        &csi_sclk_clk.common,
+        &tvd_sun4i_clk.common,
+        &tvd_sclk1_sun7i_clk.common,
+        &tvd_sclk2_sun7i_clk.common,
+        &tcon0_ch1_sclk2_clk.common,
+        &tcon0_ch1_clk.common,
+        &tcon1_ch1_sclk2_clk.common,
+        &tcon1_ch1_clk.common,
+        &csi0_clk.common,
+        &csi1_clk.common,
+        &ve_clk.common,
+        &codec_clk.common,
+        &avs_clk.common,
+        &ace_clk.common,
+        &hdmi_clk.common,
+        &gpu_sun4i_clk.common,
+        &gpu_sun7i_clk.common,
+        &mbus_sun4i_clk.common,
+        &mbus_sun7i_clk.common,
+        &hdmi1_slow_clk.common,
+        &hdmi1_clk.common,
+        &out_a_clk.common,
+        &out_b_clk.common
+};
+
+/* Post-divider for pll-audio is hardcoded to 4 */
+static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+                        "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
+                        "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
+                        "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
+                        "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
+                        "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
+                        "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
+
+
+static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
+        .hws    = {
+                [CLK_HOSC]              = &hosc_clk.common.hw,
+                [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
+                [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
+                [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
+                [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
+                [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
+                [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
+                [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
+                [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
+                [CLK_PLL_VE]            = &pll_ve_sun4i_clk.common.hw,
+                [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
+                [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
+                [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
+                [CLK_PLL_PERIPH_BASE]   = &pll_periph_base_clk.common.hw,
+                [CLK_PLL_PERIPH]        = &pll_periph_clk.hw,
+                [CLK_PLL_PERIPH_SATA]   = &pll_periph_sata_clk.common.hw,
+                [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
+                [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
+                [CLK_CPU]               = &cpu_clk.common.hw,
+                [CLK_AXI]               = &axi_clk.common.hw,
+                [CLK_AXI_DRAM]          = &axi_dram_clk.common.hw,
+                [CLK_AHB]               = &ahb_sun4i_clk.common.hw,
+                [CLK_APB0]              = &apb0_clk.common.hw,
+                [CLK_APB1]              = &apb1_clk.common.hw,
+                [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
+                [CLK_AHB_EHCI0]         = &ahb_ehci0_clk.common.hw,
+                [CLK_AHB_OHCI0]         = &ahb_ohci0_clk.common.hw,
+                [CLK_AHB_EHCI1]         = &ahb_ehci1_clk.common.hw,
+                [CLK_AHB_OHCI1]         = &ahb_ohci1_clk.common.hw,
+                [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
+                [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
+                [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
+                [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
+                [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
+                [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
+                [CLK_AHB_MMC3]          = &ahb_mmc3_clk.common.hw,
+                [CLK_AHB_MS]            = &ahb_ms_clk.common.hw,
+                [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
+                [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
+                [CLK_AHB_ACE]           = &ahb_ace_clk.common.hw,
+                [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
+                [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
+                [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
+                [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
+                [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
+                [CLK_AHB_SPI3]          = &ahb_spi3_clk.common.hw,
+                [CLK_AHB_PATA]          = &ahb_pata_clk.common.hw,
+                [CLK_AHB_SATA]          = &ahb_sata_clk.common.hw,
+                [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
+                [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
+                [CLK_AHB_TVD]           = &ahb_tvd_clk.common.hw,
+                [CLK_AHB_TVE0]          = &ahb_tve0_clk.common.hw,
+                [CLK_AHB_TVE1]          = &ahb_tve1_clk.common.hw,
+                [CLK_AHB_LCD0]          = &ahb_lcd0_clk.common.hw,
+                [CLK_AHB_LCD1]          = &ahb_lcd1_clk.common.hw,
+                [CLK_AHB_CSI0]          = &ahb_csi0_clk.common.hw,
+                [CLK_AHB_CSI1]          = &ahb_csi1_clk.common.hw,
+                [CLK_AHB_HDMI0]         = &ahb_hdmi0_clk.common.hw,
+                [CLK_AHB_DE_BE0]        = &ahb_de_be0_clk.common.hw,
+                [CLK_AHB_DE_BE1]        = &ahb_de_be1_clk.common.hw,
+                [CLK_AHB_DE_FE0]        = &ahb_de_fe0_clk.common.hw,
+                [CLK_AHB_DE_FE1]        = &ahb_de_fe1_clk.common.hw,
+                [CLK_AHB_MP]            = &ahb_mp_clk.common.hw,
+                [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
+                [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
+                [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
+                [CLK_APB0_AC97]         = &apb0_ac97_clk.common.hw,
+                [CLK_APB0_I2S0]         = &apb0_i2s0_clk.common.hw,
+                [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
+                [CLK_APB0_IR0]          = &apb0_ir0_clk.common.hw,
+                [CLK_APB0_IR1]          = &apb0_ir1_clk.common.hw,
+                [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
+                [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
+                [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
+                [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
+                [CLK_APB1_CAN]          = &apb1_can_clk.common.hw,
+                [CLK_APB1_SCR]          = &apb1_scr_clk.common.hw,
+                [CLK_APB1_PS20]         = &apb1_ps20_clk.common.hw,
+                [CLK_APB1_PS21]         = &apb1_ps21_clk.common.hw,
+                [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
+                [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
+                [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
+                [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
+                [CLK_APB1_UART4]        = &apb1_uart4_clk.common.hw,
+                [CLK_APB1_UART5]        = &apb1_uart5_clk.common.hw,
+                [CLK_APB1_UART6]        = &apb1_uart6_clk.common.hw,
+                [CLK_APB1_UART7]        = &apb1_uart7_clk.common.hw,
+                [CLK_NAND]              = &nand_clk.common.hw,
+                [CLK_MS]                = &ms_clk.common.hw,
+                [CLK_MMC0]              = &mmc0_clk.common.hw,
+                [CLK_MMC1]              = &mmc1_clk.common.hw,
+                [CLK_MMC2]              = &mmc2_clk.common.hw,
+                [CLK_MMC3]              = &mmc3_clk.common.hw,
+                [CLK_TS]                = &ts_clk.common.hw,
+                [CLK_SS]                = &ss_clk.common.hw,
+                [CLK_SPI0]              = &spi0_clk.common.hw,
+                [CLK_SPI1]              = &spi1_clk.common.hw,
+                [CLK_SPI2]              = &spi2_clk.common.hw,
+                [CLK_PATA]              = &pata_clk.common.hw,
+                [CLK_IR0]               = &ir0_sun4i_clk.common.hw,
+                [CLK_IR1]               = &ir1_sun4i_clk.common.hw,
+                [CLK_I2S0]              = &i2s0_clk.common.hw,
+                [CLK_AC97]              = &ac97_clk.common.hw,
+                [CLK_SPDIF]             = &spdif_clk.common.hw,
+                [CLK_KEYPAD]            = &keypad_clk.common.hw,
+                [CLK_SATA]              = &sata_clk.common.hw,
+                [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
+                [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
+                [CLK_USB_PHY]           = &usb_phy_clk.common.hw,
+                /* CLK_GPS is unimplemented */
+                [CLK_SPI3]              = &spi3_clk.common.hw,
+                [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
+                [CLK_DRAM_CSI0]         = &dram_csi0_clk.common.hw,
+                [CLK_DRAM_CSI1]         = &dram_csi1_clk.common.hw,
+                [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
+                [CLK_DRAM_TVD]          = &dram_tvd_clk.common.hw,
+                [CLK_DRAM_TVE0]         = &dram_tve0_clk.common.hw,
+                [CLK_DRAM_TVE1]         = &dram_tve1_clk.common.hw,
+                [CLK_DRAM_OUT]          = &dram_out_clk.common.hw,
+                [CLK_DRAM_DE_FE1]       = &dram_de_fe1_clk.common.hw,
+                [CLK_DRAM_DE_FE0]       = &dram_de_fe0_clk.common.hw,
+                [CLK_DRAM_DE_BE0]       = &dram_de_be0_clk.common.hw,
+                [CLK_DRAM_DE_BE1]       = &dram_de_be1_clk.common.hw,
+                [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
+                [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
+                [CLK_DE_BE0]            = &de_be0_clk.common.hw,
+                [CLK_DE_BE1]            = &de_be1_clk.common.hw,
+                [CLK_DE_FE0]            = &de_fe0_clk.common.hw,
+                [CLK_DE_FE1]            = &de_fe1_clk.common.hw,
+                [CLK_DE_MP]             = &de_mp_clk.common.hw,
+                [CLK_TCON0_CH0]         = &tcon0_ch0_clk.common.hw,
+                [CLK_TCON1_CH0]         = &tcon1_ch0_clk.common.hw,
+                [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
+                [CLK_TVD]               = &tvd_sun4i_clk.common.hw,
+                [CLK_TCON0_CH1_SCLK2]   = &tcon0_ch1_sclk2_clk.common.hw,
+                [CLK_TCON0_CH1]         = &tcon0_ch1_clk.common.hw,
+                [CLK_TCON1_CH1_SCLK2]   = &tcon1_ch1_sclk2_clk.common.hw,
+                [CLK_TCON1_CH1]         = &tcon1_ch1_clk.common.hw,
+                [CLK_CSI0]              = &csi0_clk.common.hw,
+                [CLK_CSI1]              = &csi1_clk.common.hw,
+                [CLK_VE]                = &ve_clk.common.hw,
+                [CLK_CODEC]             = &codec_clk.common.hw,
+                [CLK_AVS]               = &avs_clk.common.hw,
+                [CLK_ACE]               = &ace_clk.common.hw,
+                [CLK_HDMI]              = &hdmi_clk.common.hw,
+                [CLK_GPU]               = &gpu_sun7i_clk.common.hw,
+                [CLK_MBUS]              = &mbus_sun4i_clk.common.hw,
+        },
+        .num    = CLK_NUMBER_SUN4I,
+};
+static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
+        .hws    = {
+                [CLK_HOSC]              = &hosc_clk.common.hw,
+                [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
+                [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
+                [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
+                [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
+                [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
+                [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
+                [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
+                [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
+                [CLK_PLL_VE]            = &pll_ve_sun7i_clk.common.hw,
+                [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
+                [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
+                [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
+                [CLK_PLL_PERIPH_BASE]   = &pll_periph_base_clk.common.hw,
+                [CLK_PLL_PERIPH]        = &pll_periph_clk.hw,
+                [CLK_PLL_PERIPH_SATA]   = &pll_periph_sata_clk.common.hw,
+                [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
+                [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
+                [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
+                [CLK_CPU]               = &cpu_clk.common.hw,
+                [CLK_AXI]               = &axi_clk.common.hw,
+                [CLK_AHB]               = &ahb_sun7i_clk.common.hw,
+                [CLK_APB0]              = &apb0_clk.common.hw,
+                [CLK_APB1]              = &apb1_clk.common.hw,
+                [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
+                [CLK_AHB_EHCI0]         = &ahb_ehci0_clk.common.hw,
+                [CLK_AHB_OHCI0]         = &ahb_ohci0_clk.common.hw,
+                [CLK_AHB_EHCI1]         = &ahb_ehci1_clk.common.hw,
+                [CLK_AHB_OHCI1]         = &ahb_ohci1_clk.common.hw,
+                [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
+                [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
+                [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
+                [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
+                [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
+                [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
+                [CLK_AHB_MMC3]          = &ahb_mmc3_clk.common.hw,
+                [CLK_AHB_MS]            = &ahb_ms_clk.common.hw,
+                [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
+                [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
+                [CLK_AHB_ACE]           = &ahb_ace_clk.common.hw,
+                [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
+                [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
+                [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
+                [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
+                [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
+                [CLK_AHB_SPI3]          = &ahb_spi3_clk.common.hw,
+                [CLK_AHB_PATA]          = &ahb_pata_clk.common.hw,
+                [CLK_AHB_SATA]          = &ahb_sata_clk.common.hw,
+                [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
+                [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
+                [CLK_AHB_TVD]           = &ahb_tvd_clk.common.hw,
+                [CLK_AHB_TVE0]          = &ahb_tve0_clk.common.hw,
+                [CLK_AHB_TVE1]          = &ahb_tve1_clk.common.hw,
+                [CLK_AHB_LCD0]          = &ahb_lcd0_clk.common.hw,
+                [CLK_AHB_LCD1]          = &ahb_lcd1_clk.common.hw,
+                [CLK_AHB_CSI0]          = &ahb_csi0_clk.common.hw,
+                [CLK_AHB_CSI1]          = &ahb_csi1_clk.common.hw,
+                [CLK_AHB_HDMI1]         = &ahb_hdmi1_clk.common.hw,
+                [CLK_AHB_HDMI0]         = &ahb_hdmi0_clk.common.hw,
+                [CLK_AHB_DE_BE0]        = &ahb_de_be0_clk.common.hw,
+                [CLK_AHB_DE_BE1]        = &ahb_de_be1_clk.common.hw,
+                [CLK_AHB_DE_FE0]        = &ahb_de_fe0_clk.common.hw,
+                [CLK_AHB_DE_FE1]        = &ahb_de_fe1_clk.common.hw,
+                [CLK_AHB_GMAC]          = &ahb_gmac_clk.common.hw,
+                [CLK_AHB_MP]            = &ahb_mp_clk.common.hw,
+                [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
+                [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
+                [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
+                [CLK_APB0_AC97]         = &apb0_ac97_clk.common.hw,
+                [CLK_APB0_I2S0]         = &apb0_i2s0_clk.common.hw,
+                [CLK_APB0_I2S1]         = &apb0_i2s1_clk.common.hw,
+                [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
+                [CLK_APB0_IR0]          = &apb0_ir0_clk.common.hw,
+                [CLK_APB0_IR1]          = &apb0_ir1_clk.common.hw,
+                [CLK_APB0_I2S2]         = &apb0_i2s2_clk.common.hw,
+                [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
+                [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
+                [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
+                [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
+                [CLK_APB1_I2C3]         = &apb1_i2c3_clk.common.hw,
+                [CLK_APB1_CAN]          = &apb1_can_clk.common.hw,
+                [CLK_APB1_SCR]          = &apb1_scr_clk.common.hw,
+                [CLK_APB1_PS20]         = &apb1_ps20_clk.common.hw,
+                [CLK_APB1_PS21]         = &apb1_ps21_clk.common.hw,
+                [CLK_APB1_I2C4]         = &apb1_i2c4_clk.common.hw,
+                [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
+                [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
+                [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
+                [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
+                [CLK_APB1_UART4]        = &apb1_uart4_clk.common.hw,
+                [CLK_APB1_UART5]        = &apb1_uart5_clk.common.hw,
+                [CLK_APB1_UART6]        = &apb1_uart6_clk.common.hw,
+                [CLK_APB1_UART7]        = &apb1_uart7_clk.common.hw,
+                [CLK_NAND]              = &nand_clk.common.hw,
+                [CLK_MS]                = &ms_clk.common.hw,
+                [CLK_MMC0]              = &mmc0_clk.common.hw,
+                [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
+                [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
+                [CLK_MMC1]              = &mmc1_clk.common.hw,
+                [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
+                [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
+                [CLK_MMC2]              = &mmc2_clk.common.hw,
+                [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
+                [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
+                [CLK_MMC3]              = &mmc3_clk.common.hw,
+                [CLK_MMC3_OUTPUT]       = &mmc3_output_clk.common.hw,
+                [CLK_MMC3_SAMPLE]       = &mmc3_sample_clk.common.hw,
+                [CLK_TS]                = &ts_clk.common.hw,
+                [CLK_SS]                = &ss_clk.common.hw,
+                [CLK_SPI0]              = &spi0_clk.common.hw,
+                [CLK_SPI1]              = &spi1_clk.common.hw,
+                [CLK_SPI2]              = &spi2_clk.common.hw,
+                [CLK_PATA]              = &pata_clk.common.hw,
+                [CLK_IR0]               = &ir0_sun7i_clk.common.hw,
+                [CLK_IR1]               = &ir1_sun7i_clk.common.hw,
+                [CLK_I2S0]              = &i2s0_clk.common.hw,
+                [CLK_AC97]              = &ac97_clk.common.hw,
+                [CLK_SPDIF]             = &spdif_clk.common.hw,
+                [CLK_KEYPAD]            = &keypad_clk.common.hw,
+                [CLK_SATA]              = &sata_clk.common.hw,
+                [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
+                [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
+                [CLK_USB_PHY]           = &usb_phy_clk.common.hw,
+                /* CLK_GPS is unimplemented */
+                [CLK_SPI3]              = &spi3_clk.common.hw,
+                [CLK_I2S1]              = &i2s1_clk.common.hw,
+                [CLK_I2S2]              = &i2s2_clk.common.hw,
+                [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
+                [CLK_DRAM_CSI0]         = &dram_csi0_clk.common.hw,
+                [CLK_DRAM_CSI1]         = &dram_csi1_clk.common.hw,
+                [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
+                [CLK_DRAM_TVD]          = &dram_tvd_clk.common.hw,
+                [CLK_DRAM_TVE0]         = &dram_tve0_clk.common.hw,
+                [CLK_DRAM_TVE1]         = &dram_tve1_clk.common.hw,
+                [CLK_DRAM_OUT]          = &dram_out_clk.common.hw,
+                [CLK_DRAM_DE_FE1]       = &dram_de_fe1_clk.common.hw,
+                [CLK_DRAM_DE_FE0]       = &dram_de_fe0_clk.common.hw,
+                [CLK_DRAM_DE_BE0]       = &dram_de_be0_clk.common.hw,
+                [CLK_DRAM_DE_BE1]       = &dram_de_be1_clk.common.hw,
+                [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
+                [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
+                [CLK_DE_BE0]            = &de_be0_clk.common.hw,
+                [CLK_DE_BE1]            = &de_be1_clk.common.hw,
+                [CLK_DE_FE0]            = &de_fe0_clk.common.hw,
+                [CLK_DE_FE1]            = &de_fe1_clk.common.hw,
+                [CLK_DE_MP]             = &de_mp_clk.common.hw,
+                [CLK_TCON0_CH0]         = &tcon0_ch0_clk.common.hw,
+                [CLK_TCON1_CH0]         = &tcon1_ch0_clk.common.hw,
+                [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
+                [CLK_TVD_SCLK2]         = &tvd_sclk2_sun7i_clk.common.hw,
+                [CLK_TVD]               = &tvd_sclk1_sun7i_clk.common.hw,
+                [CLK_TCON0_CH1_SCLK2]   = &tcon0_ch1_sclk2_clk.common.hw,
+                [CLK_TCON0_CH1]         = &tcon0_ch1_clk.common.hw,
+                [CLK_TCON1_CH1_SCLK2]   = &tcon1_ch1_sclk2_clk.common.hw,
+                [CLK_TCON1_CH1]         = &tcon1_ch1_clk.common.hw,
+                [CLK_CSI0]              = &csi0_clk.common.hw,
+                [CLK_CSI1]              = &csi1_clk.common.hw,
+                [CLK_VE]                = &ve_clk.common.hw,
+                [CLK_CODEC]             = &codec_clk.common.hw,
+                [CLK_AVS]               = &avs_clk.common.hw,
+                [CLK_ACE]               = &ace_clk.common.hw,
+                [CLK_HDMI]              = &hdmi_clk.common.hw,
+                [CLK_GPU]               = &gpu_sun7i_clk.common.hw,
+                [CLK_MBUS]              = &mbus_sun7i_clk.common.hw,
+                [CLK_HDMI1_SLOW]        = &hdmi1_slow_clk.common.hw,
+                [CLK_HDMI1]             = &hdmi1_clk.common.hw,
+                [CLK_OUT_A]             = &out_a_clk.common.hw,
+                [CLK_OUT_B]             = &out_b_clk.common.hw,
+        },
+        .num    = CLK_NUMBER_SUN7I,
+};
+
+static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
+        [RST_USB_PHY0]          = { 0x0cc, BIT(0) },
+        [RST_USB_PHY1]          = { 0x0cc, BIT(1) },
+        [RST_USB_PHY2]          = { 0x0cc, BIT(2) },
+        [RST_GPS]               = { 0x0d0, BIT(0) },
+        [RST_DE_BE0]            = { 0x104, BIT(30) },
+        [RST_DE_BE1]            = { 0x108, BIT(30) },
+        [RST_DE_FE0]            = { 0x10c, BIT(30) },
+        [RST_DE_FE1]            = { 0x110, BIT(30) },
+        [RST_DE_MP]             = { 0x114, BIT(30) },
+        [RST_TVE0]              = { 0x118, BIT(29) },
+        [RST_TCON0]             = { 0x118, BIT(30) },
+        [RST_TVE1]              = { 0x11c, BIT(29) },
+        [RST_TCON1]             = { 0x11c, BIT(30) },
+        [RST_CSI0]              = { 0x134, BIT(30) },
+        [RST_CSI1]              = { 0x138, BIT(30) },
+        [RST_VE]                = { 0x13c, BIT(0) },
+        [RST_ACE]               = { 0x148, BIT(16) },
+        [RST_LVDS]              = { 0x14c, BIT(0) },
+        [RST_GPU]               = { 0x154, BIT(30) },
+        [RST_HDMI_H]            = { 0x170, BIT(0) },
+        [RST_HDMI_SYS]          = { 0x170, BIT(1) },
+        [RST_HDMI_AUDIO_DMA]    = { 0x170, BIT(2) },
+};
+
+static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
+        .ccu_clks       = sun4i_sun7i_ccu_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
+
+        .hw_clks        = &sun4i_a10_hw_clks,
+
+        .resets         = sunxi_a10_a20_ccu_resets,
+        .num_resets     = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
+};
+
+static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
+        .ccu_clks       = sun4i_sun7i_ccu_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
+
+        .hw_clks        = &sun7i_a20_hw_clks,
+
+        .resets         = sunxi_a10_a20_ccu_resets,
+        .num_resets     = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
+};
+
+static void __init sun4i_ccu_init(struct device_node *node,
+                                  const struct sunxi_ccu_desc *desc)
+{
+        void __iomem *reg;
+        u32 val;
+
+        reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+        if (IS_ERR(reg)) {
+                pr_err("%s: Could not map the clock registers\n",
+                       of_node_full_name(node));
+                return;
+        }
+
+        /* Force the PLL-Audio-1x divider to 4 */
+        val = readl(reg + SUN4I_PLL_AUDIO_REG);
+        val &= ~GENMASK(29, 26);
+        writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);
+
+        /*
+         * Use the peripheral PLL6 as the AHB parent, instead of CPU /
+         * AXI which have rate changes due to cpufreq.
+         *
+         * This is especially a big deal for the HS timer whose parent
+         * clock is AHB.
+         *
+         * NB! These bits are undocumented in A10 manual.
+         */
+        val = readl(reg + SUN4I_AHB_REG);
+        val &= ~GENMASK(7, 6);
+        writel(val | (2 << 6), reg + SUN4I_AHB_REG);
+
+        sunxi_ccu_probe(node, reg, desc);
+}
+
+static void __init sun4i_a10_ccu_setup(struct device_node *node)
+{
+        sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
+}
+CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
+               sun4i_a10_ccu_setup);
+
+static void __init sun7i_a20_ccu_setup(struct device_node *node)
+{
+        sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
+}
+CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
+               sun7i_a20_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
new file mode 100644
index 000000000000..c5947c7c050e
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 Priit Laes
+ *
+ * Priit Laes <plaes@plaes.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN4I_A10_H_
+#define _CCU_SUN4I_A10_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
+#include <dt-bindings/reset/sun4i-a10-ccu.h>
+
+/* The HOSC is exported */
+#define CLK_PLL_CORE            2
+#define CLK_PLL_AUDIO_BASE      3
+#define CLK_PLL_AUDIO           4
+#define CLK_PLL_AUDIO_2X        5
+#define CLK_PLL_AUDIO_4X        6
+#define CLK_PLL_AUDIO_8X        7
+#define CLK_PLL_VIDEO0          8
+#define CLK_PLL_VIDEO0_2X       9
+#define CLK_PLL_VE              10
+#define CLK_PLL_DDR_BASE        11
+#define CLK_PLL_DDR             12
+#define CLK_PLL_DDR_OTHER       13
+#define CLK_PLL_PERIPH_BASE     14
+#define CLK_PLL_PERIPH          15
+#define CLK_PLL_PERIPH_SATA     16
+#define CLK_PLL_VIDEO1          17
+#define CLK_PLL_VIDEO1_2X       18
+#define CLK_PLL_GPU             19
+
+/* The CPU clock is exported */
+#define CLK_AXI                 21
+#define CLK_AXI_DRAM            22
+#define CLK_AHB                 23
+#define CLK_APB0                24
+#define CLK_APB1                25
+
+/* AHB gates are exported (23..68) */
+/* APB0 gates are exported (69..78) */
+/* APB1 gates are exported (79..95) */
+/* IP module clocks are exported (96..128) */
+/* DRAM gates are exported (129..142)*/
+/* Media (display engine clocks & etc) are exported (143..169) */
+
+#define CLK_NUMBER_SUN4I        (CLK_MBUS + 1)
+#define CLK_NUMBER_SUN7I        (CLK_OUT_B + 1)
+
+#endif /* _CCU_SUN4I_A10_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 31d7ffda9aab..ab9e850b3707 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -976,8 +976,7 @@ static void __init sun5i_ccu_init(struct device_node *node,
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4d6078fca9ac..8af434815fba 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -1217,8 +1217,7 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 8a753ed0426d..d93b452f0df9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -716,8 +716,7 @@ static void __init sun8i_a23_ccu_setup(struct device_node *node)
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 10b38dc46f75..13eb5b23c5e7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -777,8 +777,7 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 62e4f0d2b2fc..1729ff6a5aae 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
                                              "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-                     0x050, 16, 2, CLK_IS_CRITICAL);
+                     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
         .num_resets     = ARRAY_SIZE(sun50i_h5_ccu_resets),
 };
 
+static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+        .common = &pll_cpux_clk.common,
+        /* copy from pll_cpux_clk */
+        .enable = BIT(31),
+        .lock   = BIT(28),
+};
+
 static struct ccu_mux_nb sun8i_h3_cpu_nb = {
         .common         = &cpux_clk.common,
         .cm             = &cpux_clk.mux,
@@ -1118,8 +1125,7 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
@@ -1130,6 +1136,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
 
         sunxi_ccu_probe(node, reg, desc);
 
+        /* Gate then ungate PLL CPU after any rate changes */
+        ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+
+        /* Reparent CPU during PLL CPU rate changes */
         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
                                   &sun8i_h3_cpu_nb);
 }
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index e54816ec1dbe..71feb7b24e8a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -290,8 +290,7 @@ static void __init sunxi_r_ccu_init(struct device_node *node,
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
index a7a407f12b56..fb01bffb929d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
@@ -13,7 +13,7 @@
  */
 
 #ifndef _CCU_SUN8I_R_H
-#define _CCU_SUN8I_R_H_
+#define _CCU_SUN8I_R_H
 
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/reset/sun8i-r-ccu.h>
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
new file mode 100644
index 000000000000..933f2e68f42a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-r40.h"
+
+/* TODO: The result of N*K is required to be in [10, 88] range. */
+static struct ccu_nkmp pll_cpu_clk = {
+        .enable         = BIT(31),
+        .lock           = BIT(28),
+        .n              = _SUNXI_CCU_MULT(8, 5),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .m              = _SUNXI_CCU_DIV(0, 2),
+        .p              = _SUNXI_CCU_DIV_MAX(16, 2, 4),
+        .common         = {
+                .reg            = 0x000,
+                .hw.init        = CLK_HW_INIT("pll-cpu",
+                                              "osc24M",
+                                              &ccu_nkmp_ops,
+                                              CLK_SET_RATE_UNGATE),
+        },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN8I_R40_PLL_AUDIO_REG 0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+                                   "osc24M", 0x008,
+                                   8, 7,        /* N */
+                                   0, 5,        /* M */
+                                   BIT(31),     /* gate */
+                                   BIT(28),     /* lock */
+                                   CLK_SET_RATE_UNGATE);
+
+/* TODO: The result of N/M is required to be in [8, 25] range. */
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
+                                        "osc24M", 0x0010,
+                                        8, 7,           /* N */
+                                        0, 4,           /* M */
+                                        BIT(24),        /* frac enable */
+                                        BIT(25),        /* frac select */
+                                        270000000,      /* frac rate 0 */
+                                        297000000,      /* frac rate 1 */
+                                        BIT(31),        /* gate */
+                                        BIT(28),        /* lock */
+                                        CLK_SET_RATE_UNGATE);
+
+/* TODO: The result of N/M is required to be in [8, 25] range. */
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
+                                        "osc24M", 0x0018,
+                                        8, 7,           /* N */
+                                        0, 4,           /* M */
+                                        BIT(24),        /* frac enable */
+                                        BIT(25),        /* frac select */
+                                        270000000,      /* frac rate 0 */
+                                        297000000,      /* frac rate 1 */
+                                        BIT(31),        /* gate */
+                                        BIT(28),        /* lock */
+                                        CLK_SET_RATE_UNGATE);
+
+/* TODO: The result of N*K is required to be in [10, 77] range. */
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
+                                    "osc24M", 0x020,
+                                    8, 5,       /* N */
+                                    4, 2,       /* K */
+                                    0, 2,       /* M */
+                                    BIT(31),    /* gate */
+                                    BIT(28),    /* lock */
+                                    CLK_SET_RATE_UNGATE);
+
+/* TODO: The result of N*K is required to be in [21, 58] range. */
+static struct ccu_nk pll_periph0_clk = {
+        .enable         = BIT(31),
+        .lock           = BIT(28),
+        .n              = _SUNXI_CCU_MULT(8, 5),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .fixed_post_div = 2,
+        .common         = {
+                .reg            = 0x028,
+                .features       = CCU_FEATURE_FIXED_POSTDIV,
+                .hw.init        = CLK_HW_INIT("pll-periph0", "osc24M",
+                                              &ccu_nk_ops,
+                                              CLK_SET_RATE_UNGATE),
+        },
+};
+
+static struct ccu_div pll_periph0_sata_clk = {
+        .enable         = BIT(24),
+        .div            = _SUNXI_CCU_DIV(0, 2),
+        /*
+         * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
+         * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
+         * 6/2 = 3.
+         */
+        .fixed_post_div = 3,
+        .common         = {
+                .reg            = 0x028,
+                .features       = CCU_FEATURE_FIXED_POSTDIV,
+                .hw.init        = CLK_HW_INIT("pll-periph0-sata",
+                                              "pll-periph0",
+                                              &ccu_div_ops, 0),
+        },
+};
+
+/* TODO: The result of N*K is required to be in [21, 58] range. */
+static struct ccu_nk pll_periph1_clk = {
+        .enable         = BIT(31),
+        .lock           = BIT(28),
+        .n              = _SUNXI_CCU_MULT(8, 5),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .fixed_post_div = 2,
+        .common         = {
+                .reg            = 0x02c,
+                .features       = CCU_FEATURE_FIXED_POSTDIV,
+                .hw.init        = CLK_HW_INIT("pll-periph1", "osc24M",
+                                              &ccu_nk_ops,
+                                              CLK_SET_RATE_UNGATE),
+        },
+};
+
+/* TODO: The result of N/M is required to be in [8, 25] range. */
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
+                                        "osc24M", 0x030,
+                                        8, 7,           /* N */
+                                        0, 4,           /* M */
+                                        BIT(24),        /* frac enable */
+                                        BIT(25),        /* frac select */
+                                        270000000,      /* frac rate 0 */
+                                        297000000,      /* frac rate 1 */
+                                        BIT(31),        /* gate */
+                                        BIT(28),        /* lock */
+                                        CLK_SET_RATE_UNGATE);
+
+static struct ccu_nkm pll_sata_clk = {
+        .enable         = BIT(31),
+        .lock           = BIT(28),
+        .n              = _SUNXI_CCU_MULT(8, 5),
+        .k              = _SUNXI_CCU_MULT(4, 2),
+        .m              = _SUNXI_CCU_DIV(0, 2),
+        .fixed_post_div = 6,
+        .common         = {
+                .reg            = 0x034,
+                .features       = CCU_FEATURE_FIXED_POSTDIV,
+                .hw.init        = CLK_HW_INIT("pll-sata", "osc24M",
+                                              &ccu_nkm_ops,
+                                              CLK_SET_RATE_UNGATE),
+        },
+};
+
+static const char * const pll_sata_out_parents[] = { "pll-sata",
+                                                     "pll-periph0-sata" };
+static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
+                               pll_sata_out_parents, 0x034,
+                               30, 1,   /* mux */
+                               BIT(14), /* gate */
+                               CLK_SET_RATE_PARENT);
+
+/* TODO: The result of N/M is required to be in [8, 25] range. */
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
+                                        "osc24M", 0x038,
+                                        8, 7,           /* N */
+                                        0, 4,           /* M */
+                                        BIT(24),        /* frac enable */
+                                        BIT(25),        /* frac select */
+                                        270000000,      /* frac rate 0 */
+                                        297000000,      /* frac rate 1 */
+                                        BIT(31),        /* gate */
+                                        BIT(28),        /* lock */
+                                        CLK_SET_RATE_UNGATE);
+
+/*
+ * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
+ *
+ * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
+ * integer / fractional clock with switchable multipliers and dividers.
+ * This is not supported here. We hardcode the PLL to MIPI mode.
+ *
+ * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
+ * which cannot be implemented now.
+ */
+#define SUN8I_R40_PLL_MIPI_REG  0x040
+
+static const char * const pll_mipi_parents[] = { "pll-video0" };
+static struct ccu_nkm pll_mipi_clk = {
+        .enable = BIT(31) | BIT(23) | BIT(22),
+        .lock   = BIT(28),
+        .n      = _SUNXI_CCU_MULT(8, 4),
+        .k      = _SUNXI_CCU_MULT_MIN(4, 2, 2),
+        .m      = _SUNXI_CCU_DIV(0, 4),
+        .mux    = _SUNXI_CCU_MUX(21, 1),
+        .common = {
+                .reg            = 0x040,
+                .hw.init        = CLK_HW_INIT_PARENTS("pll-mipi",
+                                                      pll_mipi_parents,
+                                                      &ccu_nkm_ops,
+                                                      CLK_SET_RATE_UNGATE)
+        },
+};
+
+/* TODO: The result of N/M is required to be in [8, 25] range. */
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
+                                        "osc24M", 0x048,
+                                        8, 7,           /* N */
+                                        0, 4,           /* M */
+                                        BIT(24),        /* frac enable */
+                                        BIT(25),        /* frac select */
+                                        270000000,      /* frac rate 0 */
+                                        297000000,      /* frac rate 1 */
+                                        BIT(31),        /* gate */
+                                        BIT(28),        /* lock */
+                                        CLK_SET_RATE_UNGATE);
+
+/* TODO: The N factor is required to be in [16, 75] range. */
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
+                                   "osc24M", 0x04c,
+                                   8, 7,        /* N */
+                                   0, 2,        /* M */
+                                   BIT(31),     /* gate */
+                                   BIT(28),     /* lock */
+                                   CLK_SET_RATE_UNGATE);
+
+static const char * const cpu_parents[] = { "osc32k", "osc24M",
+                                             "pll-cpu", "pll-cpu" };
+static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
+                     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
+
+static const char * const ahb1_parents[] = { "osc32k", "osc24M",
+                                             "axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+        { .index = 3, .shift = 6, .width = 2 },
+};
+static struct ccu_div ahb1_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+        .mux            = {
+                .shift  = 12,
+                .width  = 2,
+
+                .var_predivs    = ahb1_predivs,
+                .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
+        },
+
+        .common         = {
+                .reg            = 0x054,
+                .features       = CCU_FEATURE_VARIABLE_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
+                                                      ahb1_parents,
+                                                      &ccu_div_ops,
+                                                      0),
+        },
+};
+
+static struct clk_div_table apb1_div_table[] = {
+        { .val = 0, .div = 2 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 4 },
+        { .val = 3, .div = 8 },
+        { /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
+                           0x054, 8, 2, apb1_div_table, 0);
+
+static const char * const apb2_parents[] = { "osc32k", "osc24M",
+                                             "pll-periph0-2x",
+                                             "pll-periph0-2x" };
+static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
+                             0, 5,      /* M */
+                             16, 2,     /* P */
+                             24, 2,     /* mux */
+                             0);
+
+static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
+                      0x060, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_ce_clk,       "bus-ce",       "ahb1",
+                      0x060, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
+                      0x060, BIT(6), 0);
+static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
+                      0x060, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
+                      0x060, BIT(9), 0);
+static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
+                      0x060, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_mmc3_clk,     "bus-mmc3",     "ahb1",
+                      0x060, BIT(11), 0);
+static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
+                      0x060, BIT(13), 0);
+static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
+                      0x060, BIT(14), 0);
+static SUNXI_CCU_GATE(bus_emac_clk,     "bus-emac",     "ahb1",
+                      0x060, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_ts_clk,       "bus-ts",       "ahb1",
+                      0x060, BIT(18), 0);
+static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
+                      0x060, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
+                      0x060, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
+                      0x060, BIT(21), 0);
+static SUNXI_CCU_GATE(bus_spi2_clk,     "bus-spi2",     "ahb1",
+                      0x060, BIT(22), 0);
+static SUNXI_CCU_GATE(bus_spi3_clk,     "bus-spi3",     "ahb1",
+                      0x060, BIT(23), 0);
+static SUNXI_CCU_GATE(bus_sata_clk,     "bus-sata",     "ahb1",
+                      0x060, BIT(24), 0);
+static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
+                      0x060, BIT(25), 0);
+static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb1",
+                      0x060, BIT(26), 0);
+static SUNXI_CCU_GATE(bus_ehci1_clk,    "bus-ehci1",    "ahb1",
+                      0x060, BIT(27), 0);
+static SUNXI_CCU_GATE(bus_ehci2_clk,    "bus-ehci2",    "ahb1",
+                      0x060, BIT(28), 0);
+static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb1",
+                      0x060, BIT(29), 0);
+static SUNXI_CCU_GATE(bus_ohci1_clk,    "bus-ohci1",    "ahb1",
+                      0x060, BIT(30), 0);
+static SUNXI_CCU_GATE(bus_ohci2_clk,    "bus-ohci2",    "ahb1",
+                      0x060, BIT(31), 0);
+
+static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
+                      0x064, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_mp_clk,       "bus-mp",       "ahb1",
+                      0x064, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_deinterlace_clk,      "bus-deinterlace",      "ahb1",
+                      0x064, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_csi0_clk,     "bus-csi0",     "ahb1",
+                      0x064, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_csi1_clk,     "bus-csi1",     "ahb1",
+                      0x064, BIT(9), 0);
+static SUNXI_CCU_GATE(bus_hdmi0_clk,    "bus-hdmi0",    "ahb1",
+                      0x064, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_hdmi1_clk,    "bus-hdmi1",    "ahb1",
+                      0x064, BIT(11), 0);
+static SUNXI_CCU_GATE(bus_de_clk,       "bus-de",       "ahb1",
+                      0x064, BIT(12), 0);
+static SUNXI_CCU_GATE(bus_tve0_clk,     "bus-tve0",     "ahb1",
+                      0x064, BIT(13), 0);
+static SUNXI_CCU_GATE(bus_tve1_clk,     "bus-tve1",     "ahb1",
+                      0x064, BIT(14), 0);
+static SUNXI_CCU_GATE(bus_tve_top_clk,  "bus-tve-top",  "ahb1",
+                      0x064, BIT(15), 0);
+static SUNXI_CCU_GATE(bus_gmac_clk,     "bus-gmac",     "ahb1",
+                      0x064, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
+                      0x064, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_tvd0_clk,     "bus-tvd0",     "ahb1",
+                      0x064, BIT(21), 0);
+static SUNXI_CCU_GATE(bus_tvd1_clk,     "bus-tvd1",     "ahb1",
+                      0x064, BIT(22), 0);
+static SUNXI_CCU_GATE(bus_tvd2_clk,     "bus-tvd2",     "ahb1",
+                      0x064, BIT(23), 0);
+static SUNXI_CCU_GATE(bus_tvd3_clk,     "bus-tvd3",     "ahb1",
+                      0x064, BIT(24), 0);
+static SUNXI_CCU_GATE(bus_tvd_top_clk,  "bus-tvd-top",  "ahb1",
+                      0x064, BIT(25), 0);
+static SUNXI_CCU_GATE(bus_tcon_lcd0_clk,        "bus-tcon-lcd0",        "ahb1",
+                      0x064, BIT(26), 0);
+static SUNXI_CCU_GATE(bus_tcon_lcd1_clk,        "bus-tcon-lcd1",        "ahb1",
+                      0x064, BIT(27), 0);
+static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
+                      0x064, BIT(28), 0);
+static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
+                      0x064, BIT(29), 0);
+static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
+                      0x064, BIT(30), 0);
+
+static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
+                      0x068, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_spdif_clk,    "bus-spdif",    "apb1",
+                      0x068, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_ac97_clk,     "bus-ac97",     "apb1",
+                      0x068, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
+                      0x068, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_ir0_clk,      "bus-ir0",      "apb1",
+                      0x068, BIT(6), 0);
+static SUNXI_CCU_GATE(bus_ir1_clk,      "bus-ir1",      "apb1",
+                      0x068, BIT(7), 0);
+static SUNXI_CCU_GATE(bus_ths_clk,      "bus-ths",      "apb1",
+                      0x068, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_keypad_clk,   "bus-keypad",   "apb1",
+                      0x068, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
+                      0x068, BIT(12), 0);
+static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
+                      0x068, BIT(13), 0);
+static SUNXI_CCU_GATE(bus_i2s2_clk,     "bus-i2s2",     "apb1",
+                      0x068, BIT(14), 0);
+
+static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
+                      0x06c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
+                      0x06c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
+                      0x06c, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_i2c3_clk,     "bus-i2c3",     "apb2",
+                      0x06c, BIT(3), 0);
+/*
+ * In datasheet here's "Reserved", however the gate exists in BSP soucre
+ * code.
+ */
+static SUNXI_CCU_GATE(bus_can_clk,      "bus-can",      "apb2",
+                      0x06c, BIT(4), 0);
+static SUNXI_CCU_GATE(bus_scr_clk,      "bus-scr",      "apb2",
+                      0x06c, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_ps20_clk,     "bus-ps20",     "apb2",
+                      0x06c, BIT(6), 0);
+static SUNXI_CCU_GATE(bus_ps21_clk,     "bus-ps21",     "apb2",
+                      0x06c, BIT(7), 0);
+static SUNXI_CCU_GATE(bus_i2c4_clk,     "bus-i2c4",     "apb2",
+                      0x06c, BIT(15), 0);
+static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
+                      0x06c, BIT(16), 0);
+static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
+                      0x06c, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
+                      0x06c, BIT(18), 0);
+static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
+                      0x06c, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
+                      0x06c, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_uart5_clk,    "bus-uart5",    "apb2",
+                      0x06c, BIT(21), 0);
+static SUNXI_CCU_GATE(bus_uart6_clk,    "bus-uart6",    "apb2",
+                      0x06c, BIT(22), 0);
+static SUNXI_CCU_GATE(bus_uart7_clk,    "bus-uart7",    "apb2",
+                      0x06c, BIT(23), 0);
+
+static SUNXI_CCU_GATE(bus_dbg_clk,      "bus-dbg",      "ahb1",
+                      0x070, BIT(7), 0);
+
+static const char * const ths_parents[] = { "osc24M" };
+static struct ccu_div ths_clk = {
+        .enable = BIT(31),
+        .div    = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
+        .mux    = _SUNXI_CCU_MUX(24, 2),
+        .common = {
+                .reg            = 0x074,
+                .hw.init        = CLK_HW_INIT_PARENTS("ths",
+                                                      ths_parents,
+                                                      &ccu_div_ops,
+                                                      0),
+        },
+};
+
+static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
+                                                     "pll-periph1" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 4,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
+                                           "pll-periph1-2x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
+                                            "pll-audio-2x", "pll-audio" };
+static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
+                               0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
+                               0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
+                               0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
+                               0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
+                               0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static const char * const keypad_parents[] = { "osc24M", "osc32k" };
+static const u8 keypad_table[] = { 0, 2 };
+static struct ccu_mp keypad_clk = {
+        .enable = BIT(31),
+        .m      = _SUNXI_CCU_DIV(0, 5),
+        .p      = _SUNXI_CCU_DIV(16, 2),
+        .mux    = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
+        .common = {
+                .reg            = 0x0c4,
+                .hw.init        = CLK_HW_INIT_PARENTS("keypad",
+                                                      keypad_parents,
+                                                      &ccu_mp_ops,
+                                                      0),
+        }
+};
+
+static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
+static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
+                               0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
+
+/*
+ * There are 3 OHCI 12M clock source selection bits in this register.
+ * We will force them to 0 (12M divided from 48M).
+ */
+#define SUN8I_R40_USB_CLK_REG   0x0cc
+
+static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
+                      0x0cc, BIT(8), 0);
+static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
+                      0x0cc, BIT(9), 0);
+static SUNXI_CCU_GATE(usb_phy2_clk,     "usb-phy2",     "osc24M",
+                      0x0cc, BIT(10), 0);
+static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc12M",
+                      0x0cc, BIT(16), 0);
+static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "osc12M",
+                      0x0cc, BIT(17), 0);
+static SUNXI_CCU_GATE(usb_ohci2_clk,    "usb-ohci2",    "osc12M",
+                      0x0cc, BIT(18), 0);
+
+static const char * const ir_parents[] = { "osc24M", "pll-periph0",
+                                           "pll-periph1", "osc32k" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
+static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
+                            0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
+                      0x100, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_csi0_clk,    "dram-csi0",    "dram",
+                      0x100, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_csi1_clk,    "dram-csi1",    "dram",
+                      0x100, BIT(2), 0);
+static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "dram",
+                      0x100, BIT(3), 0);
+static SUNXI_CCU_GATE(dram_tvd_clk,     "dram-tvd",     "dram",
+                      0x100, BIT(4), 0);
+static SUNXI_CCU_GATE(dram_mp_clk,      "dram-mp",      "dram",
+                      0x100, BIT(5), 0);
+static SUNXI_CCU_GATE(dram_deinterlace_clk,     "dram-deinterlace",     "dram",
+                      0x100, BIT(6), 0);
+
+static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
+                                 0x104, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
+                                 0x108, 0, 4, 24, 3, BIT(31), 0);
+
+static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
+                                             "pll-video0-2x", "pll-video1-2x",
+                                             "pll-mipi" };
+static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
+                               0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
+                               0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
+                                 0x118, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
+                                 0x11c, 0, 4, 24, 3, BIT(31), 0);
+
+static const char * const deinterlace_parents[] = { "pll-periph0",
+                                                    "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
+                                 deinterlace_parents, 0x124, 0, 4, 24, 3,
+                                 BIT(31), 0);
+
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
+                                                 "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
+                                 0x130, 0, 5, 8, 3, BIT(15), 0);
+
+static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
+                                 0x134, 16, 4, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
+                                 0x134, 0, 5, 8, 3, BIT(15), 0);
+
+static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
+                             0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(codec_clk,        "codec",        "pll-audio",
+                      0x140, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
+                      0x144, BIT(31), 0);
+
+static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
+                                 0x150, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_GATE(hdmi_slow_clk,    "hdmi-slow",    "osc24M",
+                      0x154, BIT(31), 0);
+
+/*
+ * In the SoC's user manual, the P factor is mentioned, but not used in
+ * the frequency formula.
+ *
+ * Here the factor is included, according to the BSP kernel source,
+ * which contains the P factor of this clock.
+ */
+static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
+                                             "pll-ddr0" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
+                                  0, 4,         /* M */
+                                  16, 2,        /* P */
+                                  24, 2,        /* mux */
+                                  BIT(31),      /* gate */
+                                  CLK_IS_CRITICAL);
+
+static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
+                                                 "pll-periph0" };
+static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
+                                 0x168, 0, 4, 8, 2, BIT(15), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
+                                 0x180, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
+                                 0x184, 0, 4, 24, 3, BIT(31), 0);
+
+static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
+                                            "pll-video0-2x", "pll-video1-2x" };
+static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
+                                 0x188, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
+                                 0x18c, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
+                                 0x190, 0, 4, 24, 3, BIT(31), 0);
+static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
+                                 0x194, 0, 4, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
+                             0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
+
+static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
+static const struct ccu_mux_fixed_prediv out_predivs[] = {
+        { .index = 0, .div = 750, },
+};
+
+static struct ccu_mp outa_clk = {
+        .enable = BIT(31),
+        .m      = _SUNXI_CCU_DIV(8, 5),
+        .p      = _SUNXI_CCU_DIV(20, 2),
+        .mux    = {
+                .shift          = 24,
+                .width          = 2,
+                .fixed_predivs  = out_predivs,
+                .n_predivs      = ARRAY_SIZE(out_predivs),
+        },
+        .common = {
+                .reg            = 0x1f0,
+                .features       = CCU_FEATURE_FIXED_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("outa", out_parents,
+                                                      &ccu_mp_ops, 0),
+        }
+};
+
+static struct ccu_mp outb_clk = {
+        .enable = BIT(31),
+        .m      = _SUNXI_CCU_DIV(8, 5),
+        .p      = _SUNXI_CCU_DIV(20, 2),
+        .mux    = {
+                .shift          = 24,
+                .width          = 2,
+                .fixed_predivs  = out_predivs,
+                .n_predivs      = ARRAY_SIZE(out_predivs),
+        },
+        .common = {
+                .reg            = 0x1f4,
+                .features       = CCU_FEATURE_FIXED_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("outb", out_parents,
+                                                      &ccu_mp_ops, 0),
+        }
+};
+
+static struct ccu_common *sun8i_r40_ccu_clks[] = {
+        &pll_cpu_clk.common,
+        &pll_audio_base_clk.common,
+        &pll_video0_clk.common,
+        &pll_ve_clk.common,
+        &pll_ddr0_clk.common,
+        &pll_periph0_clk.common,
+        &pll_periph0_sata_clk.common,
+        &pll_periph1_clk.common,
+        &pll_video1_clk.common,
+        &pll_sata_clk.common,
+        &pll_sata_out_clk.common,
+        &pll_gpu_clk.common,
+        &pll_mipi_clk.common,
+        &pll_de_clk.common,
+        &pll_ddr1_clk.common,
+        &cpu_clk.common,
+        &axi_clk.common,
+        &ahb1_clk.common,
+        &apb1_clk.common,
+        &apb2_clk.common,
+        &bus_mipi_dsi_clk.common,
+        &bus_ce_clk.common,
+        &bus_dma_clk.common,
+        &bus_mmc0_clk.common,
+        &bus_mmc1_clk.common,
+        &bus_mmc2_clk.common,
+        &bus_mmc3_clk.common,
+        &bus_nand_clk.common,
+        &bus_dram_clk.common,
+        &bus_emac_clk.common,
+        &bus_ts_clk.common,
+        &bus_hstimer_clk.common,
+        &bus_spi0_clk.common,
+        &bus_spi1_clk.common,
+        &bus_spi2_clk.common,
+        &bus_spi3_clk.common,
+        &bus_sata_clk.common,
+        &bus_otg_clk.common,
+        &bus_ehci0_clk.common,
+        &bus_ehci1_clk.common,
+        &bus_ehci2_clk.common,
+        &bus_ohci0_clk.common,
+        &bus_ohci1_clk.common,
+        &bus_ohci2_clk.common,
+        &bus_ve_clk.common,
+        &bus_mp_clk.common,
+        &bus_deinterlace_clk.common,
+        &bus_csi0_clk.common,
+        &bus_csi1_clk.common,
+        &bus_hdmi0_clk.common,
+        &bus_hdmi1_clk.common,
+        &bus_de_clk.common,
+        &bus_tve0_clk.common,
+        &bus_tve1_clk.common,
+        &bus_tve_top_clk.common,
+        &bus_gmac_clk.common,
+        &bus_gpu_clk.common,
+        &bus_tvd0_clk.common,
+        &bus_tvd1_clk.common,
+        &bus_tvd2_clk.common,
+        &bus_tvd3_clk.common,
+        &bus_tvd_top_clk.common,
+        &bus_tcon_lcd0_clk.common,
+        &bus_tcon_lcd1_clk.common,
+        &bus_tcon_tv0_clk.common,
+        &bus_tcon_tv1_clk.common,
+        &bus_tcon_top_clk.common,
+        &bus_codec_clk.common,
+        &bus_spdif_clk.common,
+        &bus_ac97_clk.common,
+        &bus_pio_clk.common,
+        &bus_ir0_clk.common,
+        &bus_ir1_clk.common,
+        &bus_ths_clk.common,
+        &bus_keypad_clk.common,
+        &bus_i2s0_clk.common,
+        &bus_i2s1_clk.common,
+        &bus_i2s2_clk.common,
+        &bus_i2c0_clk.common,
+        &bus_i2c1_clk.common,
+        &bus_i2c2_clk.common,
+        &bus_i2c3_clk.common,
+        &bus_can_clk.common,
+        &bus_scr_clk.common,
+        &bus_ps20_clk.common,
+        &bus_ps21_clk.common,
+        &bus_i2c4_clk.common,
+        &bus_uart0_clk.common,
+        &bus_uart1_clk.common,
+        &bus_uart2_clk.common,
+        &bus_uart3_clk.common,
+        &bus_uart4_clk.common,
+        &bus_uart5_clk.common,
+        &bus_uart6_clk.common,
+        &bus_uart7_clk.common,
+        &bus_dbg_clk.common,
+        &ths_clk.common,
+        &nand_clk.common,
+        &mmc0_clk.common,
+        &mmc1_clk.common,
+        &mmc2_clk.common,
+        &mmc3_clk.common,
+        &ts_clk.common,
+        &ce_clk.common,
+        &spi0_clk.common,
+        &spi1_clk.common,
+        &spi2_clk.common,
+        &spi3_clk.common,
+        &i2s0_clk.common,
+        &i2s1_clk.common,
+        &i2s2_clk.common,
+        &ac97_clk.common,
+        &spdif_clk.common,
+        &keypad_clk.common,
+        &sata_clk.common,
+        &usb_phy0_clk.common,
+        &usb_phy1_clk.common,
+        &usb_phy2_clk.common,
+        &usb_ohci0_clk.common,
+        &usb_ohci1_clk.common,
+        &usb_ohci2_clk.common,
+        &ir0_clk.common,
+        &ir1_clk.common,
+        &dram_clk.common,
+        &dram_ve_clk.common,
+        &dram_csi0_clk.common,
+        &dram_csi1_clk.common,
+        &dram_ts_clk.common,
+        &dram_tvd_clk.common,
+        &dram_mp_clk.common,
+        &dram_deinterlace_clk.common,
+        &de_clk.common,
+        &mp_clk.common,
+        &tcon_lcd0_clk.common,
+        &tcon_lcd1_clk.common,
+        &tcon_tv0_clk.common,
+        &tcon_tv1_clk.common,
+        &deinterlace_clk.common,
+        &csi1_mclk_clk.common,
+        &csi_sclk_clk.common,
+        &csi0_mclk_clk.common,
+        &ve_clk.common,
+        &codec_clk.common,
+        &avs_clk.common,
+        &hdmi_clk.common,
+        &hdmi_slow_clk.common,
+        &mbus_clk.common,
+        &dsi_dphy_clk.common,
+        &tve0_clk.common,
+        &tve1_clk.common,
+        &tvd0_clk.common,
+        &tvd1_clk.common,
+        &tvd2_clk.common,
+        &tvd3_clk.common,
+        &gpu_clk.common,
+        &outa_clk.common,
+        &outb_clk.common,
+};
+
+/* Fixed Factor clocks */
+static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
+
+/* We hardcode the divider to 4 for now */
+static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+                        "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
+                        "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
+                        "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
+                        "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
+                        "pll-periph0", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
+                        "pll-periph1", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
+                        "pll-video0", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
+                        "pll-video1", 1, 2, 0);
+
+static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
+        .hws    = {
+                [CLK_OSC_12M]           = &osc12M_clk.hw,
+                [CLK_PLL_CPU]           = &pll_cpu_clk.common.hw,
+                [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
+                [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
+                [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
+                [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
+                [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
+                [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
+                [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
+                [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
+                [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
+                [CLK_PLL_PERIPH0]       = &pll_periph0_clk.common.hw,
+                [CLK_PLL_PERIPH0_SATA]  = &pll_periph0_sata_clk.common.hw,
+                [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
+                [CLK_PLL_PERIPH1]       = &pll_periph1_clk.common.hw,
+                [CLK_PLL_PERIPH1_2X]    = &pll_periph1_2x_clk.hw,
+                [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
+                [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
+                [CLK_PLL_SATA]          = &pll_sata_clk.common.hw,
+                [CLK_PLL_SATA_OUT]      = &pll_sata_out_clk.common.hw,
+                [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
+                [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
+                [CLK_PLL_DE]            = &pll_de_clk.common.hw,
+                [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
+                [CLK_CPU]               = &cpu_clk.common.hw,
+                [CLK_AXI]               = &axi_clk.common.hw,
+                [CLK_AHB1]              = &ahb1_clk.common.hw,
+                [CLK_APB1]              = &apb1_clk.common.hw,
+                [CLK_APB2]              = &apb2_clk.common.hw,
+                [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
+                [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
+                [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
+                [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
+                [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
+                [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
+                [CLK_BUS_MMC3]          = &bus_mmc3_clk.common.hw,
+                [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
+                [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
+                [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
+                [CLK_BUS_TS]            = &bus_ts_clk.common.hw,
+                [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
+                [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
+                [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
+                [CLK_BUS_SPI2]          = &bus_spi2_clk.common.hw,
+                [CLK_BUS_SPI3]          = &bus_spi3_clk.common.hw,
+                [CLK_BUS_SATA]          = &bus_sata_clk.common.hw,
+                [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
+                [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
+                [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
+                [CLK_BUS_EHCI2]         = &bus_ehci2_clk.common.hw,
+                [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
+                [CLK_BUS_OHCI1]         = &bus_ohci1_clk.common.hw,
+                [CLK_BUS_OHCI2]         = &bus_ohci2_clk.common.hw,
+                [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
+                [CLK_BUS_MP]            = &bus_mp_clk.common.hw,
+                [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
+                [CLK_BUS_CSI0]          = &bus_csi0_clk.common.hw,
+                [CLK_BUS_CSI1]          = &bus_csi1_clk.common.hw,
+                [CLK_BUS_HDMI0]         = &bus_hdmi0_clk.common.hw,
+                [CLK_BUS_HDMI1]         = &bus_hdmi1_clk.common.hw,
+                [CLK_BUS_DE]            = &bus_de_clk.common.hw,
+                [CLK_BUS_TVE0]          = &bus_tve0_clk.common.hw,
+                [CLK_BUS_TVE1]          = &bus_tve1_clk.common.hw,
+                [CLK_BUS_TVE_TOP]       = &bus_tve_top_clk.common.hw,
+                [CLK_BUS_GMAC]          = &bus_gmac_clk.common.hw,
+                [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
+                [CLK_BUS_TVD0]          = &bus_tvd0_clk.common.hw,
+                [CLK_BUS_TVD1]          = &bus_tvd1_clk.common.hw,
+                [CLK_BUS_TVD2]          = &bus_tvd2_clk.common.hw,
+                [CLK_BUS_TVD3]          = &bus_tvd3_clk.common.hw,
+                [CLK_BUS_TVD_TOP]       = &bus_tvd_top_clk.common.hw,
+                [CLK_BUS_TCON_LCD0]     = &bus_tcon_lcd0_clk.common.hw,
+                [CLK_BUS_TCON_LCD1]     = &bus_tcon_lcd1_clk.common.hw,
+                [CLK_BUS_TCON_TV0]      = &bus_tcon_tv0_clk.common.hw,
+                [CLK_BUS_TCON_TV1]      = &bus_tcon_tv1_clk.common.hw,
+                [CLK_BUS_TCON_TOP]      = &bus_tcon_top_clk.common.hw,
+                [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
+                [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
+                [CLK_BUS_AC97]          = &bus_ac97_clk.common.hw,
+                [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
+                [CLK_BUS_IR0]           = &bus_ir0_clk.common.hw,
+                [CLK_BUS_IR1]           = &bus_ir1_clk.common.hw,
+                [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
+                [CLK_BUS_KEYPAD]        = &bus_keypad_clk.common.hw,
+                [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
+                [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
+                [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
+                [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
+                [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
+                [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
+                [CLK_BUS_I2C3]          = &bus_i2c3_clk.common.hw,
+                [CLK_BUS_CAN]           = &bus_can_clk.common.hw,
+                [CLK_BUS_SCR]           = &bus_scr_clk.common.hw,
+                [CLK_BUS_PS20]          = &bus_ps20_clk.common.hw,
+                [CLK_BUS_PS21]          = &bus_ps21_clk.common.hw,
+                [CLK_BUS_I2C4]          = &bus_i2c4_clk.common.hw,
+                [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
+                [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
+                [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
+                [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
+                [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
+                [CLK_BUS_UART5]         = &bus_uart5_clk.common.hw,
+                [CLK_BUS_UART6]         = &bus_uart6_clk.common.hw,
+                [CLK_BUS_UART7]         = &bus_uart7_clk.common.hw,
+                [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
+                [CLK_THS]               = &ths_clk.common.hw,
+                [CLK_NAND]              = &nand_clk.common.hw,
+                [CLK_MMC0]              = &mmc0_clk.common.hw,
+                [CLK_MMC1]              = &mmc1_clk.common.hw,
+                [CLK_MMC2]              = &mmc2_clk.common.hw,
+                [CLK_MMC3]              = &mmc3_clk.common.hw,
+                [CLK_TS]                = &ts_clk.common.hw,
+                [CLK_CE]                = &ce_clk.common.hw,
+                [CLK_SPI0]              = &spi0_clk.common.hw,
+                [CLK_SPI1]              = &spi1_clk.common.hw,
+                [CLK_SPI2]              = &spi2_clk.common.hw,
+                [CLK_SPI3]              = &spi3_clk.common.hw,
+                [CLK_I2S0]              = &i2s0_clk.common.hw,
+                [CLK_I2S1]              = &i2s1_clk.common.hw,
+                [CLK_I2S2]              = &i2s2_clk.common.hw,
+                [CLK_AC97]              = &ac97_clk.common.hw,
+                [CLK_SPDIF]             = &spdif_clk.common.hw,
+                [CLK_KEYPAD]            = &keypad_clk.common.hw,
+                [CLK_SATA]              = &sata_clk.common.hw,
+                [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
+                [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
+                [CLK_USB_PHY2]          = &usb_phy2_clk.common.hw,
+                [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
+                [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
+                [CLK_USB_OHCI2]         = &usb_ohci2_clk.common.hw,
+                [CLK_IR0]               = &ir0_clk.common.hw,
+                [CLK_IR1]               = &ir1_clk.common.hw,
+                [CLK_DRAM]              = &dram_clk.common.hw,
+                [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
+                [CLK_DRAM_CSI0]         = &dram_csi0_clk.common.hw,
+                [CLK_DRAM_CSI1]         = &dram_csi1_clk.common.hw,
+                [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
+                [CLK_DRAM_TVD]          = &dram_tvd_clk.common.hw,
+                [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
+                [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
+                [CLK_DE]                = &de_clk.common.hw,
+                [CLK_MP]                = &mp_clk.common.hw,
+                [CLK_TCON_LCD0]         = &tcon_lcd0_clk.common.hw,
+                [CLK_TCON_LCD1]         = &tcon_lcd1_clk.common.hw,
+                [CLK_TCON_TV0]          = &tcon_tv0_clk.common.hw,
+                [CLK_TCON_TV1]          = &tcon_tv1_clk.common.hw,
+                [CLK_DEINTERLACE]       = &deinterlace_clk.common.hw,
+                [CLK_CSI1_MCLK]         = &csi1_mclk_clk.common.hw,
+                [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
+                [CLK_CSI0_MCLK]         = &csi0_mclk_clk.common.hw,
+                [CLK_VE]                = &ve_clk.common.hw,
+                [CLK_CODEC]             = &codec_clk.common.hw,
+                [CLK_AVS]               = &avs_clk.common.hw,
+                [CLK_HDMI]              = &hdmi_clk.common.hw,
+                [CLK_HDMI_SLOW]         = &hdmi_slow_clk.common.hw,
+                [CLK_MBUS]              = &mbus_clk.common.hw,
+                [CLK_DSI_DPHY]          = &dsi_dphy_clk.common.hw,
+                [CLK_TVE0]              = &tve0_clk.common.hw,
+                [CLK_TVE1]              = &tve1_clk.common.hw,
+                [CLK_TVD0]              = &tvd0_clk.common.hw,
+                [CLK_TVD1]              = &tvd1_clk.common.hw,
+                [CLK_TVD2]              = &tvd2_clk.common.hw,
+                [CLK_TVD3]              = &tvd3_clk.common.hw,
+                [CLK_GPU]               = &gpu_clk.common.hw,
+                [CLK_OUTA]              = &outa_clk.common.hw,
+                [CLK_OUTB]              = &outb_clk.common.hw,
+        },
+        .num    = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
+        [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
+        [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
+        [RST_USB_PHY2]          =  { 0x0cc, BIT(2) },
+
+        [RST_DRAM]              =  { 0x0f4, BIT(31) },
+        [RST_MBUS]              =  { 0x0fc, BIT(31) },
+
+        [RST_BUS_MIPI_DSI]      =  { 0x2c0, BIT(1) },
+        [RST_BUS_CE]            =  { 0x2c0, BIT(5) },
+        [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
+        [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
+        [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
+        [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
+        [RST_BUS_MMC3]          =  { 0x2c0, BIT(11) },
+        [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
+        [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
+        [RST_BUS_EMAC]          =  { 0x2c0, BIT(17) },
+        [RST_BUS_TS]            =  { 0x2c0, BIT(18) },
+        [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
+        [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
+        [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
+        [RST_BUS_SPI2]          =  { 0x2c0, BIT(22) },
+        [RST_BUS_SPI3]          =  { 0x2c0, BIT(23) },
+        [RST_BUS_SATA]          =  { 0x2c0, BIT(24) },
+        [RST_BUS_OTG]           =  { 0x2c0, BIT(25) },
+        [RST_BUS_EHCI0]         =  { 0x2c0, BIT(26) },
+        [RST_BUS_EHCI1]         =  { 0x2c0, BIT(27) },
+        [RST_BUS_EHCI2]         =  { 0x2c0, BIT(28) },
+        [RST_BUS_OHCI0]         =  { 0x2c0, BIT(29) },
+        [RST_BUS_OHCI1]         =  { 0x2c0, BIT(30) },
+        [RST_BUS_OHCI2]         =  { 0x2c0, BIT(31) },
+
+        [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
+        [RST_BUS_MP]            =  { 0x2c4, BIT(2) },
+        [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
+        [RST_BUS_CSI0]          =  { 0x2c4, BIT(8) },
+        [RST_BUS_CSI1]          =  { 0x2c4, BIT(9) },
+        [RST_BUS_HDMI0]         =  { 0x2c4, BIT(10) },
+        [RST_BUS_HDMI1]         =  { 0x2c4, BIT(11) },
+        [RST_BUS_DE]            =  { 0x2c4, BIT(12) },
+        [RST_BUS_TVE0]          =  { 0x2c4, BIT(13) },
+        [RST_BUS_TVE1]          =  { 0x2c4, BIT(14) },
+        [RST_BUS_TVE_TOP]       =  { 0x2c4, BIT(15) },
+        [RST_BUS_GMAC]          =  { 0x2c4, BIT(17) },
+        [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
+        [RST_BUS_TVD0]          =  { 0x2c4, BIT(21) },
+        [RST_BUS_TVD1]          =  { 0x2c4, BIT(22) },
+        [RST_BUS_TVD2]          =  { 0x2c4, BIT(23) },
+        [RST_BUS_TVD3]          =  { 0x2c4, BIT(24) },
+        [RST_BUS_TVD_TOP]       =  { 0x2c4, BIT(25) },
+        [RST_BUS_TCON_LCD0]     =  { 0x2c4, BIT(26) },
+        [RST_BUS_TCON_LCD1]     =  { 0x2c4, BIT(27) },
+        [RST_BUS_TCON_TV0]      =  { 0x2c4, BIT(28) },
+        [RST_BUS_TCON_TV1]      =  { 0x2c4, BIT(29) },
+        [RST_BUS_TCON_TOP]      =  { 0x2c4, BIT(30) },
+        [RST_BUS_DBG]           =  { 0x2c4, BIT(31) },
+
+        [RST_BUS_LVDS]          =  { 0x2c8, BIT(0) },
+
+        [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
+        [RST_BUS_SPDIF]         =  { 0x2d0, BIT(1) },
+        [RST_BUS_AC97]          =  { 0x2d0, BIT(2) },
+        [RST_BUS_IR0]           =  { 0x2d0, BIT(6) },
+        [RST_BUS_IR1]           =  { 0x2d0, BIT(7) },
+        [RST_BUS_THS]           =  { 0x2d0, BIT(8) },
+        [RST_BUS_KEYPAD]        =  { 0x2d0, BIT(10) },
+        [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
+        [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
+        [RST_BUS_I2S2]          =  { 0x2d0, BIT(14) },
+
+        [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
+        [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
+        [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
+        [RST_BUS_I2C3]          =  { 0x2d8, BIT(3) },
+        [RST_BUS_CAN]           =  { 0x2d8, BIT(4) },
+        [RST_BUS_SCR]           =  { 0x2d8, BIT(5) },
+        [RST_BUS_PS20]          =  { 0x2d8, BIT(6) },
+        [RST_BUS_PS21]          =  { 0x2d8, BIT(7) },
+        [RST_BUS_I2C4]          =  { 0x2d8, BIT(15) },
+        [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
+        [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
+        [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
+        [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
+        [RST_BUS_UART4]         =  { 0x2d8, BIT(20) },
+        [RST_BUS_UART5]         =  { 0x2d8, BIT(21) },
+        [RST_BUS_UART6]         =  { 0x2d8, BIT(22) },
+        [RST_BUS_UART7]         =  { 0x2d8, BIT(23) },
+};
+
+static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
+        .ccu_clks       = sun8i_r40_ccu_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun8i_r40_ccu_clks),
+
+        .hw_clks        = &sun8i_r40_hw_clks,
+
+        .resets         = sun8i_r40_ccu_resets,
+        .num_resets     = ARRAY_SIZE(sun8i_r40_ccu_resets),
+};
+
+static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
+        .common = &pll_cpu_clk.common,
+        /* copy from pll_cpu_clk */
+        .enable = BIT(31),
+        .lock   = BIT(28),
+};
+
+static struct ccu_mux_nb sun8i_r40_cpu_nb = {
+        .common         = &cpu_clk.common,
+        .cm             = &cpu_clk.mux,
+        .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
+        .bypass_index   = 1, /* index of 24 MHz oscillator */
+};
+
+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+        void __iomem *reg;
+        u32 val;
+
+        reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+        if (IS_ERR(reg)) {
+                pr_err("%s: Could not map the clock registers\n",
+                       of_node_full_name(node));
+                return;
+        }
+
+        /* Force the PLL-Audio-1x divider to 4 */
+        val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+        val &= ~GENMASK(19, 16);
+        writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+        /* Force PLL-MIPI to MIPI mode */
+        val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+        val &= ~BIT(16);
+        writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+        /* Force OHCI 12M parent to 12M divided from 48M */
+        val = readl(reg + SUN8I_R40_USB_CLK_REG);
+        val &= ~GENMASK(25, 20);
+        writel(val, reg + SUN8I_R40_USB_CLK_REG);
+
+        sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
+
+        /* Gate then ungate PLL CPU after any rate changes */
+        ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
+
+        /* Reparent CPU during PLL CPU rate changes */
+        ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
+                                  &sun8i_r40_cpu_nb);
+}
+CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
+               sun8i_r40_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
new file mode 100644
index 000000000000..0db8e1e97af8
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN8I_R40_H_
+#define _CCU_SUN8I_R40_H_
+
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
+
+#define CLK_OSC_12M             0
+#define CLK_PLL_CPU             1
+#define CLK_PLL_AUDIO_BASE      2
+#define CLK_PLL_AUDIO           3
+#define CLK_PLL_AUDIO_2X        4
+#define CLK_PLL_AUDIO_4X        5
+#define CLK_PLL_AUDIO_8X        6
+#define CLK_PLL_VIDEO0          7
+#define CLK_PLL_VIDEO0_2X       8
+#define CLK_PLL_VE              9
+#define CLK_PLL_DDR0            10
+#define CLK_PLL_PERIPH0         11
+#define CLK_PLL_PERIPH0_SATA    12
+#define CLK_PLL_PERIPH0_2X      13
+#define CLK_PLL_PERIPH1         14
+#define CLK_PLL_PERIPH1_2X      15
+#define CLK_PLL_VIDEO1          16
+#define CLK_PLL_VIDEO1_2X       17
+#define CLK_PLL_SATA            18
+#define CLK_PLL_SATA_OUT        19
+#define CLK_PLL_GPU             20
+#define CLK_PLL_MIPI            21
+#define CLK_PLL_DE              22
+#define CLK_PLL_DDR1            23
+
+/* The CPU clock is exported */
+
+#define CLK_AXI                 25
+#define CLK_AHB1                26
+#define CLK_APB1                27
+#define CLK_APB2                28
+
+/* All the bus gates are exported */
+
+/* The first bunch of module clocks are exported */
+
+#define CLK_DRAM                132
+
+/* All the DRAM gates are exported */
+
+/* Some more module clocks are exported */
+
+#define CLK_MBUS                155
+
+/* Another bunch of module clocks are exported */
+
+#define CLK_NUMBER              (CLK_OUTB + 1)
+
+#endif /* _CCU_SUN8I_R40_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index a34a78d7fb28..621b1cd996db 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -575,8 +575,7 @@ static void __init sun8i_v3s_ccu_setup(struct device_node *node)
 
         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
+                pr_err("%pOF: Could not map the clock registers\n", node);
                 return;
         }
 
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index c0e5c10d0091..baa3cf96507b 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -21,10 +21,18 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
 {
         struct ccu_div *cd = data;
 
-        return divider_round_rate_parent(&cd->common.hw, parent,
+        if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate *= cd->fixed_post_div;
+
+        rate = divider_round_rate_parent(&cd->common.hw, parent,
                                          rate, parent_rate,
                                          cd->div.table, cd->div.width,
                                          cd->div.flags);
+
+        if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate /= cd->fixed_post_div;
+
+        return rate;
 }
 
 static void ccu_div_disable(struct clk_hw *hw)
@@ -62,8 +70,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
         parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                   parent_rate);
 
-        return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
-                                   cd->div.flags);
+        val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
+                                  cd->div.flags);
+
+        if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                val /= cd->fixed_post_div;
+
+        return val;
 }
 
 static int ccu_div_determine_rate(struct clk_hw *hw,
@@ -86,6 +99,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
         parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                   parent_rate);
 
+        if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate *= cd->fixed_post_div;
+
         val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
                               cd->div.flags);
 
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 08d074451204..f3a5028dcd14 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -86,9 +86,10 @@ struct ccu_div_internal {
 struct ccu_div {
         u32                     enable;
 
-        struct ccu_div_internal         div;
+        struct ccu_div_internal div;
         struct ccu_mux_internal mux;
         struct ccu_common       common;
+        unsigned int            fixed_post_div;
 };
 
 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg,    \
diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
index 8b5eb7756bf7..d1d168d4c4f0 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.c
+++ b/drivers/clk/sunxi-ng/ccu_frac.c
@@ -67,25 +67,25 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
 {
         u32 reg;
 
-        printk("%s: Read fractional\n", clk_hw_get_name(&common->hw));
+        pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw));
 
         if (!(common->features & CCU_FEATURE_FRACTIONAL))
                 return 0;
 
-        printk("%s: clock is fractional (rates %lu and %lu)\n",
-               clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
+        pr_debug("%s: clock is fractional (rates %lu and %lu)\n",
+                 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
 
         reg = readl(common->base + common->reg);
 
-        printk("%s: clock reg is 0x%x (select is 0x%x)\n",
-               clk_hw_get_name(&common->hw), reg, cf->select);
+        pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
+                 clk_hw_get_name(&common->hw), reg, cf->select);
 
         return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
 }
 
 int ccu_frac_helper_set_rate(struct ccu_common *common,
                              struct ccu_frac_internal *cf,
-                             unsigned long rate)
+                             unsigned long rate, u32 lock)
 {
         unsigned long flags;
         u32 reg, sel;
@@ -106,5 +106,7 @@ int ccu_frac_helper_set_rate(struct ccu_common *common,
         writel(reg | sel, common->base + common->reg);
         spin_unlock_irqrestore(common->lock, flags);
 
+        ccu_helper_wait_for_lock(common, lock);
+
         return 0;
 }
diff --git a/drivers/clk/sunxi-ng/ccu_frac.h b/drivers/clk/sunxi-ng/ccu_frac.h
index 7b1ee380156f..efe2dd6bac01 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.h
+++ b/drivers/clk/sunxi-ng/ccu_frac.h
@@ -48,6 +48,6 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
 
 int ccu_frac_helper_set_rate(struct ccu_common *common,
                              struct ccu_frac_internal *cf,
-                             unsigned long rate);
+                             unsigned long rate, u32 lock);
 
 #endif /* _CCU_FRAC_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 20d0300867f2..12e0783caee6 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -111,10 +111,14 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
         unsigned long flags;
         u32 reg;
 
-        if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate))
-                return ccu_frac_helper_set_rate(&cm->common, &cm->frac, rate);
-        else
+        if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) {
+                ccu_frac_helper_enable(&cm->common, &cm->frac);
+
+                return ccu_frac_helper_set_rate(&cm->common, &cm->frac,
+                                                rate, cm->lock);
+        } else {
                 ccu_frac_helper_disable(&cm->common, &cm->frac);
+        }
 
         parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
                                                   parent_rate);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 44b16dc8fea6..841840e35e61 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -75,7 +75,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
                                         unsigned long parent_rate)
 {
         struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
-        unsigned long n, m, k;
+        unsigned long n, m, k, rate;
         u32 reg;
 
         reg = readl(nkm->common.base + nkm->common.reg);
@@ -98,7 +98,12 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
         if (!m)
                 m++;
 
-        return parent_rate * n  * k / m;
+        rate = parent_rate * n  * k / m;
+
+        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate /= nkm->fixed_post_div;
+
+        return rate;
 }
 
 static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
@@ -117,9 +122,17 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
         _nkm.min_m = 1;
         _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
 
+        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate *= nkm->fixed_post_div;
+
         ccu_nkm_find_best(*parent_rate, rate, &_nkm);
 
-        return *parent_rate * _nkm.n * _nkm.k / _nkm.m;
+        rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
+
+        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate /= nkm->fixed_post_div;
+
+        return rate;
 }
 
 static int ccu_nkm_determine_rate(struct clk_hw *hw,
@@ -139,6 +152,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
         unsigned long flags;
         u32 reg;
 
+        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+                rate *= nkm->fixed_post_div;
+
         _nkm.min_n = nkm->n.min ?: 1;
         _nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
         _nkm.min_k = nkm->k.min ?: 1;
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index 34580894f4d1..cc6efb70a102 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -34,6 +34,8 @@ struct ccu_nkm {
         struct ccu_div_internal         m;
         struct ccu_mux_internal mux;
 
+        unsigned int            fixed_post_div;
+
         struct ccu_common       common;
 };
 
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 5e5e90a4a50c..a32158e8f2e3 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -117,10 +117,23 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
         unsigned long flags;
         u32 reg;
 
-        if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
-                return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
-        else
+        if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
+                spin_lock_irqsave(nm->common.lock, flags);
+
+                /* most SoCs require M to be 0 if fractional mode is used */
+                reg = readl(nm->common.base + nm->common.reg);
+                reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
+                writel(reg, nm->common.base + nm->common.reg);
+
+                spin_unlock_irqrestore(nm->common.lock, flags);
+
+                ccu_frac_helper_enable(&nm->common, &nm->frac);
+
+                return ccu_frac_helper_set_rate(&nm->common, &nm->frac,
+                                                rate, nm->lock);
+        } else {
                 ccu_frac_helper_disable(&nm->common, &nm->frac);
+        }
 
         _nm.min_n = nm->n.min ?: 1;
         _nm.max_n = nm->n.max ?: 1 << nm->n.width;
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 63fdb790df29..bee305bdddbe 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -78,6 +78,10 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
                         clk_parent = APB1;
                 else if (index >= 96 && index <= 127)
                         clk_parent = APB2;
+                else {
+                        WARN_ON(true);
+                        continue;
+                }
 
                 clk_reg = reg + 4 * (index / 32);
                 clk_bit = index % 32;
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index f2c9274b8bd5..aa4add580516 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -666,15 +666,14 @@ static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
 
         reg = of_iomap(node, 0);
         if (!reg) {
-                pr_err("Could not map registers for mux-clk: %s\n",
-                       of_node_full_name(node));
+                pr_err("Could not map registers for mux-clk: %pOF\n", node);
                 return NULL;
         }
 
         i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
         if (of_property_read_string(node, "clock-output-names", &clk_name)) {
-                pr_err("%s: could not read clock-output-names from \"%s\"\n",
-                       __func__, of_node_full_name(node));
+                pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
+                       __func__, node);
                 goto out_unmap;
         }
 
@@ -797,16 +796,15 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
 
         reg = of_iomap(node, 0);
         if (!reg) {
-                pr_err("Could not map registers for mux-clk: %s\n",
-                       of_node_full_name(node));
+                pr_err("Could not map registers for mux-clk: %pOF\n", node);
                 return;
         }
 
         clk_parent = of_clk_get_parent_name(node, 0);
 
         if (of_property_read_string(node, "clock-output-names", &clk_name)) {
-                pr_err("%s: could not read clock-output-names from \"%s\"\n",
-                       __func__, of_node_full_name(node));
+                pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
+                       __func__, node);
                 goto out_unmap;
         }
 
@@ -1010,8 +1008,7 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
 
         reg = of_iomap(node, 0);
         if (!reg) {
-                pr_err("Could not map registers for divs-clk: %s\n",
-                       of_node_full_name(node));
+                pr_err("Could not map registers for divs-clk: %pOF\n", node);
                 return NULL;
         }
 
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 74e7544f861b..11a5066e5c27 100644
--- a/drivers/clk/tegra/clk-emc.c
+++ b/drivers/clk/tegra/clk-emc.c
@@ -378,7 +378,7 @@ static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
 
         err = of_property_read_u32(node, "clock-frequency", &tmp);
         if (err) {
-                pr_err("timing %s: failed to read rate\n", node->full_name);
+                pr_err("timing %pOF: failed to read rate\n", node);
                 return err;
         }
 
@@ -386,8 +386,7 @@ static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
 
         err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
         if (err) {
-                pr_err("timing %s: failed to read parent rate\n",
-                       node->full_name);
+                pr_err("timing %pOF: failed to read parent rate\n", node);
                 return err;
         }
 
@@ -395,8 +394,7 @@ static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
 
         timing->parent = of_clk_get_by_name(node, "emc-parent");
         if (IS_ERR(timing->parent)) {
-                pr_err("timing %s: failed to get parent clock\n",
-                       node->full_name);
+                pr_err("timing %pOF: failed to get parent clock\n", node);
                 return PTR_ERR(timing->parent);
         }
 
@@ -409,8 +407,8 @@ static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
                 }
         }
         if (timing->parent_index == 0xff) {
-                pr_err("timing %s: %s is not a valid parent\n",
-                       node->full_name, __clk_get_name(timing->parent));
+                pr_err("timing %pOF: %s is not a valid parent\n",
+                       node, __clk_get_name(timing->parent));
                 clk_put(timing->parent);
                 return -EINVAL;
         }
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 159a854779e6..7c369e21c91c 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
                 val = pll_readl(pll->params->iddq_reg, pll);
                 val &= ~BIT(pll->params->iddq_bit_idx);
                 pll_writel(val, pll->params->iddq_reg, pll);
-                udelay(2);
+                udelay(5);
         }
 
         if (pll->params->reset_reg) {
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
         }
 }
 
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+                val |= pll->params->ssc_ctrl_en_mask;
+                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+        }
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+                val &= ~pll->params->ssc_ctrl_en_mask;
+                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+        }
+}
+
 static int clk_pll_enable(struct clk_hw *hw)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
 
         ret = clk_pll_wait_for_lock(pll);
 
+        pll_clk_start_ss(pll);
+
         if (pll->lock)
                 spin_unlock_irqrestore(pll->lock, flags);
 
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
         if (pll->lock)
                 spin_lock_irqsave(pll->lock, flags);
 
+        pll_clk_stop_ss(pll);
+
         _clk_pll_disable(hw);
 
         if (pll->lock)
@@ -666,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
         struct tegra_clk_pll_params *params = pll->params;
         struct div_nmp *div_nmp = params->div_nmp;
 
+        *cfg = (struct tegra_clk_pll_freq_table) { };
+
         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
@@ -716,26 +742,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
         pll_writel_misc(val, pll);
 }
 
-static void pll_clk_start_ss(struct tegra_clk_pll *pll)
-{
-        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
-                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
-                val |= pll->params->ssc_ctrl_en_mask;
-                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
-        }
-}
-
-static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
-{
-        if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
-                u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
-                val &= ~pll->params->ssc_ctrl_en_mask;
-                pll_writel(val, pll->params->ssc_ctrl_reg, pll);
-        }
-}
-
 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                         unsigned long rate)
 {
@@ -2251,7 +2257,7 @@ tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
 }
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
+#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
 static const struct clk_ops tegra_clk_pllss_ops = {
         .is_enabled = clk_pll_is_enabled,
         .enable = clk_pll_enable,
@@ -2349,7 +2355,6 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name,
                           struct tegra_clk_pll_params *pll_params,
                           spinlock_t *lock, unsigned long parent_rate)
 {
-        u32 val;
         struct tegra_clk_pll *pll;
         struct clk *clk;
 
@@ -2363,26 +2368,8 @@ struct clk *tegra_clk_register_pllre_tegra210(const char *name,
         if (IS_ERR(pll))
                 return ERR_CAST(pll);
 
-        /* program minimum rate by default */
-
-        val = pll_readl_base(pll);
-        if (val & PLL_BASE_ENABLE)
-                WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
-                                BIT(pll_params->iddq_bit_idx));
-        else {
-                val = 0x4 << divm_shift(pll);
-                val |= 0x41 << divn_shift(pll);
-                pll_writel_base(val, pll);
-        }
-
-        /* disable lock override */
-
-        val = pll_readl_misc(pll);
-        val &= ~BIT(29);
-        pll_writel_misc(val, pll);
-
         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
-                                      &tegra_clk_pllre_ops);
+                                      &tegra_clk_pll_ops);
         if (IS_ERR(clk))
                 kfree(pll);
 
@@ -2604,46 +2591,6 @@ struct clk *tegra_clk_register_pllc_tegra210(const char *name,
         return clk;
 }
 
-struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
-                        const char *parent_name, void __iomem *clk_base,
-                        void __iomem *pmc, unsigned long flags,
-                        struct tegra_clk_pll_params *pll_params,
-                        spinlock_t *lock)
-{
-        struct tegra_clk_pll *pll;
-        struct clk *clk, *parent;
-        unsigned long parent_rate;
-
-        parent = __clk_lookup(parent_name);
-        if (!parent) {
-                WARN(1, "parent clk %s of %s must be registered first\n",
-                        name, parent_name);
-                return ERR_PTR(-EINVAL);
-        }
-
-        if (!pll_params->pdiv_tohw)
-                return ERR_PTR(-EINVAL);
-
-        parent_rate = clk_get_rate(parent);
-
-        pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
-
-        if (pll_params->adjust_vco)
-                pll_params->vco_min = pll_params->adjust_vco(pll_params,
-                                                             parent_rate);
-
-        pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
-        if (IS_ERR(pll))
-                return ERR_CAST(pll);
-
-        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
-                                      &tegra_clk_pll_ops);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
-}
-
 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
                                 const char *parent_name, void __iomem *clk_base,
                                 unsigned long flags,
@@ -2652,10 +2599,8 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name,
 {
         struct tegra_clk_pll *pll;
         struct clk *clk, *parent;
-        struct tegra_clk_pll_freq_table cfg;
         unsigned long parent_rate;
         u32 val;
-        int i;
 
         if (!pll_params->div_nmp)
                 return ERR_PTR(-EINVAL);
@@ -2667,13 +2612,11 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name,
                 return ERR_PTR(-EINVAL);
         }
 
-        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
-        if (IS_ERR(pll))
-                return ERR_CAST(pll);
-
-        val = pll_readl_base(pll);
-        val &= ~PLLSS_REF_SRC_SEL_MASK;
-        pll_writel_base(val, pll);
+        val = readl_relaxed(clk_base + pll_params->base_reg);
+        if (val & PLLSS_REF_SRC_SEL_MASK) {
+                WARN(1, "not supported reference clock for %s\n", name);
+                return ERR_PTR(-EINVAL);
+        }
 
         parent_rate = clk_get_rate(parent);
 
@@ -2683,36 +2626,10 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name,
                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
                                                              parent_rate);
 
-        /* initialize PLL to minimum rate */
-
-        cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
-        cfg.n = cfg.m * pll_params->vco_min / parent_rate;
-
-        for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
-                ;
-        if (!i) {
-                kfree(pll);
-                return ERR_PTR(-EINVAL);
-        }
-
-        cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
-
-        _update_pll_mnp(pll, &cfg);
-
-        pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
-
-        val = pll_readl_base(pll);
-        if (val & PLL_BASE_ENABLE) {
-                if (val & BIT(pll_params->iddq_bit_idx)) {
-                        WARN(1, "%s is on but IDDQ set\n", name);
-                        kfree(pll);
-                        return ERR_PTR(-EINVAL);
-                }
-        } else
-                val |= BIT(pll_params->iddq_bit_idx);
-
-        val &= ~PLLSS_LOCK_OVERRIDE;
-        pll_writel_base(val, pll);
+        pll_params->flags |= TEGRA_PLL_BYPASS;
+        pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
 
         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
                                         &tegra_clk_pll_ops);
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 294bfe40a4f5..848255cc0209 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -216,7 +216,8 @@
                              _clk_num, _clk_id)                 \
         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
                         30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
-                        _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
+                        _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
+                        _parents##_idx, 0, NULL)
 
 #define XUSB(_name, _parents, _offset, \
                              _clk_num, _gate_flags, _clk_id)     \
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 474de0f0c26d..4f6fd307cb70 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -232,8 +232,15 @@ static void __init tegra_super_clk_init(void __iomem *clk_base,
         if (!dt_clk)
                 return;
 
-        clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
-                        pmc_base, CLK_IGNORE_UNUSED, params, NULL);
+#if defined(CONFIG_ARCH_TEGRA_210_SOC)
+        if (gen_info->gen == gen5)
+                clk = tegra_clk_register_pllc_tegra210("pll_x", "pll_ref",
+                        clk_base, pmc_base, CLK_IGNORE_UNUSED, params, NULL);
+        else
+#endif
+                clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
+                                pmc_base, CLK_IGNORE_UNUSED, params, NULL);
+
         *dt_clk = clk;
 
         /* PLLX_OUT0 */
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 1024e853ea65..6d7a613f2656 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -146,7 +146,7 @@
 #define PLLD_SDM_EN_MASK BIT(16)
 
 #define PLLD2_SDM_EN_MASK BIT(31)
-#define PLLD2_SSC_EN_MASK BIT(30)
+#define PLLD2_SSC_EN_MASK 0
 
 #define PLLDP_SS_CFG    0x598
 #define PLLDP_SDM_EN_MASK BIT(31)
@@ -241,6 +241,9 @@
 #define PLL_SDM_COEFF BIT(13)
 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
+/* This macro returns ndiv effective scaled to SDM range */
+#define sdin_get_n_eff(cfg)     ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
+                (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
 
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
@@ -715,8 +718,6 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
         plldss->params->defaults_set = true;
 
         if (val & PLL_ENABLE) {
-                pr_warn("%s already enabled. Postponing set full defaults\n",
-                         pll_name);
 
                 /*
                  * PLL is ON: check if defaults already set, then set those
@@ -755,6 +756,10 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
                                 (~PLLDSS_MISC1_CFG_EN_SDM));
                 }
 
+                if (!plldss->params->defaults_set)
+                        pr_warn("%s already enabled. Postponing set full defaults\n",
+                                 pll_name);
+
                 /* Enable lock detect */
                 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
                         val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
@@ -1288,8 +1293,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
                         s -= PLL_SDM_COEFF / 2;
                         cfg->sdm_data = sdin_din_to_data(s);
                 }
-                cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
-                                        sdin_data_to_din(cfg->sdm_data);
+                cfg->output_rate *= sdin_get_n_eff(cfg);
                 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
         } else {
                 cfg->output_rate *= cfg->n;
@@ -1314,8 +1318,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
  */
 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
 {
-        cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
-                        sdin_data_to_din(cfg->sdm_data);
+        cfg->n = sdin_get_n_eff(cfg);
         cfg->m *= PLL_SDM_COEFF;
 }
 
@@ -2204,7 +2207,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
         [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
         [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
         [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
-        [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true },
         [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
         [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
         [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
@@ -2470,15 +2472,14 @@ static void tegra210_utmi_param_configure(void)
         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
 
         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
-
         reg |=
         UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
 
         /* Program UTMIP PLL delay and oscillator frequency counts */
         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
-        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
 
+        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
         reg |=
         UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
 
@@ -2494,7 +2495,8 @@ static void tegra210_utmi_param_configure(void)
         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
         reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
-        udelay(1);
+
+        udelay(20);
 
         /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
@@ -2552,6 +2554,7 @@ static int tegra210_enable_pllu(void)
         reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
         reg &= ~BIT(pllu.params->iddq_bit_idx);
         writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
+        udelay(5);
 
         reg = readl_relaxed(clk_base + PLLU_BASE);
         reg &= ~GENMASK(20, 0);
@@ -2559,6 +2562,7 @@ static int tegra210_enable_pllu(void)
         reg |= fentry->n << 8;
         reg |= fentry->p << 16;
         writel(reg, clk_base + PLLU_BASE);
+        udelay(1);
         reg |= PLL_ENABLE;
         writel(reg, clk_base + PLLU_BASE);
 
@@ -2699,7 +2703,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
         struct clk *clk;
 
         /* PLLC */
-        clk = tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base,
+        clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
                         pmc, 0, &pll_c_params, NULL);
         if (!WARN_ON(IS_ERR(clk)))
                 clk_register_clkdev(clk, "pll_c", NULL);
@@ -2798,14 +2802,14 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
         /* PLLU_60M */
         clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
-                                23, 0, NULL);
+                                23, 0, &pll_u_lock);
         clk_register_clkdev(clk, "pll_u_60M", NULL);
         clks[TEGRA210_CLK_PLL_U_60M] = clk;
 
         /* PLLU_48M */
         clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
-                                25, 0, NULL);
+                                25, 0, &pll_u_lock);
         clk_register_clkdev(clk, "pll_u_48M", NULL);
         clks[TEGRA210_CLK_PLL_U_48M] = clk;
 
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 945b07093afa..872f1189ad7f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -362,12 +362,6 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
                             struct tegra_clk_pll_params *pll_params,
                             spinlock_t *lock);
 
-struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
-                        const char *parent_name, void __iomem *clk_base,
-                        void __iomem *pmc, unsigned long flags,
-                        struct tegra_clk_pll_params *pll_params,
-                        spinlock_t *lock);
-
 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
                            void __iomem *clk_base, void __iomem *pmc,
                            unsigned long flags,
diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c
index 255cafb18336..d6036c788fab 100644
--- a/drivers/clk/ti/adpll.c
+++ b/drivers/clk/ti/adpll.c
@@ -222,7 +222,7 @@ static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
 
         /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
         postfix = strrchr(name, '.');
-        if (strlen(postfix) > 1) {
+        if (postfix && strlen(postfix) > 1) {
                 if (strlen(postfix) > ADPLL_MAX_CON_ID)
                         dev_warn(d->dev, "clock %s con_id lookup may fail\n",
                                  name);
@@ -486,7 +486,7 @@ static u8 ti_adpll_get_parent(struct clk_hw *hw)
         return 0;
 }
 
-static struct clk_ops ti_adpll_ops = {
+static const struct clk_ops ti_adpll_ops = {
         .prepare = ti_adpll_prepare,
         .unprepare = ti_adpll_unprepare,
         .is_prepared = ti_adpll_is_prepared,
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 06f486b3488c..83b148f8037c 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -304,7 +304,7 @@ static void omap2_apll_disable(struct clk_hw *hw)
         ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
 }
 
-static struct clk_ops omap2_apll_ops = {
+static const struct clk_ops omap2_apll_ops = {
         .enable         = &omap2_apll_enable,
         .disable        = &omap2_apll_disable,
         .is_enabled     = &omap2_apll_is_enabled,
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index fbedc6a9fed0..07a805125e98 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -138,8 +138,8 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
         for (i = 0; i < num_clks; i++) {
                 clk = of_clk_get(node, i);
                 if (IS_ERR(clk)) {
-                        pr_err("%s: Failed get %s' clock nr %d (%ld)\n",
-                               __func__, node->full_name, i, PTR_ERR(clk));
+                        pr_err("%s: Failed get %pOF' clock nr %d (%ld)\n",
+                               __func__, node, i, PTR_ERR(clk));
                         continue;
                 }
                 clk_hw = __clk_get_hw(clk);
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 66a0d0ed8b55..071af44b1ba8 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -268,7 +268,7 @@ static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
-static struct clk_ops ti_fapll_ops = {
+static const struct clk_ops ti_fapll_ops = {
         .enable = ti_fapll_enable,
         .disable = ti_fapll_disable,
         .is_enabled = ti_fapll_is_enabled,
@@ -478,7 +478,7 @@ static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
-static struct clk_ops ti_fapll_synt_ops = {
+static const struct clk_ops ti_fapll_synt_ops = {
         .enable = ti_fapll_synth_enable,
         .disable = ti_fapll_synth_disable,
         .is_enabled = ti_fapll_synth_is_enabled,
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 2cf386347f0c..e09f3dd46318 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -111,10 +111,6 @@ static int uniphier_clk_remove(struct platform_device *pdev)
 static const struct of_device_id uniphier_clk_match[] = {
         /* System clock */
         {
-                .compatible = "socionext,uniphier-sld3-clock",
-                .data = uniphier_sld3_sys_clk_data,
-        },
-        {
                 .compatible = "socionext,uniphier-ld4-clock",
                 .data = uniphier_ld4_sys_clk_data,
         },
@@ -142,22 +138,22 @@ static const struct of_device_id uniphier_clk_match[] = {
                 .compatible = "socionext,uniphier-ld20-clock",
                 .data = uniphier_ld20_sys_clk_data,
         },
-        /* Media I/O clock, SD clock */
         {
-                .compatible = "socionext,uniphier-sld3-mio-clock",
-                .data = uniphier_sld3_mio_clk_data,
+                .compatible = "socionext,uniphier-pxs3-clock",
+                .data = uniphier_pxs3_sys_clk_data,
         },
+        /* Media I/O clock, SD clock */
         {
                 .compatible = "socionext,uniphier-ld4-mio-clock",
-                .data = uniphier_sld3_mio_clk_data,
+                .data = uniphier_ld4_mio_clk_data,
         },
         {
                 .compatible = "socionext,uniphier-pro4-mio-clock",
-                .data = uniphier_sld3_mio_clk_data,
+                .data = uniphier_ld4_mio_clk_data,
         },
         {
                 .compatible = "socionext,uniphier-sld8-mio-clock",
-                .data = uniphier_sld3_mio_clk_data,
+                .data = uniphier_ld4_mio_clk_data,
         },
         {
                 .compatible = "socionext,uniphier-pro5-sd-clock",
@@ -169,12 +165,16 @@ static const struct of_device_id uniphier_clk_match[] = {
         },
         {
                 .compatible = "socionext,uniphier-ld11-mio-clock",
-                .data = uniphier_sld3_mio_clk_data,
+                .data = uniphier_ld4_mio_clk_data,
         },
         {
                 .compatible = "socionext,uniphier-ld20-sd-clock",
                 .data = uniphier_pro5_sd_clk_data,
         },
+        {
+                .compatible = "socionext,uniphier-pxs3-sd-clock",
+                .data = uniphier_pro5_sd_clk_data,
+        },
         /* Peripheral clock */
         {
                 .compatible = "socionext,uniphier-ld4-peri-clock",
@@ -204,6 +204,10 @@ static const struct of_device_id uniphier_clk_match[] = {
                 .compatible = "socionext,uniphier-ld20-peri-clock",
                 .data = uniphier_pro4_peri_clk_data,
         },
+        {
+                .compatible = "socionext,uniphier-pxs3-peri-clock",
+                .data = uniphier_pro4_peri_clk_data,
+        },
         { /* sentinel */ }
 };
 
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 218d20f099ce..16e4d303f535 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -76,7 +76,7 @@
 #define UNIPHIER_MIO_CLK_DMAC(idx)                                      \
         UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
 
-const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
+const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
         UNIPHIER_MIO_CLK_SD_FIXED,
         UNIPHIER_MIO_CLK_SD(0, 0),
         UNIPHIER_MIO_CLK_SD(1, 1),
@@ -85,11 +85,9 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
         UNIPHIER_MIO_CLK_USB2(8, 0),
         UNIPHIER_MIO_CLK_USB2(9, 1),
         UNIPHIER_MIO_CLK_USB2(10, 2),
-        UNIPHIER_MIO_CLK_USB2(11, 3),
         UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
         UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
         UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
-        UNIPHIER_MIO_CLK_USB2_PHY(15, 3),
         { /* sentinel */ }
 };
 
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ad0218182a9f..0e396f3da526 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -17,7 +17,7 @@
 
 #include "clk-uniphier.h"
 
-#define UNIPHIER_SLD3_SYS_CLK_SD                                        \
+#define UNIPHIER_LD4_SYS_CLK_SD                                 \
         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8),               \
         UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
 
@@ -30,7 +30,7 @@
         UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
 
 /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
-#define UNIPHIER_SLD3_SYS_CLK_NAND(idx)                                 \
+#define UNIPHIER_LD4_SYS_CLK_NAND(idx)                                  \
         UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8),             \
         UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
 
@@ -45,7 +45,7 @@
 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx)                                 \
         UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
 
-#define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx)                               \
+#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx)                                \
         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
 
 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                               \
@@ -57,19 +57,23 @@
 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)                             \
         UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
 
-const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
-        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
-        UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),      /* 288 MHz */
-        UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),         /* 589.824 MHz */
-        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
-        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
-        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
-        UNIPHIER_SLD3_SYS_CLK_NAND(2),
-        UNIPHIER_SLD3_SYS_CLK_SD,
-        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
-        { /* sentinel */ }
-};
+#define UNIPHIER_LD11_SYS_CLK_AIO(idx)                                  \
+        UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10),           \
+        UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
+
+#define UNIPHIER_LD11_SYS_CLK_EVEA(idx)                                 \
+        UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),          \
+        UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
+
+#define UNIPHIER_LD11_SYS_CLK_EXIV(idx)                                 \
+        UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10),          \
+        UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
+
+#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx)                                \
+        UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
+
+#define UNIPHIER_LD11_SYS_CLK_ETHER(idx)                                \
+        UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
 
 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
@@ -78,10 +82,10 @@ const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
-        UNIPHIER_SLD3_SYS_CLK_NAND(2),
-        UNIPHIER_SLD3_SYS_CLK_SD,
+        UNIPHIER_LD4_SYS_CLK_NAND(2),
+        UNIPHIER_LD4_SYS_CLK_SD,
         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* Ether, HSC, MIO */
+        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
         { /* sentinel */ }
 };
 
@@ -92,10 +96,11 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
-        UNIPHIER_SLD3_SYS_CLK_NAND(2),
-        UNIPHIER_SLD3_SYS_CLK_SD,
+        UNIPHIER_LD4_SYS_CLK_NAND(2),
+        UNIPHIER_LD4_SYS_CLK_SD,
         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* HSC, MIO, RLE */
+        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
+        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* HSC, MIO, RLE */
         UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
@@ -108,10 +113,10 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
-        UNIPHIER_SLD3_SYS_CLK_NAND(2),
-        UNIPHIER_SLD3_SYS_CLK_SD,
+        UNIPHIER_LD4_SYS_CLK_NAND(2),
+        UNIPHIER_LD4_SYS_CLK_SD,
         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* Ether, HSC, MIO */
+        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
         { /* sentinel */ }
 };
 
@@ -123,7 +128,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
         UNIPHIER_PRO5_SYS_CLK_NAND(2),
         UNIPHIER_PRO5_SYS_CLK_SD,
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                        /* HSC */
+        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC */
         UNIPHIER_PRO4_SYS_CLK_GIO(12),                          /* PCIe, USB3 */
         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
@@ -136,7 +141,8 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
         UNIPHIER_PRO5_SYS_CLK_NAND(2),
         UNIPHIER_PRO5_SYS_CLK_SD,
-        UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                        /* HSC, RLE */
+        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
+        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC, RLE */
         /* GIO is always clock-enabled: no function for 0x2104 bit6 */
         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
@@ -156,8 +162,12 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
         UNIPHIER_LD11_SYS_CLK_NAND(2),
         UNIPHIER_LD11_SYS_CLK_EMMC(4),
         /* Index 5 reserved for eMMC PHY */
+        UNIPHIER_LD11_SYS_CLK_ETHER(6),
         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
         UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
+        UNIPHIER_LD11_SYS_CLK_AIO(40),
+        UNIPHIER_LD11_SYS_CLK_EVEA(41),
+        UNIPHIER_LD11_SYS_CLK_EXIV(42),
         /* CPU gears */
         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
         UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -185,6 +195,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
         UNIPHIER_LD11_SYS_CLK_EMMC(4),
         /* Index 5 reserved for eMMC PHY */
         UNIPHIER_LD20_SYS_CLK_SD,
+        UNIPHIER_LD11_SYS_CLK_ETHER(6),
         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
         /* GIO is always clock-enabled: no function for 0x210c bit5 */
         /*
@@ -194,6 +205,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
         UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
         UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
         UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+        UNIPHIER_LD11_SYS_CLK_AIO(40),
+        UNIPHIER_LD11_SYS_CLK_EVEA(41),
+        UNIPHIER_LD11_SYS_CLK_EXIV(42),
         /* CPU gears */
         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
         UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
@@ -209,3 +223,33 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
                              "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
         { /* sentinel */ }
 };
+
+const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
+        UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1),         /* ARM: 2600 MHz */
+        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
+        UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2400 MHz */
+        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
+        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+        UNIPHIER_LD20_SYS_CLK_SD,
+        UNIPHIER_LD11_SYS_CLK_NAND(2),
+        UNIPHIER_LD11_SYS_CLK_EMMC(4),
+        UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x2104, 4),        /* =GIO0 */
+        UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x2104, 5),      /* =GIO1 */
+        UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x2104, 6),      /* =GIO1-1 */
+        UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
+        UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
+        UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
+        UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
+        UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
+        /* CPU gears */
+        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
+        UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
+        UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
+        UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
+                             "cpll/2", "spll/2", "cpll/3", "spll/3",
+                             "spll/4", "spll/8", "cpll/4", "cpll/8"),
+        UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
+                             "s2pll/2", "spll/2", "s2pll/3", "spll/3",
+                             "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
+        { /* sentinel */ }
+};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 01c16ecec48f..d10a009ada96 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -147,7 +147,6 @@ struct clk_hw *uniphier_clk_register_mux(struct device *dev,
                                          const char *name,
                                 const struct uniphier_clk_mux_data *data);
 
-extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
@@ -155,7 +154,8 @@ extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
-extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
+extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
 extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
 extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
index 0e950769ed03..f50592775c9d 100644
--- a/drivers/clk/ux500/clk-prcc.c
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -79,13 +79,13 @@ static int clk_prcc_is_enabled(struct clk_hw *hw)
         return clk->is_enabled;
 }
 
-static struct clk_ops clk_prcc_pclk_ops = {
+static const struct clk_ops clk_prcc_pclk_ops = {
         .enable = clk_prcc_pclk_enable,
         .disable = clk_prcc_pclk_disable,
         .is_enabled = clk_prcc_is_enabled,
 };
 
-static struct clk_ops clk_prcc_kclk_ops = {
+static const struct clk_ops clk_prcc_kclk_ops = {
         .enable = clk_prcc_kclk_enable,
         .disable = clk_prcc_kclk_disable,
         .is_enabled = clk_prcc_is_enabled,
@@ -96,7 +96,7 @@ static struct clk *clk_reg_prcc(const char *name,
                                 resource_size_t phy_base,
                                 u32 cg_sel,
                                 unsigned long flags,
-                                struct clk_ops *clk_prcc_ops)
+                                const struct clk_ops *clk_prcc_ops)
 {
         struct clk_prcc *clk;
         struct clk_init_data clk_prcc_init;
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 7f343821f4e4..6e3e16b2e5ca 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -186,7 +186,7 @@ static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
         clk->is_prepared = 0;
 }
 
-static struct clk_ops clk_prcmu_scalable_ops = {
+static const struct clk_ops clk_prcmu_scalable_ops = {
         .prepare = clk_prcmu_prepare,
         .unprepare = clk_prcmu_unprepare,
         .is_prepared = clk_prcmu_is_prepared,
@@ -198,7 +198,7 @@ static struct clk_ops clk_prcmu_scalable_ops = {
         .set_rate = clk_prcmu_set_rate,
 };
 
-static struct clk_ops clk_prcmu_gate_ops = {
+static const struct clk_ops clk_prcmu_gate_ops = {
         .prepare = clk_prcmu_prepare,
         .unprepare = clk_prcmu_unprepare,
         .is_prepared = clk_prcmu_is_prepared,
@@ -208,19 +208,19 @@ static struct clk_ops clk_prcmu_gate_ops = {
         .recalc_rate = clk_prcmu_recalc_rate,
 };
 
-static struct clk_ops clk_prcmu_scalable_rate_ops = {
+static const struct clk_ops clk_prcmu_scalable_rate_ops = {
         .is_enabled = clk_prcmu_is_enabled,
         .recalc_rate = clk_prcmu_recalc_rate,
         .round_rate = clk_prcmu_round_rate,
         .set_rate = clk_prcmu_set_rate,
 };
 
-static struct clk_ops clk_prcmu_rate_ops = {
+static const struct clk_ops clk_prcmu_rate_ops = {
         .is_enabled = clk_prcmu_is_enabled,
         .recalc_rate = clk_prcmu_recalc_rate,
 };
 
-static struct clk_ops clk_prcmu_opp_gate_ops = {
+static const struct clk_ops clk_prcmu_opp_gate_ops = {
         .prepare = clk_prcmu_opp_prepare,
         .unprepare = clk_prcmu_opp_unprepare,
         .is_prepared = clk_prcmu_is_prepared,
@@ -230,7 +230,7 @@ static struct clk_ops clk_prcmu_opp_gate_ops = {
         .recalc_rate = clk_prcmu_recalc_rate,
 };
 
-static struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
+static const struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
         .prepare = clk_prcmu_opp_volt_prepare,
         .unprepare = clk_prcmu_opp_volt_unprepare,
         .is_prepared = clk_prcmu_is_prepared,
@@ -247,7 +247,7 @@ static struct clk *clk_reg_prcmu(const char *name,
                                  u8 cg_sel,
                                  unsigned long rate,
                                  unsigned long flags,
-                                 struct clk_ops *clk_prcmu_ops)
+                                 const struct clk_ops *clk_prcmu_ops)
 {
         struct clk_prcmu *clk;
         struct clk_init_data clk_prcmu_init;
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index 266ddea630d2..8a4e93ce1e42 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -98,18 +98,18 @@ static u8 clk_sysctrl_get_parent(struct clk_hw *hw)
         return clk->parent_index;
 }
 
-static struct clk_ops clk_sysctrl_gate_ops = {
+static const struct clk_ops clk_sysctrl_gate_ops = {
         .prepare = clk_sysctrl_prepare,
         .unprepare = clk_sysctrl_unprepare,
 };
 
-static struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
+static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
         .prepare = clk_sysctrl_prepare,
         .unprepare = clk_sysctrl_unprepare,
         .recalc_rate = clk_sysctrl_recalc_rate,
 };
 
-static struct clk_ops clk_sysctrl_set_parent_ops = {
+static const struct clk_ops clk_sysctrl_set_parent_ops = {
         .set_parent = clk_sysctrl_set_parent,
         .get_parent = clk_sysctrl_get_parent,
 };
@@ -124,7 +124,7 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
                                 unsigned long rate,
                                 unsigned long enable_delay_us,
                                 unsigned long flags,
-                                struct clk_ops *clk_sysctrl_ops)
+                                const struct clk_ops *clk_sysctrl_ops)
 {
         struct clk_sysctrl *clk;
         struct clk_init_data clk_sysctrl_init;
diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c
index 7e5add7d7752..e7a868b83fe5 100644
--- a/drivers/clk/versatile/clk-vexpress-osc.c
+++ b/drivers/clk/versatile/clk-vexpress-osc.c
@@ -61,7 +61,7 @@ static int vexpress_osc_set_rate(struct clk_hw *hw, unsigned long rate,
         return regmap_write(osc->reg, 0, rate);
 }
 
-static struct clk_ops vexpress_osc_ops = {
+static const struct clk_ops vexpress_osc_ops = {
         .recalc_rate = vexpress_osc_recalc_rate,
         .round_rate = vexpress_osc_round_rate,
         .set_rate = vexpress_osc_set_rate,
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index 27f853d4c76b..354dd508c516 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -451,7 +451,7 @@ static struct zx_clk_fixed_factor top_ffactor_clk[] = {
         FFACTOR(0, "emmc_mux_div2",     "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
 };
 
-static struct clk_div_table noc_div_table[] = {
+static const struct clk_div_table noc_div_table[] = {
         { .val = 1, .div = 2, },
         { .val = 3, .div = 4, },
 };
@@ -644,7 +644,7 @@ static int __init top_clocks_init(struct device_node *np)
         return 0;
 }
 
-static struct clk_div_table common_even_div_table[] = {
+static const struct clk_div_table common_even_div_table[] = {
         { .val = 0, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 3, .div = 4, },
@@ -656,7 +656,7 @@ static struct clk_div_table common_even_div_table[] = {
         { .val = 15, .div = 16, },
 };
 
-static struct clk_div_table common_div_table[] = {
+static const struct clk_div_table common_div_table[] = {
         { .val = 0, .div = 1, },
         { .val = 1, .div = 2, },
         { .val = 2, .div = 3, },
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 1f5c42254798..75b07cf5eed0 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -233,6 +233,8 @@
 #define GCC_PCIE_CLKREF_CLK                                     216
 #define GCC_RX2_USB2_CLKREF_CLK                                 217
 #define GCC_RX1_USB2_CLKREF_CLK                                 218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK                      219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK                      220
 
 #define GCC_SYSTEM_NOC_BCR                                      0
 #define GCC_CONFIG_NOC_BCR                                      1
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 000000000000..4e8ae3dee590
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2                 0
+#define R8A77995_CLK_ZG                 1
+#define R8A77995_CLK_ZTR                2
+#define R8A77995_CLK_ZT                 3
+#define R8A77995_CLK_ZX                 4
+#define R8A77995_CLK_S0D1               5
+#define R8A77995_CLK_S1D1               6
+#define R8A77995_CLK_S1D2               7
+#define R8A77995_CLK_S1D4               8
+#define R8A77995_CLK_S2D1               9
+#define R8A77995_CLK_S2D2               10
+#define R8A77995_CLK_S2D4               11
+#define R8A77995_CLK_S3D1               12
+#define R8A77995_CLK_S3D2               13
+#define R8A77995_CLK_S3D4               14
+#define R8A77995_CLK_S1D4C              15
+#define R8A77995_CLK_S3D1C              16
+#define R8A77995_CLK_S3D2C              17
+#define R8A77995_CLK_S3D4C              18
+#define R8A77995_CLK_LB                 19
+#define R8A77995_CLK_CL                 20
+#define R8A77995_CLK_ZB3                21
+#define R8A77995_CLK_ZB3D2              22
+#define R8A77995_CLK_CR                 23
+#define R8A77995_CLK_CRD2               24
+#define R8A77995_CLK_SD0H               25
+#define R8A77995_CLK_SD0                26
+#define R8A77995_CLK_SSP2               27
+#define R8A77995_CLK_SSP1               28
+#define R8A77995_CLK_RPC                29
+#define R8A77995_CLK_RPCD2              30
+#define R8A77995_CLK_ZA2                31
+#define R8A77995_CLK_ZA8                32
+#define R8A77995_CLK_Z2D                33
+#define R8A77995_CLK_CANFD              34
+#define R8A77995_CLK_MSO                35
+#define R8A77995_CLK_R                  36
+#define R8A77995_CLK_OSC                37
+#define R8A77995_CLK_LV0                38
+#define R8A77995_CLK_LV1                39
+#define R8A77995_CLK_CP                 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 56f841c22801..55655ab0a4c4 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -49,6 +49,7 @@
 #define SCLK_EMMC_DRV           117
 #define SCLK_SDMMC_SAMPLE       118
 #define SCLK_SDIO_SAMPLE        119
+#define SCLK_SDIO_SRC           120
 #define SCLK_EMMC_SAMPLE        121
 #define SCLK_VOP                122
 #define SCLK_HDMI_HDCP          123
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index f269d833e41a..d8d0e0456dc2 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -67,9 +67,9 @@
 #define SCLK_SPI                        108
 #define SCLK_SARADC                     109
 #define SCLK_TSADC                      110
-#define SCLK_MACPHY_PRE                 111
-#define SCLK_MACPHY                     112
-#define SCLK_MACPHY_RX                  113
+#define SCLK_MAC_PRE                    111
+#define SCLK_MAC                        112
+#define SCLK_MAC_RX                     113
 #define SCLK_MAC_REF                    114
 #define SCLK_MAC_REFOUT                 115
 #define SCLK_DSP_PFM                    116
@@ -110,6 +110,7 @@
 #define ACLK_CIF2                       207
 #define ACLK_CIF3                       208
 #define ACLK_PERI                       209
+#define ACLK_GMAC                       210
 
 /* pclk gates */
 #define PCLK_GPIO1                      256
@@ -141,6 +142,7 @@
 #define PCLK_EFUSE0                     282
 #define PCLK_EFUSE1                     283
 #define PCLK_WDT                        284
+#define PCLK_GMAC                       285
 
 /* hclk gates */
 #define HCLK_I2S0_8CH                   320
diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 000000000000..6637272b3242
--- /dev/null
+++ b/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,165 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 000000000000..c5a53f38d654
--- /dev/null
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC                1
+#define CLK_CPU                 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG             26
+#define CLK_AHB_EHCI0           27
+#define CLK_AHB_OHCI0           28
+#define CLK_AHB_EHCI1           29
+#define CLK_AHB_OHCI1           30
+#define CLK_AHB_SS              31
+#define CLK_AHB_DMA             32
+#define CLK_AHB_BIST            33
+#define CLK_AHB_MMC0            34
+#define CLK_AHB_MMC1            35
+#define CLK_AHB_MMC2            36
+#define CLK_AHB_MMC3            37
+#define CLK_AHB_MS              38
+#define CLK_AHB_NAND            39
+#define CLK_AHB_SDRAM           40
+#define CLK_AHB_ACE             41
+#define CLK_AHB_EMAC            42
+#define CLK_AHB_TS              43
+#define CLK_AHB_SPI0            44
+#define CLK_AHB_SPI1            45
+#define CLK_AHB_SPI2            46
+#define CLK_AHB_SPI3            47
+#define CLK_AHB_PATA            48
+#define CLK_AHB_SATA            49
+#define CLK_AHB_GPS             50
+#define CLK_AHB_HSTIMER         51
+#define CLK_AHB_VE              52
+#define CLK_AHB_TVD             53
+#define CLK_AHB_TVE0            54
+#define CLK_AHB_TVE1            55
+#define CLK_AHB_LCD0            56
+#define CLK_AHB_LCD1            57
+#define CLK_AHB_CSI0            58
+#define CLK_AHB_CSI1            59
+#define CLK_AHB_HDMI0           60
+#define CLK_AHB_HDMI1           61
+#define CLK_AHB_DE_BE0          62
+#define CLK_AHB_DE_BE1          63
+#define CLK_AHB_DE_FE0          64
+#define CLK_AHB_DE_FE1          65
+#define CLK_AHB_GMAC            66
+#define CLK_AHB_MP              67
+#define CLK_AHB_GPU             68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC          69
+#define CLK_APB0_SPDIF          70
+#define CLK_APB0_I2S0           71
+#define CLK_APB0_AC97           72
+#define CLK_APB0_I2S1           73
+#define CLK_APB0_PIO            74
+#define CLK_APB0_IR0            75
+#define CLK_APB0_IR1            76
+#define CLK_APB0_I2S2           77
+#define CLK_APB0_KEYPAD         78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0           79
+#define CLK_APB1_I2C1           80
+#define CLK_APB1_I2C2           81
+#define CLK_APB1_I2C3           82
+#define CLK_APB1_CAN            83
+#define CLK_APB1_SCR            84
+#define CLK_APB1_PS20           85
+#define CLK_APB1_PS21           86
+#define CLK_APB1_I2C4           87
+#define CLK_APB1_UART0          88
+#define CLK_APB1_UART1          89
+#define CLK_APB1_UART2          90
+#define CLK_APB1_UART3          91
+#define CLK_APB1_UART4          92
+#define CLK_APB1_UART5          93
+#define CLK_APB1_UART6          94
+#define CLK_APB1_UART7          95
+
+/* IP clocks */
+#define CLK_NAND                96
+#define CLK_MS                  97
+#define CLK_MMC0                98
+#define CLK_MMC0_OUTPUT         99
+#define CLK_MMC0_SAMPLE         100
+#define CLK_MMC1                101
+#define CLK_MMC1_OUTPUT         102
+#define CLK_MMC1_SAMPLE         103
+#define CLK_MMC2                104
+#define CLK_MMC2_OUTPUT         105
+#define CLK_MMC2_SAMPLE         106
+#define CLK_MMC3                107
+#define CLK_MMC3_OUTPUT         108
+#define CLK_MMC3_SAMPLE         109
+#define CLK_TS                  110
+#define CLK_SS                  111
+#define CLK_SPI0                112
+#define CLK_SPI1                113
+#define CLK_SPI2                114
+#define CLK_PATA                115
+#define CLK_IR0                 116
+#define CLK_IR1                 117
+#define CLK_I2S0                118
+#define CLK_AC97                119
+#define CLK_SPDIF               120
+#define CLK_KEYPAD              121
+#define CLK_SATA                122
+#define CLK_USB_OHCI0           123
+#define CLK_USB_OHCI1           124
+#define CLK_USB_PHY             125
+#define CLK_GPS                 126
+#define CLK_SPI3                127
+#define CLK_I2S1                128
+#define CLK_I2S2                129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE             130
+#define CLK_DRAM_CSI0           131
+#define CLK_DRAM_CSI1           132
+#define CLK_DRAM_TS             133
+#define CLK_DRAM_TVD            134
+#define CLK_DRAM_TVE0           135
+#define CLK_DRAM_TVE1           136
+#define CLK_DRAM_OUT            137
+#define CLK_DRAM_DE_FE1         138
+#define CLK_DRAM_DE_FE0         139
+#define CLK_DRAM_DE_BE0         140
+#define CLK_DRAM_DE_BE1         141
+#define CLK_DRAM_MP             142
+#define CLK_DRAM_ACE            143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0              144
+#define CLK_DE_BE1              145
+#define CLK_DE_FE0              146
+#define CLK_DE_FE1              147
+#define CLK_DE_MP               148
+#define CLK_TCON0_CH0           149
+#define CLK_TCON1_CH0           150
+#define CLK_CSI_SCLK            151
+#define CLK_TVD_SCLK2           152
+#define CLK_TVD                 153
+#define CLK_TCON0_CH1_SCLK2     154
+#define CLK_TCON0_CH1           155
+#define CLK_TCON1_CH1_SCLK2     156
+#define CLK_TCON1_CH1           157
+#define CLK_CSI0                158
+#define CLK_CSI1                159
+#define CLK_CODEC               160
+#define CLK_VE                  161
+#define CLK_AVS                 162
+#define CLK_ACE                 163
+#define CLK_HDMI                164
+#define CLK_GPU                 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 000000000000..045a5178da0c
--- /dev/null
+++ b/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS                166
+#define CLK_HDMI1_SLOW          167
+#define CLK_HDMI1               168
+#define CLK_OUT_A               169
+#define CLK_OUT_B               170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 000000000000..4fa5f69fc297
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU                 24
+
+#define CLK_BUS_MIPI_DSI        29
+#define CLK_BUS_CE              30
+#define CLK_BUS_DMA             31
+#define CLK_BUS_MMC0            32
+#define CLK_BUS_MMC1            33
+#define CLK_BUS_MMC2            34
+#define CLK_BUS_MMC3            35
+#define CLK_BUS_NAND            36
+#define CLK_BUS_DRAM            37
+#define CLK_BUS_EMAC            38
+#define CLK_BUS_TS              39
+#define CLK_BUS_HSTIMER         40
+#define CLK_BUS_SPI0            41
+#define CLK_BUS_SPI1            42
+#define CLK_BUS_SPI2            43
+#define CLK_BUS_SPI3            44
+#define CLK_BUS_SATA            45
+#define CLK_BUS_OTG             46
+#define CLK_BUS_EHCI0           47
+#define CLK_BUS_EHCI1           48
+#define CLK_BUS_EHCI2           49
+#define CLK_BUS_OHCI0           50
+#define CLK_BUS_OHCI1           51
+#define CLK_BUS_OHCI2           52
+#define CLK_BUS_VE              53
+#define CLK_BUS_MP              54
+#define CLK_BUS_DEINTERLACE     55
+#define CLK_BUS_CSI0            56
+#define CLK_BUS_CSI1            57
+#define CLK_BUS_HDMI1           58
+#define CLK_BUS_HDMI0           59
+#define CLK_BUS_DE              60
+#define CLK_BUS_TVE0            61
+#define CLK_BUS_TVE1            62
+#define CLK_BUS_TVE_TOP         63
+#define CLK_BUS_GMAC            64
+#define CLK_BUS_GPU             65
+#define CLK_BUS_TVD0            66
+#define CLK_BUS_TVD1            67
+#define CLK_BUS_TVD2            68
+#define CLK_BUS_TVD3            69
+#define CLK_BUS_TVD_TOP         70
+#define CLK_BUS_TCON_LCD0       71
+#define CLK_BUS_TCON_LCD1       72
+#define CLK_BUS_TCON_TV0        73
+#define CLK_BUS_TCON_TV1        74
+#define CLK_BUS_TCON_TOP        75
+#define CLK_BUS_CODEC           76
+#define CLK_BUS_SPDIF           77
+#define CLK_BUS_AC97            78
+#define CLK_BUS_PIO             79
+#define CLK_BUS_IR0             80
+#define CLK_BUS_IR1             81
+#define CLK_BUS_THS             82
+#define CLK_BUS_KEYPAD          83
+#define CLK_BUS_I2S0            84
+#define CLK_BUS_I2S1            85
+#define CLK_BUS_I2S2            86
+#define CLK_BUS_I2C0            87
+#define CLK_BUS_I2C1            88
+#define CLK_BUS_I2C2            89
+#define CLK_BUS_I2C3            90
+#define CLK_BUS_CAN             91
+#define CLK_BUS_SCR             92
+#define CLK_BUS_PS20            93
+#define CLK_BUS_PS21            94
+#define CLK_BUS_I2C4            95
+#define CLK_BUS_UART0           96
+#define CLK_BUS_UART1           97
+#define CLK_BUS_UART2           98
+#define CLK_BUS_UART3           99
+#define CLK_BUS_UART4           100
+#define CLK_BUS_UART5           101
+#define CLK_BUS_UART6           102
+#define CLK_BUS_UART7           103
+#define CLK_BUS_DBG             104
+
+#define CLK_THS                 105
+#define CLK_NAND                106
+#define CLK_MMC0                107
+#define CLK_MMC1                108
+#define CLK_MMC2                109
+#define CLK_MMC3                110
+#define CLK_TS                  111
+#define CLK_CE                  112
+#define CLK_SPI0                113
+#define CLK_SPI1                114
+#define CLK_SPI2                115
+#define CLK_SPI3                116
+#define CLK_I2S0                117
+#define CLK_I2S1                118
+#define CLK_I2S2                119
+#define CLK_AC97                120
+#define CLK_SPDIF               121
+#define CLK_KEYPAD              122
+#define CLK_SATA                123
+#define CLK_USB_PHY0            124
+#define CLK_USB_PHY1            125
+#define CLK_USB_PHY2            126
+#define CLK_USB_OHCI0           127
+#define CLK_USB_OHCI1           128
+#define CLK_USB_OHCI2           129
+#define CLK_IR0                 130
+#define CLK_IR1                 131
+
+#define CLK_DRAM_VE             133
+#define CLK_DRAM_CSI0           134
+#define CLK_DRAM_CSI1           135
+#define CLK_DRAM_TS             136
+#define CLK_DRAM_TVD            137
+#define CLK_DRAM_MP             138
+#define CLK_DRAM_DEINTERLACE    139
+#define CLK_DE                  140
+#define CLK_MP                  141
+#define CLK_TCON_LCD0           142
+#define CLK_TCON_LCD1           143
+#define CLK_TCON_TV0            144
+#define CLK_TCON_TV1            145
+#define CLK_DEINTERLACE         146
+#define CLK_CSI1_MCLK           147
+#define CLK_CSI_SCLK            148
+#define CLK_CSI0_MCLK           149
+#define CLK_VE                  150
+#define CLK_CODEC               151
+#define CLK_AVS                 152
+#define CLK_HDMI                153
+#define CLK_HDMI_SLOW           154
+
+#define CLK_DSI_DPHY            156
+#define CLK_TVE0                157
+#define CLK_TVE1                158
+#define CLK_TVD0                159
+#define CLK_TVD1                160
+#define CLK_TVD2                161
+#define CLK_TVD3                162
+#define CLK_GPU                 163
+#define CLK_OUTA                164
+#define CLK_OUTB                165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h
new file mode 100644
index 000000000000..461a8e04453a
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32h7-rcc.h
@@ -0,0 +1,136 @@
+/*
+ * This header provides constants for the STM32H7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
+#define _DT_BINDINGS_MFD_STM32H7_RCC_H
+
+/* AHB3 */
+#define STM32H7_RCC_AHB3_MDMA           0
+#define STM32H7_RCC_AHB3_DMA2D          4
+#define STM32H7_RCC_AHB3_JPGDEC         5
+#define STM32H7_RCC_AHB3_FMC            12
+#define STM32H7_RCC_AHB3_QUADSPI        14
+#define STM32H7_RCC_AHB3_SDMMC1         16
+#define STM32H7_RCC_AHB3_CPU            31
+
+#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
+
+/* AHB1 */
+#define STM32H7_RCC_AHB1_DMA1           0
+#define STM32H7_RCC_AHB1_DMA2           1
+#define STM32H7_RCC_AHB1_ADC12          5
+#define STM32H7_RCC_AHB1_ART            14
+#define STM32H7_RCC_AHB1_ETH1MAC        15
+#define STM32H7_RCC_AHB1_USB1OTG        25
+#define STM32H7_RCC_AHB1_USB2OTG        27
+
+#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
+
+/* AHB2 */
+#define STM32H7_RCC_AHB2_CAMITF         0
+#define STM32H7_RCC_AHB2_CRYPT          4
+#define STM32H7_RCC_AHB2_HASH           5
+#define STM32H7_RCC_AHB2_RNG            6
+#define STM32H7_RCC_AHB2_SDMMC2         9
+
+#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
+
+/* AHB4 */
+#define STM32H7_RCC_AHB4_GPIOA          0
+#define STM32H7_RCC_AHB4_GPIOB          1
+#define STM32H7_RCC_AHB4_GPIOC          2
+#define STM32H7_RCC_AHB4_GPIOD          3
+#define STM32H7_RCC_AHB4_GPIOE          4
+#define STM32H7_RCC_AHB4_GPIOF          5
+#define STM32H7_RCC_AHB4_GPIOG          6
+#define STM32H7_RCC_AHB4_GPIOH          7
+#define STM32H7_RCC_AHB4_GPIOI          8
+#define STM32H7_RCC_AHB4_GPIOJ          9
+#define STM32H7_RCC_AHB4_GPIOK          10
+#define STM32H7_RCC_AHB4_CRC            19
+#define STM32H7_RCC_AHB4_BDMA           21
+#define STM32H7_RCC_AHB4_ADC3           24
+#define STM32H7_RCC_AHB4_HSEM           25
+
+#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
+
+/* APB3 */
+#define STM32H7_RCC_APB3_LTDC           3
+#define STM32H7_RCC_APB3_DSI            4
+
+#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
+
+/* APB1L */
+#define STM32H7_RCC_APB1L_TIM2          0
+#define STM32H7_RCC_APB1L_TIM3          1
+#define STM32H7_RCC_APB1L_TIM4          2
+#define STM32H7_RCC_APB1L_TIM5          3
+#define STM32H7_RCC_APB1L_TIM6          4
+#define STM32H7_RCC_APB1L_TIM7          5
+#define STM32H7_RCC_APB1L_TIM12         6
+#define STM32H7_RCC_APB1L_TIM13         7
+#define STM32H7_RCC_APB1L_TIM14         8
+#define STM32H7_RCC_APB1L_LPTIM1        9
+#define STM32H7_RCC_APB1L_SPI2          14
+#define STM32H7_RCC_APB1L_SPI3          15
+#define STM32H7_RCC_APB1L_SPDIF_RX      16
+#define STM32H7_RCC_APB1L_USART2        17
+#define STM32H7_RCC_APB1L_USART3        18
+#define STM32H7_RCC_APB1L_UART4         19
+#define STM32H7_RCC_APB1L_UART5         20
+#define STM32H7_RCC_APB1L_I2C1          21
+#define STM32H7_RCC_APB1L_I2C2          22
+#define STM32H7_RCC_APB1L_I2C3          23
+#define STM32H7_RCC_APB1L_HDMICEC       27
+#define STM32H7_RCC_APB1L_DAC12         29
+#define STM32H7_RCC_APB1L_USART7        30
+#define STM32H7_RCC_APB1L_USART8        31
+
+#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
+
+/* APB1H */
+#define STM32H7_RCC_APB1H_CRS           1
+#define STM32H7_RCC_APB1H_SWP           2
+#define STM32H7_RCC_APB1H_OPAMP         4
+#define STM32H7_RCC_APB1H_MDIOS         5
+#define STM32H7_RCC_APB1H_FDCAN         8
+
+#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
+
+/* APB2 */
+#define STM32H7_RCC_APB2_TIM1           0
+#define STM32H7_RCC_APB2_TIM8           1
+#define STM32H7_RCC_APB2_USART1         4
+#define STM32H7_RCC_APB2_USART6         5
+#define STM32H7_RCC_APB2_SPI1           12
+#define STM32H7_RCC_APB2_SPI4           13
+#define STM32H7_RCC_APB2_TIM15          16
+#define STM32H7_RCC_APB2_TIM16          17
+#define STM32H7_RCC_APB2_TIM17          18
+#define STM32H7_RCC_APB2_SPI5           20
+#define STM32H7_RCC_APB2_SAI1           22
+#define STM32H7_RCC_APB2_SAI2           23
+#define STM32H7_RCC_APB2_SAI3           24
+#define STM32H7_RCC_APB2_DFSDM1         28
+#define STM32H7_RCC_APB2_HRTIM          29
+
+#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
+
+/* APB4 */
+#define STM32H7_RCC_APB4_SYSCFG         1
+#define STM32H7_RCC_APB4_LPUART1        3
+#define STM32H7_RCC_APB4_SPI6           5
+#define STM32H7_RCC_APB4_I2C4           7
+#define STM32H7_RCC_APB4_LPTIM2         9
+#define STM32H7_RCC_APB4_LPTIM3         10
+#define STM32H7_RCC_APB4_LPTIM4         11
+#define STM32H7_RCC_APB4_LPTIM5         12
+#define STM32H7_RCC_APB4_COMP12         14
+#define STM32H7_RCC_APB4_VREF           15
+#define STM32H7_RCC_APB4_SAI4           21
+#define STM32H7_RCC_APB4_TMPSENS        26
+
+#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
+
+#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h
new file mode 100644
index 000000000000..5f4480bedc8a
--- /dev/null
+++ b/include/dt-bindings/reset/sun4i-a10-ccu.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
+#define _DT_BINDINGS_RST_SUN4I_A10_H
+
+#define RST_USB_PHY0            1
+#define RST_USB_PHY1            2
+#define RST_USB_PHY2            3
+#define RST_GPS                 4
+#define RST_DE_BE0              5
+#define RST_DE_BE1              6
+#define RST_DE_FE0              7
+#define RST_DE_FE1              8
+#define RST_DE_MP               9
+#define RST_TVE0                10
+#define RST_TCON0               11
+#define RST_TVE1                12
+#define RST_TCON1               13
+#define RST_CSI0                14
+#define RST_CSI1                15
+#define RST_VE                  16
+#define RST_ACE                 17
+#define RST_LVDS                18
+#define RST_GPU                 19
+#define RST_HDMI_H              20
+#define RST_HDMI_SYS            21
+#define RST_HDMI_AUDIO_DMA      22
+
+#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h
new file mode 100644
index 000000000000..c5ebcf6672e4
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r40-ccu.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
+#define _DT_BINDINGS_RST_SUN8I_R40_H_
+
+#define RST_USB_PHY0            0
+#define RST_USB_PHY1            1
+#define RST_USB_PHY2            2
+
+#define RST_DRAM                3
+#define RST_MBUS                4
+
+#define RST_BUS_MIPI_DSI        5
+#define RST_BUS_CE              6
+#define RST_BUS_DMA             7
+#define RST_BUS_MMC0            8
+#define RST_BUS_MMC1            9
+#define RST_BUS_MMC2            10
+#define RST_BUS_MMC3            11
+#define RST_BUS_NAND            12
+#define RST_BUS_DRAM            13
+#define RST_BUS_EMAC            14
+#define RST_BUS_TS              15
+#define RST_BUS_HSTIMER         16
+#define RST_BUS_SPI0            17
+#define RST_BUS_SPI1            18
+#define RST_BUS_SPI2            19
+#define RST_BUS_SPI3            20
+#define RST_BUS_SATA            21
+#define RST_BUS_OTG             22
+#define RST_BUS_EHCI0           23
+#define RST_BUS_EHCI1           24
+#define RST_BUS_EHCI2           25
+#define RST_BUS_OHCI0           26
+#define RST_BUS_OHCI1           27
+#define RST_BUS_OHCI2           28
+#define RST_BUS_VE              29
+#define RST_BUS_MP              30
+#define RST_BUS_DEINTERLACE     31
+#define RST_BUS_CSI0            32
+#define RST_BUS_CSI1            33
+#define RST_BUS_HDMI0           34
+#define RST_BUS_HDMI1           35
+#define RST_BUS_DE              36
+#define RST_BUS_TVE0            37
+#define RST_BUS_TVE1            38
+#define RST_BUS_TVE_TOP         39
+#define RST_BUS_GMAC            40
+#define RST_BUS_GPU             41
+#define RST_BUS_TVD0            42
+#define RST_BUS_TVD1            43
+#define RST_BUS_TVD2            44
+#define RST_BUS_TVD3            45
+#define RST_BUS_TVD_TOP         46
+#define RST_BUS_TCON_LCD0       47
+#define RST_BUS_TCON_LCD1       48
+#define RST_BUS_TCON_TV0        49
+#define RST_BUS_TCON_TV1        50
+#define RST_BUS_TCON_TOP        51
+#define RST_BUS_DBG             52
+#define RST_BUS_LVDS            53
+#define RST_BUS_CODEC           54
+#define RST_BUS_SPDIF           55
+#define RST_BUS_AC97            56
+#define RST_BUS_IR0             57
+#define RST_BUS_IR1             58
+#define RST_BUS_THS             59
+#define RST_BUS_KEYPAD          60
+#define RST_BUS_I2S0            61
+#define RST_BUS_I2S1            62
+#define RST_BUS_I2S2            63
+#define RST_BUS_I2C0            64
+#define RST_BUS_I2C1            65
+#define RST_BUS_I2C2            66
+#define RST_BUS_I2C3            67
+#define RST_BUS_CAN             68
+#define RST_BUS_SCR             69
+#define RST_BUS_PS20            70
+#define RST_BUS_PS21            71
+#define RST_BUS_I2C4            72
+#define RST_BUS_UART0           73
+#define RST_BUS_UART1           74
+#define RST_BUS_UART2           75
+#define RST_BUS_UART3           76
+#define RST_BUS_UART4           77
+#define RST_BUS_UART5           78
+#define RST_BUS_UART6           79
+#define RST_BUS_UART7           80
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c59c62571e4f..5100ec1b5d55 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -343,6 +343,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
                 u8 clk_gate_flags, spinlock_t *lock);
 void clk_unregister_gate(struct clk *clk);
 void clk_hw_unregister_gate(struct clk_hw *hw);
+int clk_gate_is_enabled(struct clk_hw *hw);
 
 struct clk_div_table {
         unsigned int    val;
@@ -565,6 +566,9 @@ struct clk_fractional_divider {
         u8              nwidth;
         u32             nmask;
         u8              flags;
+        void            (*approximation)(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *parent_rate,
+                                unsigned long *m, unsigned long *n);
         spinlock_t      *lock;
 };
 
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413bbbedf..6aca5ce8a99a 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -185,4 +185,29 @@
 #define         AT91_PMC_PCR_EN                 (0x1  <<  28)                           /* Enable */
 #define         AT91_PMC_PCR_GCKEN              (0x1  <<  29)                           /* GCK Enable */
 
+#define AT91_PMC_AUDIO_PLL0     0x14c
+#define         AT91_PMC_AUDIO_PLL_PLLEN        (1  <<  0)
+#define         AT91_PMC_AUDIO_PLL_PADEN        (1  <<  1)
+#define         AT91_PMC_AUDIO_PLL_PMCEN        (1  <<  2)
+#define         AT91_PMC_AUDIO_PLL_RESETN       (1  <<  3)
+#define         AT91_PMC_AUDIO_PLL_ND_OFFSET    8
+#define         AT91_PMC_AUDIO_PLL_ND_MASK      (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_ND(n)        ((n)  << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
+#define         AT91_PMC_AUDIO_PLL_QDPMC_MASK   (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPMC(n)     ((n)  << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+
+#define AT91_PMC_AUDIO_PLL1     0x150
+#define         AT91_PMC_AUDIO_PLL_FRACR_MASK           0x3fffff
+#define         AT91_PMC_AUDIO_PLL_QDPAD_OFFSET         24
+#define         AT91_PMC_AUDIO_PLL_QDPAD_MASK           (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD(n)             ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET     AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK       (0x3  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_DIV(n)         ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET  26
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX     0x1f
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK    (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+#define         AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n)      ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+
 #endif
diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c
index 0cd7caaed9c4..8445edd06737 100644
--- a/sound/soc/atmel/atmel-classd.c
+++ b/sound/soc/atmel/atmel-classd.c
@@ -32,7 +32,6 @@ struct atmel_classd {
         struct regmap *regmap;
         struct clk *pclk;
         struct clk *gclk;
-        struct clk *aclk;
         int irq;
         const struct atmel_classd_pdata *pdata;
 };
@@ -330,11 +329,6 @@ static int atmel_classd_codec_dai_startup(struct snd_pcm_substream *substream,
 {
         struct snd_soc_pcm_runtime *rtd = substream->private_data;
         struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
-        int ret;
-
-        ret = clk_prepare_enable(dd->aclk);
-        if (ret)
-                return ret;
 
         return clk_prepare_enable(dd->gclk);
 }
@@ -357,31 +351,31 @@ static int atmel_classd_codec_dai_digital_mute(struct snd_soc_dai *codec_dai,
         return 0;
 }
 
-#define CLASSD_ACLK_RATE_11M2896_MPY_8 (112896 * 100 * 8)
-#define CLASSD_ACLK_RATE_12M288_MPY_8  (12288 * 1000 * 8)
+#define CLASSD_GCLK_RATE_11M2896_MPY_8 (112896 * 100 * 8)
+#define CLASSD_GCLK_RATE_12M288_MPY_8  (12288 * 1000 * 8)
 
 static struct {
         int rate;
         int sample_rate;
         int dsp_clk;
-        unsigned long aclk_rate;
+        unsigned long gclk_rate;
 } const sample_rates[] = {
         { 8000,  CLASSD_INTPMR_FRAME_8K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
         { 16000, CLASSD_INTPMR_FRAME_16K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
         { 32000, CLASSD_INTPMR_FRAME_32K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
         { 48000, CLASSD_INTPMR_FRAME_48K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
         { 96000, CLASSD_INTPMR_FRAME_96K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_ACLK_RATE_12M288_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
         { 22050, CLASSD_INTPMR_FRAME_22K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
         { 44100, CLASSD_INTPMR_FRAME_44K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
         { 88200, CLASSD_INTPMR_FRAME_88K,
-        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_ACLK_RATE_11M2896_MPY_8 },
+        CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
 };
 
 static int
@@ -410,13 +404,12 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream,
         }
 
         dev_dbg(codec->dev,
-                "Selected SAMPLE_RATE of %dHz, ACLK_RATE of %ldHz\n",
-                sample_rates[best].rate, sample_rates[best].aclk_rate);
+                "Selected SAMPLE_RATE of %dHz, GCLK_RATE of %ldHz\n",
+                sample_rates[best].rate, sample_rates[best].gclk_rate);
 
         clk_disable_unprepare(dd->gclk);
-        clk_disable_unprepare(dd->aclk);
 
-        ret = clk_set_rate(dd->aclk, sample_rates[best].aclk_rate);
+        ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate);
         if (ret)
                 return ret;
 
@@ -426,10 +419,6 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream,
 
         snd_soc_update_bits(codec, CLASSD_INTPMR, mask, val);
 
-        ret = clk_prepare_enable(dd->aclk);
-        if (ret)
-                return ret;
-
         return clk_prepare_enable(dd->gclk);
 }
 
@@ -441,7 +430,6 @@ atmel_classd_codec_dai_shutdown(struct snd_pcm_substream *substream,
         struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
 
         clk_disable_unprepare(dd->gclk);
-        clk_disable_unprepare(dd->aclk);
 }
 
 static int atmel_classd_codec_dai_prepare(struct snd_pcm_substream *substream,
@@ -596,13 +584,6 @@ static int atmel_classd_probe(struct platform_device *pdev)
                 return ret;
         }
 
-        dd->aclk = devm_clk_get(dev, "aclk");
-        if (IS_ERR(dd->aclk)) {
-                ret = PTR_ERR(dd->aclk);
-                dev_err(dev, "failed to get audio clock: %d\n", ret);
-                return ret;
-        }
-
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         io_base = devm_ioremap_resource(dev, res);
         if (IS_ERR(io_base)) {