drivers/net: support hdlc function for QE-UCC

The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 21 insertions, 2 deletions

diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index c3b1dc8a21a7..70339d7958c0 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -657,6 +657,7 @@ struct ucc_slow_pram {
 #define UCC_SLOW_GUMR_L_MODE_QMC        0x00000002
 
 /* General UCC FAST Mode Register */
+#define UCC_FAST_GUMR_LOOPBACK  0x40000000
 #define UCC_FAST_GUMR_TCI       0x20000000
 #define UCC_FAST_GUMR_TRX       0x10000000
 #define UCC_FAST_GUMR_TTX       0x08000000
diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h
index e898895223f9..3ee9e7c1a7d7 100644
--- a/include/soc/fsl/qe/ucc_fast.h
+++ b/include/soc/fsl/qe/ucc_fast.h
@@ -21,19 +21,37 @@
 
 #include <soc/fsl/qe/ucc.h>
 
-/* Receive BD's status */
+/* Receive BD's status and length*/
 #define R_E     0x80000000      /* buffer empty */
 #define R_W     0x20000000      /* wrap bit */
 #define R_I     0x10000000      /* interrupt on reception */
 #define R_L     0x08000000      /* last */
 #define R_F     0x04000000      /* first */
 
-/* transmit BD's status */
+/* transmit BD's status and length*/
 #define T_R     0x80000000      /* ready bit */
 #define T_W     0x20000000      /* wrap bit */
 #define T_I     0x10000000      /* interrupt on completion */
 #define T_L     0x08000000      /* last */
 
+/* Receive BD's status */
+#define R_E_S   0x8000  /* buffer empty */
+#define R_W_S   0x2000  /* wrap bit */
+#define R_I_S   0x1000  /* interrupt on reception */
+#define R_L_S   0x0800  /* last */
+#define R_F_S   0x0400  /* first */
+#define R_CM_S  0x0200  /* continuous mode */
+#define R_CR_S  0x0004  /* crc */
+#define R_OV_S  0x0002  /* crc */
+
+/* transmit BD's status */
+#define T_R_S   0x8000  /* ready bit */
+#define T_W_S   0x2000  /* wrap bit */
+#define T_I_S   0x1000  /* interrupt on completion */
+#define T_L_S   0x0800  /* last */
+#define T_TC_S  0x0400  /* crc */
+#define T_TM_S  0x0200  /* continuous mode */
+
 /* Rx Data buffer must be 4 bytes aligned in most cases */
 #define UCC_FAST_RX_ALIGN                       4
 #define UCC_FAST_MRBLR_ALIGNMENT                4