drivers/net: support hdlc function for QE-UCC

The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

7 files changed, 1379 insertions, 2 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index f8d5a3772e47..16e1500d7c52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4870,6 +4870,13 @@ F:	drivers/net/ethernet/freescale/gianfar*
 X:      drivers/net/ethernet/freescale/gianfar_ptp.c
 F:      Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
 
+FREESCALE QUICC ENGINE UCC HDLC DRIVER
+M:      Zhao Qiang <qiang.zhao@nxp.com>
+L:      netdev@vger.kernel.org
+L:      linuxppc-dev@lists.ozlabs.org
+S:      Maintained
+F:      drivers/net/wan/fsl_ucc_hdlc*
+
 FREESCALE QUICC ENGINE UCC UART DRIVER
 M:      Timur Tabi <timur@tabi.org>
 L:      linuxppc-dev@lists.ozlabs.org
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index a2fdd15f285a..9e314b791150 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -280,6 +280,17 @@ config DSCC4
           To compile this driver as a module, choose M here: the
           module will be called dscc4.
 
+config FSL_UCC_HDLC
+        tristate "Freescale QUICC Engine HDLC support"
+        depends on HDLC
+        depends on QUICC_ENGINE
+        help
+          Driver for Freescale QUICC Engine HDLC controller. The driver
+          supports HDLC in NMSI and TDM mode.
+
+          To compile this driver as a module, choose M here: the
+          module will be called fsl_ucc_hdlc.
+
 config DSCC4_PCISYNC
         bool "Etinc PCISYNC features"
         depends on DSCC4
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index c135ef47cbca..25fec40d4353 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_WANXL)		+= wanxl.o
 obj-$(CONFIG_PCI200SYN)         += pci200syn.o
 obj-$(CONFIG_PC300TOO)          += pc300too.o
 obj-$(CONFIG_IXP4XX_HSS)        += ixp4xx_hss.o
+obj-$(CONFIG_FSL_UCC_HDLC)      += fsl_ucc_hdlc.o
 
 clean-files := wanxlfw.inc
 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
new file mode 100644
index 000000000000..19174ac1e338
--- /dev/null
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -0,0 +1,1192 @@
+/* Freescale QUICC Engine HDLC Device Driver
+ *
+ * Copyright 2016 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/hdlc.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/stddef.h>
+#include <soc/fsl/qe/qe_tdm.h>
+#include <uapi/linux/if_arp.h>
+
+#include "fsl_ucc_hdlc.h"
+
+#define DRV_DESC "Freescale QE UCC HDLC Driver"
+#define DRV_NAME "ucc_hdlc"
+
+#define TDM_PPPOHT_SLIC_MAXIN
+#define BROKEN_FRAME_INFO
+
+static struct ucc_tdm_info utdm_primary_info = {
+        .uf_info = {
+                .tsa = 0,
+                .cdp = 0,
+                .cds = 1,
+                .ctsp = 1,
+                .ctss = 1,
+                .revd = 0,
+                .urfs = 256,
+                .utfs = 256,
+                .urfet = 128,
+                .urfset = 192,
+                .utfet = 128,
+                .utftt = 0x40,
+                .ufpt = 256,
+                .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
+                .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
+                .tenc = UCC_FAST_TX_ENCODING_NRZ,
+                .renc = UCC_FAST_RX_ENCODING_NRZ,
+                .tcrc = UCC_FAST_16_BIT_CRC,
+                .synl = UCC_FAST_SYNC_LEN_NOT_USED,
+        },
+
+        .si_info = {
+#ifdef TDM_PPPOHT_SLIC_MAXIN
+                .simr_rfsd = 1,
+                .simr_tfsd = 2,
+#else
+                .simr_rfsd = 0,
+                .simr_tfsd = 0,
+#endif
+                .simr_crt = 0,
+                .simr_sl = 0,
+                .simr_ce = 1,
+                .simr_fe = 1,
+                .simr_gm = 0,
+        },
+};
+
+static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
+
+static int uhdlc_init(struct ucc_hdlc_private *priv)
+{
+        struct ucc_tdm_info *ut_info;
+        struct ucc_fast_info *uf_info;
+        u32 cecr_subblock;
+        u16 bd_status;
+        int ret, i;
+        void *bd_buffer;
+        dma_addr_t bd_dma_addr;
+        u32 riptr;
+        u32 tiptr;
+        u32 gumr;
+
+        ut_info = priv->ut_info;
+        uf_info = &ut_info->uf_info;
+
+        if (priv->tsa) {
+                uf_info->tsa = 1;
+                uf_info->ctsp = 1;
+        }
+        uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
+                                UCC_HDLC_UCCE_TXB) << 16);
+
+        ret = ucc_fast_init(uf_info, &priv->uccf);
+        if (ret) {
+                dev_err(priv->dev, "Failed to init uccf.");
+                return ret;
+        }
+
+        priv->uf_regs = priv->uccf->uf_regs;
+        ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
+
+        /* Loopback mode */
+        if (priv->loopback) {
+                dev_info(priv->dev, "Loopback Mode\n");
+                gumr = ioread32be(&priv->uf_regs->gumr);
+                gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
+                         UCC_FAST_GUMR_TCI);
+                gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
+                iowrite32be(gumr, &priv->uf_regs->gumr);
+        }
+
+        /* Initialize SI */
+        if (priv->tsa)
+                ucc_tdm_init(priv->utdm, priv->ut_info);
+
+        /* Write to QE CECR, UCCx channel to Stop Transmission */
+        cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
+        ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
+                           QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+        /* Set UPSMR normal mode (need fixed)*/
+        iowrite32be(0, &priv->uf_regs->upsmr);
+
+        priv->rx_ring_size = RX_BD_RING_LEN;
+        priv->tx_ring_size = TX_BD_RING_LEN;
+        /* Alloc Rx BD */
+        priv->rx_bd_base = dma_alloc_coherent(priv->dev,
+                        RX_BD_RING_LEN * sizeof(struct qe_bd *),
+                        &priv->dma_rx_bd, GFP_KERNEL);
+
+        if (!priv->rx_bd_base) {
+                dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
+                ret = -ENOMEM;
+                goto rxbd_alloc_error;
+        }
+