Merge branch 'next/late' with mainline

* next/late: (25 commits)
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ARM64: dts: meson-gxbb-vega-s95: Add LED
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 63 insertions, 8 deletions

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 9d9af446bafc..1c1ec137a3cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
         },
 };
 
+static struct clk_mux gxbb_sar_adc_clk_sel = {
+        .reg = (void *)HHI_SAR_CLK_CNTL,
+        .mask = 0x3,
+        .shift = 9,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sar_adc_clk_sel",
+                .ops = &clk_mux_ops,
+                /* NOTE: The datasheet doesn't list the parents for bit 10 */
+                .parent_names = (const char *[]){ "xtal", "clk81", },
+                .num_parents = 2,
+        },
+};
+
+static struct clk_divider gxbb_sar_adc_clk_div = {
+        .reg = (void *)HHI_SAR_CLK_CNTL,
+        .shift = 0,
+        .width = 8,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sar_adc_clk_div",
+                .ops = &clk_divider_ops,
+                .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+                .num_parents = 1,
+        },
+};
+
+static struct clk_gate gxbb_sar_adc_clk = {
+        .reg = (void *)HHI_SAR_CLK_CNTL,
+        .bit_idx = 8,
+        .lock = &clk_lock,
+        .hw.init = &(struct clk_init_data){
+                .name = "sar_adc_clk",
+                .ops = &clk_gate_ops,
+                .parent_names = (const char *[]){ "sar_adc_clk_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
+                [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
+                [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
+                [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
         },
         .num = NR_CLKS,
 };
@@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
         &gxbb_emmc_a,
         &gxbb_emmc_b,
         &gxbb_emmc_c,
+        &gxbb_sar_adc_clk,
 };
 
 static int gxbb_clkc_probe(struct platform_device *pdev)
@@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
         gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
         gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
 
+        /* Populate the base address for the SAR ADC clks */
+        gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
+        gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
+
         /* Populate base address for gates */
         for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
                 gxbb_clk_gates[i]->reg = clk_base +
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 0252939ba58f..8ee2022ce5d5 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -191,7 +191,7 @@
 #define CLKID_PERIPHS             20
 #define CLKID_SPICC               21
 /* CLKID_I2C */
-#define CLKID_SAR_ADC             23
+/* #define CLKID_SAR_ADC */
 #define CLKID_SMART_CARD          24
 #define CLKID_RNG0                25
 #define CLKID_UART0               26
@@ -204,7 +204,7 @@
 #define CLKID_ASSIST_MISC         33
 /* CLKID_SPI */
 #define CLKID_I2S_SPDIF           35
-#define CLKID_ETH                 36
+/* CLKID_ETH */
 #define CLKID_DEMUX               37
 #define CLKID_AIU_GLUE            38
 #define CLKID_IEC958              39
@@ -231,13 +231,13 @@
 #define CLKID_AHB_DATA_BUS        60
 #define CLKID_AHB_CTRL_BUS        61
 #define CLKID_HDMI_INTR_SYNC      62
-#define CLKID_HDMI_PCLK           63
+/* CLKID_HDMI_PCLK */
 /* CLKID_USB1_DDR_BRIDGE */
 /* CLKID_USB0_DDR_BRIDGE */
 #define CLKID_MMC_PCLK            66
 #define CLKID_DVIN                67
 #define CLKID_UART2               68
-#define CLKID_SANA                69
+/* #define CLKID_SANA */
 #define CLKID_VPU_INTR            70
 #define CLKID_SEC_AHB_AHB3_BRIDGE 71
 #define CLKID_CLK81_A53           72
@@ -245,7 +245,7 @@
 #define CLKID_VCLK2_VENCI1        74
 #define CLKID_VCLK2_VENCP0        75
 #define CLKID_VCLK2_VENCP1        76
-#define CLKID_GCLK_VENCI_INT0     77
+/* CLKID_GCLK_VENCI_INT0 */
 #define CLKID_GCLK_VENCI_INT      78
 #define CLKID_DAC_CLK             79
 #define CLKID_AOCLK_GATE          80
@@ -265,8 +265,11 @@
 /* CLKID_SD_EMMC_A */
 /* CLKID_SD_EMMC_B */
 /* CLKID_SD_EMMC_C */
+/* CLKID_SAR_ADC_CLK */
+/* CLKID_SAR_ADC_SEL */
+#define CLKID_SAR_ADC_DIV         99
 
-#define NR_CLKS                   97
+#define NR_CLKS                   100
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index f096bd7df40c..3feaea8be40e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
         PLL_35XX_RATE(350000000U,  350, 6,  2),
         PLL_35XX_RATE(333000000U,  222, 4,  2),
         PLL_35XX_RATE(300000000U,  500, 5,  3),
+        PLL_35XX_RATE(278000000U,  556, 6,  3),
         PLL_35XX_RATE(266000000U,  532, 6,  3),
+        PLL_35XX_RATE(250000000U,  500, 6,  3),
         PLL_35XX_RATE(200000000U,  400, 6,  3),
         PLL_35XX_RATE(166000000U,  332, 6,  3),
         PLL_35XX_RATE(160000000U,  320, 6,  3),
@@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
         FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
         FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
         /* PHY clocks from MIPI_DPHY0 */
-        FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
-        FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+        FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
+                        NULL, 0, 188000000),
+        FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
+                        NULL, 0, 100000000),
         /* PHY clocks from HDMI_PHY */
         FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
                         NULL, 0, 300000000),