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authorVille Syrjälä <ville.syrjala@linux.intel.com>2016-05-13 16:41:40 -0400
committerVille Syrjälä <ville.syrjala@linux.intel.com>2016-05-23 14:11:17 -0400
commitd1b32c32e8943d18a104f347fbe40c46276011d9 (patch)
tree8350456ebcade73784cb483f8ba1c5dc821d70f1 /drivers
parent342be926e0368018d9c22c4ab54d4a2bc6e9c15f (diff)
drm/i915: Set BXT cdclk to minimum initially
In case the driver is initialized without active displays, we should just drop the cdclk to the minimum frequency right off the bat. There might not be a modeset to drop it to the minimum late rafter all. With DMC supposedly we should always have the cdclk up and running. The DMC will shut the DE PLL down when appropriate, so let's nuke the related FIXMEs as well. Trying to do anything different would go against the expectations of the DMC firmware, and we all know how fragile the DMC firmware is. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-22-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d53b670328e4..fd171fd2b255 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -119,6 +119,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state);
119static void intel_modeset_verify_crtc(struct drm_crtc *crtc, 119static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
120 struct drm_crtc_state *old_state, 120 struct drm_crtc_state *old_state,
121 struct drm_crtc_state *new_state); 121 struct drm_crtc_state *new_state);
122static int broxton_calc_cdclk(int max_pixclk);
122 123
123struct intel_limit { 124struct intel_limit {
124 struct { 125 struct {
@@ -5421,10 +5422,8 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5421 * FIXME: 5422 * FIXME:
5422 * - The initial CDCLK needs to be read from VBT. 5423 * - The initial CDCLK needs to be read from VBT.
5423 * Need to make this change after VBT has changes for BXT. 5424 * Need to make this change after VBT has changes for BXT.
5424 * - check if setting the max (or any) cdclk freq is really necessary
5425 * here, it belongs to modeset time
5426 */ 5425 */
5427 broxton_set_cdclk(dev_priv, 624000); 5426 broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
5428} 5427}
5429 5428
5430void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) 5429void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -5864,10 +5863,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5864 5863
5865static int broxton_calc_cdclk(int max_pixclk) 5864static int broxton_calc_cdclk(int max_pixclk)
5866{ 5865{
5867 /*
5868 * FIXME:
5869 * - set 19.2MHz bypass frequency if there are no active pipes
5870 */
5871 if (max_pixclk > 576000) 5866 if (max_pixclk > 576000)
5872 return 624000; 5867 return 624000;
5873 else if (max_pixclk > 384000) 5868 else if (max_pixclk > 384000)