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authorAlexandre Bounine <alexandre.bounine@idt.com>2016-08-02 17:06:37 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 19:35:33 -0400
commit4498c31adff99d243b34b0bf39363a35ea070928 (patch)
treeb3bedd78df56080a34ba8f607a0ad9dbdbb24c8e /drivers/rapidio/devices/tsi721_dma.c
parentf8e3a68c05f0f09a0da947b9d447268d2d3f8780 (diff)
rapidio/tsi721_dma: add channel mask and queue size parameters
Add module parameters to allow load time configuration of DMA channels. Depending on application, performance of DMA data transfers can benefit from adjusted sizes of buffer descriptor ring and/or transaction requests queue. Having HW DMA channel selector mask allows to define which channels (from seven available) are controlled by the mport device driver and reserve some of them for direct use by other drivers. Link: http://lkml.kernel.org/r/1469125134-16523-5-git-send-email-alexandre.bounine@idt.com Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Tested-by: Barry Wood <barry.wood@idt.com> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Andre van Herk <andre.van.herk@prodrive-technologies.com> Cc: Barry Wood <barry.wood@idt.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/rapidio/devices/tsi721_dma.c')
-rw-r--r--drivers/rapidio/devices/tsi721_dma.c26
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/rapidio/devices/tsi721_dma.c b/drivers/rapidio/devices/tsi721_dma.c
index 155cae1e62de..13c669bac019 100644
--- a/drivers/rapidio/devices/tsi721_dma.c
+++ b/drivers/rapidio/devices/tsi721_dma.c
@@ -36,18 +36,26 @@
36 36
37#include "tsi721.h" 37#include "tsi721.h"
38 38
39#define TSI721_DMA_TX_QUEUE_SZ 16 /* number of transaction descriptors */
40
41#ifdef CONFIG_PCI_MSI 39#ifdef CONFIG_PCI_MSI
42static irqreturn_t tsi721_bdma_msix(int irq, void *ptr); 40static irqreturn_t tsi721_bdma_msix(int irq, void *ptr);
43#endif 41#endif
44static int tsi721_submit_sg(struct tsi721_tx_desc *desc); 42static int tsi721_submit_sg(struct tsi721_tx_desc *desc);
45 43
46static unsigned int dma_desc_per_channel = 128; 44static unsigned int dma_desc_per_channel = 128;
47module_param(dma_desc_per_channel, uint, S_IWUSR | S_IRUGO); 45module_param(dma_desc_per_channel, uint, S_IRUGO);
48MODULE_PARM_DESC(dma_desc_per_channel, 46MODULE_PARM_DESC(dma_desc_per_channel,
49 "Number of DMA descriptors per channel (default: 128)"); 47 "Number of DMA descriptors per channel (default: 128)");
50 48
49static unsigned int dma_txqueue_sz = 16;
50module_param(dma_txqueue_sz, uint, S_IRUGO);
51MODULE_PARM_DESC(dma_txqueue_sz,
52 "DMA Transactions Queue Size (default: 16)");
53
54static u8 dma_sel = 0x7f;
55module_param(dma_sel, byte, S_IRUGO);
56MODULE_PARM_DESC(dma_sel,
57 "DMA Channel Selection Mask (default: 0x7f = all)");
58
51static inline struct tsi721_bdma_chan *to_tsi721_chan(struct dma_chan *chan) 59static inline struct tsi721_bdma_chan *to_tsi721_chan(struct dma_chan *chan)
52{ 60{
53 return container_of(chan, struct tsi721_bdma_chan, dchan); 61 return container_of(chan, struct tsi721_bdma_chan, dchan);
@@ -732,7 +740,7 @@ static int tsi721_alloc_chan_resources(struct dma_chan *dchan)
732 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id); 740 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
733 741
734 if (bdma_chan->bd_base) 742 if (bdma_chan->bd_base)
735 return TSI721_DMA_TX_QUEUE_SZ; 743 return dma_txqueue_sz;
736 744
737 /* Initialize BDMA channel */ 745 /* Initialize BDMA channel */
738 if (tsi721_bdma_ch_init(bdma_chan, dma_desc_per_channel)) { 746 if (tsi721_bdma_ch_init(bdma_chan, dma_desc_per_channel)) {
@@ -742,7 +750,7 @@ static int tsi721_alloc_chan_resources(struct dma_chan *dchan)
742 } 750 }
743 751
744 /* Allocate queue of transaction descriptors */ 752 /* Allocate queue of transaction descriptors */
745 desc = kcalloc(TSI721_DMA_TX_QUEUE_SZ, sizeof(struct tsi721_tx_desc), 753 desc = kcalloc(dma_txqueue_sz, sizeof(struct tsi721_tx_desc),
746 GFP_ATOMIC); 754 GFP_ATOMIC);
747 if (!desc) { 755 if (!desc) {
748 tsi_err(&dchan->dev->device, 756 tsi_err(&dchan->dev->device,
@@ -754,7 +762,7 @@ static int tsi721_alloc_chan_resources(struct dma_chan *dchan)
754 762
755 bdma_chan->tx_desc = desc; 763 bdma_chan->tx_desc = desc;
756 764
757 for (i = 0; i < TSI721_DMA_TX_QUEUE_SZ; i++) { 765 for (i = 0; i < dma_txqueue_sz; i++) {
758 dma_async_tx_descriptor_init(&desc[i].txd, dchan); 766 dma_async_tx_descriptor_init(&desc[i].txd, dchan);
759 desc[i].txd.tx_submit = tsi721_tx_submit; 767 desc[i].txd.tx_submit = tsi721_tx_submit;
760 desc[i].txd.flags = DMA_CTRL_ACK; 768 desc[i].txd.flags = DMA_CTRL_ACK;
@@ -766,7 +774,7 @@ static int tsi721_alloc_chan_resources(struct dma_chan *dchan)
766 bdma_chan->active = true; 774 bdma_chan->active = true;
767 tsi721_bdma_interrupt_enable(bdma_chan, 1); 775 tsi721_bdma_interrupt_enable(bdma_chan, 1);
768 776
769 return TSI721_DMA_TX_QUEUE_SZ; 777 return dma_txqueue_sz;
770} 778}
771 779
772static void tsi721_sync_dma_irq(struct tsi721_bdma_chan *bdma_chan) 780static void tsi721_sync_dma_irq(struct tsi721_bdma_chan *bdma_chan)
@@ -962,7 +970,7 @@ void tsi721_dma_stop_all(struct tsi721_device *priv)
962 int i; 970 int i;
963 971
964 for (i = 0; i < TSI721_DMA_MAXCH; i++) { 972 for (i = 0; i < TSI721_DMA_MAXCH; i++) {
965 if (i != TSI721_DMACH_MAINT) 973 if ((i != TSI721_DMACH_MAINT) && (dma_sel & (1 << i)))
966 tsi721_dma_stop(&priv->bdma[i]); 974 tsi721_dma_stop(&priv->bdma[i]);
967 } 975 }
968} 976}
@@ -979,7 +987,7 @@ int tsi721_register_dma(struct tsi721_device *priv)
979 for (i = 0; i < TSI721_DMA_MAXCH; i++) { 987 for (i = 0; i < TSI721_DMA_MAXCH; i++) {
980 struct tsi721_bdma_chan *bdma_chan = &priv->bdma[i]; 988 struct tsi721_bdma_chan *bdma_chan = &priv->bdma[i];
981 989
982 if (i == TSI721_DMACH_MAINT) 990 if ((i == TSI721_DMACH_MAINT) || (dma_sel & (1 << i)) == 0)
983 continue; 991 continue;
984 992
985 bdma_chan->regs = priv->regs + TSI721_DMAC_BASE(i); 993 bdma_chan->regs = priv->regs + TSI721_DMAC_BASE(i);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 17:34:22 -0400