aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/controller/dwc
diff options
context:
space:
mode:
authorBjorn Helgaas <bhelgaas@google.com>2018-10-20 12:45:51 -0400
committerBjorn Helgaas <bhelgaas@google.com>2018-10-20 12:45:51 -0400
commitfc23af0cb1efa4c5b0c7ecd226d827e4824a4dcf (patch)
treee3bc9a2cd68b3763603cb352a191f9bd1d77e2a4 /drivers/pci/controller/dwc
parentdeab1f261cd34ed1c0d9b6558c6ce90fd49a431e (diff)
parent261de72f0169fd9e5bf7113ad9b52e8678f2fdf0 (diff)
Merge branch 'remotes/lorenzo/pci/keystone'
- Quirk Keystone K2G to limit MRRS to 256 (Kishon Vijay Abraham I) - Update Keystone to use MRRS quirk for host bridge instead of open coding (Kishon Vijay Abraham I) - Refactor Keystone link establishment (Kishon Vijay Abraham I) - Simplify and speed up Keystone link training (Kishon Vijay Abraham I) - Remove unused Keystone host_init argument (Kishon Vijay Abraham I) - Merge Keystone driver files into one (Kishon Vijay Abraham I) - Remove redundant Keystone platform_set_drvdata() (Kishon Vijay Abraham I) - Rename Keystone functions for uniformity (Kishon Vijay Abraham I) - Add Keystone device control module DT binding (Kishon Vijay Abraham I) - Use SYSCON API to get Keystone control module device IDs (Kishon Vijay Abraham I) - Clean up Keystone PHY handling (Kishon Vijay Abraham I) - Use runtime PM APIs to enable Keystone clock (Kishon Vijay Abraham I) - Clean up Keystone config space access checks (Kishon Vijay Abraham I) - Get Keystone outbound window count from DT (Kishon Vijay Abraham I) - Clean up Keystone outbound window configuration (Kishon Vijay Abraham I) - Clean up Keystone DBI setup (Kishon Vijay Abraham I) - Clean up Keystone ks_pcie_link_up() (Kishon Vijay Abraham I) - Fix Keystone IRQ status checking (Kishon Vijay Abraham I) - Add debug messages for all Keystone errors (Kishon Vijay Abraham I) - Clean up Keystone includes and macros (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: PCI: keystone: Cleanup macros defined in pci-keystone.c PCI: keystone: Reorder header file in alphabetical order PCI: keystone: Add debug error message for all errors PCI: keystone: Use ERR_IRQ_STATUS instead of ERR_IRQ_STATUS_RAW to get interrupt status PCI: keystone: Cleanup ks_pcie_link_up() PCI: keystone: Cleanup set_dbi_mode() and get_dbi_mode() PCI: keystone: Cleanup outbound window configuration PCI: keystone: Get number of outbound windows from DT PCI: keystone: Cleanup configuration space access PCI: keystone: Invoke runtime PM APIs to enable clock PCI: keystone: Cleanup PHY handling PCI: keystone: Use SYSCON APIs to get device ID from control module dt-bindings: PCI: keystone: Add bindings to get device control module PCI: keystone: Use uniform function naming convention PCI: keystone: Remove redundant platform_set_drvdata() invocation PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() PCI: keystone: Do not initiate link training multiple times PCI: keystone: Move dw_pcie_setup_rc() out of ks_pcie_establish_link() PCI: keystone: Use quirk to set MRRS for PCI host bridge PCI: keystone: Use quirk to limit MRRS for K2G
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r--drivers/pci/controller/dwc/Makefile2
-rw-r--r--drivers/pci/controller/dwc/pci-keystone-dw.c484
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.c788
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.h57
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.h4
5 files changed, 682 insertions, 653 deletions
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 5d2ce72c7a52..fcf91eacfc63 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
7obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o 7obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8obj-$(CONFIG_PCI_IMX6) += pci-imx6.o 8obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
9obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o 9obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
10obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o 10obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
11obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o 11obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
12obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o 12obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
13obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o 13obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c
deleted file mode 100644
index 0682213328e9..000000000000
--- a/drivers/pci/controller/dwc/pci-keystone-dw.c
+++ /dev/null
@@ -1,484 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DesignWare application register space functions for Keystone PCI controller
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * http://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 */
10
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/irqreturn.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_pci.h>
17#include <linux/pci.h>
18#include <linux/platform_device.h>
19
20#include "pcie-designware.h"
21#include "pci-keystone.h"
22
23/* Application register defines */
24#define LTSSM_EN_VAL 1
25#define LTSSM_STATE_MASK 0x1f
26#define LTSSM_STATE_L0 0x11
27#define DBI_CS2_EN_VAL 0x20
28#define OB_XLAT_EN_VAL 2
29
30/* Application registers */
31#define CMD_STATUS 0x004
32#define CFG_SETUP 0x008
33#define OB_SIZE 0x030
34#define CFG_PCIM_WIN_SZ_IDX 3
35#define CFG_PCIM_WIN_CNT 32
36#define SPACE0_REMOTE_CFG_OFFSET 0x1000
37#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
38#define OB_OFFSET_HI(n) (0x204 + (8 * n))
39
40/* IRQ register defines */
41#define IRQ_EOI 0x050
42#define IRQ_STATUS 0x184
43#define IRQ_ENABLE_SET 0x188
44#define IRQ_ENABLE_CLR 0x18c
45
46#define MSI_IRQ 0x054
47#define MSI0_IRQ_STATUS 0x104
48#define MSI0_IRQ_ENABLE_SET 0x108
49#define MSI0_IRQ_ENABLE_CLR 0x10c
50#define IRQ_STATUS 0x184
51#define MSI_IRQ_OFFSET 4
52
53/* Error IRQ bits */
54#define ERR_AER BIT(5) /* ECRC error */
55#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
56#define ERR_CORR BIT(3) /* Correctable error */
57#define ERR_NONFATAL BIT(2) /* Non-fatal error */
58#define ERR_FATAL BIT(1) /* Fatal error */
59#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
60#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
61 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
62#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
63#define ERR_IRQ_STATUS_RAW 0x1c0
64#define ERR_IRQ_STATUS 0x1c4
65#define ERR_IRQ_ENABLE_SET 0x1c8
66#define ERR_IRQ_ENABLE_CLR 0x1cc
67
68/* Config space registers */
69#define DEBUG0 0x728
70
71#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
72
73static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
74 u32 *bit_pos)
75{
76 *reg_offset = offset % 8;
77 *bit_pos = offset >> 3;
78}
79
80phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
81{
82 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
83 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
84
85 return ks_pcie->app.start + MSI_IRQ;
86}
87
88static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
89{
90 return readl(ks_pcie->va_app_base + offset);
91}
92
93static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
94{
95 writel(val, ks_pcie->va_app_base + offset);
96}
97
98void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
99{
100 struct dw_pcie *pci = ks_pcie->pci;
101 struct pcie_port *pp = &pci->pp;
102 struct device *dev = pci->dev;
103 u32 pending, vector;
104 int src, virq;
105
106 pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
107
108 /*
109 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
110 * shows 1, 9, 17, 25 and so forth
111 */
112 for (src = 0; src < 4; src++) {
113 if (BIT(src) & pending) {
114 vector = offset + (src << 3);
115 virq = irq_linear_revmap(pp->irq_domain, vector);
116 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
117 src, vector, virq);
118 generic_handle_irq(virq);
119 }
120 }
121}
122
123void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
124{
125 u32 reg_offset, bit_pos;
126 struct keystone_pcie *ks_pcie;
127 struct dw_pcie *pci;
128
129 pci = to_dw_pcie_from_pp(pp);
130 ks_pcie = to_keystone_pcie(pci);
131 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
132
133 ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
134 BIT(bit_pos));
135 ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
136}
137
138void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
139{
140 u32 reg_offset, bit_pos;
141 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
142 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
143
144 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
145 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
146 BIT(bit_pos));
147}
148
149void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
150{
151 u32 reg_offset, bit_pos;
152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
153 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
154
155 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
156 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
157 BIT(bit_pos));
158}
159
160int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
161{
162 return dw_pcie_allocate_domains(pp);
163}
164
165void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
166{
167 int i;
168
169 for (i = 0; i < PCI_NUM_INTX; i++)
170 ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
171}
172
173void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
174{
175 struct dw_pcie *pci = ks_pcie->pci;
176 struct device *dev = pci->dev;
177 u32 pending;
178 int virq;
179
180 pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
181
182 if (BIT(0) & pending) {
183 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
184 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
185 generic_handle_irq(virq);
186 }
187
188 /* EOI the INTx interrupt */
189 ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
190}
191
192void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
193{
194 ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
195}
196
197irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
198{
199 u32 status;
200
201 status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
202 if (!status)
203 return IRQ_NONE;
204
205 if (status & ERR_FATAL_IRQ)
206 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
207 status);
208
209 /* Ack the IRQ; status bits are RW1C */
210 ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
211 return IRQ_HANDLED;
212}
213
214static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
215{
216}
217
218static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
219{
220}
221
222static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
223{
224}
225
226static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
227 .name = "Keystone-PCI-Legacy-IRQ",
228 .irq_ack = ks_dw_pcie_ack_legacy_irq,
229 .irq_mask = ks_dw_pcie_mask_legacy_irq,
230 .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
231};
232
233static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
234 unsigned int irq, irq_hw_number_t hw_irq)
235{
236 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
237 handle_level_irq);
238 irq_set_chip_data(irq, d->host_data);
239
240 return 0;
241}
242
243static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
244 .map = ks_dw_pcie_init_legacy_irq_map,
245 .xlate = irq_domain_xlate_onetwocell,
246};
247
248/**
249 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
250 * registers
251 *
252 * Since modification of dbi_cs2 involves different clock domain, read the
253 * status back to ensure the transition is complete.
254 */
255static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
256{
257 u32 val;
258
259 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
260 ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
261
262 do {
263 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
264 } while (!(val & DBI_CS2_EN_VAL));
265}
266
267/**
268 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
269 *
270 * Since modification of dbi_cs2 involves different clock domain, read the
271 * status back to ensure the transition is complete.
272 */
273static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
274{
275 u32 val;
276
277 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
278 ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
279
280 do {
281 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
282 } while (val & DBI_CS2_EN_VAL);
283}
284
285void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
286{
287 struct dw_pcie *pci = ks_pcie->pci;
288 struct pcie_port *pp = &pci->pp;
289 u32 start = pp->mem->start, end = pp->mem->end;
290 int i, tr_size;
291 u32 val;
292
293 /* Disable BARs for inbound access */
294 ks_dw_pcie_set_dbi_mode(ks_pcie);
295 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
296 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
297 ks_dw_pcie_clear_dbi_mode(ks_pcie);
298
299 /* Set outbound translation size per window division */
300 ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
301
302 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
303
304 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
305 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
306 ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
307 ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
308 start += tr_size;
309 }
310
311 /* Enable OB translation */
312 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
313 ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
314}
315
316/**
317 * ks_pcie_cfg_setup() - Set up configuration space address for a device
318 *
319 * @ks_pcie: ptr to keystone_pcie structure
320 * @bus: Bus number the device is residing on
321 * @devfn: device, function number info
322 *
323 * Forms and returns the address of configuration space mapped in PCIESS
324 * address space 0. Also configures CFG_SETUP for remote configuration space
325 * access.
326 *
327 * The address space has two regions to access configuration - local and remote.
328 * We access local region for bus 0 (as RC is attached on bus 0) and remote
329 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
330 * we will do TYPE 0 access as it will be on our secondary bus (logical).
331 * CFG_SETUP is needed only for remote configuration access.
332 */
333static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
334 unsigned int devfn)
335{
336 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
337 struct dw_pcie *pci = ks_pcie->pci;
338 struct pcie_port *pp = &pci->pp;
339 u32 regval;
340
341 if (bus == 0)
342 return pci->dbi_base;
343
344 regval = (bus << 16) | (device << 8) | function;
345
346 /*
347 * Since Bus#1 will be a virtual bus, we need to have TYPE0
348 * access only.
349 * TYPE 1
350 */
351 if (bus != 1)
352 regval |= BIT(24);
353
354 ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
355 return pp->va_cfg0_base;
356}
357
358int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
359 unsigned int devfn, int where, int size, u32 *val)
360{
361 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
362 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
363 u8 bus_num = bus->number;
364 void __iomem *addr;
365
366 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
367
368 return dw_pcie_read(addr + where, size, val);
369}
370
371int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
372 unsigned int devfn, int where, int size, u32 val)
373{
374 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
375 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
376 u8 bus_num = bus->number;
377 void __iomem *addr;
378
379 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
380
381 return dw_pcie_write(addr + where, size, val);
382}
383
384/**
385 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
386 *
387 * This sets BAR0 to enable inbound access for MSI_IRQ register
388 */
389void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
390{
391 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
392 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
393
394 /* Configure and set up BAR0 */
395 ks_dw_pcie_set_dbi_mode(ks_pcie);
396
397 /* Enable BAR0 */
398 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
399 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
400
401 ks_dw_pcie_clear_dbi_mode(ks_pcie);
402
403 /*
404 * For BAR0, just setting bus address for inbound writes (MSI) should
405 * be sufficient. Use physical address to avoid any conflicts.
406 */
407 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
408}
409
410/**
411 * ks_dw_pcie_link_up() - Check if link up
412 */
413int ks_dw_pcie_link_up(struct dw_pcie *pci)
414{
415 u32 val;
416
417 val = dw_pcie_readl_dbi(pci, DEBUG0);
418 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
419}
420
421void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
422{
423 u32 val;
424
425 /* Disable Link training */
426 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
427 val &= ~LTSSM_EN_VAL;
428 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
429
430 /* Initiate Link Training */
431 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
432 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
433}
434
435/**
436 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
437 *
438 * Ioremap the register resources, initialize legacy irq domain
439 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
440 * PCI host controller.
441 */
442int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
443 struct device_node *msi_intc_np)
444{
445 struct dw_pcie *pci = ks_pcie->pci;
446 struct pcie_port *pp = &pci->pp;
447 struct device *dev = pci->dev;
448 struct platform_device *pdev = to_platform_device(dev);
449 struct resource *res;
450
451 /* Index 0 is the config reg. space address */
452 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
454 if (IS_ERR(pci->dbi_base))
455 return PTR_ERR(pci->dbi_base);
456
457 /*
458 * We set these same and is used in pcie rd/wr_other_conf
459 * functions
460 */
461 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
462 pp->va_cfg1_base = pp->va_cfg0_base;
463
464 /* Index 1 is the application reg. space address */
465 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
466 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
467 if (IS_ERR(ks_pcie->va_app_base))
468 return PTR_ERR(ks_pcie->va_app_base);
469
470 ks_pcie->app = *res;
471
472 /* Create legacy IRQ domain */
473 ks_pcie->legacy_irq_domain =
474 irq_domain_add_linear(ks_pcie->legacy_intc_np,
475 PCI_NUM_INTX,
476 &ks_dw_pcie_legacy_irq_domain_ops,
477 NULL);
478 if (!ks_pcie->legacy_irq_domain) {
479 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
480 return -EINVAL;
481 }
482
483 return dw_pcie_host_init(pp);
484}
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index e88bd221fffe..14f2b0b4ed5e 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -9,40 +9,510 @@
9 * Implementation based on pci-exynos.c and pcie-designware.c 9 * Implementation based on pci-exynos.c and pcie-designware.c
10 */ 10 */
11 11
12#include <linux/irqchip/chained_irq.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
17#include <linux/init.h> 18#include <linux/mfd/syscon.h>
18#include <linux/msi.h> 19#include <linux/msi.h>
19#include <linux/of_irq.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_irq.h>
21#include <linux/of_pci.h> 22#include <linux/of_pci.h>
22#include <linux/platform_device.h>
23#include <linux/phy/phy.h> 23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
24#include <linux/resource.h> 26#include <linux/resource.h>
25#include <linux/signal.h> 27#include <linux/signal.h>
26 28
27#include "pcie-designware.h" 29#include "pcie-designware.h"
28#include "pci-keystone.h"
29 30
30#define DRIVER_NAME "keystone-pcie" 31#define PCIE_VENDORID_MASK 0xffff
32#define PCIE_DEVICEID_SHIFT 16
33
34/* Application registers */
35#define CMD_STATUS 0x004
36#define LTSSM_EN_VAL BIT(0)
37#define OB_XLAT_EN_VAL BIT(1)
38#define DBI_CS2 BIT(5)
39
40#define CFG_SETUP 0x008
41#define CFG_BUS(x) (((x) & 0xff) << 16)
42#define CFG_DEVICE(x) (((x) & 0x1f) << 8)
43#define CFG_FUNC(x) ((x) & 0x7)
44#define CFG_TYPE1 BIT(24)
45
46#define OB_SIZE 0x030
47#define SPACE0_REMOTE_CFG_OFFSET 0x1000
48#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
49#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
50#define OB_ENABLEN BIT(0)
51#define OB_WIN_SIZE 8 /* 8MB */
52
53/* IRQ register defines */
54#define IRQ_EOI 0x050
55#define IRQ_STATUS 0x184
56#define IRQ_ENABLE_SET 0x188
57#define IRQ_ENABLE_CLR 0x18c
58
59#define MSI_IRQ 0x054
60#define MSI0_IRQ_STATUS 0x104
61#define MSI0_IRQ_ENABLE_SET 0x108
62#define MSI0_IRQ_ENABLE_CLR 0x10c
63#define IRQ_STATUS 0x184
64#define MSI_IRQ_OFFSET 4
65
66#define ERR_IRQ_STATUS 0x1c4
67#define ERR_IRQ_ENABLE_SET 0x1c8
68#define ERR_AER BIT(5) /* ECRC error */
69#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
70#define ERR_CORR BIT(3) /* Correctable error */
71#define ERR_NONFATAL BIT(2) /* Non-fatal error */
72#define ERR_FATAL BIT(1) /* Fatal error */
73#define ERR_SYS BIT(0) /* System error */
74#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
75 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
76
77#define MAX_MSI_HOST_IRQS 8
78/* PCIE controller device IDs */
79#define PCIE_RC_K2HK 0xb008
80#define PCIE_RC_K2E 0xb009
81#define PCIE_RC_K2L 0xb00a
82#define PCIE_RC_K2G 0xb00b
83
84#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
85
86struct keystone_pcie {
87 struct dw_pcie *pci;
88 /* PCI Device ID */
89 u32 device_id;
90 int num_legacy_host_irqs;
91 int legacy_host_irqs[PCI_NUM_INTX];
92 struct device_node *legacy_intc_np;
93
94 int num_msi_host_irqs;
95 int msi_host_irqs[MAX_MSI_HOST_IRQS];
96 int num_lanes;
97 u32 num_viewport;
98 struct phy **phy;
99 struct device_link **link;
100 struct device_node *msi_intc_np;
101 struct irq_domain *legacy_irq_domain;
102 struct device_node *np;
103
104 int error_irq;
105
106 /* Application register space */
107 void __iomem *va_app_base; /* DT 1st resource */
108 struct resource app;
109};
31 110
32/* DEV_STAT_CTRL */ 111static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
33#define PCIE_CAP_BASE 0x70 112 u32 *bit_pos)
113{
114 *reg_offset = offset % 8;
115 *bit_pos = offset >> 3;
116}
34 117
35/* PCIE controller device IDs */ 118static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp)
36#define PCIE_RC_K2HK 0xb008 119{
37#define PCIE_RC_K2E 0xb009 120 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
38#define PCIE_RC_K2L 0xb00a 121 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
122
123 return ks_pcie->app.start + MSI_IRQ;
124}
125
126static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
127{
128 return readl(ks_pcie->va_app_base + offset);
129}
130
131static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
132 u32 val)
133{
134 writel(val, ks_pcie->va_app_base + offset);
135}
136
137static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
138{
139 struct dw_pcie *pci = ks_pcie->pci;
140 struct pcie_port *pp = &pci->pp;
141 struct device *dev = pci->dev;
142 u32 pending, vector;
143 int src, virq;
144
145 pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
146
147 /*
148 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
149 * shows 1, 9, 17, 25 and so forth
150 */
151 for (src = 0; src < 4; src++) {
152 if (BIT(src) & pending) {
153 vector = offset + (src << 3);
154 virq = irq_linear_revmap(pp->irq_domain, vector);
155 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
156 src, vector, virq);
157 generic_handle_irq(virq);
158 }
159 }
160}
161
162static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
163{
164 u32 reg_offset, bit_pos;
165 struct keystone_pcie *ks_pcie;
166 struct dw_pcie *pci;
167
168 pci = to_dw_pcie_from_pp(pp);
169 ks_pcie = to_keystone_pcie(pci);
170 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
171
172 ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
173 BIT(bit_pos));
174 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
175}
176
177static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq)
178{
179 u32 reg_offset, bit_pos;
180 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
181 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
182
183 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
184 ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
185 BIT(bit_pos));
186}
187
188static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
189{
190 u32 reg_offset, bit_pos;
191 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
192 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
193
194 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
195 ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
196 BIT(bit_pos));
197}
198
199static int ks_pcie_msi_host_init(struct pcie_port *pp)
200{
201 return dw_pcie_allocate_domains(pp);
202}
203
204static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
205{
206 int i;
207
208 for (i = 0; i < PCI_NUM_INTX; i++)
209 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
210}
211
212static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
213 int offset)
214{
215 struct dw_pcie *pci = ks_pcie->pci;
216 struct device *dev = pci->dev;
217 u32 pending;
218 int virq;
219
220 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
221
222 if (BIT(0) & pending) {
223 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
224 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
225 generic_handle_irq(virq);
226 }
227
228 /* EOI the INTx interrupt */
229 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
230}
231
232static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
233{
234 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
235}
236
237static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
238{
239 u32 reg;
240 struct device *dev = ks_pcie->pci->dev;
241
242 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS);
243 if (!reg)
244 return IRQ_NONE;
245
246 if (reg & ERR_SYS)
247 dev_err(dev, "System Error\n");
248
249 if (reg & ERR_FATAL)
250 dev_err(dev, "Fatal Error\n");
251
252 if (reg & ERR_NONFATAL)
253 dev_dbg(dev, "Non Fatal Error\n");
254
255 if (reg & ERR_CORR)
256 dev_dbg(dev, "Correctable Error\n");
257
258 if (reg & ERR_AXI)
259 dev_err(dev, "AXI tag lookup fatal Error\n");
260
261 if (reg & ERR_AER)
262 dev_err(dev, "ECRC Error\n");
263
264 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg);
265
266 return IRQ_HANDLED;
267}
268
269static void ks_pcie_ack_legacy_irq(struct irq_data *d)
270{
271}
272
273static void ks_pcie_mask_legacy_irq(struct irq_data *d)
274{
275}
276
277static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
278{
279}
280
281static struct irq_chip ks_pcie_legacy_irq_chip = {
282 .name = "Keystone-PCI-Legacy-IRQ",
283 .irq_ack = ks_pcie_ack_legacy_irq,
284 .irq_mask = ks_pcie_mask_legacy_irq,
285 .irq_unmask = ks_pcie_unmask_legacy_irq,
286};
287
288static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
289 unsigned int irq,
290 irq_hw_number_t hw_irq)
291{
292 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
293 handle_level_irq);
294 irq_set_chip_data(irq, d->host_data);
295
296 return 0;
297}
298
299static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
300 .map = ks_pcie_init_legacy_irq_map,
301 .xlate = irq_domain_xlate_onetwocell,
302};
303
304/**
305 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
306 * registers
307 *
308 * Since modification of dbi_cs2 involves different clock domain, read the
309 * status back to ensure the transition is complete.
310 */
311static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
312{
313 u32 val;
314
315 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
316 val |= DBI_CS2;
317 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
318
319 do {
320 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
321 } while (!(val & DBI_CS2));
322}
323
324/**
325 * ks_pcie_clear_dbi_mode() - Disable DBI mode
326 *
327 * Since modification of dbi_cs2 involves different clock domain, read the
328 * status back to ensure the transition is complete.
329 */
330static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
331{
332 u32 val;
333
334 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
335 val &= ~DBI_CS2;
336 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
337
338 do {
339 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
340 } while (val & DBI_CS2);
341}
342
343static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
344{
345 u32 val;
346 u32 num_viewport = ks_pcie->num_viewport;
347 struct dw_pcie *pci = ks_pcie->pci;
348 struct pcie_port *pp = &pci->pp;
349 u64 start = pp->mem->start;
350 u64 end = pp->mem->end;
351 int i;
352
353 /* Disable BARs for inbound access */
354 ks_pcie_set_dbi_mode(ks_pcie);
355 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
356 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
357 ks_pcie_clear_dbi_mode(ks_pcie);
358
359 val = ilog2(OB_WIN_SIZE);
360 ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
361
362 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
363 for (i = 0; i < num_viewport && (start < end); i++) {
364 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
365 lower_32_bits(start) | OB_ENABLEN);
366 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
367 upper_32_bits(start));
368 start += OB_WIN_SIZE;
369 }
370
371 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
372 val |= OB_XLAT_EN_VAL;
373 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
374}
375
376static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
377 unsigned int devfn, int where, int size,
378 u32 *val)
379{
380 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
381 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
382 u32 reg;
383
384 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
385 CFG_FUNC(PCI_FUNC(devfn));
386 if (bus->parent->number != pp->root_bus_nr)
387 reg |= CFG_TYPE1;
388 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
389
390 return dw_pcie_read(pp->va_cfg0_base + where, size, val);
391}
392
393static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
394 unsigned int devfn, int where, int size,
395 u32 val)
396{
397 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
398 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
399 u32 reg;
400
401 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
402 CFG_FUNC(PCI_FUNC(devfn));
403 if (bus->parent->number != pp->root_bus_nr)
404 reg |= CFG_TYPE1;
405 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
406
407 return dw_pcie_write(pp->va_cfg0_base + where, size, val);
408}
409
410/**
411 * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
412 *
413 * This sets BAR0 to enable inbound access for MSI_IRQ register
414 */
415static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
416{
417 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
418 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
419
420 /* Configure and set up BAR0 */
421 ks_pcie_set_dbi_mode(ks_pcie);
422
423 /* Enable BAR0 */
424 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
425 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
426
427 ks_pcie_clear_dbi_mode(ks_pcie);
428
429 /*
430 * For BAR0, just setting bus address for inbound writes (MSI) should
431 * be sufficient. Use physical address to avoid any conflicts.
432 */
433 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
434}
435
436/**
437 * ks_pcie_link_up() - Check if link up
438 */
439static int ks_pcie_link_up(struct dw_pcie *pci)
440{
441 u32 val;
442
443 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
444 val &= PORT_LOGIC_LTSSM_STATE_MASK;
445 return (val == PORT_LOGIC_LTSSM_STATE_L0);
446}
447
448static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
449{
450 u32 val;
39 451
40#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 452 /* Disable Link training */
453 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
454 val &= ~LTSSM_EN_VAL;
455 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
41 456
42static void quirk_limit_mrrs(struct pci_dev *dev) 457 /* Initiate Link Training */
458 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
459 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
460}
461
462/**
463 * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware
464 *
465 * Ioremap the register resources, initialize legacy irq domain
466 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
467 * PCI host controller.
468 */
469static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie)
470{
471 struct dw_pcie *pci = ks_pcie->pci;
472 struct pcie_port *pp = &pci->pp;
473 struct device *dev = pci->dev;
474 struct platform_device *pdev = to_platform_device(dev);
475 struct resource *res;
476
477 /* Index 0 is the config reg. space address */
478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
479 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
480 if (IS_ERR(pci->dbi_base))
481 return PTR_ERR(pci->dbi_base);
482
483 /*
484 * We set these same and is used in pcie rd/wr_other_conf
485 * functions
486 */
487 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
488 pp->va_cfg1_base = pp->va_cfg0_base;
489
490 /* Index 1 is the application reg. space address */
491 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
492 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
493 if (IS_ERR(ks_pcie->va_app_base))
494 return PTR_ERR(ks_pcie->va_app_base);
495
496 ks_pcie->app = *res;
497
498 /* Create legacy IRQ domain */
499 ks_pcie->legacy_irq_domain =
500 irq_domain_add_linear(ks_pcie->legacy_intc_np,
501 PCI_NUM_INTX,
502 &ks_pcie_legacy_irq_domain_ops,
503 NULL);
504 if (!ks_pcie->legacy_irq_domain) {
505 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
506 return -EINVAL;
507 }
508
509 return dw_pcie_host_init(pp);
510}
511
512static void ks_pcie_quirk(struct pci_dev *dev)
43{ 513{
44 struct pci_bus *bus = dev->bus; 514 struct pci_bus *bus = dev->bus;
45 struct pci_dev *bridge = bus->self; 515 struct pci_dev *bridge;
46 static const struct pci_device_id rc_pci_devids[] = { 516 static const struct pci_device_id rc_pci_devids[] = {
47 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 517 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
48 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 518 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
@@ -50,11 +520,13 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
50 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 520 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
51 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 521 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
52 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 522 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
523 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
524 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
53 { 0, }, 525 { 0, },
54 }; 526 };
55 527
56 if (pci_is_root_bus(bus)) 528 if (pci_is_root_bus(bus))
57 return; 529 bridge = dev;
58 530
59 /* look for the host bridge */ 531 /* look for the host bridge */
60 while (!pci_is_root_bus(bus)) { 532 while (!pci_is_root_bus(bus)) {
@@ -62,43 +534,39 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
62 bus = bus->parent; 534 bus = bus->parent;
63 } 535 }
64 536
65 if (bridge) { 537 if (!bridge)
66 /* 538 return;
67 * Keystone PCI controller has a h/w limitation of 539
68 * 256 bytes maximum read request size. It can't handle 540 /*
69 * anything higher than this. So force this limit on 541 * Keystone PCI controller has a h/w limitation of
70 * all downstream devices. 542 * 256 bytes maximum read request size. It can't handle
71 */ 543 * anything higher than this. So force this limit on
72 if (pci_match_id(rc_pci_devids, bridge)) { 544 * all downstream devices.
73 if (pcie_get_readrq(dev) > 256) { 545 */
74 dev_info(&dev->dev, "limiting MRRS to 256\n"); 546 if (pci_match_id(rc_pci_devids, bridge)) {
75 pcie_set_readrq(dev, 256); 547 if (pcie_get_readrq(dev) > 256) {
76 } 548 dev_info(&dev->dev, "limiting MRRS to 256\n");
549 pcie_set_readrq(dev, 256);
77 } 550 }
78 } 551 }
79} 552}
80DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); 553DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
81 554
82static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) 555static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
83{ 556{
84 struct dw_pcie *pci = ks_pcie->pci; 557 struct dw_pcie *pci = ks_pcie->pci;
85 struct pcie_port *pp = &pci->pp;
86 struct device *dev = pci->dev; 558 struct device *dev = pci->dev;
87 unsigned int retries;
88
89 dw_pcie_setup_rc(pp);
90 559
91 if (dw_pcie_link_up(pci)) { 560 if (dw_pcie_link_up(pci)) {
92 dev_info(dev, "Link already up\n"); 561 dev_info(dev, "Link already up\n");
93 return 0; 562 return 0;
94 } 563 }
95 564
565 ks_pcie_initiate_link_train(ks_pcie);
566
96 /* check if the link is up or not */ 567 /* check if the link is up or not */
97 for (retries = 0; retries < 5; retries++) { 568 if (!dw_pcie_wait_for_link(pci))
98 ks_dw_pcie_initiate_link_train(ks_pcie); 569 return 0;
99 if (!dw_pcie_wait_for_link(pci))
100 return 0;
101 }
102 570
103 dev_err(dev, "phy link never came up\n"); 571 dev_err(dev, "phy link never came up\n");
104 return -ETIMEDOUT; 572 return -ETIMEDOUT;
@@ -121,7 +589,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
121 * ack operation. 589 * ack operation.
122 */ 590 */
123 chained_irq_enter(chip, desc); 591 chained_irq_enter(chip, desc);
124 ks_dw_pcie_handle_msi_irq(ks_pcie, offset); 592 ks_pcie_handle_msi_irq(ks_pcie, offset);
125 chained_irq_exit(chip, desc); 593 chained_irq_exit(chip, desc);
126} 594}
127 595
@@ -150,7 +618,7 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
150 * ack operation. 618 * ack operation.
151 */ 619 */
152 chained_irq_enter(chip, desc); 620 chained_irq_enter(chip, desc);
153 ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset); 621 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
154 chained_irq_exit(chip, desc); 622 chained_irq_exit(chip, desc);
155} 623}
156 624
@@ -222,7 +690,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
222 ks_pcie_legacy_irq_handler, 690 ks_pcie_legacy_irq_handler,
223 ks_pcie); 691 ks_pcie);
224 } 692 }
225 ks_dw_pcie_enable_legacy_irqs(ks_pcie); 693 ks_pcie_enable_legacy_irqs(ks_pcie);
226 694
227 /* MSI IRQ */ 695 /* MSI IRQ */
228 if (IS_ENABLED(CONFIG_PCI_MSI)) { 696 if (IS_ENABLED(CONFIG_PCI_MSI)) {
@@ -234,7 +702,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
234 } 702 }
235 703
236 if (ks_pcie->error_irq > 0) 704 if (ks_pcie->error_irq > 0)
237 ks_dw_pcie_enable_error_irq(ks_pcie); 705 ks_pcie_enable_error_irq(ks_pcie);
238} 706}
239 707
240/* 708/*
@@ -242,8 +710,8 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
242 * bus error instead of returning 0xffffffff. This handler always returns 0 710 * bus error instead of returning 0xffffffff. This handler always returns 0
243 * for this kind of faults. 711 * for this kind of faults.
244 */ 712 */
245static int keystone_pcie_fault(unsigned long addr, unsigned int fsr, 713static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
246 struct pt_regs *regs) 714 struct pt_regs *regs)
247{ 715{
248 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 716 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
249 717
@@ -257,59 +725,78 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
257 return 0; 725 return 0;
258} 726}
259 727
728static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
729{
730 int ret;
731 unsigned int id;
732 struct regmap *devctrl_regs;
733 struct dw_pcie *pci = ks_pcie->pci;
734 struct device *dev = pci->dev;
735 struct device_node *np = dev->of_node;
736
737 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id");
738 if (IS_ERR(devctrl_regs))
739 return PTR_ERR(devctrl_regs);
740
741 ret = regmap_read(devctrl_regs, 0, &id);
742 if (ret)
743 return ret;
744
745 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK);
746 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT);
747
748 return 0;
749}
750
260static int __init ks_pcie_host_init(struct pcie_port *pp) 751static int __init ks_pcie_host_init(struct pcie_port *pp)
261{ 752{
262 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 753 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
263 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 754 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
264 u32 val; 755 int ret;
756
757 dw_pcie_setup_rc(pp);
265 758
266 ks_pcie_establish_link(ks_pcie); 759 ks_pcie_establish_link(ks_pcie);
267 ks_dw_pcie_setup_rc_app_regs(ks_pcie); 760 ks_pcie_setup_rc_app_regs(ks_pcie);
268 ks_pcie_setup_interrupts(ks_pcie); 761 ks_pcie_setup_interrupts(ks_pcie);
269 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 762 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
270 pci->dbi_base + PCI_IO_BASE); 763 pci->dbi_base + PCI_IO_BASE);
271 764
272 /* update the Vendor ID */ 765 ret = ks_pcie_init_id(ks_pcie);
273 writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); 766 if (ret < 0)
274 767 return ret;
275 /* update the DEV_STAT_CTRL to publish right mrrs */
276 val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
277 val &= ~PCI_EXP_DEVCTL_READRQ;
278 /* set the mrrs to 256 bytes */
279 val |= BIT(12);
280 writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
281 768
282 /* 769 /*
283 * PCIe access errors that result into OCP errors are caught by ARM as 770 * PCIe access errors that result into OCP errors are caught by ARM as
284 * "External aborts" 771 * "External aborts"
285 */ 772 */
286 hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0, 773 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
287 "Asynchronous external abort"); 774 "Asynchronous external abort");
288 775
289 return 0; 776 return 0;
290} 777}
291 778
292static const struct dw_pcie_host_ops keystone_pcie_host_ops = { 779static const struct dw_pcie_host_ops ks_pcie_host_ops = {
293 .rd_other_conf = ks_dw_pcie_rd_other_conf, 780 .rd_other_conf = ks_pcie_rd_other_conf,
294 .wr_other_conf = ks_dw_pcie_wr_other_conf, 781 .wr_other_conf = ks_pcie_wr_other_conf,
295 .host_init = ks_pcie_host_init, 782 .host_init = ks_pcie_host_init,
296 .msi_set_irq = ks_dw_pcie_msi_set_irq, 783 .msi_set_irq = ks_pcie_msi_set_irq,
297 .msi_clear_irq = ks_dw_pcie_msi_clear_irq, 784 .msi_clear_irq = ks_pcie_msi_clear_irq,
298 .get_msi_addr = ks_dw_pcie_get_msi_addr, 785 .get_msi_addr = ks_pcie_get_msi_addr,
299 .msi_host_init = ks_dw_pcie_msi_host_init, 786 .msi_host_init = ks_pcie_msi_host_init,
300 .msi_irq_ack = ks_dw_pcie_msi_irq_ack, 787 .msi_irq_ack = ks_pcie_msi_irq_ack,
301 .scan_bus = ks_dw_pcie_v3_65_scan_bus, 788 .scan_bus = ks_pcie_v3_65_scan_bus,
302}; 789};
303 790
304static irqreturn_t pcie_err_irq_handler(int irq, void *priv) 791static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
305{ 792{
306 struct keystone_pcie *ks_pcie = priv; 793 struct keystone_pcie *ks_pcie = priv;
307 794
308 return ks_dw_pcie_handle_error_irq(ks_pcie); 795 return ks_pcie_handle_error_irq(ks_pcie);
309} 796}
310 797
311static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, 798static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
312 struct platform_device *pdev) 799 struct platform_device *pdev)
313{ 800{
314 struct dw_pcie *pci = ks_pcie->pci; 801 struct dw_pcie *pci = ks_pcie->pci;
315 struct pcie_port *pp = &pci->pp; 802 struct pcie_port *pp = &pci->pp;
@@ -338,7 +825,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
338 if (ks_pcie->error_irq <= 0) 825 if (ks_pcie->error_irq <= 0)
339 dev_info(dev, "no error IRQ defined\n"); 826 dev_info(dev, "no error IRQ defined\n");
340 else { 827 else {
341 ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler, 828 ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler,
342 IRQF_SHARED, "pcie-error-irq", ks_pcie); 829 IRQF_SHARED, "pcie-error-irq", ks_pcie);
343 if (ret < 0) { 830 if (ret < 0) {
344 dev_err(dev, "failed to request error IRQ %d\n", 831 dev_err(dev, "failed to request error IRQ %d\n",
@@ -347,8 +834,8 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
347 } 834 }
348 } 835 }
349 836
350 pp->ops = &keystone_pcie_host_ops; 837 pp->ops = &ks_pcie_host_ops;
351 ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); 838 ret = ks_pcie_dw_host_init(ks_pcie);
352 if (ret) { 839 if (ret) {
353 dev_err(dev, "failed to initialize host\n"); 840 dev_err(dev, "failed to initialize host\n");
354 return ret; 841 return ret;
@@ -365,28 +852,62 @@ static const struct of_device_id ks_pcie_of_match[] = {
365 { }, 852 { },
366}; 853};
367 854
368static const struct dw_pcie_ops dw_pcie_ops = { 855static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
369 .link_up = ks_dw_pcie_link_up, 856 .link_up = ks_pcie_link_up,
370}; 857};
371 858
372static int __exit ks_pcie_remove(struct platform_device *pdev) 859static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
373{ 860{
374 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 861 int num_lanes = ks_pcie->num_lanes;
375 862
376 clk_disable_unprepare(ks_pcie->clk); 863 while (num_lanes--) {
864 phy_power_off(ks_pcie->phy[num_lanes]);
865 phy_exit(ks_pcie->phy[num_lanes]);
866 }
867}
868
869static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie)
870{
871 int i;
872 int ret;
873 int num_lanes = ks_pcie->num_lanes;
874
875 for (i = 0; i < num_lanes; i++) {
876 ret = phy_init(ks_pcie->phy[i]);
877 if (ret < 0)
878 goto err_phy;
879
880 ret = phy_power_on(ks_pcie->phy[i]);
881 if (ret < 0) {
882 phy_exit(ks_pcie->phy[i]);
883 goto err_phy;
884 }
885 }
377 886
378 return 0; 887 return 0;
888
889err_phy:
890 while (--i >= 0) {
891 phy_power_off(ks_pcie->phy[i]);
892 phy_exit(ks_pcie->phy[i]);
893 }
894
895 return ret;
379} 896}
380 897
381static int __init ks_pcie_probe(struct platform_device *pdev) 898static int __init ks_pcie_probe(struct platform_device *pdev)
382{ 899{
383 struct device *dev = &pdev->dev; 900 struct device *dev = &pdev->dev;
901 struct device_node *np = dev->of_node;
384 struct dw_pcie *pci; 902 struct dw_pcie *pci;
385 struct keystone_pcie *ks_pcie; 903 struct keystone_pcie *ks_pcie;
386 struct resource *res; 904 struct device_link **link;
387 void __iomem *reg_p; 905 u32 num_viewport;
388 struct phy *phy; 906 struct phy **phy;
907 u32 num_lanes;
908 char name[10];
389 int ret; 909 int ret;
910 int i;
390 911
391 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 912 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
392 if (!ks_pcie) 913 if (!ks_pcie)
@@ -397,54 +918,99 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
397 return -ENOMEM; 918 return -ENOMEM;
398 919
399 pci->dev = dev; 920 pci->dev = dev;
400 pci->ops = &dw_pcie_ops; 921 pci->ops = &ks_pcie_dw_pcie_ops;
401 922
402 ks_pcie->pci = pci; 923 ret = of_property_read_u32(np, "num-viewport", &num_viewport);
924 if (ret < 0) {
925 dev_err(dev, "unable to read *num-viewport* property\n");
926 return ret;
927 }
403 928
404 /* initialize SerDes Phy if present */ 929 ret = of_property_read_u32(np, "num-lanes", &num_lanes);
405 phy = devm_phy_get(dev, "pcie-phy"); 930 if (ret)
406 if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER) 931 num_lanes = 1;
407 return PTR_ERR(phy);
408 932
409 if (!IS_ERR_OR_NULL(phy)) { 933 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL);
410 ret = phy_init(phy); 934 if (!phy)
411 if (ret < 0) 935 return -ENOMEM;
412 return ret; 936
937 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL);
938 if (!link)
939 return -ENOMEM;
940
941 for (i = 0; i < num_lanes; i++) {
942 snprintf(name, sizeof(name), "pcie-phy%d", i);
943 phy[i] = devm_phy_optional_get(dev, name);
944 if (IS_ERR(phy[i])) {
945 ret = PTR_ERR(phy[i]);
946 goto err_link;
947 }
948
949 if (!phy[i])
950 continue;
951
952 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
953 if (!link[i]) {
954 ret = -EINVAL;
955 goto err_link;
956 }
413 } 957 }
414 958
415 /* index 2 is to read PCI DEVICE_ID */ 959 ks_pcie->np = np;
416 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 960 ks_pcie->pci = pci;
417 reg_p = devm_ioremap_resource(dev, res); 961 ks_pcie->link = link;
418 if (IS_ERR(reg_p)) 962 ks_pcie->num_lanes = num_lanes;
419 return PTR_ERR(reg_p); 963 ks_pcie->num_viewport = num_viewport;
420 ks_pcie->device_id = readl(reg_p) >> 16; 964 ks_pcie->phy = phy;
421 devm_iounmap(dev, reg_p);
422 devm_release_mem_region(dev, res->start, resource_size(res));
423 965
424 ks_pcie->np = dev->of_node; 966 ret = ks_pcie_enable_phy(ks_pcie);
425 platform_set_drvdata(pdev, ks_pcie); 967 if (ret) {
426 ks_pcie->clk = devm_clk_get(dev, "pcie"); 968 dev_err(dev, "failed to enable phy\n");
427 if (IS_ERR(ks_pcie->clk)) { 969 goto err_link;
428 dev_err(dev, "Failed to get pcie rc clock\n");
429 return PTR_ERR(ks_pcie->clk);
430 } 970 }
431 ret = clk_prepare_enable(ks_pcie->clk);
432 if (ret)
433 return ret;
434 971
435 platform_set_drvdata(pdev, ks_pcie); 972 platform_set_drvdata(pdev, ks_pcie);
973 pm_runtime_enable(dev);
974 ret = pm_runtime_get_sync(dev);
975 if (ret < 0) {
976 dev_err(dev, "pm_runtime_get_sync failed\n");
977 goto err_get_sync;
978 }
436 979
437 ret = ks_add_pcie_port(ks_pcie, pdev); 980 ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
438 if (ret < 0) 981 if (ret < 0)
439 goto fail_clk; 982 goto err_get_sync;
440 983
441 return 0; 984 return 0;
442fail_clk: 985
443 clk_disable_unprepare(ks_pcie->clk); 986err_get_sync:
987 pm_runtime_put(dev);
988 pm_runtime_disable(dev);
989 ks_pcie_disable_phy(ks_pcie);
990
991err_link:
992 while (--i >= 0 && link[i])
993 device_link_del(link[i]);
444 994
445 return ret; 995 return ret;
446} 996}
447 997
998static int __exit ks_pcie_remove(struct platform_device *pdev)
999{
1000 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
1001 struct device_link **link = ks_pcie->link;
1002 int num_lanes = ks_pcie->num_lanes;
1003 struct device *dev = &pdev->dev;
1004
1005 pm_runtime_put(dev);
1006 pm_runtime_disable(dev);
1007 ks_pcie_disable_phy(ks_pcie);
1008 while (num_lanes--)
1009 device_link_del(link[num_lanes]);
1010
1011 return 0;
1012}
1013
448static struct platform_driver ks_pcie_driver __refdata = { 1014static struct platform_driver ks_pcie_driver __refdata = {
449 .probe = ks_pcie_probe, 1015 .probe = ks_pcie_probe,
450 .remove = __exit_p(ks_pcie_remove), 1016 .remove = __exit_p(ks_pcie_remove),
diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h
deleted file mode 100644
index 8a13da391543..000000000000
--- a/drivers/pci/controller/dwc/pci-keystone.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Keystone PCI Controller's common includes
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * http://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 */
10
11#define MAX_MSI_HOST_IRQS 8
12
13struct keystone_pcie {
14 struct dw_pcie *pci;
15 struct clk *clk;
16 /* PCI Device ID */
17 u32 device_id;
18 int num_legacy_host_irqs;
19 int legacy_host_irqs[PCI_NUM_INTX];
20 struct device_node *legacy_intc_np;
21
22 int num_msi_host_irqs;
23 int msi_host_irqs[MAX_MSI_HOST_IRQS];
24 struct device_node *msi_intc_np;
25 struct irq_domain *legacy_irq_domain;
26 struct device_node *np;
27
28 int error_irq;
29
30 /* Application register space */
31 void __iomem *va_app_base; /* DT 1st resource */
32 struct resource app;
33};
34
35/* Keystone DW specific MSI controller APIs/definitions */
36void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
37phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
38
39/* Keystone specific PCI controller APIs */
40void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
41void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
42void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
43irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
44int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
45 struct device_node *msi_intc_np);
46int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
47 unsigned int devfn, int where, int size, u32 val);
48int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
49 unsigned int devfn, int where, int size, u32 *val);
50void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
51void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
52void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
53void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
54void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
55void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
56int ks_dw_pcie_msi_host_init(struct pcie_port *pp);
57int ks_dw_pcie_link_up(struct dw_pcie *pci);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 96126fd8403c..a4d939536faf 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -37,6 +37,10 @@
37#define PORT_LINK_MODE_4_LANES (0x7 << 16) 37#define PORT_LINK_MODE_4_LANES (0x7 << 16)
38#define PORT_LINK_MODE_8_LANES (0xf << 16) 38#define PORT_LINK_MODE_8_LANES (0xf << 16)
39 39
40#define PCIE_PORT_DEBUG0 0x728
41#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
42#define PORT_LOGIC_LTSSM_STATE_L0 0x11
43
40#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 44#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
41#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 45#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
42#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 46#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 14:10:58 -0400