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authorVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>2016-09-09 10:25:22 -0400
committerKalle Valo <kvalo@qca.qualcomm.com>2016-09-13 08:30:57 -0400
commitae02c8719aab19bf311b6ce2881feb844456297e (patch)
tree53f6b88d685d68a2c43ca02e3c04b8cd8e840eea /drivers/net/wireless/ath/ath10k
parent43d923e2c192ecef19447dc2b0ca0bab6d8b1f64 (diff)
ath10k: add provision for Rx descriptor abstraction
There are slight differences in Rx hw descriptor information among different chips. So far driver does not use those new information for any functionalities, but there is one important information which is available from QCA99X0 onwards to indicate the number of bytes that hw padded at the begining of the rx payload and this information is needed to undecap the rx packet. Add an abstraction for Rx desc to make use of the new desc information available. The callback that this patch defines to retrieve the padding bytes will be used in follow-up patch. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath10k')
-rw-r--r--drivers/net/wireless/ath/ath10k/core.c12
-rw-r--r--drivers/net/wireless/ath/ath10k/hw.c13
-rw-r--r--drivers/net/wireless/ath/ath10k/hw.h12
3 files changed, 37 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index e859ca626ca0..2d405a6c3375 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -68,6 +68,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
68 .board_size = QCA988X_BOARD_DATA_SZ, 68 .board_size = QCA988X_BOARD_DATA_SZ,
69 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 69 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
70 }, 70 },
71 .hw_ops = &qca988x_ops,
71 }, 72 },
72 { 73 {
73 .id = QCA9887_HW_1_0_VERSION, 74 .id = QCA9887_HW_1_0_VERSION,
@@ -87,6 +88,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
87 .board_size = QCA9887_BOARD_DATA_SZ, 88 .board_size = QCA9887_BOARD_DATA_SZ,
88 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 89 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
89 }, 90 },
91 .hw_ops = &qca988x_ops,
90 }, 92 },
91 { 93 {
92 .id = QCA6174_HW_2_1_VERSION, 94 .id = QCA6174_HW_2_1_VERSION,
@@ -104,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
104 .board_size = QCA6174_BOARD_DATA_SZ, 106 .board_size = QCA6174_BOARD_DATA_SZ,
105 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 107 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
106 }, 108 },
109 .hw_ops = &qca988x_ops,
107 }, 110 },
108 { 111 {
109 .id = QCA6174_HW_2_1_VERSION, 112 .id = QCA6174_HW_2_1_VERSION,
@@ -122,6 +125,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
122 .board_size = QCA6174_BOARD_DATA_SZ, 125 .board_size = QCA6174_BOARD_DATA_SZ,
123 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 126 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
124 }, 127 },
128 .hw_ops = &qca988x_ops,
125 }, 129 },
126 { 130 {
127 .id = QCA6174_HW_3_0_VERSION, 131 .id = QCA6174_HW_3_0_VERSION,
@@ -140,6 +144,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
140 .board_size = QCA6174_BOARD_DATA_SZ, 144 .board_size = QCA6174_BOARD_DATA_SZ,
141 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 145 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
142 }, 146 },
147 .hw_ops = &qca988x_ops,
143 }, 148 },
144 { 149 {
145 .id = QCA6174_HW_3_2_VERSION, 150 .id = QCA6174_HW_3_2_VERSION,
@@ -159,6 +164,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
159 .board_size = QCA6174_BOARD_DATA_SZ, 164 .board_size = QCA6174_BOARD_DATA_SZ,
160 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 165 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
161 }, 166 },
167 .hw_ops = &qca988x_ops,
162 }, 168 },
163 { 169 {
164 .id = QCA99X0_HW_2_0_DEV_VERSION, 170 .id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -183,6 +189,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
183 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 189 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
184 }, 190 },
185 .sw_decrypt_mcast_mgmt = true, 191 .sw_decrypt_mcast_mgmt = true,
192 .hw_ops = &qca99x0_ops,
186 }, 193 },
187 { 194 {
188 .id = QCA9984_HW_1_0_DEV_VERSION, 195 .id = QCA9984_HW_1_0_DEV_VERSION,
@@ -207,6 +214,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
207 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 214 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
208 }, 215 },
209 .sw_decrypt_mcast_mgmt = true, 216 .sw_decrypt_mcast_mgmt = true,
217 .hw_ops = &qca99x0_ops,
210 }, 218 },
211 { 219 {
212 .id = QCA9888_HW_2_0_DEV_VERSION, 220 .id = QCA9888_HW_2_0_DEV_VERSION,
@@ -230,6 +238,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
230 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 238 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
231 }, 239 },
232 .sw_decrypt_mcast_mgmt = true, 240 .sw_decrypt_mcast_mgmt = true,
241 .hw_ops = &qca99x0_ops,
233 }, 242 },
234 { 243 {
235 .id = QCA9377_HW_1_0_DEV_VERSION, 244 .id = QCA9377_HW_1_0_DEV_VERSION,
@@ -247,6 +256,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
247 .board_size = QCA9377_BOARD_DATA_SZ, 256 .board_size = QCA9377_BOARD_DATA_SZ,
248 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 257 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
249 }, 258 },
259 .hw_ops = &qca988x_ops,
250 }, 260 },
251 { 261 {
252 .id = QCA9377_HW_1_1_DEV_VERSION, 262 .id = QCA9377_HW_1_1_DEV_VERSION,
@@ -264,6 +274,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
264 .board_size = QCA9377_BOARD_DATA_SZ, 274 .board_size = QCA9377_BOARD_DATA_SZ,
265 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 275 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
266 }, 276 },
277 .hw_ops = &qca988x_ops,
267 }, 278 },
268 { 279 {
269 .id = QCA4019_HW_1_0_DEV_VERSION, 280 .id = QCA4019_HW_1_0_DEV_VERSION,
@@ -289,6 +300,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
289 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 300 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
290 }, 301 },
291 .sw_decrypt_mcast_mgmt = true, 302 .sw_decrypt_mcast_mgmt = true,
303 .hw_ops = &qca99x0_ops,
292 }, 304 },
293}; 305};
294 306
diff --git a/drivers/net/wireless/ath/ath10k/hw.c b/drivers/net/wireless/ath/ath10k/hw.c
index f903d468dbe6..c2ecb9bd824a 100644
--- a/drivers/net/wireless/ath/ath10k/hw.c
+++ b/drivers/net/wireless/ath/ath10k/hw.c
@@ -219,3 +219,16 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
219 survey->time = CCNT_TO_MSEC(ar, cc); 219 survey->time = CCNT_TO_MSEC(ar, cc);
220 survey->time_busy = CCNT_TO_MSEC(ar, rcc); 220 survey->time_busy = CCNT_TO_MSEC(ar, rcc);
221} 221}
222
223const struct ath10k_hw_ops qca988x_ops = {
224};
225
226static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
227{
228 return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
229 RX_MSDU_END_INFO1_L3_HDR_PAD);
230}
231
232const struct ath10k_hw_ops qca99x0_ops = {
233 .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
234};
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index af0d5d1e8213..1b5ea3147f3a 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -414,8 +414,20 @@ struct ath10k_hw_params {
414 * frames encrypted and expect software do decryption. 414 * frames encrypted and expect software do decryption.
415 */ 415 */
416 bool sw_decrypt_mcast_mgmt; 416 bool sw_decrypt_mcast_mgmt;
417
418 const struct ath10k_hw_ops *hw_ops;
417}; 419};
418 420
421struct htt_rx_desc;
422
423/* Defines needed for Rx descriptor abstraction */
424struct ath10k_hw_ops {
425 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
426};
427
428extern const struct ath10k_hw_ops qca988x_ops;
429extern const struct ath10k_hw_ops qca99x0_ops;
430
419/* Target specific defines for MAIN firmware */ 431/* Target specific defines for MAIN firmware */
420#define TARGET_NUM_VDEVS 8 432#define TARGET_NUM_VDEVS 8
421#define TARGET_NUM_PEER_AST 2 433#define TARGET_NUM_PEER_AST 2