ath10k: move ath10k_hw_params definition to hw.h

This is to prepare for rx descriptor abstraction where we'll
be dereferencing ath10k_hw_params member in hw.h. Moreover
hw.h looks more suitable to house ath10k_hw_params definition
than core.h

Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>

2 files changed, 54 insertions, 52 deletions

diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h
index c22391394ad1..6ec9495bcc04 100644
--- a/drivers/net/wireless/ath/ath10k/core.h
+++ b/drivers/net/wireless/ath/ath10k/core.h
@@ -736,58 +736,7 @@ struct ath10k {
         struct ath10k_htc htc;
         struct ath10k_htt htt;
 
-        struct ath10k_hw_params {
-                u32 id;
-                u16 dev_id;
-                const char *name;
-                u32 patch_load_addr;
-                int uart_pin;
-                u32 otp_exe_param;
-
-                /* Type of hw cycle counter wraparound logic, for more info
-                 * refer enum ath10k_hw_cc_wraparound_type.
-                 */
-                enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
-
-                /* Some of chip expects fragment descriptor to be continuous
-                 * memory for any TX operation. Set continuous_frag_desc flag
-                 * for the hardware which have such requirement.
-                 */
-                bool continuous_frag_desc;
-
-                /* CCK hardware rate table mapping for the newer chipsets
-                 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
-                 * are in a proper order with respect to the rate/preamble
-                 */
-                bool cck_rate_map_rev2;
-
-                u32 channel_counters_freq_hz;
-
-                /* Mgmt tx descriptors threshold for limiting probe response
-                 * frames.
-                 */
-                u32 max_probe_resp_desc_thres;
-
-                /* The padding bytes's location is different on various chips */
-                enum ath10k_hw_4addr_pad hw_4addr_pad;
-
-                u32 tx_chain_mask;
-                u32 rx_chain_mask;
-                u32 max_spatial_stream;
-                u32 cal_data_len;
-
-                struct ath10k_hw_params_fw {
-                        const char *dir;
-                        const char *board;
-                        size_t board_size;
-                        size_t board_ext_size;
-                } fw;
-
-                /* qca99x0 family chips deliver broadcast/multicast management
-                 * frames encrypted and expect software do decryption.
-                 */
-                bool sw_decrypt_mcast_mgmt;
-        } hw_params;
+        struct ath10k_hw_params hw_params;
 
         /* contains the firmware images used with ATH10K_FIRMWARE_MODE_NORMAL */
         struct ath10k_fw_components normal_mode_fw;
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index e014cd732a0d..af0d5d1e8213 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -363,6 +363,59 @@ enum ath10k_hw_cc_wraparound_type {
         ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
 };
 
+struct ath10k_hw_params {
+        u32 id;
+        u16 dev_id;
+        const char *name;
+        u32 patch_load_addr;
+        int uart_pin;
+        u32 otp_exe_param;
+
+        /* Type of hw cycle counter wraparound logic, for more info
+         * refer enum ath10k_hw_cc_wraparound_type.
+         */
+        enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
+
+        /* Some of chip expects fragment descriptor to be continuous
+         * memory for any TX operation. Set continuous_frag_desc flag
+         * for the hardware which have such requirement.
+         */
+        bool continuous_frag_desc;
+
+        /* CCK hardware rate table mapping for the newer chipsets
+         * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
+         * are in a proper order with respect to the rate/preamble
+         */
+        bool cck_rate_map_rev2;
+
+        u32 channel_counters_freq_hz;
+
+        /* Mgmt tx descriptors threshold for limiting probe response
+         * frames.
+         */
+        u32 max_probe_resp_desc_thres;
+
+        /* The padding bytes's location is different on various chips */
+        enum ath10k_hw_4addr_pad hw_4addr_pad;
+
+        u32 tx_chain_mask;
+        u32 rx_chain_mask;
+        u32 max_spatial_stream;
+        u32 cal_data_len;
+
+        struct ath10k_hw_params_fw {
+                const char *dir;
+                const char *board;
+                size_t board_size;
+                size_t board_ext_size;
+        } fw;
+
+        /* qca99x0 family chips deliver broadcast/multicast management
+         * frames encrypted and expect software do decryption.
+         */
+        bool sw_decrypt_mcast_mgmt;
+};
+
 /* Target specific defines for MAIN firmware */
 #define TARGET_NUM_VDEVS                        8
 #define TARGET_NUM_PEER_AST                     2