drm/i915/icl: apply Display WA #1178 to fix type C dongles

Display WA #1178 is meant to fix Aux channel voltage swing too low with
some type C dongles. It applies to external ports on combo phy. On
Icelake this is port A and B when those are not eDP.

v2: follow the spec to the letter: include Aux A and just check if it's
    not eDP instead of checking only for Aux B.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181012215758.25342-1-lucas.demarchi@intel.com

2 files changed, 18 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e13e51fee47..f8f5c85098b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8934,6 +8934,15 @@ enum skl_power_gate {
 #define   CNL_AUX_ANAOVRD1_ENABLE       (1 << 16)
 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 23)
 
+#define _ICL_AUX_REG_IDX(pw_idx)        ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
+#define _ICL_AUX_ANAOVRD1_A             0x162398
+#define _ICL_AUX_ANAOVRD1_B             0x6C398
+#define ICL_AUX_ANAOVRD1(pw_idx)        _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
+                                                    _ICL_AUX_ANAOVRD1_A, \
+                                                    _ICL_AUX_ANAOVRD1_B))
+#define   ICL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 7)
+#define   ICL_AUX_ANAOVRD1_ENABLE       (1 << 0)
+
 /* HDCP Key Registers */
 #define HDCP_KEY_CONF                   _MMIO(0x66c00)
 #define  HDCP_AKSV_SEND_TRIGGER         BIT(31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3cf8533e0834..31a49bdcf193 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -436,6 +436,15 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
         I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
 
         hsw_wait_for_power_well_enable(dev_priv, power_well);
+
+        /* Display WA #1178: icl */
+        if (IS_ICELAKE(dev_priv) &&
+            pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+            !intel_bios_is_port_edp(dev_priv, port)) {
+                val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
+                val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
+                I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
+        }
 }
 
 static void