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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h9
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c9
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e13e51fee47..f8f5c85098b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8934,6 +8934,15 @@ enum skl_power_gate {
8934#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 8934#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
8935#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 8935#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
8936 8936
8937#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
8938#define _ICL_AUX_ANAOVRD1_A 0x162398
8939#define _ICL_AUX_ANAOVRD1_B 0x6C398
8940#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
8941 _ICL_AUX_ANAOVRD1_A, \
8942 _ICL_AUX_ANAOVRD1_B))
8943#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
8944#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
8945
8937/* HDCP Key Registers */ 8946/* HDCP Key Registers */
8938#define HDCP_KEY_CONF _MMIO(0x66c00) 8947#define HDCP_KEY_CONF _MMIO(0x66c00)
8939#define HDCP_AKSV_SEND_TRIGGER BIT(31) 8948#define HDCP_AKSV_SEND_TRIGGER BIT(31)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3cf8533e0834..31a49bdcf193 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -436,6 +436,15 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
436 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); 436 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
437 437
438 hsw_wait_for_power_well_enable(dev_priv, power_well); 438 hsw_wait_for_power_well_enable(dev_priv, power_well);
439
440 /* Display WA #1178: icl */
441 if (IS_ICELAKE(dev_priv) &&
442 pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
443 !intel_bios_is_port_edp(dev_priv, port)) {
444 val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
445 val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
446 I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
447 }
439} 448}
440 449
441static void 450static void