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authorRex Zhu <Rex.Zhu@amd.com>2017-09-04 06:22:02 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-18 23:30:33 -0400
commit698f88e697cc8852558d120fdecfdb38c18c2ff7 (patch)
tree0b269e308fd514a7363649294f024f35c9191f77 /drivers/gpu
parentcf2623d951c1c52923a776e01cf2e2afc9d042a0 (diff)
drm/amd/powerplay: delete dead code in powerplay
delete functiontable related codes Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/Makefile2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c3
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c161
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c93
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c12
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c3
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c3
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h49
9 files changed, 22 insertions, 310 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 79119d6cd07f..dc4bbcfe1243 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the 'hw manager' sub-component of powerplay. 2# Makefile for the 'hw manager' sub-component of powerplay.
3# It provides the hardware management services for the driver. 3# It provides the hardware management services for the driver.
4 4
5HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ 5HARDWARE_MGR = hwmgr.o processpptables.o \
6 hardwaremanager.o pp_acpi.o cz_hwmgr.o \ 6 hardwaremanager.o pp_acpi.o cz_hwmgr.o \
7 cz_clockpowergating.o pppcielanes.o\ 7 cz_clockpowergating.o pppcielanes.o\
8 process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \ 8 process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 7efe00881aa8..d3b46462072d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1142,8 +1142,7 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1142 return -ENOMEM; 1142 return -ENOMEM;
1143 1143
1144 hwmgr->backend = data; 1144 hwmgr->backend = data;
1145 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1145
1146 PHM_PlatformCaps_TablelessHardwareInterface);
1147 result = cz_initialize_dpm_defaults(hwmgr); 1146 result = cz_initialize_dpm_defaults(hwmgr);
1148 if (result != 0) { 1147 if (result != 0) {
1149 pr_err("cz_initialize_dpm_defaults failed\n"); 1148 pr_err("cz_initialize_dpm_defaults failed\n");
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
deleted file mode 100644
index bc7d8bd7e7cb..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include "hwmgr.h"
27
28static int phm_run_table(struct pp_hwmgr *hwmgr,
29 struct phm_runtime_table_header *rt_table,
30 void *input,
31 void *output,
32 void *temp_storage)
33{
34 int result = 0;
35 phm_table_function *function;
36
37 if (rt_table->function_list == NULL) {
38 pr_debug("this function not implement!\n");
39 return 0;
40 }
41
42 for (function = rt_table->function_list; NULL != *function; function++) {
43 int tmp = (*function)(hwmgr, input, output, temp_storage, result);
44
45 if (tmp == PP_Result_TableImmediateExit)
46 break;
47 if (tmp) {
48 if (0 == result)
49 result = tmp;
50 if (rt_table->exit_error)
51 break;
52 }
53 }
54
55 return result;
56}
57
58int phm_dispatch_table(struct pp_hwmgr *hwmgr,
59 struct phm_runtime_table_header *rt_table,
60 void *input, void *output)
61{
62 int result;
63 void *temp_storage;
64
65 if (hwmgr == NULL || rt_table == NULL) {
66 pr_err("Invalid Parameter!\n");
67 return -EINVAL;
68 }
69
70 if (0 != rt_table->storage_size) {
71 temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
72 if (temp_storage == NULL) {
73 pr_err("Could not allocate table temporary storage\n");
74 return -ENOMEM;
75 }
76 } else {
77 temp_storage = NULL;
78 }
79
80 result = phm_run_table(hwmgr, rt_table, input, output, temp_storage);
81
82 kfree(temp_storage);
83
84 return result;
85}
86
87int phm_construct_table(struct pp_hwmgr *hwmgr,
88 const struct phm_master_table_header *master_table,
89 struct phm_runtime_table_header *rt_table)
90{
91 uint32_t function_count = 0;
92 const struct phm_master_table_item *table_item;
93 uint32_t size;
94 phm_table_function *run_time_list;
95 phm_table_function *rtf;
96
97 if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
98 pr_err("Invalid Parameter!\n");
99 return -EINVAL;
100 }
101
102 for (table_item = master_table->master_list;
103 NULL != table_item->tableFunction; table_item++) {
104 if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
105 (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
106 function_count++;
107 }
108
109 size = (function_count + 1) * sizeof(phm_table_function);
110 run_time_list = kzalloc(size, GFP_KERNEL);
111
112 if (NULL == run_time_list)
113 return -ENOMEM;
114
115 rtf = run_time_list;
116 for (table_item = master_table->master_list;
117 NULL != table_item->tableFunction; table_item++) {
118 if ((rtf - run_time_list) > function_count) {
119 pr_err("Check function results have changed\n");
120 kfree(run_time_list);
121 return -EINVAL;
122 }
123
124 if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
125 (table_item->isFunctionNeededInRuntimeTable(hwmgr))) {
126 *(rtf++) = table_item->tableFunction;
127 }
128 }
129
130 if ((rtf - run_time_list) > function_count) {
131 pr_err("Check function results have changed\n");
132 kfree(run_time_list);
133 return -EINVAL;
134 }
135
136 *rtf = NULL;
137 rt_table->function_list = run_time_list;
138 rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError));
139 rt_table->storage_size = master_table->storage_size;
140 return 0;
141}
142
143int phm_destroy_table(struct pp_hwmgr *hwmgr,
144 struct phm_runtime_table_header *rt_table)
145{
146 if (hwmgr == NULL || rt_table == NULL) {
147 pr_err("Invalid Parameter\n");
148 return -EINVAL;
149 }
150
151 if (NULL == rt_table->function_list)
152 return 0;
153
154 kfree(rt_table->function_list);
155
156 rt_table->function_list = NULL;
157 rt_table->storage_size = 0;
158 rt_table->exit_error = false;
159
160 return 0;
161}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index a3991c0dff2e..fa4fbc25ebe1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -36,29 +36,12 @@
36 return -EINVAL; \ 36 return -EINVAL; \
37 } while (0) 37 } while (0)
38 38
39bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
40{
41 return hwmgr->block_hw_access;
42}
43
44int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
45{
46 hwmgr->block_hw_access = block;
47 return 0;
48}
49
50int phm_setup_asic(struct pp_hwmgr *hwmgr) 39int phm_setup_asic(struct pp_hwmgr *hwmgr)
51{ 40{
52 PHM_FUNC_CHECK(hwmgr); 41 PHM_FUNC_CHECK(hwmgr);
53 42
54 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 43 if (NULL != hwmgr->hwmgr_func->asic_setup)
55 PHM_PlatformCaps_TablelessHardwareInterface)) { 44 return hwmgr->hwmgr_func->asic_setup(hwmgr);
56 if (NULL != hwmgr->hwmgr_func->asic_setup)
57 return hwmgr->hwmgr_func->asic_setup(hwmgr);
58 } else {
59 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
60 NULL, NULL);
61 }
62 45
63 return 0; 46 return 0;
64} 47}
@@ -67,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr)
67{ 50{
68 PHM_FUNC_CHECK(hwmgr); 51 PHM_FUNC_CHECK(hwmgr);
69 52
70 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 53 if (NULL != hwmgr->hwmgr_func->power_off_asic)
71 PHM_PlatformCaps_TablelessHardwareInterface)) { 54 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
72 if (NULL != hwmgr->hwmgr_func->power_off_asic)
73 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
74 } else {
75 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
76 NULL, NULL);
77 }
78 55
79 return 0; 56 return 0;
80} 57}
@@ -90,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
90 states.pcurrent_state = pcurrent_state; 67 states.pcurrent_state = pcurrent_state;
91 states.pnew_state = pnew_power_state; 68 states.pnew_state = pnew_power_state;
92 69
93 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 70 if (NULL != hwmgr->hwmgr_func->power_state_set)
94 PHM_PlatformCaps_TablelessHardwareInterface)) { 71 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
95 if (NULL != hwmgr->hwmgr_func->power_state_set)
96 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
97 } else {
98 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
99 }
100 72
101 return 0; 73 return 0;
102} 74}
@@ -107,15 +79,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
107 bool enabled; 79 bool enabled;
108 PHM_FUNC_CHECK(hwmgr); 80 PHM_FUNC_CHECK(hwmgr);
109 81
110 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 82 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
111 PHM_PlatformCaps_TablelessHardwareInterface)) { 83 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
112 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
113 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
114 } else {
115 ret = phm_dispatch_table(hwmgr,
116 &(hwmgr->enable_dynamic_state_management),
117 NULL, NULL);
118 }
119 84
120 enabled = ret == 0; 85 enabled = ret == 0;
121 86
@@ -131,15 +96,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
131 96
132 PHM_FUNC_CHECK(hwmgr); 97 PHM_FUNC_CHECK(hwmgr);
133 98
134 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 99 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
135 PHM_PlatformCaps_TablelessHardwareInterface)) { 100 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
136 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
137 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
138 } else {
139 ret = phm_dispatch_table(hwmgr,
140 &(hwmgr->disable_dynamic_state_management),
141 NULL, NULL);
142 }
143 101
144 enabled = ret == 0 ? false : true; 102 enabled = ret == 0 ? false : true;
145 103
@@ -219,13 +177,9 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
219{ 177{
220 PHM_FUNC_CHECK(hwmgr); 178 PHM_FUNC_CHECK(hwmgr);
221 179
222 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 180 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
223 PHM_PlatformCaps_TablelessHardwareInterface)) { 181 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
224 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) 182
225 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
226 } else {
227 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
228 }
229 return 0; 183 return 0;
230} 184}
231 185
@@ -233,11 +187,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
233{ 187{
234 PHM_FUNC_CHECK(hwmgr); 188 PHM_FUNC_CHECK(hwmgr);
235 189
236 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 190 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
237 PHM_PlatformCaps_TablelessHardwareInterface)) { 191 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
238 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) 192
239 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
240 }
241 return 0; 193 return 0;
242} 194}
243 195
@@ -246,12 +198,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
246{ 198{
247 PHM_FUNC_CHECK(hwmgr); 199 PHM_FUNC_CHECK(hwmgr);
248 200
249 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 201 if (NULL != hwmgr->hwmgr_func->display_config_changed)
250 PHM_PlatformCaps_TablelessHardwareInterface)) { 202 hwmgr->hwmgr_func->display_config_changed(hwmgr);
251 if (NULL != hwmgr->hwmgr_func->display_config_changed) 203
252 hwmgr->hwmgr_func->display_config_changed(hwmgr);
253 } else
254 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
255 return 0; 204 return 0;
256} 205}
257 206
@@ -259,9 +208,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
259{ 208{
260 PHM_FUNC_CHECK(hwmgr); 209 PHM_FUNC_CHECK(hwmgr);
261 210
262 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 211 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
263 PHM_PlatformCaps_TablelessHardwareInterface))
264 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
265 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); 212 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
266 213
267 return 0; 214 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 387d0b62100c..e3bf69c924fd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -852,10 +852,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
852 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 852 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
853 PHM_PlatformCaps_AutomaticDCTransition); 853 PHM_PlatformCaps_AutomaticDCTransition);
854 854
855 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
856 PHM_PlatformCaps_TablelessHardwareInterface);
857
858
859 if (hwmgr->chip_id != CHIP_POLARIS10) 855 if (hwmgr->chip_id != CHIP_POLARIS10)
860 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 856 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
861 PHM_PlatformCaps_SPLLShutdownSupport); 857 PHM_PlatformCaps_SPLLShutdownSupport);
@@ -882,9 +878,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
882 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 878 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
883 PHM_PlatformCaps_TCPRamping); 879 PHM_PlatformCaps_TCPRamping);
884 880
885 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
886 PHM_PlatformCaps_TablelessHardwareInterface);
887
888 return 0; 881 return 0;
889} 882}
890 883
@@ -904,9 +897,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
904 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 897 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
905 PHM_PlatformCaps_VCEPowerGating); 898 PHM_PlatformCaps_VCEPowerGating);
906 899
907 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
908 PHM_PlatformCaps_TablelessHardwareInterface);
909
910 return 0; 900 return 0;
911} 901}
912 902
@@ -921,8 +911,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
921 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 911 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
922 PHM_PlatformCaps_TCPRamping); 912 PHM_PlatformCaps_TCPRamping);
923 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 913 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
924 PHM_PlatformCaps_TablelessHardwareInterface);
925 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
926 PHM_PlatformCaps_EVV); 914 PHM_PlatformCaps_EVV);
927 return 0; 915 return 0;
928} 916}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index da74f95fb86b..594b978f46d9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -435,9 +435,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
435 435
436 hwmgr->backend = data; 436 hwmgr->backend = data;
437 437
438 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
439 PHM_PlatformCaps_TablelessHardwareInterface);
440
441 result = rv_initialize_dpm_defaults(hwmgr); 438 result = rv_initialize_dpm_defaults(hwmgr);
442 if (result != 0) { 439 if (result != 0) {
443 pr_err("rv_initialize_dpm_defaults failed\n"); 440 pr_err("rv_initialize_dpm_defaults failed\n");
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index c631b1926be7..8b8e202b45b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3854,9 +3854,6 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
3854 hwmgr->thermal_controller. 3854 hwmgr->thermal_controller.
3855 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 3855 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
3856 3856
3857 if (phm_is_hw_access_blocked(hwmgr))
3858 return 0;
3859
3860 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3857 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3861 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); 3858 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
3862} 3859}
@@ -3959,9 +3956,6 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
3959 hwmgr->thermal_controller. 3956 hwmgr->thermal_controller.
3960 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 3957 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
3961 3958
3962 if (phm_is_hw_access_blocked(hwmgr))
3963 return 0;
3964
3965 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, 3959 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3966 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); 3960 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
3967} 3961}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 0eb3c2907de9..ad34178b4ae3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -201,9 +201,6 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
201 PHM_PlatformCaps_ControlVDDCI); 201 PHM_PlatformCaps_ControlVDDCI);
202 202
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_TablelessHardwareInterface);
205
206 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
207 PHM_PlatformCaps_EnableSMU7ThermalManagement); 204 PHM_PlatformCaps_EnableSMU7ThermalManagement);
208 205
209 sys_info.size = sizeof(struct cgs_system_info); 206 sys_info.size = sizeof(struct cgs_system_info);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 831add448614..2a10d8174126 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -109,10 +109,6 @@ enum PHM_BackEnd_Magic {
109#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 109#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
110#define PHM_PCIE_POWERGATING_TARGET_PHY 3 110#define PHM_PCIE_POWERGATING_TARGET_PHY 3
111 111
112typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
113 void *output, void *storage, int result);
114
115typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
116 112
117struct phm_set_power_state_input { 113struct phm_set_power_state_input {
118 const struct pp_hw_power_state *pcurrent_state; 114 const struct pp_hw_power_state *pcurrent_state;
@@ -149,30 +145,6 @@ struct phm_gfx_arbiter {
149 uint32_t fclk; 145 uint32_t fclk;
150}; 146};
151 147
152/* Entries in the master tables */
153struct phm_master_table_item {
154 phm_check_function isFunctionNeededInRuntimeTable;
155 phm_table_function tableFunction;
156};
157
158enum phm_master_table_flag {
159 PHM_MasterTableFlag_None = 0,
160 PHM_MasterTableFlag_ExitOnError = 1,
161};
162
163/* The header of the master tables */
164struct phm_master_table_header {
165 uint32_t storage_size;
166 uint32_t flags;
167 const struct phm_master_table_item *master_list;
168};
169
170struct phm_runtime_table_header {
171 uint32_t storage_size;
172 bool exit_error;
173 phm_table_function *function_list;
174};
175
176struct phm_clock_array { 148struct phm_clock_array {
177 uint32_t count; 149 uint32_t count;
178 uint32_t values[1]; 150 uint32_t values[1];
@@ -216,19 +188,6 @@ struct phm_phase_shedding_limits_record {
216 uint32_t Mclk; 188 uint32_t Mclk;
217}; 189};
218 190
219
220extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
221 struct phm_runtime_table_header *rt_table,
222 void *input, void *output);
223
224extern int phm_construct_table(struct pp_hwmgr *hwmgr,
225 const struct phm_master_table_header *master_table,
226 struct phm_runtime_table_header *rt_table);
227
228extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
229 struct phm_runtime_table_header *rt_table);
230
231
232struct phm_uvd_clock_voltage_dependency_record { 191struct phm_uvd_clock_voltage_dependency_record {
233 uint32_t vclk; 192 uint32_t vclk;
234 uint32_t dclk; 193 uint32_t dclk;
@@ -749,7 +708,6 @@ struct pp_hwmgr {
749 enum amd_dpm_forced_level dpm_level; 708 enum amd_dpm_forced_level dpm_level;
750 enum amd_dpm_forced_level saved_dpm_level; 709 enum amd_dpm_forced_level saved_dpm_level;
751 enum amd_dpm_forced_level request_dpm_level; 710 enum amd_dpm_forced_level request_dpm_level;
752 bool block_hw_access;
753 struct phm_gfx_arbiter gfx_arbiter; 711 struct phm_gfx_arbiter gfx_arbiter;
754 struct phm_acp_arbiter acp_arbiter; 712 struct phm_acp_arbiter acp_arbiter;
755 struct phm_uvd_arbiter uvd_arbiter; 713 struct phm_uvd_arbiter uvd_arbiter;
@@ -760,13 +718,6 @@ struct pp_hwmgr {
760 void *backend; 718 void *backend;
761 enum PP_DAL_POWERLEVEL dal_power_level; 719 enum PP_DAL_POWERLEVEL dal_power_level;
762 struct phm_dynamic_state_info dyn_state; 720 struct phm_dynamic_state_info dyn_state;
763 struct phm_runtime_table_header setup_asic;
764 struct phm_runtime_table_header power_down_asic;
765 struct phm_runtime_table_header disable_dynamic_state_management;
766 struct phm_runtime_table_header enable_dynamic_state_management;
767 struct phm_runtime_table_header set_power_state;
768 struct phm_runtime_table_header enable_clock_power_gatings;
769 struct phm_runtime_table_header display_configuration_changed;
770 const struct pp_hwmgr_func *hwmgr_func; 721 const struct pp_hwmgr_func *hwmgr_func;
771 const struct pp_table_func *pptable_func; 722 const struct pp_table_func *pptable_func;
772 struct pp_power_state *ps; 723 struct pp_power_state *ps;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 04:20:14 -0400