diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 93 |
1 files changed, 20 insertions, 73 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c index a3991c0dff2e..fa4fbc25ebe1 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | |||
| @@ -36,29 +36,12 @@ | |||
| 36 | return -EINVAL; \ | 36 | return -EINVAL; \ |
| 37 | } while (0) | 37 | } while (0) |
| 38 | 38 | ||
| 39 | bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr) | ||
| 40 | { | ||
| 41 | return hwmgr->block_hw_access; | ||
| 42 | } | ||
| 43 | |||
| 44 | int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block) | ||
| 45 | { | ||
| 46 | hwmgr->block_hw_access = block; | ||
| 47 | return 0; | ||
| 48 | } | ||
| 49 | |||
| 50 | int phm_setup_asic(struct pp_hwmgr *hwmgr) | 39 | int phm_setup_asic(struct pp_hwmgr *hwmgr) |
| 51 | { | 40 | { |
| 52 | PHM_FUNC_CHECK(hwmgr); | 41 | PHM_FUNC_CHECK(hwmgr); |
| 53 | 42 | ||
| 54 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 43 | if (NULL != hwmgr->hwmgr_func->asic_setup) |
| 55 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 44 | return hwmgr->hwmgr_func->asic_setup(hwmgr); |
| 56 | if (NULL != hwmgr->hwmgr_func->asic_setup) | ||
| 57 | return hwmgr->hwmgr_func->asic_setup(hwmgr); | ||
| 58 | } else { | ||
| 59 | return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic), | ||
| 60 | NULL, NULL); | ||
| 61 | } | ||
| 62 | 45 | ||
| 63 | return 0; | 46 | return 0; |
| 64 | } | 47 | } |
| @@ -67,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr) | |||
| 67 | { | 50 | { |
| 68 | PHM_FUNC_CHECK(hwmgr); | 51 | PHM_FUNC_CHECK(hwmgr); |
| 69 | 52 | ||
| 70 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 53 | if (NULL != hwmgr->hwmgr_func->power_off_asic) |
| 71 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 54 | return hwmgr->hwmgr_func->power_off_asic(hwmgr); |
| 72 | if (NULL != hwmgr->hwmgr_func->power_off_asic) | ||
| 73 | return hwmgr->hwmgr_func->power_off_asic(hwmgr); | ||
| 74 | } else { | ||
| 75 | return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic), | ||
| 76 | NULL, NULL); | ||
| 77 | } | ||
| 78 | 55 | ||
| 79 | return 0; | 56 | return 0; |
| 80 | } | 57 | } |
| @@ -90,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr, | |||
| 90 | states.pcurrent_state = pcurrent_state; | 67 | states.pcurrent_state = pcurrent_state; |
| 91 | states.pnew_state = pnew_power_state; | 68 | states.pnew_state = pnew_power_state; |
| 92 | 69 | ||
| 93 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 70 | if (NULL != hwmgr->hwmgr_func->power_state_set) |
| 94 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 71 | return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); |
| 95 | if (NULL != hwmgr->hwmgr_func->power_state_set) | ||
| 96 | return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); | ||
| 97 | } else { | ||
| 98 | return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL); | ||
| 99 | } | ||
| 100 | 72 | ||
| 101 | return 0; | 73 | return 0; |
| 102 | } | 74 | } |
| @@ -107,15 +79,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) | |||
| 107 | bool enabled; | 79 | bool enabled; |
| 108 | PHM_FUNC_CHECK(hwmgr); | 80 | PHM_FUNC_CHECK(hwmgr); |
| 109 | 81 | ||
| 110 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 82 | if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) |
| 111 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 83 | ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); |
| 112 | if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) | ||
| 113 | ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); | ||
| 114 | } else { | ||
| 115 | ret = phm_dispatch_table(hwmgr, | ||
| 116 | &(hwmgr->enable_dynamic_state_management), | ||
| 117 | NULL, NULL); | ||
| 118 | } | ||
| 119 | 84 | ||
| 120 | enabled = ret == 0; | 85 | enabled = ret == 0; |
| 121 | 86 | ||
| @@ -131,15 +96,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) | |||
| 131 | 96 | ||
| 132 | PHM_FUNC_CHECK(hwmgr); | 97 | PHM_FUNC_CHECK(hwmgr); |
| 133 | 98 | ||
| 134 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 99 | if (hwmgr->hwmgr_func->dynamic_state_management_disable) |
| 135 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 100 | ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); |
| 136 | if (hwmgr->hwmgr_func->dynamic_state_management_disable) | ||
| 137 | ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); | ||
| 138 | } else { | ||
| 139 | ret = phm_dispatch_table(hwmgr, | ||
| 140 | &(hwmgr->disable_dynamic_state_management), | ||
| 141 | NULL, NULL); | ||
| 142 | } | ||
| 143 | 101 | ||
| 144 | enabled = ret == 0 ? false : true; | 102 | enabled = ret == 0 ? false : true; |
| 145 | 103 | ||
| @@ -219,13 +177,9 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) | |||
| 219 | { | 177 | { |
| 220 | PHM_FUNC_CHECK(hwmgr); | 178 | PHM_FUNC_CHECK(hwmgr); |
| 221 | 179 | ||
| 222 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 180 | if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) |
| 223 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 181 | return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); |
| 224 | if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) | 182 | |
| 225 | return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); | ||
| 226 | } else { | ||
| 227 | return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL); | ||
| 228 | } | ||
| 229 | return 0; | 183 | return 0; |
| 230 | } | 184 | } |
| 231 | 185 | ||
| @@ -233,11 +187,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) | |||
| 233 | { | 187 | { |
| 234 | PHM_FUNC_CHECK(hwmgr); | 188 | PHM_FUNC_CHECK(hwmgr); |
| 235 | 189 | ||
| 236 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 190 | if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) |
| 237 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 191 | return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); |
| 238 | if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) | 192 | |
| 239 | return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); | ||
| 240 | } | ||
| 241 | return 0; | 193 | return 0; |
| 242 | } | 194 | } |
| 243 | 195 | ||
| @@ -246,12 +198,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) | |||
| 246 | { | 198 | { |
| 247 | PHM_FUNC_CHECK(hwmgr); | 199 | PHM_FUNC_CHECK(hwmgr); |
| 248 | 200 | ||
| 249 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 201 | if (NULL != hwmgr->hwmgr_func->display_config_changed) |
| 250 | PHM_PlatformCaps_TablelessHardwareInterface)) { | 202 | hwmgr->hwmgr_func->display_config_changed(hwmgr); |
| 251 | if (NULL != hwmgr->hwmgr_func->display_config_changed) | 203 | |
| 252 | hwmgr->hwmgr_func->display_config_changed(hwmgr); | ||
| 253 | } else | ||
| 254 | return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL); | ||
| 255 | return 0; | 204 | return 0; |
| 256 | } | 205 | } |
| 257 | 206 | ||
| @@ -259,9 +208,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) | |||
| 259 | { | 208 | { |
| 260 | PHM_FUNC_CHECK(hwmgr); | 209 | PHM_FUNC_CHECK(hwmgr); |
| 261 | 210 | ||
| 262 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, | 211 | if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) |
| 263 | PHM_PlatformCaps_TablelessHardwareInterface)) | ||
| 264 | if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) | ||
| 265 | hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); | 212 | hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); |
| 266 | 213 | ||
| 267 | return 0; | 214 | return 0; |
