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authorRex Zhu <Rex.Zhu@amd.com>2016-09-09 01:25:22 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-09-19 13:22:10 -0400
commit599a7e9fe1b683d04f889d68f866f5548b1e0239 (patch)
tree431dbac8284d21d8c517036cc2bf1b85575d5b13 /drivers/gpu
parentee1a51f882f6197e05948de615842761c3386524 (diff)
drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/Makefile23
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c488
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h40
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h55
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c4350
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h353
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c729
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h62
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c577
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h58
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu7_common.h58
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h412
12 files changed, 7195 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 6e359c90dfda..d5d5626b5195 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -3,16 +3,19 @@
3# It provides the hardware management services for the driver. 3# It provides the hardware management services for the driver.
4 4
5HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ 5HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
6 hardwaremanager.o pp_acpi.o cz_hwmgr.o \ 6 hardwaremanager.o pp_acpi.o cz_hwmgr.o \
7 cz_clockpowergating.o tonga_powertune.o\ 7 cz_clockpowergating.o tonga_powertune.o\
8 process_pptables_v1_0.o ppatomctrl.o \ 8 process_pptables_v1_0.o ppatomctrl.o \
9 tonga_hwmgr.o pppcielanes.o tonga_thermal.o\ 9 tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
10 fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \ 10 fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
11 fiji_clockpowergating.o fiji_thermal.o \ 11 fiji_clockpowergating.o fiji_thermal.o \
12 polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \ 12 polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \
13 polaris10_clockpowergating.o iceland_hwmgr.o \ 13 polaris10_clockpowergating.o \
14 iceland_clockpowergating.o iceland_thermal.o \ 14 smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
15 iceland_powertune.o 15 smu7_clockpowergating.o iceland_hwmgr.o \
16 iceland_clockpowergating.o iceland_thermal.o \
17 iceland_powertune.o
18
16 19
17AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) 20AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
18 21
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
new file mode 100644
index 000000000000..6eb6db199250
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -0,0 +1,488 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "smu7_hwmgr.h"
25#include "smu7_clockpowergating.h"
26#include "smu7_common.h"
27
28static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
29{
30 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
31 PPSMC_MSG_UVDDPM_Enable :
32 PPSMC_MSG_UVDDPM_Disable);
33}
34
35static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
36{
37 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
38 PPSMC_MSG_VCEDPM_Enable :
39 PPSMC_MSG_VCEDPM_Disable);
40}
41
42static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
43{
44 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
45 PPSMC_MSG_SAMUDPM_Enable :
46 PPSMC_MSG_SAMUDPM_Disable);
47}
48
49static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
50{
51 if (!bgate)
52 smum_update_smc_table(hwmgr, SMU_UVD_TABLE);
53 return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);
54}
55
56static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
57{
58 if (!bgate)
59 smum_update_smc_table(hwmgr, SMU_VCE_TABLE);
60 return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
61}
62
63static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
64{
65 if (!bgate)
66 smum_update_smc_table(hwmgr, SMU_SAMU_TABLE);
67 return smu7_enable_disable_samu_dpm(hwmgr, !bgate);
68}
69
70int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
71{
72 if (phm_cf_want_uvd_power_gating(hwmgr))
73 return smum_send_msg_to_smc(hwmgr->smumgr,
74 PPSMC_MSG_UVDPowerOFF);
75 return 0;
76}
77
78int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
79{
80 if (phm_cf_want_uvd_power_gating(hwmgr)) {
81 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
82 PHM_PlatformCaps_UVDDynamicPowerGating)) {
83 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
84 PPSMC_MSG_UVDPowerON, 1);
85 } else {
86 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
87 PPSMC_MSG_UVDPowerON, 0);
88 }
89 }
90
91 return 0;
92}
93
94int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
95{
96 if (phm_cf_want_vce_power_gating(hwmgr))
97 return smum_send_msg_to_smc(hwmgr->smumgr,
98 PPSMC_MSG_VCEPowerOFF);
99 return 0;
100}
101
102int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
103{
104 if (phm_cf_want_vce_power_gating(hwmgr))
105 return smum_send_msg_to_smc(hwmgr->smumgr,
106 PPSMC_MSG_VCEPowerON);
107 return 0;
108}
109
110int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
111{
112 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
113 PHM_PlatformCaps_SamuPowerGating))
114 return smum_send_msg_to_smc(hwmgr->smumgr,
115 PPSMC_MSG_SAMPowerOFF);
116 return 0;
117}
118
119int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
120{
121 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
122 PHM_PlatformCaps_SamuPowerGating))
123 return smum_send_msg_to_smc(hwmgr->smumgr,
124 PPSMC_MSG_SAMPowerON);
125 return 0;
126}
127
128int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
129{
130 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
131
132 data->uvd_power_gated = false;
133 data->vce_power_gated = false;
134 data->samu_power_gated = false;
135
136 smu7_powerup_uvd(hwmgr);
137 smu7_powerup_vce(hwmgr);
138 smu7_powerup_samu(hwmgr);
139
140 return 0;
141}
142
143int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
144{
145 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
146
147 data->uvd_power_gated = bgate;
148
149 if (bgate) {
150 cgs_set_clockgating_state(hwmgr->device,
151 AMD_IP_BLOCK_TYPE_UVD,
152 AMD_CG_STATE_GATE);
153 smu7_update_uvd_dpm(hwmgr, true);
154 smu7_powerdown_uvd(hwmgr);
155 } else {
156 smu7_powerup_uvd(hwmgr);
157 smu7_update_uvd_dpm(hwmgr, false);
158 cgs_set_clockgating_state(hwmgr->device,
159 AMD_IP_BLOCK_TYPE_UVD,
160 AMD_CG_STATE_UNGATE);
161 }
162
163 return 0;
164}
165
166int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
167{
168 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
169
170 if (data->vce_power_gated == bgate)
171 return 0;
172
173 data->vce_power_gated = bgate;
174
175 if (bgate) {
176 cgs_set_clockgating_state(hwmgr->device,
177 AMD_IP_BLOCK_TYPE_VCE,
178 AMD_CG_STATE_GATE);
179 smu7_update_vce_dpm(hwmgr, true);
180 smu7_powerdown_vce(hwmgr);
181 } else {
182 smu7_powerup_vce(hwmgr);
183 smu7_update_vce_dpm(hwmgr, false);
184 cgs_set_clockgating_state(hwmgr->device,
185 AMD_IP_BLOCK_TYPE_VCE,
186 AMD_CG_STATE_UNGATE);
187 }
188 return 0;
189}
190
191int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
192{
193 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
194
195 if (data->samu_power_gated == bgate)
196 return 0;
197
198 data->samu_power_gated = bgate;
199
200 if (bgate) {
201 smu7_update_samu_dpm(hwmgr, true);
202 smu7_powerdown_samu(hwmgr);
203 } else {
204 smu7_powerup_samu(hwmgr);
205 smu7_update_samu_dpm(hwmgr, false);
206 }
207
208 return 0;
209}
210
211int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
212 const uint32_t *msg_id)
213{
214 PPSMC_Msg msg;
215 uint32_t value;
216
217 if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
218 return 0;
219
220 switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
221 case PP_GROUP_GFX:
222 switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
223 case PP_BLOCK_GFX_CG:
224 if (PP_STATE_SUPPORT_CG & *msg_id) {
225 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
226 PPSMC_MSG_EnableClockGatingFeature :
227 PPSMC_MSG_DisableClockGatingFeature;
228 value = CG_GFX_CGCG_MASK;
229
230 if (smum_send_msg_to_smc_with_parameter(
231 hwmgr->smumgr, msg, value))
232 return -EINVAL;
233 }
234 if (PP_STATE_SUPPORT_LS & *msg_id) {
235 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
236 ? PPSMC_MSG_EnableClockGatingFeature
237 : PPSMC_MSG_DisableClockGatingFeature;
238 value = CG_GFX_CGLS_MASK;
239
240 if (smum_send_msg_to_smc_with_parameter(
241 hwmgr->smumgr, msg, value))
242 return -EINVAL;
243 }
244 break;
245
246 case PP_BLOCK_GFX_3D:
247 if (PP_STATE_SUPPORT_CG & *msg_id) {
248 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
249 PPSMC_MSG_EnableClockGatingFeature :
250 PPSMC_MSG_DisableClockGatingFeature;
251 value = CG_GFX_3DCG_MASK;
252
253 if (smum_send_msg_to_smc_with_parameter(
254 hwmgr->smumgr, msg, value))
255 return -EINVAL;
256 }
257
258 if (PP_STATE_SUPPORT_LS & *msg_id) {
259 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
260 PPSMC_MSG_EnableClockGatingFeature :
261 PPSMC_MSG_DisableClockGatingFeature;
262 value = CG_GFX_3DLS_MASK;
263
264 if (smum_send_msg_to_smc_with_parameter(
265 hwmgr->smumgr, msg, value))
266 return -EINVAL;
267 }
268 break;
269
270 case PP_BLOCK_GFX_RLC:
271 if (PP_STATE_SUPPORT_LS & *msg_id) {
272 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
273 PPSMC_MSG_EnableClockGatingFeature :
274 PPSMC_MSG_DisableClockGatingFeature;
275 value = CG_GFX_RLC_LS_MASK;
276
277 if (smum_send_msg_to_smc_with_parameter(
278 hwmgr->smumgr, msg, value))
279 return -EINVAL;
280 }
281 break;
282
283 case PP_BLOCK_GFX_CP:
284 if (PP_STATE_SUPPORT_LS & *msg_id) {
285 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
286 PPSMC_MSG_EnableClockGatingFeature :
287 PPSMC_MSG_DisableClockGatingFeature;
288 value = CG_GFX_CP_LS_MASK;
289
290 if (smum_send_msg_to_smc_with_parameter(
291 hwmgr->smumgr, msg, value))
292 return -EINVAL;
293 }
294 break;
295
296 case PP_BLOCK_GFX_MG:
297 if (PP_STATE_SUPPORT_CG & *msg_id) {
298 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
299 PPSMC_MSG_EnableClockGatingFeature :
300 PPSMC_MSG_DisableClockGatingFeature;
301 value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |
302 CG_GFX_OTHERS_MGCG_MASK);
303
304 if (smum_send_msg_to_smc_with_parameter(
305 hwmgr->smumgr, msg, value))
306 return -EINVAL;
307 }
308 break;
309
310 default:
311 return -EINVAL;
312 }
313 break;
314
315 case PP_GROUP_SYS:
316 switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
317 case PP_BLOCK_SYS_BIF:
318 if (PP_STATE_SUPPORT_CG & *msg_id) {
319 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
320 PPSMC_MSG_EnableClockGatingFeature :
321 PPSMC_MSG_DisableClockGatingFeature;
322 value = CG_SYS_BIF_MGCG_MASK;
323
324 if (smum_send_msg_to_smc_with_parameter(
325 hwmgr->smumgr, msg, value))
326 return -EINVAL;
327 }
328 if (PP_STATE_SUPPORT_LS & *msg_id) {
329 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
330 PPSMC_MSG_EnableClockGatingFeature :
331 PPSMC_MSG_DisableClockGatingFeature;
332 value = CG_SYS_BIF_MGLS_MASK;
333
334 if (smum_send_msg_to_smc_with_parameter(
335 hwmgr->smumgr, msg, value))
336 return -EINVAL;
337 }
338 break;
339
340 case PP_BLOCK_SYS_MC:
341 if (PP_STATE_SUPPORT_CG & *msg_id) {
342 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
343 PPSMC_MSG_EnableClockGatingFeature :
344 PPSMC_MSG_DisableClockGatingFeature;
345 value = CG_SYS_MC_MGCG_MASK;
346
347 if (smum_send_msg_to_smc_with_parameter(
348 hwmgr->smumgr, msg, value))
349 return -EINVAL;
350 }
351
352 if (PP_STATE_SUPPORT_LS & *msg_id) {
353 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
354 PPSMC_MSG_EnableClockGatingFeature :
355 PPSMC_MSG_DisableClockGatingFeature;
356 value = CG_SYS_MC_MGLS_MASK;
357
358 if (smum_send_msg_to_smc_with_parameter(
359 hwmgr->smumgr, msg, value))
360 return -EINVAL;
361 }
362 break;
363
364 case PP_BLOCK_SYS_DRM:
365 if (PP_STATE_SUPPORT_CG & *msg_id) {
366 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
367 PPSMC_MSG_EnableClockGatingFeature :
368 PPSMC_MSG_DisableClockGatingFeature;
369 value = CG_SYS_DRM_MGCG_MASK;
370
371 if (smum_send_msg_to_smc_with_parameter(
372 hwmgr->smumgr, msg, value))
373 return -EINVAL;
374 }
375 if (PP_STATE_SUPPORT_LS & *msg_id) {
376 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
377 PPSMC_MSG_EnableClockGatingFeature :
378 PPSMC_MSG_DisableClockGatingFeature;
379 value = CG_SYS_DRM_MGLS_MASK;
380
381 if (smum_send_msg_to_smc_with_parameter(
382 hwmgr->smumgr, msg, value))
383 return -EINVAL;
384 }
385 break;
386
387 case PP_BLOCK_SYS_HDP:
388 if (PP_STATE_SUPPORT_CG & *msg_id) {
389 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
390 PPSMC_MSG_EnableClockGatingFeature :
391 PPSMC_MSG_DisableClockGatingFeature;
392 value = CG_SYS_HDP_MGCG_MASK;
393
394 if (smum_send_msg_to_smc_with_parameter(
395 hwmgr->smumgr, msg, value))
396 return -EINVAL;
397 }
398
399 if (PP_STATE_SUPPORT_LS & *msg_id) {
400 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
401 PPSMC_MSG_EnableClockGatingFeature :
402 PPSMC_MSG_DisableClockGatingFeature;
403 value = CG_SYS_HDP_MGLS_MASK;
404
405 if (smum_send_msg_to_smc_with_parameter(
406 hwmgr->smumgr, msg, value))
407 return -EINVAL;
408 }
409 break;
410
411 case PP_BLOCK_SYS_SDMA:
412 if (PP_STATE_SUPPORT_CG & *msg_id) {
413 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
414 PPSMC_MSG_EnableClockGatingFeature :
415 PPSMC_MSG_DisableClockGatingFeature;
416 value = CG_SYS_SDMA_MGCG_MASK;
417
418 if (smum_send_msg_to_smc_with_parameter(
419 hwmgr->smumgr, msg, value))
420 return -EINVAL;
421 }
422
423 if (PP_STATE_SUPPORT_LS & *msg_id) {
424 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
425 PPSMC_MSG_EnableClockGatingFeature :
426 PPSMC_MSG_DisableClockGatingFeature;
427 value = CG_SYS_SDMA_MGLS_MASK;
428
429 if (smum_send_msg_to_smc_with_parameter(
430 hwmgr->smumgr, msg, value))
431 return -EINVAL;
432 }
433 break;
434
435 case PP_BLOCK_SYS_ROM:
436 if (PP_STATE_SUPPORT_CG & *msg_id) {
437 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
438 PPSMC_MSG_EnableClockGatingFeature :
439 PPSMC_MSG_DisableClockGatingFeature;
440 value = CG_SYS_ROM_MASK;
441
442 if (smum_send_msg_to_smc_with_parameter(
443 hwmgr->smumgr, msg, value))
444 return -EINVAL;
445 }
446 break;
447
448 default:
449 return -EINVAL;
450
451 }
452 break;
453
454 default:
455 return -EINVAL;
456
457 }
458
459 return 0;
460}
461
462/* This function is for Polaris11 only for now,
463 * Powerplay will only control the static per CU Power Gating.
464 * Dynamic per CU Power Gating will be done in gfx.
465 */
466int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
467{
468 struct cgs_system_info sys_info = {0};
469 uint32_t active_cus;
470 int result;
471
472 sys_info.size = sizeof(struct cgs_system_info);
473 sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
474
475 result = cgs_query_system_info(hwmgr->device, &sys_info);
476
477 if (result)
478 return -EINVAL;
479
480 active_cus = sys_info.value;
481
482 if (enable)
483 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
484 PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
485 else
486 return smum_send_msg_to_smc(hwmgr->smumgr,
487 PPSMC_MSG_GFX_CU_PG_DISABLE);
488}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
new file mode 100644
index 000000000000..d52a28c343e3
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _SMU7_CLOCK_POWER_GATING_H_
25#define _SMU7_CLOCK__POWER_GATING_H_
26
27#include "smu7_hwmgr.h"
28#include "pp_asicblocks.h"
29
30int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
31int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
32int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
33int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
34int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
35int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
36int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
37 const uint32_t *msg_id);
38int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
39
40#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
new file mode 100644
index 000000000000..f967613191cf
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _SMU7_DYN_DEFAULTS_H
25#define _SMU7_DYN_DEFAULTS_H
26
27
28/* We need to fill in the default values */
29
30
31#define SMU7_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
32#define SMU7_VOTINGRIGHTSCLIENTS_DFLT1 0x000400
33#define SMU7_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080
34#define SMU7_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200
35#define SMU7_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680
36#define SMU7_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033
37#define SMU7_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033
38#define SMU7_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000
39
40
41#define SMU7_THERMALPROTECTCOUNTER_DFLT 0x200
42#define SMU7_STATICSCREENTHRESHOLDUNIT_DFLT 0
43#define SMU7_STATICSCREENTHRESHOLD_DFLT 0x00C8
44#define SMU7_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200
45#define SMU7_REFERENCEDIVIDER_DFLT 4
46
47#define SMU7_ULVVOLTAGECHANGEDELAY_DFLT 1687
48
49#define SMU7_CGULVPARAMETER_DFLT 0x00040035
50#define SMU7_CGULVCONTROL_DFLT 0x00007450
51#define SMU7_TARGETACTIVITY_DFLT 50
52#define SMU7_MCLK_TARGETACTIVITY_DFLT 10
53
54#endif
55
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
new file mode 100644
index 000000000000..f67e1e260b30
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -0,0 +1,4350 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <asm/div64.h>
27#include "linux/delay.h"
28#include "pp_acpi.h"
29#include "pp_debug.h"
30#include "ppatomctrl.h"
31#include "atombios.h"
32#include "pptable_v1_0.h"
33#include "pppcielanes.h"
34#include "amd_pcie_helpers.h"
35#include "hardwaremanager.h"
36#include "process_pptables_v1_0.h"
37#include "cgs_common.h"
38
39#include "smu7_common.h"
40
41#include "hwmgr.h"
42#include "smu7_hwmgr.h"
43#include "smu7_powertune.h"
44#include "smu7_dyn_defaults.h"
45#include "smu7_thermal.h"
46#include "smu7_clockpowergating.h"
47#include "processpptables.h"
48
49#define MC_CG_ARB_FREQ_F0 0x0a
50#define MC_CG_ARB_FREQ_F1 0x0b
51#define MC_CG_ARB_FREQ_F2 0x0c
52#define MC_CG_ARB_FREQ_F3 0x0d
53
54#define MC_CG_SEQ_DRAMCONF_S0 0x05
55#define MC_CG_SEQ_DRAMCONF_S1 0x06
56#define MC_CG_SEQ_YCLK_SUSPEND 0x04
57#define MC_CG_SEQ_YCLK_RESUME 0x0a
58
59#define SMC_CG_IND_START 0xc0030000
60#define SMC_CG_IND_END 0xc0040000
61
62#define VOLTAGE_SCALE 4
63#define VOLTAGE_VID_OFFSET_SCALE1 625
64#define VOLTAGE_VID_OFFSET_SCALE2 100
65
66#define MEM_FREQ_LOW_LATENCY 25000
67#define MEM_FREQ_HIGH_LATENCY 80000
68
69#define MEM_LATENCY_HIGH 45
70#define MEM_LATENCY_LOW 35
71#define MEM_LATENCY_ERR 0xFFFF
72
73#define MC_SEQ_MISC0_GDDR5_SHIFT 28
74#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
75#define MC_SEQ_MISC0_GDDR5_VALUE 5
76
77#define PCIE_BUS_CLK 10000
78#define TCLK (PCIE_BUS_CLK / 10)
79
80
81/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
82enum DPM_EVENT_SRC {
83 DPM_EVENT_SRC_ANALOG = 0,
84 DPM_EVENT_SRC_EXTERNAL = 1,
85 DPM_EVENT_SRC_DIGITAL = 2,
86 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
87 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
88};
89
90static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
91
92struct smu7_power_state *cast_phw_smu7_power_state(
93 struct pp_hw_power_state *hw_ps)
94{
95 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
96 "Invalid Powerstate Type!",
97 return NULL);
98
99 return (struct smu7_power_state *)hw_ps;
100}
101
102const struct smu7_power_state *cast_const_phw_smu7_power_state(
103 const struct pp_hw_power_state *hw_ps)
104{
105 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
106 "Invalid Powerstate Type!",
107 return NULL);
108
109 return (const struct smu7_power_state *)hw_ps;
110}
111
112/**
113 * Find the MC microcode version and store it in the HwMgr struct
114 *
115 * @param hwmgr the address of the powerplay hardware manager.
116 * @return always 0
117 */
118int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
119{
120 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
121
122 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
123
124 return 0;
125}
126
127uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
128{
129 uint32_t speedCntl = 0;
130
131 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
132 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
133 ixPCIE_LC_SPEED_CNTL);
134 return((uint16_t)PHM_GET_FIELD(speedCntl,
135 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
136}
137
138int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
139{
140 uint32_t link_width;
141
142 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
143 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
144 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
145
146 PP_ASSERT_WITH_CODE((7 >= link_width),
147 "Invalid PCIe lane width!", return 0);
148
149 return decode_pcie_lane_width(link_width);
150}
151
152/**
153* Enable voltage control
154*
155* @param pHwMgr the address of the powerplay hardware manager.
156* @return always PP_Result_OK
157*/
158int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
159{
160 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
161 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);
162
163 return 0;
164}
165
166/**
167* Checks if we want to support voltage control
168*
169* @param hwmgr the address of the powerplay hardware manager.
170*/
171static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
172{
173 const struct smu7_hwmgr *data =
174 (const struct smu7_hwmgr *)(hwmgr->backend);
175
176 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
177}
178
179/**
180* Enable voltage control
181*
182* @param hwmgr the address of the powerplay hardware manager.
183* @return always 0
184*/
185static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
186{
187 /* enable voltage control */
188 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
189 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
190
191 return 0;
192}
193
194static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
195 struct phm_clock_voltage_dependency_table *voltage_dependency_table
196 )
197{
198 uint32_t i;
199
200 PP_ASSERT_WITH_CODE((NULL != voltage_table),
201 "Voltage Dependency Table empty.", return -EINVAL;);
202
203 voltage_table->mask_low = 0;
204 voltage_table->phase_delay = 0;
205 voltage_table->count = voltage_dependency_table->count;
206
207 for (i = 0; i < voltage_dependency_table->count; i++) {
208 voltage_table->entries[i].value =
209 voltage_dependency_table->entries[i].v;
210 voltage_table->entries[i].smio_low = 0;
211 }
212
213 return 0;
214}
215
216
217/**
218* Create Voltage Tables.
219*
220* @param hwmgr the address of the powerplay hardware manager.
221* @return always 0
222*/
223static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
224{
225 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
226 struct phm_ppt_v1_information *table_info =
227 (struct phm_ppt_v1_information *)hwmgr->pptable;
228 int result = 0;
229 uint32_t tmp;
230
231 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
232 result = atomctrl_get_voltage_table_v3(hwmgr,
233 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
234 &(data->mvdd_voltage_table));
235 PP_ASSERT_WITH_CODE((0 == result),
236 "Failed to retrieve MVDD table.",
237 return result);
238 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
239 if (hwmgr->pp_table_version == PP_TABLE_V1)
240 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
241 table_info->vdd_dep_on_mclk);
242 else if (hwmgr->pp_table_version == PP_TABLE_V0)
243 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
244 hwmgr->dyn_state.mvdd_dependency_on_mclk);
245
246 PP_ASSERT_WITH_CODE((0 == result),
247 "Failed to retrieve SVI2 MVDD table from dependancy table.",
248 return result;);
249 }
250
251 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
252 result = atomctrl_get_voltage_table_v3(hwmgr,
253 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
254 &(data->vddci_voltage_table));
255 PP_ASSERT_WITH_CODE((0 == result),
256 "Failed to retrieve VDDCI table.",
257 return result);
258 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
259 if (hwmgr->pp_table_version == PP_TABLE_V1)
260 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
261 table_info->vdd_dep_on_mclk);
262 else if (hwmgr->pp_table_version == PP_TABLE_V0)
263 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
264 hwmgr->dyn_state.vddci_dependency_on_mclk);
265 PP_ASSERT_WITH_CODE((0 == result),
266 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
267 return result);
268 }
269
270 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
271 /* VDDGFX has only SVI2 voltage control */
272 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
273 table_info->vddgfx_lookup_table);
274 PP_ASSERT_WITH_CODE((0 == result),
275 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
276 }
277
278
279 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
280 result = atomctrl_get_voltage_table_v3(hwmgr,
281 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
282 &data->vddc_voltage_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve VDDC table.", return result;);
285 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
286
287 if (hwmgr->pp_table_version == PP_TABLE_V0)
288 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
289 hwmgr->dyn_state.vddc_dependency_on_mclk);
290 else if (hwmgr->pp_table_version == PP_TABLE_V1)
291 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
292 table_info->vddc_lookup_table);
293
294 PP_ASSERT_WITH_CODE((0 == result),
295 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
296 }
297
298 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC);
299 PP_ASSERT_WITH_CODE(
300 (data->vddc_voltage_table.count <= tmp),
301 "Too many voltage values for VDDC. Trimming to fit state table.",
302 phm_trim_voltage_table_to_fit_state_table(tmp,
303 &(data->vddc_voltage_table)));
304
305 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
306 PP_ASSERT_WITH_CODE(
307 (data->vddgfx_voltage_table.count <= tmp),
308 "Too many voltage values for VDDC. Trimming to fit state table.",
309 phm_trim_voltage_table_to_fit_state_table(tmp,
310 &(data->vddgfx_voltage_table)));
311
312 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI);
313 PP_ASSERT_WITH_CODE(
314 (data->vddci_voltage_table.count <= tmp),
315 "Too many voltage values for VDDCI. Trimming to fit state table.",
316 phm_trim_voltage_table_to_fit_state_table(tmp,
317 &(data->vddci_voltage_table)));
318
319 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD);
320 PP_ASSERT_WITH_CODE(
321 (data->mvdd_voltage_table.count <= tmp),
322 "Too many voltage values for MVDD. Trimming to fit state table.",
323 phm_trim_voltage_table_to_fit_state_table(tmp,
324 &(data->mvdd_voltage_table)));
325
326 return 0;
327}
328
329/**
330* Programs static screed detection parameters
331*
332* @param hwmgr the address of the powerplay hardware manager.
333* @return always 0
334*/
335static int smu7_program_static_screen_threshold_parameters(
336 struct pp_hwmgr *hwmgr)
337{
338 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
339
340 /* Set static screen threshold unit */
341 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
342 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
343 data->static_screen_threshold_unit);
344 /* Set static screen threshold */
345 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
346 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
347 data->static_screen_threshold);
348
349 return 0;
350}
351
352/**
353* Setup display gap for glitch free memory clock switching.
354*
355* @param hwmgr the address of the powerplay hardware manager.
356* @return always 0
357*/
358static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
359{
360 uint32_t display_gap =
361 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
362 ixCG_DISPLAY_GAP_CNTL);
363
364 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
365 DISP_GAP, DISPLAY_GAP_IGNORE);
366
367 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
368 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
369
370 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
371 ixCG_DISPLAY_GAP_CNTL, display_gap);
372
373 return 0;
374}
375
376/**
377* Programs activity state transition voting clients
378*
379* @param hwmgr the address of the powerplay hardware manager.
380* @return always 0
381*/
382static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
383{
384 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
385
386 /* Clear reset for voting clients before enabling DPM */
387 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
388 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
389 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
390 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
391
392 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
393 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
394 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
395 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
396 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
397 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
398 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
399 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
401 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
402 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
403 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
404 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
405 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
407 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
408
409 return 0;
410}
411
412static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
413{
414 /* Reset voting clients before disabling DPM */
415 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
416 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
417 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
418 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
419
420 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
421 ixCG_FREQ_TRAN_VOTING_0, 0);
422 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
423 ixCG_FREQ_TRAN_VOTING_1, 0);
424 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
425 ixCG_FREQ_TRAN_VOTING_2, 0);
426 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
427 ixCG_FREQ_TRAN_VOTING_3, 0);
428 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
429 ixCG_FREQ_TRAN_VOTING_4, 0);
430 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
431 ixCG_FREQ_TRAN_VOTING_5, 0);
432 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
433 ixCG_FREQ_TRAN_VOTING_6, 0);
434 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
435 ixCG_FREQ_TRAN_VOTING_7, 0);
436
437 return 0;
438}
439
440/* Copy one arb setting to another and then switch the active set.
441 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
442 */
443static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
444 uint32_t arb_src, uint32_t arb_dest)
445{
446 uint32_t mc_arb_dram_timing;
447 uint32_t mc_arb_dram_timing2;
448 uint32_t burst_time;
449 uint32_t mc_cg_config;
450
451 switch (arb_src) {
452 case MC_CG_ARB_FREQ_F0:
453 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
454 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
455 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
456 break;
457 case MC_CG_ARB_FREQ_F1:
458 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
459 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
460 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
461 break;
462 default:
463 return -EINVAL;
464 }
465
466 switch (arb_dest) {
467 case MC_CG_ARB_FREQ_F0:
468 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
469 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
470 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
471 break;
472 case MC_CG_ARB_FREQ_F1:
473 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
474 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
475 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
482 mc_cg_config |= 0x0000000F;
483 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
484 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
485
486 return 0;
487}
488
489static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
490{
491 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
492}
493
494/**
495* Initial switch from ARB F0->F1
496*
497* @param hwmgr the address of the powerplay hardware manager.
498* @return always 0
499* This function is to be called from the SetPowerState table.
500*/
501static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
502{
503 return smu7_copy_and_switch_arb_sets(hwmgr,
504 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
505}
506
507static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
508{
509 uint32_t tmp;
510
511 tmp = (cgs_read_ind_register(hwmgr->device,
512 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
513 0x0000ff00) >> 8;
514
515 if (tmp == MC_CG_ARB_FREQ_F0)
516 return 0;
517
518 return smu7_copy_and_switch_arb_sets(hwmgr,
519 tmp, MC_CG_ARB_FREQ_F0);
520}
521
522static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
523{
524 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
525
526 struct phm_ppt_v1_information *table_info =
527 (struct phm_ppt_v1_information *)(hwmgr->pptable);
528 struct phm_ppt_v1_pcie_table *pcie_table = NULL;
529
530 uint32_t i, max_entry;
531 uint32_t tmp;
532
533 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
534 data->use_pcie_power_saving_levels), "No pcie performance levels!",
535 return -EINVAL);
536
537 if (table_info != NULL)
538 pcie_table = table_info->pcie_table;
539
540 if (data->use_pcie_performance_levels &&
541 !data->use_pcie_power_saving_levels) {
542 data->pcie_gen_power_saving = data->pcie_gen_performance;
543 data->pcie_lane_power_saving = data->pcie_lane_performance;
544 } else if (!data->use_pcie_performance_levels &&
545 data->use_pcie_power_saving_levels) {
546 data->pcie_gen_performance = data->pcie_gen_power_saving;
547 data->pcie_lane_performance = data->pcie_lane_power_saving;
548 }
549 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK);
550 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
551 tmp,
552 MAX_REGULAR_DPM_NUMBER);
553
554 if (pcie_table != NULL) {
555 /* max_entry is used to make sure we reserve one PCIE level
556 * for boot level (fix for A+A PSPP issue).
557 * If PCIE table from PPTable have ULV entry + 8 entries,
558 * then ignore the last entry.*/
559 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
560 for (i = 1; i < max_entry; i++) {
561 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
562 get_pcie_gen_support(data->pcie_gen_cap,
563 pcie_table->entries[i].gen_speed),
564 get_pcie_lane_support(data->pcie_lane_cap,
565 pcie_table->entries[i].lane_width));
566 }
567 data->dpm_table.pcie_speed_table.count = max_entry - 1;
568 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
569 } else {
570 /* Hardcode Pcie Table */
571 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
572 get_pcie_gen_support(data->pcie_gen_cap,
573 PP_Min_PCIEGen),
574 get_pcie_lane_support(data->pcie_lane_cap,
575 PP_Max_PCIELane));
576 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
577 get_pcie_gen_support(data->pcie_gen_cap,
578 PP_Min_PCIEGen),
579 get_pcie_lane_support(data->pcie_lane_cap,
580 PP_Max_PCIELane));
581 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
582 get_pcie_gen_support(data->pcie_gen_cap,
583 PP_Max_PCIEGen),
584 get_pcie_lane_support(data->pcie_lane_cap,
585 PP_Max_PCIELane));
586 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
587 get_pcie_gen_support(data->pcie_gen_cap,
588 PP_Max_PCIEGen),
589 get_pcie_lane_support(data->pcie_lane_cap,
590 PP_Max_PCIELane));
591 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
592 get_pcie_gen_support(data->pcie_gen_cap,
593 PP_Max_PCIEGen),
594 get_pcie_lane_support(data->pcie_lane_cap,
595 PP_Max_PCIELane));
596 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
597 get_pcie_gen_support(data->pcie_gen_cap,
598 PP_Max_PCIEGen),
599 get_pcie_lane_support(data->pcie_lane_cap,
600 PP_Max_PCIELane));
601
602 data->dpm_table.pcie_speed_table.count = 6;
603 }
604 /* Populate last level for boot PCIE level, but do not increment count. */
605 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
606 data->dpm_table.pcie_speed_table.count,
607 get_pcie_gen_support(data->pcie_gen_cap,
608 PP_Min_PCIEGen),
609 get_pcie_lane_support(data->pcie_lane_cap,
610 PP_Max_PCIELane));
611
612 return 0;
613}
614
615static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
616{
617 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
618
619 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
620
621 phm_reset_single_dpm_table(
622 &data->dpm_table.sclk_table,
623 smum_get_mac_definition(hwmgr->smumgr,
624 SMU_MAX_LEVELS_GRAPHICS),
625 MAX_REGULAR_DPM_NUMBER);
626 phm_reset_single_dpm_table(
627 &data->dpm_table.mclk_table,
628 smum_get_mac_definition(hwmgr->smumgr,
629 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
630
631 phm_reset_single_dpm_table(
632 &data->dpm_table.vddc_table,
633 smum_get_mac_definition(hwmgr->smumgr,
634 SMU_MAX_LEVELS_VDDC),
635 MAX_REGULAR_DPM_NUMBER);
636 phm_reset_single_dpm_table(
637 &data->dpm_table.vddci_table,
638 smum_get_mac_definition(hwmgr->smumgr,
639 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
640
641 phm_reset_single_dpm_table(
642 &data->dpm_table.mvdd_table,
643 smum_get_mac_definition(hwmgr->smumgr,
644 SMU_MAX_LEVELS_MVDD),
645 MAX_REGULAR_DPM_NUMBER);
646 return 0;
647}
648/*
649 * This function is to initialize all DPM state tables
650 * for SMU7 based on the dependency table.
651 * Dynamic state patching function will then trim these
652 * state tables to the allowed range based
653 * on the power policy or external client requests,
654 * such as UVD request, etc.
655 */
656
657static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
658{
659 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
660 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
661 hwmgr->dyn_state.vddc_dependency_on_sclk;
662 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
663 hwmgr->dyn_state.vddc_dependency_on_mclk;
664 struct phm_cac_leakage_table *std_voltage_table =
665 hwmgr->dyn_state.cac_leakage_table;
666 uint32_t i;
667
668 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
669 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
670 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
671 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
672
673 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
674 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
675 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
676 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
677
678
679 /* Initialize Sclk DPM table based on allow Sclk values*/
680 data->dpm_table.sclk_table.count = 0;
681
682 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
683 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
684 allowed_vdd_sclk_table->entries[i].clk) {
685 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
686 allowed_vdd_sclk_table->entries[i].clk;
687 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
688 data->dpm_table.sclk_table.count++;
689 }
690 }
691
692 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
693 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
694 /* Initialize Mclk DPM table based on allow Mclk values */
695 data->dpm_table.mclk_table.count = 0;
696 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
697 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
698 allowed_vdd_mclk_table->entries[i].clk) {
699 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
700 allowed_vdd_mclk_table->entries[i].clk;
701 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
702 data->dpm_table.mclk_table.count++;
703 }
704 }
705
706 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
707 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
708 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
709 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
710 /* param1 is for corresponding std voltage */
711 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
712 }
713
714 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
715 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
716
717 if (NULL != allowed_vdd_mclk_table) {
718 /* Initialize Vddci DPM table based on allow Mclk values */
719 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
720 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
721 data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
722 }
723 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
724 }
725
726 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
727
728 if (NULL != allowed_vdd_mclk_table) {
729 /*
730 * Initialize MVDD DPM table based on allow Mclk
731 * values
732 */
733 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
734 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
735 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
736 }
737 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
738 }
739
740 return 0;
741}
742
743static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
744{
745 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
746 struct phm_ppt_v1_information *table_info =
747 (struct phm_ppt_v1_information *)(hwmgr->pptable);
748 uint32_t i;
749
750 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
751 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
752
753 if (table_info == NULL)
754 return -EINVAL;
755
756 dep_sclk_table = table_info->vdd_dep_on_sclk;
757 dep_mclk_table = table_info->vdd_dep_on_mclk;
758
759 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
760 "SCLK dependency table is missing.",
761 return -EINVAL);
762 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
763 "SCLK dependency table count is 0.",
764 return -EINVAL);
765
766 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
767 "MCLK dependency table is missing.",
768 return -EINVAL);
769 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
770 "MCLK dependency table count is 0",
771 return -EINVAL);
772
773 /* Initialize Sclk DPM table based on allow Sclk values */
774 data->dpm_table.sclk_table.count = 0;
775 for (i = 0; i < dep_sclk_table->count; i++) {
776 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
777 dep_sclk_table->entries[i].clk) {
778
779 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
780 dep_sclk_table->entries[i].clk;
781
782 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
783 (i == 0) ? true : false;
784 data->dpm_table.sclk_table.count++;
785 }
786 }
787
788 /* Initialize Mclk DPM table based on allow Mclk values */
789 data->dpm_table.mclk_table.count = 0;
790 for (i = 0; i < dep_mclk_table->count; i++) {
791 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
792 [data->dpm_table.mclk_table.count - 1].value !=
793 dep_mclk_table->entries[i].clk) {
794 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
795 dep_mclk_table->entries[i].clk;
796 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
797 (i == 0) ? true : false;
798 data->dpm_table.mclk_table.count++;
799 }
800 }
801
802 return 0;
803}
804
805int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
806{
807 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
808
809 smu7_reset_dpm_tables(hwmgr);
810
811 if (hwmgr->pp_table_version == PP_TABLE_V1)
812 smu7_setup_dpm_tables_v1(hwmgr);
813 else if (hwmgr->pp_table_version == PP_TABLE_V0)
814 smu7_setup_dpm_tables_v0(hwmgr);
815
816 smu7_setup_default_pcie_table(hwmgr);
817
818 /* save a copy of the default DPM table */
819 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
820 sizeof(struct smu7_dpm_table));
821 return 0;
822}
823
824uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr)
825{
826 uint32_t reference_clock, tmp;
827 struct cgs_display_info info = {0};
828 struct cgs_mode_info mode_info;
829
830 info.mode_info = &mode_info;
831
832 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
833
834 if (tmp)
835 return TCLK;
836
837 cgs_get_active_displays_info(hwmgr->device, &info);
838 reference_clock = mode_info.ref_clock;
839
840 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
841
842 if (0 != tmp)
843 return reference_clock / 4;
844
845 return reference_clock;
846}
847
848static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
849{
850
851 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
852 PHM_PlatformCaps_RegulatorHot))
853 return smum_send_msg_to_smc(hwmgr->smumgr,
854 PPSMC_MSG_EnableVRHotGPIOInterrupt);
855
856 return 0;
857}
858
859static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
860{
861 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
862 SCLK_PWRMGT_OFF, 0);
863 return 0;
864}
865
866static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
867{
868 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
869
870 if (data->ulv_supported)
871 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
872
873 return 0;
874}
875
876static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
877{
878 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
879
880 if (data->ulv_supported)
881 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
882
883 return 0;
884}
885
886static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
887{
888 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
889 PHM_PlatformCaps_SclkDeepSleep)) {
890 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
891 PP_ASSERT_WITH_CODE(false,
892 "Attempt to enable Master Deep Sleep switch failed!",
893 return -EINVAL);
894 } else {
895 if (smum_send_msg_to_smc(hwmgr->smumgr,
896 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
897 PP_ASSERT_WITH_CODE(false,
898 "Attempt to disable Master Deep Sleep switch failed!",
899 return -EINVAL);
900 }
901 }
902
903 return 0;
904}
905
906static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
907{
908 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
909 PHM_PlatformCaps_SclkDeepSleep)) {
910 if (smum_send_msg_to_smc(hwmgr->smumgr,
911 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
912 PP_ASSERT_WITH_CODE(false,
913 "Attempt to disable Master Deep Sleep switch failed!",
914 return -EINVAL);
915 }
916 }
917
918 return 0;
919}
920
921static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
922{
923 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
924 uint32_t soft_register_value = 0;
925 uint32_t handshake_disables_offset = data->soft_regs_start
926 + smum_get_offsetof(hwmgr->smumgr,
927 SMU_SoftRegisters, HandshakeDisables);
928
929 soft_register_value = cgs_read_ind_register(hwmgr->device,
930 CGS_IND_REG__SMC, handshake_disables_offset);
931 soft_register_value |= smum_get_mac_definition(hwmgr->smumgr,
932 SMU_UVD_MCLK_HANDSHAKE_DISABLE);
933 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
934 handshake_disables_offset, soft_register_value);
935 return 0;
936}
937
938static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
939{
940 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
941
942 /* enable SCLK dpm */
943 if (!data->sclk_dpm_key_disabled)
944 PP_ASSERT_WITH_CODE(
945 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
946 "Failed to enable SCLK DPM during DPM Start Function!",
947 return -EINVAL);
948
949 /* enable MCLK dpm */
950 if (0 == data->mclk_dpm_key_disabled) {
951 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
952 smu7_disable_handshake_uvd(hwmgr);
953 PP_ASSERT_WITH_CODE(
954 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
955 PPSMC_MSG_MCLKDPM_Enable)),
956 "Failed to enable MCLK DPM during DPM Start Function!",
957 return -EINVAL);
958
959 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
960
961 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
962 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
963 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
964 udelay(10);
965 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
966 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
967 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
968 }
969
970 return 0;
971}
972
973static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
974{
975 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
976
977 /*enable general power management */
978
979 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
980 GLOBAL_PWRMGT_EN, 1);
981
982 /* enable sclk deep sleep */
983
984 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
985 DYNAMIC_PM_EN, 1);
986
987 /* prepare for PCIE DPM */
988
989 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
990 data->soft_regs_start +
991 smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters,
992 VoltageChangeTimeout), 0x1000);
993 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
994 SWRST_COMMAND_1, RESETLC, 0x0);
995
996 PP_ASSERT_WITH_CODE(
997 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
998 PPSMC_MSG_Voltage_Cntl_Enable)),
999 "Failed to enable voltage DPM during DPM Start Function!",
1000 return -EINVAL);
1001
1002
1003 if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1004 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
1005 return -EINVAL;
1006 }
1007
1008 /* enable PCIE dpm */
1009 if (0 == data->pcie_dpm_key_disabled) {
1010 PP_ASSERT_WITH_CODE(
1011 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
1012 PPSMC_MSG_PCIeDPM_Enable)),
1013 "Failed to enable pcie DPM during DPM Start Function!",
1014 return -EINVAL);
1015 }
1016
1017 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1018 PHM_PlatformCaps_Falcon_QuickTransition)) {
1019 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
1020 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1021 "Failed to enable AC DC GPIO Interrupt!",
1022 );
1023 }
1024
1025 return 0;
1026}
1027
1028static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1029{
1030 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1031
1032 /* disable SCLK dpm */
1033 if (!data->sclk_dpm_key_disabled)
1034 PP_ASSERT_WITH_CODE(
1035 (smum_send_msg_to_smc(hwmgr->smumgr,
1036 PPSMC_MSG_DPM_Disable) == 0),
1037 "Failed to disable SCLK DPM!",
1038 return -EINVAL);
1039
1040 /* disable MCLK dpm */
1041 if (!data->mclk_dpm_key_disabled) {
1042 PP_ASSERT_WITH_CODE(
1043 (smum_send_msg_to_smc(hwmgr->smumgr,
1044 PPSMC_MSG_MCLKDPM_Disable) == 0),
1045 "Failed to disable MCLK DPM!",
1046 return -EINVAL);
1047 }
1048
1049 return 0;
1050}
1051
1052static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1053{
1054 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1055
1056 /* disable general power management */
1057 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1058 GLOBAL_PWRMGT_EN, 0);
1059 /* disable sclk deep sleep */
1060 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1061 DYNAMIC_PM_EN, 0);
1062
1063 /* disable PCIE dpm */
1064 if (!data->pcie_dpm_key_disabled) {
1065 PP_ASSERT_WITH_CODE(
1066 (smum_send_msg_to_smc(hwmgr->smumgr,
1067 PPSMC_MSG_PCIeDPM_Disable) == 0),
1068 "Failed to disable pcie DPM during DPM Stop Function!",
1069 return -EINVAL);
1070 }
1071
1072 if (smu7_disable_sclk_mclk_dpm(hwmgr)) {
1073 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
1074 return -EINVAL;
1075 }
1076
1077 return 0;
1078}
1079
1080static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1081{
1082 bool protection;
1083 enum DPM_EVENT_SRC src;
1084
1085 switch (sources) {
1086 default:
1087 printk(KERN_ERR "Unknown throttling event sources.");
1088 /* fall through */
1089 case 0:
1090 protection = false;
1091 /* src is unused */
1092 break;
1093 case (1 << PHM_AutoThrottleSource_Thermal):
1094 protection = true;
1095 src = DPM_EVENT_SRC_DIGITAL;
1096 break;
1097 case (1 << PHM_AutoThrottleSource_External):
1098 protection = true;
1099 src = DPM_EVENT_SRC_EXTERNAL;
1100 break;
1101 case (1 << PHM_AutoThrottleSource_External) |
1102 (1 << PHM_AutoThrottleSource_Thermal):
1103 protection = true;
1104 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1105 break;
1106 }
1107 /* Order matters - don't enable thermal protection for the wrong source. */
1108 if (protection) {
1109 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1110 DPM_EVENT_SRC, src);
1111 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1112 THERMAL_PROTECTION_DIS,
1113 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1114 PHM_PlatformCaps_ThermalController));
1115 } else
1116 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1117 THERMAL_PROTECTION_DIS, 1);
1118}
1119
1120static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1121 PHM_AutoThrottleSource source)
1122{
1123 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1124
1125 if (!(data->active_auto_throttle_sources & (1 << source))) {
1126 data->active_auto_throttle_sources |= 1 << source;
1127 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1128 }
1129 return 0;
1130}
1131
1132static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1133{
1134 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1135}
1136
1137static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1138 PHM_AutoThrottleSource source)
1139{
1140 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1141
1142 if (data->active_auto_throttle_sources & (1 << source)) {
1143 data->active_auto_throttle_sources &= ~(1 << source);
1144 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1145 }
1146 return 0;
1147}
1148
1149static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1150{
1151 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1152}
1153
1154int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1155{
1156 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1157 data->pcie_performance_request = true;
1158
1159 return 0;
1160}
1161
1162int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1163{
1164 int tmp_result = 0;
1165 int result = 0;
1166
1167 tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1;
1168 PP_ASSERT_WITH_CODE(tmp_result == 0,
1169 "DPM is already running right now, no need to enable DPM!",
1170 return 0);
1171
1172 if (smu7_voltage_control(hwmgr)) {
1173 tmp_result = smu7_enable_voltage_control(hwmgr);
1174 PP_ASSERT_WITH_CODE(tmp_result == 0,
1175 "Failed to enable voltage control!",
1176 result = tmp_result);
1177
1178 tmp_result = smu7_construct_voltage_tables(hwmgr);
1179 PP_ASSERT_WITH_CODE((0 == tmp_result),
1180 "Failed to contruct voltage tables!",
1181 result = tmp_result);
1182 }
1183 smum_initialize_mc_reg_table(hwmgr);
1184
1185 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1186 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1187 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1188 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1189
1190 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1191 PHM_PlatformCaps_ThermalController))
1192 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1193 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1194
1195 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1196 PP_ASSERT_WITH_CODE((0 == tmp_result),
1197 "Failed to program static screen threshold parameters!",
1198 result = tmp_result);
1199
1200 tmp_result = smu7_enable_display_gap(hwmgr);
1201 PP_ASSERT_WITH_CODE((0 == tmp_result),
1202 "Failed to enable display gap!", result = tmp_result);
1203
1204 tmp_result = smu7_program_voting_clients(hwmgr);
1205 PP_ASSERT_WITH_CODE((0 == tmp_result),
1206 "Failed to program voting clients!", result = tmp_result);
1207
1208 tmp_result = smum_process_firmware_header(hwmgr);
1209 PP_ASSERT_WITH_CODE((0 == tmp_result),
1210 "Failed to process firmware header!", result = tmp_result);
1211
1212 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1213 PP_ASSERT_WITH_CODE((0 == tmp_result),
1214 "Failed to initialize switch from ArbF0 to F1!",
1215 result = tmp_result);
1216
1217 result = smu7_setup_default_dpm_tables(hwmgr);
1218 PP_ASSERT_WITH_CODE(0 == result,
1219 "Failed to setup default DPM tables!", return result);
1220
1221 tmp_result = smum_init_smc_table(hwmgr);
1222 PP_ASSERT_WITH_CODE((0 == tmp_result),
1223 "Failed to initialize SMC table!", result = tmp_result);
1224
1225 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1226 PP_ASSERT_WITH_CODE((0 == tmp_result),
1227 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1228
1229 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
1230
1231 tmp_result = smu7_enable_sclk_control(hwmgr);
1232 PP_ASSERT_WITH_CODE((0 == tmp_result),
1233 "Failed to enable SCLK control!", result = tmp_result);
1234
1235 tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1236 PP_ASSERT_WITH_CODE((0 == tmp_result),
1237 "Failed to enable voltage control!", result = tmp_result);
1238
1239 tmp_result = smu7_enable_ulv(hwmgr);
1240 PP_ASSERT_WITH_CODE((0 == tmp_result),
1241 "Failed to enable ULV!", result = tmp_result);
1242
1243 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1244 PP_ASSERT_WITH_CODE((0 == tmp_result),
1245 "Failed to enable deep sleep master switch!", result = tmp_result);
1246
1247 tmp_result = smu7_enable_didt_config(hwmgr);
1248 PP_ASSERT_WITH_CODE((tmp_result == 0),
1249 "Failed to enable deep sleep master switch!", result = tmp_result);
1250
1251 tmp_result = smu7_start_dpm(hwmgr);
1252 PP_ASSERT_WITH_CODE((0 == tmp_result),
1253 "Failed to start DPM!", result = tmp_result);
1254
1255 tmp_result = smu7_enable_smc_cac(hwmgr);
1256 PP_ASSERT_WITH_CODE((0 == tmp_result),
1257 "Failed to enable SMC CAC!", result = tmp_result);
1258
1259 tmp_result = smu7_enable_power_containment(hwmgr);
1260 PP_ASSERT_WITH_CODE((0 == tmp_result),
1261 "Failed to enable power containment!", result = tmp_result);
1262
1263 tmp_result = smu7_power_control_set_level(hwmgr);
1264 PP_ASSERT_WITH_CODE((0 == tmp_result),
1265 "Failed to power control set level!", result = tmp_result);
1266
1267 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1268 PP_ASSERT_WITH_CODE((0 == tmp_result),
1269 "Failed to enable thermal auto throttle!", result = tmp_result);
1270
1271 tmp_result = smu7_pcie_performance_request(hwmgr);
1272 PP_ASSERT_WITH_CODE((0 == tmp_result),
1273 "pcie performance request failed!", result = tmp_result);
1274
1275 return 0;
1276}
1277
1278int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1279{
1280 int tmp_result, result = 0;
1281
1282 tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1;
1283 PP_ASSERT_WITH_CODE(tmp_result == 0,
1284 "DPM is not running right now, no need to disable DPM!",
1285 return 0);
1286
1287 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1288 PHM_PlatformCaps_ThermalController))
1289 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1290 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1291
1292 tmp_result = smu7_disable_power_containment(hwmgr);
1293 PP_ASSERT_WITH_CODE((tmp_result == 0),
1294 "Failed to disable power containment!", result = tmp_result);
1295
1296 tmp_result = smu7_disable_smc_cac(hwmgr);
1297 PP_ASSERT_WITH_CODE((tmp_result == 0),
1298 "Failed to disable SMC CAC!", result = tmp_result);
1299
1300 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1301 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1302 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1303 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1304
1305 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1306 PP_ASSERT_WITH_CODE((tmp_result == 0),
1307 "Failed to disable thermal auto throttle!", result = tmp_result);
1308
1309 tmp_result = smu7_stop_dpm(hwmgr);
1310 PP_ASSERT_WITH_CODE((tmp_result == 0),
1311 "Failed to stop DPM!", result = tmp_result);
1312
1313 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1314 PP_ASSERT_WITH_CODE((tmp_result == 0),
1315 "Failed to disable deep sleep master switch!", result = tmp_result);
1316
1317 tmp_result = smu7_disable_ulv(hwmgr);
1318 PP_ASSERT_WITH_CODE((tmp_result == 0),
1319 "Failed to disable ULV!", result = tmp_result);
1320
1321 tmp_result = smu7_clear_voting_clients(hwmgr);
1322 PP_ASSERT_WITH_CODE((tmp_result == 0),
1323 "Failed to clear voting clients!", result = tmp_result);
1324
1325 tmp_result = smu7_reset_to_default(hwmgr);
1326 PP_ASSERT_WITH_CODE((tmp_result == 0),
1327 "Failed to reset to default!", result = tmp_result);
1328
1329 tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1330 PP_ASSERT_WITH_CODE((tmp_result == 0),
1331 "Failed to force to switch arbf0!", result = tmp_result);
1332
1333 return result;
1334}
1335
1336int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1337{
1338
1339 return 0;
1340}
1341
1342static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1343{
1344 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1345 struct phm_ppt_v1_information *table_info =
1346 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1347
1348 data->dll_default_on = false;
1349 data->mclk_dpm0_activity_target = 0xa;
1350 data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT;
1351 data->vddc_vddgfx_delta = 300;
1352 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1353 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1354 data->voting_rights_clients0 = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1355 data->voting_rights_clients1 = SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1356 data->voting_rights_clients2 = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1357 data->voting_rights_clients3 = SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1358 data->voting_rights_clients4 = SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1359 data->voting_rights_clients5 = SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1360 data->voting_rights_clients6 = SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1361 data->voting_rights_clients7 = SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1362
1363 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1364 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1365 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1366 /* need to set voltage control types before EVV patching */
1367 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1368 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1369 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1370 data->enable_tdc_limit_feature = true;
1371 data->enable_pkg_pwr_tracking_feature = true;
1372 data->force_pcie_gen = PP_PCIEGenInvalid;
1373 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1374
1375 data->fast_watermark_threshold = 100;
1376 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1377 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1378 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1379
1380 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1381 PHM_PlatformCaps_ControlVDDGFX)) {
1382 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1383 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1384 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1385 }
1386 }
1387
1388 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1389 PHM_PlatformCaps_EnableMVDDControl)) {
1390 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1391 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1392 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1393 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1394 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1395 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1396 }
1397
1398 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
1399 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1400 PHM_PlatformCaps_ControlVDDGFX);
1401 }
1402
1403 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1404 PHM_PlatformCaps_ControlVDDCI)) {
1405 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1406 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1407 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1408 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
1409 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1410 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1411 }
1412
1413 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1414 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1415 PHM_PlatformCaps_EnableMVDDControl);
1416
1417 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1418 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1419 PHM_PlatformCaps_ControlVDDCI);
1420
1421 if ((hwmgr->pp_table_version != PP_TABLE_V0)
1422 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1423 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1424 PHM_PlatformCaps_ClockStretcher);
1425
1426 data->pcie_gen_performance.max = PP_PCIEGen1;
1427 data->pcie_gen_performance.min = PP_PCIEGen3;
1428 data->pcie_gen_power_saving.max = PP_PCIEGen1;
1429 data->pcie_gen_power_saving.min = PP_PCIEGen3;
1430 data->pcie_lane_performance.max = 0;
1431 data->pcie_lane_performance.min = 16;
1432 data->pcie_lane_power_saving.max = 0;
1433 data->pcie_lane_power_saving.min = 16;
1434}
1435
1436/**
1437* Get Leakage VDDC based on leakage ID.
1438*
1439* @param hwmgr the address of the powerplay hardware manager.
1440* @return always 0
1441*/
1442static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1443{
1444 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1445 uint16_t vv_id;
1446 uint16_t vddc = 0;
1447 uint16_t vddgfx = 0;
1448 uint16_t i, j;
1449 uint32_t sclk = 0;
1450 struct phm_ppt_v1_information *table_info =
1451 (struct phm_ppt_v1_information *)hwmgr->pptable;
1452 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1453
1454
1455 if (table_info != NULL)
1456 sclk_table = table_info->vdd_dep_on_sclk;
1457
1458 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1459 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1460
1461 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1462 if (0 == phm_get_sclk_for_voltage_evv(hwmgr,
1463 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1464 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1465 PHM_PlatformCaps_ClockStretcher)) {
1466 for (j = 1; j < sclk_table->count; j++) {
1467 if (sclk_table->entries[j].clk == sclk &&
1468 sclk_table->entries[j].cks_enable == 0) {
1469 sclk += 5000;
1470 break;
1471 }
1472 }
1473 }
1474 if (0 == atomctrl_get_voltage_evv_on_sclk
1475 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1476 vv_id, &vddgfx)) {
1477 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1478 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1479
1480 /* the voltage should not be zero nor equal to leakage ID */
1481 if (vddgfx != 0 && vddgfx != vv_id) {
1482 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1483 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1484 data->vddcgfx_leakage.count++;
1485 }
1486 } else {
1487 printk("Error retrieving EVV voltage value!\n");
1488 }
1489 }
1490 } else {
1491
1492 if ((hwmgr->pp_table_version == PP_TABLE_V0)
1493 || !phm_get_sclk_for_voltage_evv(hwmgr,
1494 table_info->vddc_lookup_table, vv_id, &sclk)) {
1495 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1496 PHM_PlatformCaps_ClockStretcher)) {
1497 for (j = 1; j < sclk_table->count; j++) {
1498 if (sclk_table->entries[j].clk == sclk &&
1499 sclk_table->entries[j].cks_enable == 0) {
1500 sclk += 5000;
1501 break;
1502 }
1503 }
1504 }
1505
1506 if (phm_get_voltage_evv_on_sclk(hwmgr,
1507 VOLTAGE_TYPE_VDDC,
1508 sclk, vv_id, &vddc) == 0) {
1509 if (vddc >= 2000 || vddc == 0)
1510 return -EINVAL;
1511 } else {
1512 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
1513 continue;
1514 }
1515
1516 /* the voltage should not be zero nor equal to leakage ID */
1517 if (vddc != 0 && vddc != vv_id) {
1518 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1519 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1520 data->vddc_leakage.count++;
1521 }
1522 }
1523 }
1524 }
1525
1526 return 0;
1527}
1528
1529/**
1530 * Change virtual leakage voltage to actual value.
1531 *
1532 * @param hwmgr the address of the powerplay hardware manager.
1533 * @param pointer to changing voltage
1534 * @param pointer to leakage table
1535 */
1536static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1537 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1538{
1539 uint32_t index;
1540
1541 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1542 for (index = 0; index < leakage_table->count; index++) {
1543 /* if this voltage matches a leakage voltage ID */
1544 /* patch with actual leakage voltage */
1545 if (leakage_table->leakage_id[index] == *voltage) {
1546 *voltage = leakage_table->actual_voltage[index];
1547 break;
1548 }
1549 }
1550
1551 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1552 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
1553}
1554
1555/**
1556* Patch voltage lookup table by EVV leakages.
1557*
1558* @param hwmgr the address of the powerplay hardware manager.
1559* @param pointer to voltage lookup table
1560* @param pointer to leakage table
1561* @return always 0
1562*/
1563static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1564 phm_ppt_v1_voltage_lookup_table *lookup_table,
1565 struct smu7_leakage_voltage *leakage_table)
1566{
1567 uint32_t i;
1568
1569 for (i = 0; i < lookup_table->count; i++)
1570 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1571 &lookup_table->entries[i].us_vdd, leakage_table);
1572
1573 return 0;
1574}
1575
1576static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1577 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1578 uint16_t *vddc)
1579{
1580 struct phm_ppt_v1_information *table_info =
1581 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1582 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1583 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1584 table_info->max_clock_voltage_on_dc.vddc;
1585 return 0;
1586}
1587
1588static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1589 struct pp_hwmgr *hwmgr)
1590{
1591 uint8_t entry_id;
1592 uint8_t voltage_id;
1593 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1594 struct phm_ppt_v1_information *table_info =
1595 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1596
1597 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1598 table_info->vdd_dep_on_sclk;
1599 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1600 table_info->vdd_dep_on_mclk;
1601 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1602 table_info->mm_dep_table;
1603
1604 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1605 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1606 voltage_id = sclk_table->entries[entry_id].vddInd;
1607 sclk_table->entries[entry_id].vddgfx =
1608 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1609 }
1610 } else {
1611 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1612 voltage_id = sclk_table->entries[entry_id].vddInd;
1613 sclk_table->entries[entry_id].vddc =
1614 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1615 }
1616 }
1617
1618 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1619 voltage_id = mclk_table->entries[entry_id].vddInd;
1620 mclk_table->entries[entry_id].vddc =
1621 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1622 }
1623
1624 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1625 voltage_id = mm_table->entries[entry_id].vddcInd;
1626 mm_table->entries[entry_id].vddc =
1627 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1628 }
1629
1630 return 0;
1631
1632}
1633
1634static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1635 phm_ppt_v1_voltage_lookup_table *look_up_table,
1636 phm_ppt_v1_voltage_lookup_record *record)
1637{
1638 uint32_t i;
1639
1640 PP_ASSERT_WITH_CODE((NULL != look_up_table),
1641 "Lookup Table empty.", return -EINVAL);
1642 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1643 "Lookup Table empty.", return -EINVAL);
1644
1645 i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
1646 PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1647 "Lookup Table is full.", return -EINVAL);
1648
1649 /* This is to avoid entering duplicate calculated records. */
1650 for (i = 0; i < look_up_table->count; i++) {
1651 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1652 if (look_up_table->entries[i].us_calculated == 1)
1653 return 0;
1654 break;
1655 }
1656 }
1657
1658 look_up_table->entries[i].us_calculated = 1;
1659 look_up_table->entries[i].us_vdd = record->us_vdd;
1660 look_up_table->entries[i].us_cac_low = record->us_cac_low;
1661 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1662 look_up_table->entries[i].us_cac_high = record->us_cac_high;
1663 /* Only increment the count when we're appending, not replacing duplicate entry. */
1664 if (i == look_up_table->count)
1665 look_up_table->count++;
1666
1667 return 0;
1668}
1669
1670
1671static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1672{
1673 uint8_t entry_id;
1674 struct phm_ppt_v1_voltage_lookup_record v_record;
1675 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1676 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1677
1678 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1679 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1680
1681 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1682 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1683 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1684 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1685 sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1686 else
1687 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1688 sclk_table->entries[entry_id].vdd_offset;
1689
1690 sclk_table->entries[entry_id].vddc =
1691 v_record.us_cac_low = v_record.us_cac_mid =
1692 v_record.us_cac_high = v_record.us_vdd;
1693
1694 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1695 }
1696
1697 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1698 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1699 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1700 mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1701 else
1702 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1703 mclk_table->entries[entry_id].vdd_offset;
1704
1705 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1706 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1707 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1708 }
1709 }
1710 return 0;
1711}
1712
1713static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1714{
1715 uint8_t entry_id;
1716 struct phm_ppt_v1_voltage_lookup_record v_record;
1717 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1718 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1719 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1720
1721 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1722 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1723 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1724 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1725 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1726 else
1727 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1728 mm_table->entries[entry_id].vddgfx_offset;
1729
1730 /* Add the calculated VDDGFX to the VDDGFX lookup table */
1731 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1732 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1733 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1734 }
1735 }
1736 return 0;
1737}
1738
1739static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1740 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1741{
1742 uint32_t table_size, i, j;
1743 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
1744 table_size = lookup_table->count;
1745
1746 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
1747 "Lookup table is empty", return -EINVAL);
1748
1749 /* Sorting voltages */
1750 for (i = 0; i < table_size - 1; i++) {
1751 for (j = i + 1; j > 0; j--) {
1752 if (lookup_table->entries[j].us_vdd <
1753 lookup_table->entries[j - 1].us_vdd) {
1754 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
1755 lookup_table->entries[j - 1] = lookup_table->entries[j];
1756 lookup_table->entries[j] = tmp_voltage_lookup_record;
1757 }
1758 }
1759 }
1760
1761 return 0;
1762}
1763
1764static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
1765{
1766 int result = 0;
1767 int tmp_result;
1768 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1769 struct phm_ppt_v1_information *table_info =
1770 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1771
1772 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1773 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
1774 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
1775 if (tmp_result != 0)
1776 result = tmp_result;
1777
1778 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1779 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
1780 } else {
1781
1782 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
1783 table_info->vddc_lookup_table, &(data->vddc_leakage));
1784 if (tmp_result)
1785 result = tmp_result;
1786
1787 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
1788 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
1789 if (tmp_result)
1790 result = tmp_result;
1791 }
1792
1793 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
1794 if (tmp_result)
1795 result = tmp_result;
1796
1797 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
1798 if (tmp_result)
1799 result = tmp_result;
1800
1801 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
1802 if (tmp_result)
1803 result = tmp_result;
1804
1805 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
1806 if (tmp_result)
1807 result = tmp_result;
1808
1809 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
1810 if (tmp_result)
1811 result = tmp_result;
1812
1813 return result;
1814}
1815
1816static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
1817{
1818 struct phm_ppt_v1_information *table_info =
1819 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1820
1821 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
1822 table_info->vdd_dep_on_sclk;
1823 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
1824 table_info->vdd_dep_on_mclk;
1825
1826 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
1827 "VDD dependency on SCLK table is missing.",
1828 return -EINVAL);
1829 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
1830 "VDD dependency on SCLK table has to have is missing.",
1831 return -EINVAL);
1832
1833 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
1834 "VDD dependency on MCLK table is missing",
1835 return -EINVAL);
1836 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
1837 "VDD dependency on MCLK table has to have is missing.",
1838 return -EINVAL);
1839
1840 table_info->max_clock_voltage_on_ac.sclk =
1841 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
1842 table_info->max_clock_voltage_on_ac.mclk =
1843 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
1844 table_info->max_clock_voltage_on_ac.vddc =
1845 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
1846 table_info->max_clock_voltage_on_ac.vddci =
1847 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
1848
1849 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
1850 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
1851 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
1852 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
1853
1854 return 0;
1855}
1856
1857int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
1858{
1859 struct phm_ppt_v1_information *table_info =
1860 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1861 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
1862 struct phm_ppt_v1_voltage_lookup_table *lookup_table;
1863 uint32_t i;
1864 uint32_t hw_revision, sub_vendor_id, sub_sys_id;
1865 struct cgs_system_info sys_info = {0};
1866
1867 if (table_info != NULL) {
1868 dep_mclk_table = table_info->vdd_dep_on_mclk;
1869 lookup_table = table_info->vddc_lookup_table;
1870 } else
1871 return 0;
1872
1873 sys_info.size = sizeof(struct cgs_system_info);
1874
1875 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
1876 cgs_query_system_info(hwmgr->device, &sys_info);
1877 hw_revision = (uint32_t)sys_info.value;
1878
1879 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID;
1880 cgs_query_system_info(hwmgr->device, &sys_info);
1881 sub_sys_id = (uint32_t)sys_info.value;
1882
1883 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID;
1884 cgs_query_system_info(hwmgr->device, &sys_info);
1885 sub_vendor_id = (uint32_t)sys_info.value;
1886
1887 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
1888 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
1889 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
1890 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
1891 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
1892 return 0;
1893
1894 for (i = 0; i < lookup_table->count; i++) {
1895 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
1896 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
1897 return 0;
1898 }
1899 }
1900 }
1901 return 0;
1902}
1903
1904static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
1905{
1906 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
1907 uint32_t temp_reg;
1908 struct phm_ppt_v1_information *table_info =
1909 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1910
1911
1912 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
1913 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
1914 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
1915 case 0:
1916 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
1917 break;
1918 case 1:
1919 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
1920 break;
1921 case 2:
1922 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
1923 break;
1924 case 3:
1925 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
1926 break;
1927 case 4:
1928 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
1929 break;
1930 default:
1931 PP_ASSERT_WITH_CODE(0,
1932 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
1933 );
1934 break;
1935 }
1936 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
1937 }
1938
1939 if (table_info == NULL)
1940 return 0;
1941
1942 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
1943 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
1944 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
1945 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
1946
1947 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
1948 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
1949
1950 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
1951
1952 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
1953
1954 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
1955 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
1956
1957 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
1958
1959 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
1960 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
1961
1962 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
1963 table_info->cac_dtp_table->usOperatingTempStep = 1;
1964 table_info->cac_dtp_table->usOperatingTempHyst = 1;
1965
1966 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
1967 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
1968
1969 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
1970 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
1971
1972 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
1973 table_info->cac_dtp_table->usOperatingTempMinLimit;
1974
1975 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
1976 table_info->cac_dtp_table->usOperatingTempMaxLimit;
1977
1978 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
1979 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
1980
1981 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
1982 table_info->cac_dtp_table->usOperatingTempStep;
1983
1984 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
1985 table_info->cac_dtp_table->usTargetOperatingTemp;
1986 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1987 PHM_PlatformCaps_ODFuzzyFanControlSupport);
1988 }
1989
1990 return 0;
1991}
1992
1993/**
1994 * Change virtual leakage voltage to actual value.
1995 *
1996 * @param hwmgr the address of the powerplay hardware manager.
1997 * @param pointer to changing voltage
1998 * @param pointer to leakage table
1999 */
2000static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2001 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2002{
2003 uint32_t index;
2004
2005 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2006 for (index = 0; index < leakage_table->count; index++) {
2007 /* if this voltage matches a leakage voltage ID */
2008 /* patch with actual leakage voltage */
2009 if (leakage_table->leakage_id[index] == *voltage) {
2010 *voltage = leakage_table->actual_voltage[index];
2011 break;
2012 }
2013 }
2014
2015 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2016 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2017}
2018
2019
2020static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2021 struct phm_clock_voltage_dependency_table *tab)
2022{
2023 uint16_t i;
2024 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2025
2026 if (tab)
2027 for (i = 0; i < tab->count; i++)
2028 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2029 &data->vddc_leakage);
2030
2031 return 0;
2032}
2033
2034static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2035 struct phm_clock_voltage_dependency_table *tab)
2036{
2037 uint16_t i;
2038 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2039
2040 if (tab)
2041 for (i = 0; i < tab->count; i++)
2042 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2043 &data->vddci_leakage);
2044
2045 return 0;
2046}
2047
2048static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2049 struct phm_vce_clock_voltage_dependency_table *tab)
2050{
2051 uint16_t i;
2052 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2053
2054 if (tab)
2055 for (i = 0; i < tab->count; i++)
2056 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2057 &data->vddc_leakage);
2058
2059 return 0;
2060}
2061
2062
2063static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2064 struct phm_uvd_clock_voltage_dependency_table *tab)
2065{
2066 uint16_t i;
2067 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2068
2069 if (tab)
2070 for (i = 0; i < tab->count; i++)
2071 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2072 &data->vddc_leakage);
2073
2074 return 0;
2075}
2076
2077static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2078 struct phm_phase_shedding_limits_table *tab)
2079{
2080 uint16_t i;
2081 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2082
2083 if (tab)
2084 for (i = 0; i < tab->count; i++)
2085 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2086 &data->vddc_leakage);
2087
2088 return 0;
2089}
2090
2091static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2092 struct phm_samu_clock_voltage_dependency_table *tab)
2093{
2094 uint16_t i;
2095 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2096
2097 if (tab)
2098 for (i = 0; i < tab->count; i++)
2099 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2100 &data->vddc_leakage);
2101
2102 return 0;
2103}
2104
2105static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2106 struct phm_acp_clock_voltage_dependency_table *tab)
2107{
2108 uint16_t i;
2109 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2110
2111 if (tab)
2112 for (i = 0; i < tab->count; i++)
2113 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2114 &data->vddc_leakage);
2115
2116 return 0;
2117}
2118
2119static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2120 struct phm_clock_and_voltage_limits *tab)
2121{
2122 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2123
2124 if (tab) {
2125 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddc,
2126 &data->vddc_leakage);
2127 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddci,
2128 &data->vddci_leakage);
2129 }
2130
2131 return 0;
2132}
2133
2134static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2135{
2136 uint32_t i;
2137 uint32_t vddc;
2138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2139
2140 if (tab) {
2141 for (i = 0; i < tab->count; i++) {
2142 vddc = (uint32_t)(tab->entries[i].Vddc);
2143 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2144 tab->entries[i].Vddc = (uint16_t)vddc;
2145 }
2146 }
2147
2148 return 0;
2149}
2150
2151static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2152{
2153 int tmp;
2154
2155 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2156 if (tmp)
2157 return -EINVAL;
2158
2159 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2160 if (tmp)
2161 return -EINVAL;
2162
2163 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2164 if (tmp)
2165 return -EINVAL;
2166
2167 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2168 if (tmp)
2169 return -EINVAL;
2170
2171 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2172 if (tmp)
2173 return -EINVAL;
2174
2175 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2176 if (tmp)
2177 return -EINVAL;
2178
2179 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2180 if (tmp)
2181 return -EINVAL;
2182
2183 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2184 if (tmp)
2185 return -EINVAL;
2186
2187 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2188 if (tmp)
2189 return -EINVAL;
2190
2191 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2192 if (tmp)
2193 return -EINVAL;
2194
2195 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2196 if (tmp)
2197 return -EINVAL;
2198
2199 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2200 if (tmp)
2201 return -EINVAL;
2202
2203 return 0;
2204}
2205
2206
2207static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2208{
2209 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2210
2211 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2212 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2213 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2214
2215 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2216 "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL);
2217 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2218 "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
2219
2220 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2221 "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL);
2222 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2223 "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
2224
2225 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2226 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2227
2228 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2229 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2230 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2231 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2232 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2233 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2234
2235 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2236 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2237 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2238 }
2239
2240 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1)
2241 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2242
2243 return 0;
2244}
2245
2246int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2247{
2248 struct smu7_hwmgr *data;
2249 int result;
2250
2251 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2252 if (data == NULL)
2253 return -ENOMEM;
2254
2255 hwmgr->backend = data;
2256
2257 smu7_patch_voltage_workaround(hwmgr);
2258 smu7_init_dpm_defaults(hwmgr);
2259
2260 /* Get leakage voltage based on leakage ID. */
2261 result = smu7_get_evv_voltages(hwmgr);
2262
2263 if (result) {
2264 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
2265 return -EINVAL;
2266 }
2267
2268 if (hwmgr->pp_table_version == PP_TABLE_V1) {
2269 smu7_complete_dependency_tables(hwmgr);
2270 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2271 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2272 smu7_patch_dependency_tables_with_leakage(hwmgr);
2273 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2274 }
2275
2276 /* Initalize Dynamic State Adjustment Rule Settings */
2277 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2278
2279 if (0 == result) {
2280 struct cgs_system_info sys_info = {0};
2281
2282 data->is_tlu_enabled = false;
2283
2284 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2285 SMU7_MAX_HARDWARE_POWERLEVELS;
2286 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2287 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2288
2289 sys_info.size = sizeof(struct cgs_system_info);
2290 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
2291 result = cgs_query_system_info(hwmgr->device, &sys_info);
2292 if (result)
2293 data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2294 else
2295 data->pcie_gen_cap = (uint32_t)sys_info.value;
2296 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2297 data->pcie_spc_cap = 20;
2298 sys_info.size = sizeof(struct cgs_system_info);
2299 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
2300 result = cgs_query_system_info(hwmgr->device, &sys_info);
2301 if (result)
2302 data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2303 else
2304 data->pcie_lane_cap = (uint32_t)sys_info.value;
2305
2306 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2307/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2308 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2309 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2310 smu7_thermal_parameter_init(hwmgr);
2311 } else {
2312 /* Ignore return value in here, we are cleaning up a mess. */
2313 phm_hwmgr_backend_fini(hwmgr);
2314 }
2315
2316 return 0;
2317}
2318
2319static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2320{
2321 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2322 uint32_t level, tmp;
2323
2324 if (!data->pcie_dpm_key_disabled) {
2325 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2326 level = 0;
2327 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2328 while (tmp >>= 1)
2329 level++;
2330
2331 if (level)
2332 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2333 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2334 }
2335 }
2336
2337 if (!data->sclk_dpm_key_disabled) {
2338 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2339 level = 0;
2340 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2341 while (tmp >>= 1)
2342 level++;
2343
2344 if (level)
2345 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2346 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2347 (1 << level));
2348 }
2349 }
2350
2351 if (!data->mclk_dpm_key_disabled) {
2352 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2353 level = 0;
2354 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2355 while (tmp >>= 1)
2356 level++;
2357
2358 if (level)
2359 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2360 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2361 (1 << level));
2362 }
2363 }
2364
2365 return 0;
2366}
2367
2368static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2369{
2370 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2371
2372 if (hwmgr->pp_table_version == PP_TABLE_V1)
2373 phm_apply_dal_min_voltage_request(hwmgr);
2374/* TO DO for v0 iceland and Ci*/
2375
2376 if (!data->sclk_dpm_key_disabled) {
2377 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2378 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2379 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2380 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2381 }
2382
2383 if (!data->mclk_dpm_key_disabled) {
2384 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2385 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2386 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2387 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2388 }
2389
2390 return 0;
2391}
2392
2393static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2394{
2395 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2396
2397 if (!smum_is_dpm_running(hwmgr))
2398 return -EINVAL;
2399
2400 if (!data->pcie_dpm_key_disabled) {
2401 smum_send_msg_to_smc(hwmgr->smumgr,
2402 PPSMC_MSG_PCIeDPM_UnForceLevel);
2403 }
2404
2405 return smu7_upload_dpm_level_enable_mask(hwmgr);
2406}
2407
2408static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2409{
2410 struct smu7_hwmgr *data =
2411 (struct smu7_hwmgr *)(hwmgr->backend);
2412 uint32_t level;
2413
2414 if (!data->sclk_dpm_key_disabled)
2415 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2416 level = phm_get_lowest_enabled_level(hwmgr,
2417 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2418 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2419 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2420 (1 << level));
2421
2422 }
2423
2424 if (!data->mclk_dpm_key_disabled) {
2425 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2426 level = phm_get_lowest_enabled_level(hwmgr,
2427 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2428 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2429 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2430 (1 << level));
2431 }
2432 }
2433
2434 if (!data->pcie_dpm_key_disabled) {
2435 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2436 level = phm_get_lowest_enabled_level(hwmgr,
2437 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2438 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2439 PPSMC_MSG_PCIeDPM_ForceLevel,
2440 (level));
2441 }
2442 }
2443
2444 return 0;
2445
2446}
2447static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2448 enum amd_dpm_forced_level level)
2449{
2450 int ret = 0;
2451
2452 switch (level) {
2453 case AMD_DPM_FORCED_LEVEL_HIGH:
2454 ret = smu7_force_dpm_highest(hwmgr);
2455 if (ret)
2456 return ret;
2457 break;
2458 case AMD_DPM_FORCED_LEVEL_LOW:
2459 ret = smu7_force_dpm_lowest(hwmgr);
2460 if (ret)
2461 return ret;
2462 break;
2463 case AMD_DPM_FORCED_LEVEL_AUTO:
2464 ret = smu7_unforce_dpm_levels(hwmgr);
2465 if (ret)
2466 return ret;
2467 break;
2468 default:
2469 break;
2470 }
2471
2472 hwmgr->dpm_level = level;
2473
2474 return ret;
2475}
2476
2477static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2478{
2479 return sizeof(struct smu7_power_state);
2480}
2481
2482
2483static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2484 struct pp_power_state *request_ps,
2485 const struct pp_power_state *current_ps)
2486{
2487
2488 struct smu7_power_state *smu7_ps =
2489 cast_phw_smu7_power_state(&request_ps->hardware);
2490 uint32_t sclk;
2491 uint32_t mclk;
2492 struct PP_Clocks minimum_clocks = {0};
2493 bool disable_mclk_switching;
2494 bool disable_mclk_switching_for_frame_lock;
2495 struct cgs_display_info info = {0};
2496 const struct phm_clock_and_voltage_limits *max_limits;
2497 uint32_t i;
2498 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2499 struct phm_ppt_v1_information *table_info =
2500 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2501 int32_t count;
2502 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2503
2504 data->battery_state = (PP_StateUILabel_Battery ==
2505 request_ps->classification.ui_label);
2506
2507 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2508 "VI should always have 2 performance levels",
2509 );
2510
2511 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
2512 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2513 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2514
2515 /* Cap clock DPM tables at DC MAX if it is in DC. */
2516 if (PP_PowerSource_DC == hwmgr->power_source) {
2517 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2518 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2519 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2520 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2521 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2522 }
2523 }
2524
2525 smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
2526 smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
2527
2528 cgs_get_active_displays_info(hwmgr->device, &info);
2529
2530 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
2531
2532 minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
2533 minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
2534
2535 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2536 PHM_PlatformCaps_StablePState)) {
2537 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2538 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2539
2540 for (count = table_info->vdd_dep_on_sclk->count - 1;
2541 count >= 0; count--) {
2542 if (stable_pstate_sclk >=
2543 table_info->vdd_dep_on_sclk->entries[count].clk) {
2544 stable_pstate_sclk =
2545 table_info->vdd_dep_on_sclk->entries[count].clk;
2546 break;
2547 }
2548 }
2549
2550 if (count < 0)
2551 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2552
2553 stable_pstate_mclk = max_limits->mclk;
2554
2555 minimum_clocks.engineClock = stable_pstate_sclk;
2556 minimum_clocks.memoryClock = stable_pstate_mclk;
2557 }
2558
2559 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
2560 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
2561
2562 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
2563 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
2564
2565 smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
2566
2567 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
2568 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
2569 hwmgr->platform_descriptor.overdriveLimit.engineClock),
2570 "Overdrive sclk exceeds limit",
2571 hwmgr->gfx_arbiter.sclk_over_drive =
2572 hwmgr->platform_descriptor.overdriveLimit.engineClock);
2573
2574 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2575 smu7_ps->performance_levels[1].engine_clock =
2576 hwmgr->gfx_arbiter.sclk_over_drive;
2577 }
2578
2579 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
2580 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
2581 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
2582 "Overdrive mclk exceeds limit",
2583 hwmgr->gfx_arbiter.mclk_over_drive =
2584 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
2585
2586 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2587 smu7_ps->performance_levels[1].memory_clock =
2588 hwmgr->gfx_arbiter.mclk_over_drive;
2589 }
2590
2591 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2592 hwmgr->platform_descriptor.platformCaps,
2593 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2594
2595
2596 disable_mclk_switching = (1 < info.display_count) ||
2597 disable_mclk_switching_for_frame_lock;
2598
2599 sclk = smu7_ps->performance_levels[0].engine_clock;
2600 mclk = smu7_ps->performance_levels[0].memory_clock;
2601
2602 if (disable_mclk_switching)
2603 mclk = smu7_ps->performance_levels
2604 [smu7_ps->performance_level_count - 1].memory_clock;
2605
2606 if (sclk < minimum_clocks.engineClock)
2607 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2608 max_limits->sclk : minimum_clocks.engineClock;
2609
2610 if (mclk < minimum_clocks.memoryClock)
2611 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2612 max_limits->mclk : minimum_clocks.memoryClock;
2613
2614 smu7_ps->performance_levels[0].engine_clock = sclk;
2615 smu7_ps->performance_levels[0].memory_clock = mclk;
2616
2617 smu7_ps->performance_levels[1].engine_clock =
2618 (smu7_ps->performance_levels[1].engine_clock >=
2619 smu7_ps->performance_levels[0].engine_clock) ?
2620 smu7_ps->performance_levels[1].engine_clock :
2621 smu7_ps->performance_levels[0].engine_clock;
2622
2623 if (disable_mclk_switching) {
2624 if (mclk < smu7_ps->performance_levels[1].memory_clock)
2625 mclk = smu7_ps->performance_levels[1].memory_clock;
2626
2627 smu7_ps->performance_levels[0].memory_clock = mclk;
2628 smu7_ps->performance_levels[1].memory_clock = mclk;
2629 } else {
2630 if (smu7_ps->performance_levels[1].memory_clock <
2631 smu7_ps->performance_levels[0].memory_clock)
2632 smu7_ps->performance_levels[1].memory_clock =
2633 smu7_ps->performance_levels[0].memory_clock;
2634 }
2635
2636 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2637 PHM_PlatformCaps_StablePState)) {
2638 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2639 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
2640 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
2641 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
2642 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
2643 }
2644 }
2645 return 0;
2646}
2647
2648
2649static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2650{
2651 struct pp_power_state *ps;
2652 struct smu7_power_state *smu7_ps;
2653
2654 if (hwmgr == NULL)
2655 return -EINVAL;
2656
2657 ps = hwmgr->request_ps;
2658
2659 if (ps == NULL)
2660 return -EINVAL;
2661
2662 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
2663
2664 if (low)
2665 return smu7_ps->performance_levels[0].memory_clock;
2666 else
2667 return smu7_ps->performance_levels
2668 [smu7_ps->performance_level_count-1].memory_clock;
2669}
2670
2671static int smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2672{
2673 struct pp_power_state *ps;
2674 struct smu7_power_state *smu7_ps;
2675
2676 if (hwmgr == NULL)
2677 return -EINVAL;
2678
2679 ps = hwmgr->request_ps;
2680
2681 if (ps == NULL)
2682 return -EINVAL;
2683
2684 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
2685
2686 if (low)
2687 return smu7_ps->performance_levels[0].engine_clock;
2688 else
2689 return smu7_ps->performance_levels
2690 [smu7_ps->performance_level_count-1].engine_clock;
2691}
2692
2693static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
2694 struct pp_hw_power_state *hw_ps)
2695{
2696 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2697 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
2698 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
2699 uint16_t size;
2700 uint8_t frev, crev;
2701 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2702
2703 /* First retrieve the Boot clocks and VDDC from the firmware info table.
2704 * We assume here that fw_info is unchanged if this call fails.
2705 */
2706 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
2707 hwmgr->device, index,
2708 &size, &frev, &crev);
2709 if (!fw_info)
2710 /* During a test, there is no firmware info table. */
2711 return 0;
2712
2713 /* Patch the state. */
2714 data->vbios_boot_state.sclk_bootup_value =
2715 le32_to_cpu(fw_info->ulDefaultEngineClock);
2716 data->vbios_boot_state.mclk_bootup_value =
2717 le32_to_cpu(fw_info->ulDefaultMemoryClock);
2718 data->vbios_boot_state.mvdd_bootup_value =
2719 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
2720 data->vbios_boot_state.vddc_bootup_value =
2721 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
2722 data->vbios_boot_state.vddci_bootup_value =
2723 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
2724 data->vbios_boot_state.pcie_gen_bootup_value =
2725 smu7_get_current_pcie_speed(hwmgr);
2726
2727 data->vbios_boot_state.pcie_lane_bootup_value =
2728 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
2729
2730 /* set boot power state */
2731 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
2732 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
2733 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
2734 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
2735
2736 return 0;
2737}
2738
2739static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
2740{
2741 int result;
2742 unsigned long ret = 0;
2743
2744 if (hwmgr->pp_table_version == PP_TABLE_V0) {
2745 result = pp_tables_get_num_of_entries(hwmgr, &ret);
2746 return result ? 0 : ret;
2747 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2748 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
2749 return result;
2750 }
2751 return 0;
2752}
2753
2754static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
2755 void *state, struct pp_power_state *power_state,
2756 void *pp_table, uint32_t classification_flag)
2757{
2758 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2759 struct smu7_power_state *smu7_power_state =
2760 (struct smu7_power_state *)(&(power_state->hardware));
2761 struct smu7_performance_level *performance_level;
2762 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
2763 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
2764 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
2765 PPTable_Generic_SubTable_Header *sclk_dep_table =
2766 (PPTable_Generic_SubTable_Header *)
2767 (((unsigned long)powerplay_table) +
2768 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
2769
2770 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
2771 (ATOM_Tonga_MCLK_Dependency_Table *)
2772 (((unsigned long)powerplay_table) +
2773 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2774
2775 /* The following fields are not initialized here: id orderedList allStatesList */
2776 power_state->classification.ui_label =
2777 (le16_to_cpu(state_entry->usClassification) &
2778 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2779 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2780 power_state->classification.flags = classification_flag;
2781 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
2782
2783 power_state->classification.temporary_state = false;
2784 power_state->classification.to_be_deleted = false;
2785
2786 power_state->validation.disallowOnDC =
2787 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2788 ATOM_Tonga_DISALLOW_ON_DC));
2789
2790 power_state->pcie.lanes = 0;
2791
2792 power_state->display.disableFrameModulation = false;
2793 power_state->display.limitRefreshrate = false;
2794 power_state->display.enableVariBright =
2795 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
2796 ATOM_Tonga_ENABLE_VARIBRIGHT));
2797
2798 power_state->validation.supportedPowerLevels = 0;
2799 power_state->uvd_clocks.VCLK = 0;
2800 power_state->uvd_clocks.DCLK = 0;
2801 power_state->temperatures.min = 0;
2802 power_state->temperatures.max = 0;
2803
2804 performance_level = &(smu7_power_state->performance_levels
2805 [smu7_power_state->performance_level_count++]);
2806
2807 PP_ASSERT_WITH_CODE(
2808 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
2809 "Performance levels exceeds SMC limit!",
2810 return -EINVAL);
2811
2812 PP_ASSERT_WITH_CODE(
2813 (smu7_power_state->performance_level_count <=
2814 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
2815 "Performance levels exceeds Driver limit!",
2816 return -EINVAL);
2817
2818 /* Performance levels are arranged from low to high. */
2819 performance_level->memory_clock = mclk_dep_table->entries
2820 [state_entry->ucMemoryClockIndexLow].ulMclk;
2821 if (sclk_dep_table->ucRevId == 0)
2822 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
2823 [state_entry->ucEngineClockIndexLow].ulSclk;
2824 else if (sclk_dep_table->ucRevId == 1)
2825 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
2826 [state_entry->ucEngineClockIndexLow].ulSclk;
2827 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
2828 state_entry->ucPCIEGenLow);
2829 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
2830 state_entry->ucPCIELaneHigh);
2831
2832 performance_level = &(smu7_power_state->performance_levels
2833 [smu7_power_state->performance_level_count++]);
2834 performance_level->memory_clock = mclk_dep_table->entries
2835 [state_entry->ucMemoryClockIndexHigh].ulMclk;
2836
2837 if (sclk_dep_table->ucRevId == 0)
2838 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
2839 [state_entry->ucEngineClockIndexHigh].ulSclk;
2840 else if (sclk_dep_table->ucRevId == 1)
2841 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
2842 [state_entry->ucEngineClockIndexHigh].ulSclk;
2843
2844 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
2845 state_entry->ucPCIEGenHigh);
2846 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
2847 state_entry->ucPCIELaneHigh);
2848
2849 return 0;
2850}
2851
2852static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
2853 unsigned long entry_index, struct pp_power_state *state)
2854{
2855 int result;
2856 struct smu7_power_state *ps;
2857 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2858 struct phm_ppt_v1_information *table_info =
2859 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2860 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
2861 table_info->vdd_dep_on_mclk;
2862
2863 state->hardware.magic = PHM_VIslands_Magic;
2864
2865 ps = (struct smu7_power_state *)(&state->hardware);
2866
2867 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
2868 smu7_get_pp_table_entry_callback_func_v1);
2869
2870 /* This is the earliest time we have all the dependency table and the VBIOS boot state
2871 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
2872 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
2873 */
2874 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
2875 if (dep_mclk_table->entries[0].clk !=
2876 data->vbios_boot_state.mclk_bootup_value)
2877 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
2878 "does not match VBIOS boot MCLK level");
2879 if (dep_mclk_table->entries[0].vddci !=
2880 data->vbios_boot_state.vddci_bootup_value)
2881 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
2882 "does not match VBIOS boot VDDCI level");
2883 }
2884
2885 /* set DC compatible flag if this state supports DC */
2886 if (!state->validation.disallowOnDC)
2887 ps->dc_compatible = true;
2888
2889 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
2890 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
2891
2892 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
2893 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
2894
2895 if (!result) {
2896 uint32_t i;
2897
2898 switch (state->classification.ui_label) {
2899 case PP_StateUILabel_Performance:
2900 data->use_pcie_performance_levels = true;
2901 for (i = 0; i < ps->performance_level_count; i++) {
2902 if (data->pcie_gen_performance.max <
2903 ps->performance_levels[i].pcie_gen)
2904 data->pcie_gen_performance.max =
2905 ps->performance_levels[i].pcie_gen;
2906
2907 if (data->pcie_gen_performance.min >
2908 ps->performance_levels[i].pcie_gen)
2909 data->pcie_gen_performance.min =
2910 ps->performance_levels[i].pcie_gen;
2911
2912 if (data->pcie_lane_performance.max <
2913 ps->performance_levels[i].pcie_lane)
2914 data->pcie_lane_performance.max =
2915 ps->performance_levels[i].pcie_lane;
2916 if (data->pcie_lane_performance.min >
2917 ps->performance_levels[i].pcie_lane)
2918 data->pcie_lane_performance.min =
2919 ps->performance_levels[i].pcie_lane;
2920 }
2921 break;
2922 case PP_StateUILabel_Battery:
2923 data->use_pcie_power_saving_levels = true;
2924
2925 for (i = 0; i < ps->performance_level_count; i++) {
2926 if (data->pcie_gen_power_saving.max <
2927 ps->performance_levels[i].pcie_gen)
2928 data->pcie_gen_power_saving.max =
2929 ps->performance_levels[i].pcie_gen;
2930
2931 if (data->pcie_gen_power_saving.min >
2932 ps->performance_levels[i].pcie_gen)
2933 data->pcie_gen_power_saving.min =
2934 ps->performance_levels[i].pcie_gen;
2935
2936 if (data->pcie_lane_power_saving.max <
2937 ps->performance_levels[i].pcie_lane)
2938 data->pcie_lane_power_saving.max =
2939 ps->performance_levels[i].pcie_lane;
2940
2941 if (data->pcie_lane_power_saving.min >
2942 ps->performance_levels[i].pcie_lane)
2943 data->pcie_lane_power_saving.min =
2944 ps->performance_levels[i].pcie_lane;
2945 }
2946 break;
2947 default:
2948 break;
2949 }
2950 }
2951 return 0;
2952}
2953
2954static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
2955 struct pp_hw_power_state *power_state,
2956 unsigned int index, const void *clock_info)
2957{
2958 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2959 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state);
2960 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
2961 struct smu7_performance_level *performance_level;
2962 uint32_t engine_clock, memory_clock;
2963 uint16_t pcie_gen_from_bios;
2964
2965 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
2966 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
2967
2968 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
2969 data->highest_mclk = memory_clock;
2970
2971 performance_level = &(ps->performance_levels
2972 [ps->performance_level_count++]);
2973
2974 PP_ASSERT_WITH_CODE(
2975 (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
2976 "Performance levels exceeds SMC limit!",
2977 return -EINVAL);
2978
2979 PP_ASSERT_WITH_CODE(
2980 (ps->performance_level_count <=
2981 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
2982 "Performance levels exceeds Driver limit!",
2983 return -EINVAL);
2984
2985 /* Performance levels are arranged from low to high. */
2986 performance_level->memory_clock = memory_clock;
2987 performance_level->engine_clock = engine_clock;
2988
2989 pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
2990
2991 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
2992 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
2993
2994 return 0;
2995}
2996
2997static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
2998 unsigned long entry_index, struct pp_power_state *state)
2999{
3000 int result;
3001 struct smu7_power_state *ps;
3002 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3003 struct phm_clock_voltage_dependency_table *dep_mclk_table =
3004 hwmgr->dyn_state.vddci_dependency_on_mclk;
3005
3006 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3007
3008 state->hardware.magic = PHM_VIslands_Magic;
3009
3010 ps = (struct smu7_power_state *)(&state->hardware);
3011
3012 result = pp_tables_get_entry(hwmgr, entry_index, state,
3013 smu7_get_pp_table_entry_callback_func_v0);
3014
3015 /*
3016 * This is the earliest time we have all the dependency table
3017 * and the VBIOS boot state as
3018 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3019 * state if there is only one VDDCI/MCLK level, check if it's
3020 * the same as VBIOS boot state
3021 */
3022 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3023 if (dep_mclk_table->entries[0].clk !=
3024 data->vbios_boot_state.mclk_bootup_value)
3025 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3026 "does not match VBIOS boot MCLK level");
3027 if (dep_mclk_table->entries[0].v !=
3028 data->vbios_boot_state.vddci_bootup_value)
3029 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3030 "does not match VBIOS boot VDDCI level");
3031 }
3032
3033 /* set DC compatible flag if this state supports DC */
3034 if (!state->validation.disallowOnDC)
3035 ps->dc_compatible = true;
3036
3037 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3038 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3039
3040 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3041 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3042
3043 if (!result) {
3044 uint32_t i;
3045
3046 switch (state->classification.ui_label) {
3047 case PP_StateUILabel_Performance:
3048 data->use_pcie_performance_levels = true;
3049
3050 for (i = 0; i < ps->performance_level_count; i++) {
3051 if (data->pcie_gen_performance.max <
3052 ps->performance_levels[i].pcie_gen)
3053 data->pcie_gen_performance.max =
3054 ps->performance_levels[i].pcie_gen;
3055
3056 if (data->pcie_gen_performance.min >
3057 ps->performance_levels[i].pcie_gen)
3058 data->pcie_gen_performance.min =
3059 ps->performance_levels[i].pcie_gen;
3060
3061 if (data->pcie_lane_performance.max <
3062 ps->performance_levels[i].pcie_lane)
3063 data->pcie_lane_performance.max =
3064 ps->performance_levels[i].pcie_lane;
3065
3066 if (data->pcie_lane_performance.min >
3067 ps->performance_levels[i].pcie_lane)
3068 data->pcie_lane_performance.min =
3069 ps->performance_levels[i].pcie_lane;
3070 }
3071 break;
3072 case PP_StateUILabel_Battery:
3073 data->use_pcie_power_saving_levels = true;
3074
3075 for (i = 0; i < ps->performance_level_count; i++) {
3076 if (data->pcie_gen_power_saving.max <
3077 ps->performance_levels[i].pcie_gen)
3078 data->pcie_gen_power_saving.max =
3079 ps->performance_levels[i].pcie_gen;
3080
3081 if (data->pcie_gen_power_saving.min >
3082 ps->performance_levels[i].pcie_gen)
3083 data->pcie_gen_power_saving.min =
3084 ps->performance_levels[i].pcie_gen;
3085
3086 if (data->pcie_lane_power_saving.max <
3087 ps->performance_levels[i].pcie_lane)
3088 data->pcie_lane_power_saving.max =
3089 ps->performance_levels[i].pcie_lane;
3090
3091 if (data->pcie_lane_power_saving.min >
3092 ps->performance_levels[i].pcie_lane)
3093 data->pcie_lane_power_saving.min =
3094 ps->performance_levels[i].pcie_lane;
3095 }
3096 break;
3097 default:
3098 break;
3099 }
3100 }
3101 return 0;
3102}
3103
3104static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3105 unsigned long entry_index, struct pp_power_state *state)
3106{
3107 if (hwmgr->pp_table_version == PP_TABLE_V0)
3108 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3109 else if (hwmgr->pp_table_version == PP_TABLE_V1)
3110 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3111
3112 return 0;
3113}
3114
3115static void
3116smu7_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3117{
3118 uint32_t sclk, mclk, activity_percent;
3119 uint32_t offset;
3120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3121
3122 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3123
3124 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3125
3126 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3127
3128 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3129 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3130 mclk / 100, sclk / 100);
3131
3132 offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
3133 SMU_SoftRegisters,
3134 AverageGraphicsActivity);
3135
3136 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3137 activity_percent += 0x80;
3138 activity_percent >>= 8;
3139
3140 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3141
3142 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3143
3144 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
3145}
3146
3147static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3148{
3149 const struct phm_set_power_state_input *states =
3150 (const struct phm_set_power_state_input *)input;
3151 const struct smu7_power_state *smu7_ps =
3152 cast_const_phw_smu7_power_state(states->pnew_state);
3153 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3154 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3155 uint32_t sclk = smu7_ps->performance_levels
3156 [smu7_ps->performance_level_count - 1].engine_clock;
3157 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3158 uint32_t mclk = smu7_ps->performance_levels
3159 [smu7_ps->performance_level_count - 1].memory_clock;
3160 struct PP_Clocks min_clocks = {0};
3161 uint32_t i;
3162 struct cgs_display_info info = {0};
3163
3164 data->need_update_smu7_dpm_table = 0;
3165
3166 for (i = 0; i < sclk_table->count; i++) {
3167 if (sclk == sclk_table->dpm_levels[i].value)
3168 break;
3169 }
3170
3171 if (i >= sclk_table->count)
3172 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3173 else {
3174 /* TODO: Check SCLK in DAL's minimum clocks
3175 * in case DeepSleep divider update is required.
3176 */
3177 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3178 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3179 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3180 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3181 }
3182
3183 for (i = 0; i < mclk_table->count; i++) {
3184 if (mclk == mclk_table->dpm_levels[i].value)
3185 break;
3186 }
3187
3188 if (i >= mclk_table->count)
3189 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3190
3191 cgs_get_active_displays_info(hwmgr->device, &info);
3192
3193 if (data->display_timing.num_existing_displays != info.display_count)
3194 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3195
3196 return 0;
3197}
3198
3199static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3200 const struct smu7_power_state *smu7_ps)
3201{
3202 uint32_t i;
3203 uint32_t sclk, max_sclk = 0;
3204 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3205 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3206
3207 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3208 sclk = smu7_ps->performance_levels[i].engine_clock;
3209 if (max_sclk < sclk)
3210 max_sclk = sclk;
3211 }
3212
3213 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3214 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3215 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3216 dpm_table->pcie_speed_table.dpm_levels
3217 [dpm_table->pcie_speed_table.count - 1].value :
3218 dpm_table->pcie_speed_table.dpm_levels[i].value);
3219 }
3220
3221 return 0;
3222}
3223
3224static int smu7_request_link_speed_change_before_state_change(
3225 struct pp_hwmgr *hwmgr, const void *input)
3226{
3227 const struct phm_set_power_state_input *states =
3228 (const struct phm_set_power_state_input *)input;
3229 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3230 const struct smu7_power_state *smu7_nps =
3231 cast_const_phw_smu7_power_state(states->pnew_state);
3232 const struct smu7_power_state *polaris10_cps =
3233 cast_const_phw_smu7_power_state(states->pcurrent_state);
3234
3235 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3236 uint16_t current_link_speed;
3237
3238 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3239 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3240 else
3241 current_link_speed = data->force_pcie_gen;
3242
3243 data->force_pcie_gen = PP_PCIEGenInvalid;
3244 data->pspp_notify_required = false;
3245
3246 if (target_link_speed > current_link_speed) {
3247 switch (target_link_speed) {
3248 case PP_PCIEGen3:
3249 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3250 break;
3251 data->force_pcie_gen = PP_PCIEGen2;
3252 if (current_link_speed == PP_PCIEGen2)
3253 break;
3254 case PP_PCIEGen2:
3255 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3256 break;
3257 default:
3258 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3259 break;
3260 }
3261 } else {
3262 if (target_link_speed < current_link_speed)
3263 data->pspp_notify_required = true;
3264 }
3265
3266 return 0;
3267}
3268
3269static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3270{
3271 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3272
3273 if (0 == data->need_update_smu7_dpm_table)
3274 return 0;
3275
3276 if ((0 == data->sclk_dpm_key_disabled) &&
3277 (data->need_update_smu7_dpm_table &
3278 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3279 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3280 "Trying to freeze SCLK DPM when DPM is disabled",
3281 );
3282 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3283 PPSMC_MSG_SCLKDPM_FreezeLevel),
3284 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3285 return -EINVAL);
3286 }
3287
3288 if ((0 == data->mclk_dpm_key_disabled) &&
3289 (data->need_update_smu7_dpm_table &
3290 DPMTABLE_OD_UPDATE_MCLK)) {
3291 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3292 "Trying to freeze MCLK DPM when DPM is disabled",
3293 );
3294 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3295 PPSMC_MSG_MCLKDPM_FreezeLevel),
3296 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3297 return -EINVAL);
3298 }
3299
3300 return 0;
3301}
3302
3303static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3304 struct pp_hwmgr *hwmgr, const void *input)
3305{
3306 int result = 0;
3307 const struct phm_set_power_state_input *states =
3308 (const struct phm_set_power_state_input *)input;
3309 const struct smu7_power_state *smu7_ps =
3310 cast_const_phw_smu7_power_state(states->pnew_state);
3311 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3312 uint32_t sclk = smu7_ps->performance_levels
3313 [smu7_ps->performance_level_count - 1].engine_clock;
3314 uint32_t mclk = smu7_ps->performance_levels
3315 [smu7_ps->performance_level_count - 1].memory_clock;
3316 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3317
3318 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3319 uint32_t dpm_count, clock_percent;
3320 uint32_t i;
3321
3322 if (0 == data->need_update_smu7_dpm_table)
3323 return 0;
3324
3325 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3326 dpm_table->sclk_table.dpm_levels
3327 [dpm_table->sclk_table.count - 1].value = sclk;
3328
3329 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3330 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3331 /* Need to do calculation based on the golden DPM table
3332 * as the Heatmap GPU Clock axis is also based on the default values
3333 */
3334 PP_ASSERT_WITH_CODE(
3335 (golden_dpm_table->sclk_table.dpm_levels
3336 [golden_dpm_table->sclk_table.count - 1].value != 0),
3337 "Divide by 0!",
3338 return -EINVAL);
3339 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3340
3341 for (i = dpm_count; i > 1; i--) {
3342 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3343 clock_percent =
3344 ((sclk
3345 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3346 ) * 100)
3347 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3348
3349 dpm_table->sclk_table.dpm_levels[i].value =
3350 golden_dpm_table->sclk_table.dpm_levels[i].value +
3351 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3352 clock_percent)/100;
3353
3354 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3355 clock_percent =
3356 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3357 - sclk) * 100)
3358 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3359
3360 dpm_table->sclk_table.dpm_levels[i].value =
3361 golden_dpm_table->sclk_table.dpm_levels[i].value -
3362 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3363 clock_percent) / 100;
3364 } else
3365 dpm_table->sclk_table.dpm_levels[i].value =
3366 golden_dpm_table->sclk_table.dpm_levels[i].value;
3367 }
3368 }
3369 }
3370
3371 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3372 dpm_table->mclk_table.dpm_levels
3373 [dpm_table->mclk_table.count - 1].value = mclk;
3374
3375 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3376 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3377
3378 PP_ASSERT_WITH_CODE(
3379 (golden_dpm_table->mclk_table.dpm_levels
3380 [golden_dpm_table->mclk_table.count-1].value != 0),
3381 "Divide by 0!",
3382 return -EINVAL);
3383 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3384 for (i = dpm_count; i > 1; i--) {
3385 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3386 clock_percent = ((mclk -
3387 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3388 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3389
3390 dpm_table->mclk_table.dpm_levels[i].value =
3391 golden_dpm_table->mclk_table.dpm_levels[i].value +
3392 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3393 clock_percent) / 100;
3394
3395 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
3396 clock_percent = (
3397 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
3398 * 100)
3399 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3400
3401 dpm_table->mclk_table.dpm_levels[i].value =
3402 golden_dpm_table->mclk_table.dpm_levels[i].value -
3403 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3404 clock_percent) / 100;
3405 } else
3406 dpm_table->mclk_table.dpm_levels[i].value =
3407 golden_dpm_table->mclk_table.dpm_levels[i].value;
3408 }
3409 }
3410 }
3411
3412 if (data->need_update_smu7_dpm_table &
3413 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3414 result = smum_populate_all_graphic_levels(hwmgr);
3415 PP_ASSERT_WITH_CODE((0 == result),
3416 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3417 return result);
3418 }
3419
3420 if (data->need_update_smu7_dpm_table &
3421 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3422 /*populate MCLK dpm table to SMU7 */
3423 result = smum_populate_all_memory_levels(hwmgr);
3424 PP_ASSERT_WITH_CODE((0 == result),
3425 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3426 return result);
3427 }
3428
3429 return result;
3430}
3431
3432static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3433 struct smu7_single_dpm_table *dpm_table,
3434 uint32_t low_limit, uint32_t high_limit)
3435{
3436 uint32_t i;
3437
3438 for (i = 0; i < dpm_table->count; i++) {
3439 if ((dpm_table->dpm_levels[i].value < low_limit)
3440 || (dpm_table->dpm_levels[i].value > high_limit))
3441 dpm_table->dpm_levels[i].enabled = false;
3442 else
3443 dpm_table->dpm_levels[i].enabled = true;
3444 }
3445
3446 return 0;
3447}
3448
3449static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3450 const struct smu7_power_state *smu7_ps)
3451{
3452 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3453 uint32_t high_limit_count;
3454
3455 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3456 "power state did not have any performance level",
3457 return -EINVAL);
3458
3459 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3460
3461 smu7_trim_single_dpm_states(hwmgr,
3462 &(data->dpm_table.sclk_table),
3463 smu7_ps->performance_levels[0].engine_clock,
3464 smu7_ps->performance_levels[high_limit_count].engine_clock);
3465
3466 smu7_trim_single_dpm_states(hwmgr,
3467 &(data->dpm_table.mclk_table),
3468 smu7_ps->performance_levels[0].memory_clock,
3469 smu7_ps->performance_levels[high_limit_count].memory_clock);
3470
3471 return 0;
3472}
3473
3474static int smu7_generate_dpm_level_enable_mask(
3475 struct pp_hwmgr *hwmgr, const void *input)
3476{
3477 int result;
3478 const struct phm_set_power_state_input *states =
3479 (const struct phm_set_power_state_input *)input;
3480 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3481 const struct smu7_power_state *smu7_ps =
3482 cast_const_phw_smu7_power_state(states->pnew_state);
3483
3484 result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3485 if (result)
3486 return result;
3487
3488 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3489 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3490 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3491 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3492 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3493 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3494
3495 return 0;
3496}
3497
3498static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3499{
3500 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3501
3502 if (0 == data->need_update_smu7_dpm_table)
3503 return 0;
3504
3505 if ((0 == data->sclk_dpm_key_disabled) &&
3506 (data->need_update_smu7_dpm_table &
3507 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3508
3509 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3510 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3511 );
3512 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3513 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3514 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3515 return -EINVAL);
3516 }
3517
3518 if ((0 == data->mclk_dpm_key_disabled) &&
3519 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3520
3521 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3522 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3523 );
3524 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3525 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3526 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3527 return -EINVAL);
3528 }
3529
3530 data->need_update_smu7_dpm_table = 0;
3531
3532 return 0;
3533}
3534
3535static int smu7_notify_link_speed_change_after_state_change(
3536 struct pp_hwmgr *hwmgr, const void *input)
3537{
3538 const struct phm_set_power_state_input *states =
3539 (const struct phm_set_power_state_input *)input;
3540 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3541 const struct smu7_power_state *smu7_ps =
3542 cast_const_phw_smu7_power_state(states->pnew_state);
3543 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3544 uint8_t request;
3545
3546 if (data->pspp_notify_required) {
3547 if (target_link_speed == PP_PCIEGen3)
3548 request = PCIE_PERF_REQ_GEN3;
3549 else if (target_link_speed == PP_PCIEGen2)
3550 request = PCIE_PERF_REQ_GEN2;
3551 else
3552 request = PCIE_PERF_REQ_GEN1;
3553
3554 if (request == PCIE_PERF_REQ_GEN1 &&
3555 smu7_get_current_pcie_speed(hwmgr) > 0)
3556 return 0;
3557
3558 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
3559 if (PP_PCIEGen2 == target_link_speed)
3560 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
3561 else
3562 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
3563 }
3564 }
3565
3566 return 0;
3567}
3568
3569static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3570{
3571 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3572
3573 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK)
3574 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3575 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
3576 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
3577}
3578
3579static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3580{
3581 int tmp_result, result = 0;
3582 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3583
3584 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3585 PP_ASSERT_WITH_CODE((0 == tmp_result),
3586 "Failed to find DPM states clocks in DPM table!",
3587 result = tmp_result);
3588
3589 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3590 PHM_PlatformCaps_PCIEPerformanceRequest)) {
3591 tmp_result =
3592 smu7_request_link_speed_change_before_state_change(hwmgr, input);
3593 PP_ASSERT_WITH_CODE((0 == tmp_result),
3594 "Failed to request link speed change before state change!",
3595 result = tmp_result);
3596 }
3597
3598 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
3599 PP_ASSERT_WITH_CODE((0 == tmp_result),
3600 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
3601
3602 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3603 PP_ASSERT_WITH_CODE((0 == tmp_result),
3604 "Failed to populate and upload SCLK MCLK DPM levels!",
3605 result = tmp_result);
3606
3607 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
3608 PP_ASSERT_WITH_CODE((0 == tmp_result),
3609 "Failed to generate DPM level enabled mask!",
3610 result = tmp_result);
3611
3612 tmp_result = smum_update_sclk_threshold(hwmgr);
3613 PP_ASSERT_WITH_CODE((0 == tmp_result),
3614 "Failed to update SCLK threshold!",
3615 result = tmp_result);
3616
3617 tmp_result = smu7_notify_smc_display(hwmgr);
3618 PP_ASSERT_WITH_CODE((0 == tmp_result),
3619 "Failed to notify smc display settings!",
3620 result = tmp_result);
3621
3622 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
3623 PP_ASSERT_WITH_CODE((0 == tmp_result),
3624 "Failed to unfreeze SCLK MCLK DPM!",
3625 result = tmp_result);
3626
3627 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
3628 PP_ASSERT_WITH_CODE((0 == tmp_result),
3629 "Failed to upload DPM level enabled mask!",
3630 result = tmp_result);
3631
3632 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3633 PHM_PlatformCaps_PCIEPerformanceRequest)) {
3634 tmp_result =
3635 smu7_notify_link_speed_change_after_state_change(hwmgr, input);
3636 PP_ASSERT_WITH_CODE((0 == tmp_result),
3637 "Failed to notify link speed change after state change!",
3638 result = tmp_result);
3639 }
3640 data->apply_optimized_settings = false;
3641 return result;
3642}
3643
3644static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
3645{
3646 hwmgr->thermal_controller.
3647 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
3648
3649 if (phm_is_hw_access_blocked(hwmgr))
3650 return 0;
3651
3652 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3653 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
3654}
3655
3656int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
3657{
3658 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
3659
3660 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
3661}
3662
3663int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
3664{
3665 uint32_t num_active_displays = 0;
3666 struct cgs_display_info info = {0};
3667
3668 info.mode_info = NULL;
3669 cgs_get_active_displays_info(hwmgr->device, &info);
3670
3671 num_active_displays = info.display_count;
3672
3673 if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)
3674 smu7_notify_smc_display_change(hwmgr, false);
3675
3676 return 0;
3677}
3678
3679/**
3680* Programs the display gap
3681*
3682* @param hwmgr the address of the powerplay hardware manager.
3683* @return always OK
3684*/
3685int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
3686{
3687 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3688 uint32_t num_active_displays = 0;
3689 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
3690 uint32_t display_gap2;
3691 uint32_t pre_vbi_time_in_us;
3692 uint32_t frame_time_in_us;
3693 uint32_t ref_clock;
3694 uint32_t refresh_rate = 0;
3695 struct cgs_display_info info = {0};
3696 struct cgs_mode_info mode_info;
3697
3698 info.mode_info = &mode_info;
3699
3700 cgs_get_active_displays_info(hwmgr->device, &info);
3701 num_active_displays = info.display_count;
3702
3703 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
3704 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
3705
3706 ref_clock = mode_info.ref_clock;
3707 refresh_rate = mode_info.refresh_rate;
3708
3709 if (0 == refresh_rate)
3710 refresh_rate = 60;
3711
3712 frame_time_in_us = 1000000 / refresh_rate;
3713
3714 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
3715 data->frame_time_x2 = frame_time_in_us * 2 / 100;
3716
3717 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
3718
3719 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
3720
3721 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3722 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
3723 SMU_SoftRegisters,
3724 PreVBlankGap), 0x64);
3725
3726 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3727 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
3728 SMU_SoftRegisters,
3729 VBlankTimeout),
3730 (frame_time_in_us - pre_vbi_time_in_us));
3731
3732 return 0;
3733}
3734
3735int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3736{
3737 return smu7_program_display_gap(hwmgr);
3738}
3739
3740/**
3741* Set maximum target operating fan output RPM
3742*
3743* @param hwmgr: the address of the powerplay hardware manager.
3744* @param usMaxFanRpm: max operating fan RPM value.
3745* @return The response that came from the SMC.
3746*/
3747static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
3748{
3749 hwmgr->thermal_controller.
3750 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
3751
3752 if (phm_is_hw_access_blocked(hwmgr))
3753 return 0;
3754
3755 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3756 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
3757}
3758
3759int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
3760 const void *thermal_interrupt_info)
3761{
3762 return 0;
3763}
3764
3765bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3766{
3767 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3768 bool is_update_required = false;
3769 struct cgs_display_info info = {0, 0, NULL};
3770
3771 cgs_get_active_displays_info(hwmgr->device, &info);
3772
3773 if (data->display_timing.num_existing_displays != info.display_count)
3774 is_update_required = true;
3775
3776 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
3777 if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr &&
3778 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
3779 hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3780 is_update_required = true;
3781 }
3782 return is_update_required;
3783}
3784
3785static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
3786 const struct smu7_performance_level *pl2)
3787{
3788 return ((pl1->memory_clock == pl2->memory_clock) &&
3789 (pl1->engine_clock == pl2->engine_clock) &&
3790 (pl1->pcie_gen == pl2->pcie_gen) &&
3791 (pl1->pcie_lane == pl2->pcie_lane));
3792}
3793
3794int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
3795{
3796 const struct smu7_power_state *psa = cast_const_phw_smu7_power_state(pstate1);
3797 const struct smu7_power_state *psb = cast_const_phw_smu7_power_state(pstate2);
3798 int i;
3799
3800 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
3801 return -EINVAL;
3802
3803 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
3804 if (psa->performance_level_count != psb->performance_level_count) {
3805 *equal = false;
3806 return 0;
3807 }
3808
3809 for (i = 0; i < psa->performance_level_count; i++) {
3810 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
3811 /* If we have found even one performance level pair that is different the states are different. */
3812 *equal = false;
3813 return 0;
3814 }
3815 }
3816
3817 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
3818 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
3819 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
3820 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
3821
3822 return 0;
3823}
3824
3825int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr)
3826{
3827 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3828
3829 uint32_t vbios_version;
3830 uint32_t tmp;
3831
3832 /* Read MC indirect register offset 0x9F bits [3:0] to see
3833 * if VBIOS has already loaded a full version of MC ucode
3834 * or not.
3835 */
3836
3837 smu7_get_mc_microcode_version(hwmgr);
3838 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
3839
3840 data->need_long_memory_training = false;
3841
3842 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
3843 ixMC_IO_DEBUG_UP_13);
3844 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3845
3846 if (tmp & (1 << 23)) {
3847 data->mem_latency_high = MEM_LATENCY_HIGH;
3848 data->mem_latency_low = MEM_LATENCY_LOW;
3849 } else {
3850 data->mem_latency_high = 330;
3851 data->mem_latency_low = 330;
3852 }
3853
3854 return 0;
3855}
3856
3857static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
3858{
3859 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3860
3861 data->clock_registers.vCG_SPLL_FUNC_CNTL =
3862 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
3863 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
3864 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
3865 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
3866 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
3867 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
3868 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
3869 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
3870 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
3871 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
3872 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
3873 data->clock_registers.vDLL_CNTL =
3874 cgs_read_register(hwmgr->device, mmDLL_CNTL);
3875 data->clock_registers.vMCLK_PWRMGT_CNTL =
3876 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
3877 data->clock_registers.vMPLL_AD_FUNC_CNTL =
3878 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
3879 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
3880 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
3881 data->clock_registers.vMPLL_FUNC_CNTL =
3882 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
3883 data->clock_registers.vMPLL_FUNC_CNTL_1 =
3884 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
3885 data->clock_registers.vMPLL_FUNC_CNTL_2 =
3886 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
3887 data->clock_registers.vMPLL_SS1 =
3888 cgs_read_register(hwmgr->device, mmMPLL_SS1);
3889 data->clock_registers.vMPLL_SS2 =
3890 cgs_read_register(hwmgr->device, mmMPLL_SS2);
3891 return 0;
3892
3893}
3894
3895/**
3896 * Find out if memory is GDDR5.
3897 *
3898 * @param hwmgr the address of the powerplay hardware manager.
3899 * @return always 0
3900 */
3901static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
3902{
3903 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3904 uint32_t temp;
3905
3906 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
3907
3908 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
3909 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
3910 MC_SEQ_MISC0_GDDR5_SHIFT));
3911
3912 return 0;
3913}
3914
3915/**
3916 * Enables Dynamic Power Management by SMC
3917 *
3918 * @param hwmgr the address of the powerplay hardware manager.
3919 * @return always 0
3920 */
3921static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
3922{
3923 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3924 GENERAL_PWRMGT, STATIC_PM_EN, 1);
3925
3926 return 0;
3927}
3928
3929/**
3930 * Initialize PowerGating States for different engines
3931 *
3932 * @param hwmgr the address of the powerplay hardware manager.
3933 * @return always 0
3934 */
3935static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
3936{
3937 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3938
3939 data->uvd_power_gated = false;
3940 data->vce_power_gated = false;
3941 data->samu_power_gated = false;
3942
3943 return 0;
3944}
3945
3946static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3947{
3948 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3949
3950 data->low_sclk_interrupt_threshold = 0;
3951 return 0;
3952}
3953
3954int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
3955{
3956 int tmp_result, result = 0;
3957
3958 smu7_upload_mc_firmware(hwmgr);
3959
3960 tmp_result = smu7_read_clock_registers(hwmgr);
3961 PP_ASSERT_WITH_CODE((0 == tmp_result),
3962 "Failed to read clock registers!", result = tmp_result);
3963
3964 tmp_result = smu7_get_memory_type(hwmgr);
3965 PP_ASSERT_WITH_CODE((0 == tmp_result),
3966 "Failed to get memory type!", result = tmp_result);
3967
3968 tmp_result = smu7_enable_acpi_power_management(hwmgr);
3969 PP_ASSERT_WITH_CODE((0 == tmp_result),
3970 "Failed to enable ACPI power management!", result = tmp_result);
3971
3972 tmp_result = smu7_init_power_gate_state(hwmgr);
3973 PP_ASSERT_WITH_CODE((0 == tmp_result),
3974 "Failed to init power gate state!", result = tmp_result);
3975
3976 tmp_result = smu7_get_mc_microcode_version(hwmgr);
3977 PP_ASSERT_WITH_CODE((0 == tmp_result),
3978 "Failed to get MC microcode version!", result = tmp_result);
3979
3980 tmp_result = smu7_init_sclk_threshold(hwmgr);
3981 PP_ASSERT_WITH_CODE((0 == tmp_result),
3982 "Failed to init sclk threshold!", result = tmp_result);
3983
3984 return result;
3985}
3986
3987static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
3988 enum pp_clock_type type, uint32_t mask)
3989{
3990 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3991
3992 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
3993 return -EINVAL;
3994
3995 switch (type) {
3996 case PP_SCLK:
3997 if (!data->sclk_dpm_key_disabled)
3998 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3999 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4000 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4001 break;
4002 case PP_MCLK:
4003 if (!data->mclk_dpm_key_disabled)
4004 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4005 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4006 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4007 break;
4008 case PP_PCIE:
4009 {
4010 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4011 uint32_t level = 0;
4012
4013 while (tmp >>= 1)
4014 level++;
4015
4016 if (!data->pcie_dpm_key_disabled)
4017 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4018 PPSMC_MSG_PCIeDPM_ForceLevel,
4019 level);
4020 break;
4021 }
4022 default:
4023 break;
4024 }
4025
4026 return 0;
4027}
4028
4029static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4030 enum pp_clock_type type, char *buf)
4031{
4032 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4033 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4034 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4035 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4036 int i, now, size = 0;
4037 uint32_t clock, pcie_speed;
4038
4039 switch (type) {
4040 case PP_SCLK:
4041 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4042 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4043
4044 for (i = 0; i < sclk_table->count; i++) {
4045 if (clock > sclk_table->dpm_levels[i].value)
4046 continue;
4047 break;
4048 }
4049 now = i;
4050
4051 for (i = 0; i < sclk_table->count; i++)
4052 size += sprintf(buf + size, "%d: %uMhz %s\n",
4053 i, sclk_table->dpm_levels[i].value / 100,
4054 (i == now) ? "*" : "");
4055 break;
4056 case PP_MCLK:
4057 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4058 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4059
4060 for (i = 0; i < mclk_table->count; i++) {
4061 if (clock > mclk_table->dpm_levels[i].value)
4062 continue;
4063 break;
4064 }
4065 now = i;
4066
4067 for (i = 0; i < mclk_table->count; i++)
4068 size += sprintf(buf + size, "%d: %uMhz %s\n",
4069 i, mclk_table->dpm_levels[i].value / 100,
4070 (i == now) ? "*" : "");
4071 break;
4072 case PP_PCIE:
4073 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4074 for (i = 0; i < pcie_table->count; i++) {
4075 if (pcie_speed != pcie_table->dpm_levels[i].value)
4076 continue;
4077 break;
4078 }
4079 now = i;
4080
4081 for (i = 0; i < pcie_table->count; i++)
4082 size += sprintf(buf + size, "%d: %s %s\n", i,
4083 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4084 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4085 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4086 (i == now) ? "*" : "");
4087 break;
4088 default:
4089 break;
4090 }
4091 return size;
4092}
4093
4094static int smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4095{
4096 if (mode) {
4097 /* stop auto-manage */
4098 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4099 PHM_PlatformCaps_MicrocodeFanControl))
4100 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4101 smu7_fan_ctrl_set_static_mode(hwmgr, mode);
4102 } else
4103 /* restart auto-manage */
4104 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4105
4106 return 0;
4107}
4108
4109static int smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4110{
4111 if (hwmgr->fan_ctrl_is_in_default_mode)
4112 return hwmgr->fan_ctrl_default_mode;
4113 else
4114 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4115 CG_FDO_CTRL2, FDO_PWM_MODE);
4116}
4117
4118static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4119{
4120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4121 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4122 struct smu7_single_dpm_table *golden_sclk_table =
4123 &(data->golden_dpm_table.sclk_table);
4124 int value;
4125
4126 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4127 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4128 100 /
4129 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4130
4131 return value;
4132}
4133
4134static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4135{
4136 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4137 struct smu7_single_dpm_table *golden_sclk_table =
4138 &(data->golden_dpm_table.sclk_table);
4139 struct pp_power_state *ps;
4140 struct smu7_power_state *smu7_ps;
4141
4142 if (value > 20)
4143 value = 20;
4144
4145 ps = hwmgr->request_ps;
4146
4147 if (ps == NULL)
4148 return -EINVAL;
4149
4150 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4151
4152 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4153 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4154 value / 100 +
4155 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4156
4157 return 0;
4158}
4159
4160static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4161{
4162 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4163 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4164 struct smu7_single_dpm_table *golden_mclk_table =
4165 &(data->golden_dpm_table.mclk_table);
4166 int value;
4167
4168 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
4169 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
4170 100 /
4171 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4172
4173 return value;
4174}
4175
4176static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4177{
4178 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4179 struct smu7_single_dpm_table *golden_mclk_table =
4180 &(data->golden_dpm_table.mclk_table);
4181 struct pp_power_state *ps;
4182 struct smu7_power_state *smu7_ps;
4183
4184 if (value > 20)
4185 value = 20;
4186
4187 ps = hwmgr->request_ps;
4188
4189 if (ps == NULL)
4190 return -EINVAL;
4191
4192 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4193
4194 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4195 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4196 value / 100 +
4197 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4198
4199 return 0;
4200}
4201
4202
4203static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4204{
4205 struct phm_ppt_v1_information *table_info =
4206 (struct phm_ppt_v1_information *)hwmgr->pptable;
4207 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
4208 int i;
4209
4210 if (table_info == NULL)
4211 return -EINVAL;
4212
4213 dep_sclk_table = table_info->vdd_dep_on_sclk;
4214
4215 for (i = 0; i < dep_sclk_table->count; i++) {
4216 clocks->clock[i] = dep_sclk_table->entries[i].clk;
4217 clocks->count++;
4218 }
4219 return 0;
4220}
4221
4222static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4223{
4224 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4225
4226 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4227 return data->mem_latency_high;
4228 else if (clk >= MEM_FREQ_HIGH_LATENCY)
4229 return data->mem_latency_low;
4230 else
4231 return MEM_LATENCY_ERR;
4232}
4233
4234static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4235{
4236 struct phm_ppt_v1_information *table_info =
4237 (struct phm_ppt_v1_information *)hwmgr->pptable;
4238 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4239 int i;
4240
4241 if (table_info == NULL)
4242 return -EINVAL;
4243
4244 dep_mclk_table = table_info->vdd_dep_on_mclk;
4245
4246 for (i = 0; i < dep_mclk_table->count; i++) {
4247 clocks->clock[i] = dep_mclk_table->entries[i].clk;
4248 clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4249 dep_mclk_table->entries[i].clk);
4250 clocks->count++;
4251 }
4252 return 0;
4253}
4254
4255static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4256 struct amd_pp_clocks *clocks)
4257{
4258 switch (type) {
4259 case amd_pp_sys_clock:
4260 smu7_get_sclks(hwmgr, clocks);
4261 break;
4262 case amd_pp_mem_clock:
4263 smu7_get_mclks(hwmgr, clocks);
4264 break;
4265 default:
4266 return -EINVAL;
4267 }
4268
4269 return 0;
4270}
4271
4272static struct pp_hwmgr_func smu7_hwmgr_funcs = {
4273 .backend_init = &smu7_hwmgr_backend_init,
4274 .backend_fini = &phm_hwmgr_backend_fini,
4275 .asic_setup = &smu7_setup_asic_task,
4276 .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
4277 .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
4278 .force_dpm_level = &smu7_force_dpm_level,
4279 .power_state_set = smu7_set_power_state_tasks,
4280 .get_power_state_size = smu7_get_power_state_size,
4281 .get_mclk = smu7_dpm_get_mclk,
4282 .get_sclk = smu7_dpm_get_sclk,
4283 .patch_boot_state = smu7_dpm_patch_boot_state,
4284 .get_pp_table_entry = smu7_get_pp_table_entry,
4285 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
4286 .print_current_perforce_level = smu7_print_current_perforce_level,
4287 .powerdown_uvd = smu7_powerdown_uvd,
4288 .powergate_uvd = smu7_powergate_uvd,
4289 .powergate_vce = smu7_powergate_vce,
4290 .disable_clock_power_gating = smu7_disable_clock_power_gating,
4291 .update_clock_gatings = smu7_update_clock_gatings,
4292 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
4293 .display_config_changed = smu7_display_configuration_changed_task,
4294 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
4295 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
4296 .get_temperature = smu7_thermal_get_temperature,
4297 .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
4298 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
4299 .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
4300 .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
4301 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
4302 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
4303 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
4304 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
4305 .register_internal_thermal_interrupt = smu7_register_internal_thermal_interrupt,
4306 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
4307 .check_states_equal = smu7_check_states_equal,
4308 .set_fan_control_mode = smu7_set_fan_control_mode,
4309 .get_fan_control_mode = smu7_get_fan_control_mode,
4310 .force_clock_level = smu7_force_clock_level,
4311 .print_clock_levels = smu7_print_clock_levels,
4312 .enable_per_cu_power_gating = smu7_enable_per_cu_power_gating,
4313 .get_sclk_od = smu7_get_sclk_od,
4314 .set_sclk_od = smu7_set_sclk_od,
4315 .get_mclk_od = smu7_get_mclk_od,
4316 .set_mclk_od = smu7_set_mclk_od,
4317 .get_clock_by_type = smu7_get_clock_by_type,
4318};
4319
4320uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
4321 uint32_t clock_insr)
4322{
4323 uint8_t i;
4324 uint32_t temp;
4325 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
4326
4327 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
4328 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
4329 temp = clock >> i;
4330
4331 if (temp >= min || i == 0)
4332 break;
4333 }
4334 return i;
4335}
4336
4337int smu7_hwmgr_init(struct pp_hwmgr *hwmgr)
4338{
4339 int ret = 0;
4340
4341 hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
4342 if (hwmgr->pp_table_version == PP_TABLE_V0)
4343 hwmgr->pptable_func = &pptable_funcs;
4344 else if (hwmgr->pp_table_version == PP_TABLE_V1)
4345 hwmgr->pptable_func = &pptable_v1_0_funcs;
4346
4347 pp_smu7_thermal_initialize(hwmgr);
4348 return ret;
4349}
4350
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
new file mode 100644
index 000000000000..27e7f76ad8a6
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -0,0 +1,353 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _SMU7_HWMGR_H
25#define _SMU7_HWMGR_H
26
27#include "hwmgr.h"
28#include "ppatomctrl.h"
29
30#define SMU7_MAX_HARDWARE_POWERLEVELS 2
31
32#define SMU7_VOLTAGE_CONTROL_NONE 0x0
33#define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1
34#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
35#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
36
37#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
38#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
39#define DPMTABLE_UPDATE_SCLK 0x00000004
40#define DPMTABLE_UPDATE_MCLK 0x00000008
41
42enum gpu_pt_config_reg_type {
43 GPU_CONFIGREG_MMR = 0,
44 GPU_CONFIGREG_SMC_IND,
45 GPU_CONFIGREG_DIDT_IND,
46 GPU_CONFIGREG_GC_CAC_IND,
47 GPU_CONFIGREG_CACHE,
48 GPU_CONFIGREG_MAX
49};
50
51struct gpu_pt_config_reg {
52 uint32_t offset;
53 uint32_t mask;
54 uint32_t shift;
55 uint32_t value;
56 enum gpu_pt_config_reg_type type;
57};
58
59struct smu7_performance_level {
60 uint32_t memory_clock;
61 uint32_t engine_clock;
62 uint16_t pcie_gen;
63 uint16_t pcie_lane;
64};
65
66struct smu7_thermal_temperature_setting {
67 long temperature_low;
68 long temperature_high;
69 long temperature_shutdown;
70};
71
72struct smu7_uvd_clocks {
73 uint32_t vclk;
74 uint32_t dclk;
75};
76
77struct smu7_vce_clocks {
78 uint32_t evclk;
79 uint32_t ecclk;
80};
81
82struct smu7_power_state {
83 uint32_t magic;
84 struct smu7_uvd_clocks uvd_clks;
85 struct smu7_vce_clocks vce_clks;
86 uint32_t sam_clk;
87 uint16_t performance_level_count;
88 bool dc_compatible;
89 uint32_t sclk_threshold;
90 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
91};
92
93struct smu7_dpm_level {
94 bool enabled;
95 uint32_t value;
96 uint32_t param1;
97};
98
99#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
100#define MAX_REGULAR_DPM_NUMBER 8
101#define SMU7_MINIMUM_ENGINE_CLOCK 2500
102
103struct smu7_single_dpm_table {
104 uint32_t count;
105 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
106};
107
108struct smu7_dpm_table {
109 struct smu7_single_dpm_table sclk_table;
110 struct smu7_single_dpm_table mclk_table;
111 struct smu7_single_dpm_table pcie_speed_table;
112 struct smu7_single_dpm_table vddc_table;
113 struct smu7_single_dpm_table vddci_table;
114 struct smu7_single_dpm_table mvdd_table;
115};
116
117struct smu7_clock_registers {
118 uint32_t vCG_SPLL_FUNC_CNTL;
119 uint32_t vCG_SPLL_FUNC_CNTL_2;
120 uint32_t vCG_SPLL_FUNC_CNTL_3;
121 uint32_t vCG_SPLL_FUNC_CNTL_4;
122 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
123 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
124 uint32_t vDLL_CNTL;
125 uint32_t vMCLK_PWRMGT_CNTL;
126 uint32_t vMPLL_AD_FUNC_CNTL;
127 uint32_t vMPLL_DQ_FUNC_CNTL;
128 uint32_t vMPLL_FUNC_CNTL;
129 uint32_t vMPLL_FUNC_CNTL_1;
130 uint32_t vMPLL_FUNC_CNTL_2;
131 uint32_t vMPLL_SS1;
132 uint32_t vMPLL_SS2;
133};
134
135#define DISABLE_MC_LOADMICROCODE 1
136#define DISABLE_MC_CFGPROGRAMMING 2
137
138struct smu7_voltage_smio_registers {
139 uint32_t vS0_VID_LOWER_SMIO_CNTL;
140};
141
142#define SMU7_MAX_LEAKAGE_COUNT 8
143
144struct smu7_leakage_voltage {
145 uint16_t count;
146 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT];
147 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT];
148};
149
150struct smu7_vbios_boot_state {
151 uint16_t mvdd_bootup_value;
152 uint16_t vddc_bootup_value;
153 uint16_t vddci_bootup_value;
154 uint16_t vddgfx_bootup_value;
155 uint32_t sclk_bootup_value;
156 uint32_t mclk_bootup_value;
157 uint16_t pcie_gen_bootup_value;
158 uint16_t pcie_lane_bootup_value;
159};
160
161struct smu7_display_timing {
162 uint32_t min_clock_in_sr;
163 uint32_t num_existing_displays;
164};
165
166struct smu7_dpmlevel_enable_mask {
167 uint32_t uvd_dpm_enable_mask;
168 uint32_t vce_dpm_enable_mask;
169 uint32_t acp_dpm_enable_mask;
170 uint32_t samu_dpm_enable_mask;
171 uint32_t sclk_dpm_enable_mask;
172 uint32_t mclk_dpm_enable_mask;
173 uint32_t pcie_dpm_enable_mask;
174};
175
176struct smu7_pcie_perf_range {
177 uint16_t max;
178 uint16_t min;
179};
180
181struct smu7_hwmgr {
182 struct smu7_dpm_table dpm_table;
183 struct smu7_dpm_table golden_dpm_table;
184
185 uint32_t voting_rights_clients0;
186 uint32_t voting_rights_clients1;
187 uint32_t voting_rights_clients2;
188 uint32_t voting_rights_clients3;
189 uint32_t voting_rights_clients4;
190 uint32_t voting_rights_clients5;
191 uint32_t voting_rights_clients6;
192 uint32_t voting_rights_clients7;
193 uint32_t static_screen_threshold_unit;
194 uint32_t static_screen_threshold;
195 uint32_t voltage_control;
196 uint32_t vdd_gfx_control;
197 uint32_t vddc_vddgfx_delta;
198 uint32_t active_auto_throttle_sources;
199
200 struct smu7_clock_registers clock_registers;
201
202 bool is_memory_gddr5;
203 uint16_t acpi_vddc;
204 bool pspp_notify_required;
205 uint16_t force_pcie_gen;
206 uint16_t acpi_pcie_gen;
207 uint32_t pcie_gen_cap;
208 uint32_t pcie_lane_cap;
209 uint32_t pcie_spc_cap;
210 struct smu7_leakage_voltage vddc_leakage;
211 struct smu7_leakage_voltage vddci_leakage;
212 struct smu7_leakage_voltage vddcgfx_leakage;
213
214 uint32_t mvdd_control;
215 uint32_t vddc_mask_low;
216 uint32_t mvdd_mask_low;
217 uint16_t max_vddc_in_pptable;
218 uint16_t min_vddc_in_pptable;
219 uint16_t max_vddci_in_pptable;
220 uint16_t min_vddci_in_pptable;
221 bool is_uvd_enabled;
222 struct smu7_vbios_boot_state vbios_boot_state;
223
224 bool pcie_performance_request;
225 bool battery_state;
226 bool is_tlu_enabled;
227 bool disable_handshake;
228 bool smc_voltage_control_enabled;
229 bool vbi_time_out_support;
230
231 uint32_t soft_regs_start;
232 /* ---- Stuff originally coming from Evergreen ---- */
233 uint32_t vddci_control;
234 struct pp_atomctrl_voltage_table vddc_voltage_table;
235 struct pp_atomctrl_voltage_table vddci_voltage_table;
236 struct pp_atomctrl_voltage_table mvdd_voltage_table;
237 struct pp_atomctrl_voltage_table vddgfx_voltage_table;
238
239 uint32_t mgcg_cgtt_local2;
240 uint32_t mgcg_cgtt_local3;
241 uint32_t gpio_debug;
242 uint32_t mc_micro_code_feature;
243 uint32_t highest_mclk;
244 uint16_t acpi_vddci;
245 uint8_t mvdd_high_index;
246 uint8_t mvdd_low_index;
247 bool dll_default_on;
248 bool performance_request_registered;
249
250 /* ---- Low Power Features ---- */
251 bool ulv_supported;
252
253 /* ---- CAC Stuff ---- */
254 uint32_t cac_table_start;
255 bool cac_configuration_required;
256 bool driver_calculate_cac_leakage;
257 bool cac_enabled;
258
259 /* ---- DPM2 Parameters ---- */
260 uint32_t power_containment_features;
261 bool enable_dte_feature;
262 bool enable_tdc_limit_feature;
263 bool enable_pkg_pwr_tracking_feature;
264 bool disable_uvd_power_tune_feature;
265
266
267 uint32_t dte_tj_offset;
268 uint32_t fast_watermark_threshold;
269
270 /* ---- Phase Shedding ---- */
271 bool vddc_phase_shed_control;
272
273 /* ---- DI/DT ---- */
274 struct smu7_display_timing display_timing;
275
276 /* ---- Thermal Temperature Setting ---- */
277 struct smu7_thermal_temperature_setting thermal_temp_setting;
278 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask;
279 uint32_t need_update_smu7_dpm_table;
280 uint32_t sclk_dpm_key_disabled;
281 uint32_t mclk_dpm_key_disabled;
282 uint32_t pcie_dpm_key_disabled;
283 uint32_t min_engine_clocks;
284 struct smu7_pcie_perf_range pcie_gen_performance;
285 struct smu7_pcie_perf_range pcie_lane_performance;
286 struct smu7_pcie_perf_range pcie_gen_power_saving;
287 struct smu7_pcie_perf_range pcie_lane_power_saving;
288 bool use_pcie_performance_levels;
289 bool use_pcie_power_saving_levels;
290 uint32_t mclk_activity_target;
291 uint32_t mclk_dpm0_activity_target;
292 uint32_t low_sclk_interrupt_threshold;
293 uint32_t last_mclk_dpm_enable_mask;
294 bool uvd_enabled;
295
296 /* ---- Power Gating States ---- */
297 bool uvd_power_gated;
298 bool vce_power_gated;
299 bool samu_power_gated;
300 bool need_long_memory_training;
301
302 /* Application power optimization parameters */
303 bool update_up_hyst;
304 bool update_down_hyst;
305 uint32_t down_hyst;
306 uint32_t up_hyst;
307 uint32_t disable_dpm_mask;
308 bool apply_optimized_settings;
309
310 uint32_t avfs_vdroop_override_setting;
311 bool apply_avfs_cks_off_voltage;
312 uint32_t frame_time_x2;
313 uint16_t mem_latency_high;
314 uint16_t mem_latency_low;
315};
316
317/* To convert to Q8.8 format for firmware */
318#define SMU7_Q88_FORMAT_CONVERSION_UNIT 256
319
320enum SMU7_I2CLineID {
321 SMU7_I2CLineID_DDC1 = 0x90,
322 SMU7_I2CLineID_DDC2 = 0x91,
323 SMU7_I2CLineID_DDC3 = 0x92,
324 SMU7_I2CLineID_DDC4 = 0x93,
325 SMU7_I2CLineID_DDC5 = 0x94,
326 SMU7_I2CLineID_DDC6 = 0x95,
327 SMU7_I2CLineID_SCLSDA = 0x96,
328 SMU7_I2CLineID_DDCVGA = 0x97
329};
330
331#define SMU7_I2C_DDC1DATA 0
332#define SMU7_I2C_DDC1CLK 1
333#define SMU7_I2C_DDC2DATA 2
334#define SMU7_I2C_DDC2CLK 3
335#define SMU7_I2C_DDC3DATA 4
336#define SMU7_I2C_DDC3CLK 5
337#define SMU7_I2C_SDA 40
338#define SMU7_I2C_SCL 41
339#define SMU7_I2C_DDC4DATA 65
340#define SMU7_I2C_DDC4CLK 66
341#define SMU7_I2C_DDC5DATA 0x48
342#define SMU7_I2C_DDC5CLK 0x49
343#define SMU7_I2C_DDC6DATA 0x4a
344#define SMU7_I2C_DDC6CLK 0x4b
345#define SMU7_I2C_DDCVGADATA 0x4c
346#define SMU7_I2C_DDCVGACLK 0x4d
347
348#define SMU7_UNUSED_GPIO_PIN 0x7F
349uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
350uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
351 uint32_t clock_insr);
352#endif
353
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
new file mode 100644
index 000000000000..260fce050175
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -0,0 +1,729 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "hwmgr.h"
24#include "smumgr.h"
25#include "smu7_hwmgr.h"
26#include "smu7_powertune.h"
27#include "pp_debug.h"
28#include "smu7_common.h"
29
30#define VOLTAGE_SCALE 4
31
32static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
33
34static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
35/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
36 * Offset Mask Shift Value Type
37 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
38 */
39 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060013, GPU_CONFIGREG_GC_CAC_IND },
40 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860013, GPU_CONFIGREG_GC_CAC_IND },
41 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060013, GPU_CONFIGREG_GC_CAC_IND },
42 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860013, GPU_CONFIGREG_GC_CAC_IND },
43 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060013, GPU_CONFIGREG_GC_CAC_IND },
44 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860013, GPU_CONFIGREG_GC_CAC_IND },
45 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060013, GPU_CONFIGREG_GC_CAC_IND },
46 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860013, GPU_CONFIGREG_GC_CAC_IND },
47 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060013, GPU_CONFIGREG_GC_CAC_IND },
48
49 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0013, GPU_CONFIGREG_GC_CAC_IND },
50 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0013, GPU_CONFIGREG_GC_CAC_IND },
51 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0013, GPU_CONFIGREG_GC_CAC_IND },
52 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0013, GPU_CONFIGREG_GC_CAC_IND },
53 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0013, GPU_CONFIGREG_GC_CAC_IND },
54
55 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100013, GPU_CONFIGREG_GC_CAC_IND },
56 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900013, GPU_CONFIGREG_GC_CAC_IND },
57 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100013, GPU_CONFIGREG_GC_CAC_IND },
58 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900013, GPU_CONFIGREG_GC_CAC_IND },
59 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100013, GPU_CONFIGREG_GC_CAC_IND },
60 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900013, GPU_CONFIGREG_GC_CAC_IND },
61
62 { 0xFFFFFFFF }
63};
64
65static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
66/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
67 * Offset Mask Shift Value Type
68 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
69 */
70 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060011, GPU_CONFIGREG_GC_CAC_IND },
71 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860011, GPU_CONFIGREG_GC_CAC_IND },
72 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060011, GPU_CONFIGREG_GC_CAC_IND },
73 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860011, GPU_CONFIGREG_GC_CAC_IND },
74 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060011, GPU_CONFIGREG_GC_CAC_IND },
75 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860011, GPU_CONFIGREG_GC_CAC_IND },
76 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060011, GPU_CONFIGREG_GC_CAC_IND },
77 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860011, GPU_CONFIGREG_GC_CAC_IND },
78 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060011, GPU_CONFIGREG_GC_CAC_IND },
79
80 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0011, GPU_CONFIGREG_GC_CAC_IND },
81 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0011, GPU_CONFIGREG_GC_CAC_IND },
82 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0011, GPU_CONFIGREG_GC_CAC_IND },
83 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0011, GPU_CONFIGREG_GC_CAC_IND },
84 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0011, GPU_CONFIGREG_GC_CAC_IND },
85
86 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00100011, GPU_CONFIGREG_GC_CAC_IND },
87 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x00900011, GPU_CONFIGREG_GC_CAC_IND },
88 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01100011, GPU_CONFIGREG_GC_CAC_IND },
89 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x01900011, GPU_CONFIGREG_GC_CAC_IND },
90 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02100011, GPU_CONFIGREG_GC_CAC_IND },
91 { ixGC_CAC_CNTL, 0xFFFFFFFF, 0, 0x02900011, GPU_CONFIGREG_GC_CAC_IND },
92
93 { 0xFFFFFFFF }
94};
95
96static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
97/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
98 * Offset Mask Shift Value Type
99 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
100 */
101 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND },
102 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND },
103 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND },
104 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND },
105
106 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND },
107 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND },
108 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND },
109 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND },
110
111 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND },
112 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
113 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
114 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
115
116 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
117 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
118
119 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
120 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
121
122 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND },
123 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
124 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND },
125 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
126 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
127 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
128
129 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
130 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
131 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
132 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND },
133 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
134
135 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
136 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND },
137 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND },
138 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
139
140 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
141 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
142 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
143 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
144 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
145 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
146 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
147 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
148
149 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND },
150 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
151 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND },
152 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND },
153
154 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND },
155 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND },
156 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
157 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
158
159 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
160 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
161
162 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
163 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
164
165 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
166 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
167 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
168 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
169 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
170 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
171
172 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
173 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
174 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
175 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
176 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
177
178 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
179 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
180 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
181 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
182
183 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
184 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
185 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
186 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
187 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
188 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND },
189 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0009, GPU_CONFIGREG_DIDT_IND },
190 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
191
192 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND },
193 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND },
194 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
195 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
196
197 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND },
198 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
199 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
200 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
201
202 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
203 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
204
205 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
206 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
207
208 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
209 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
210 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND },
211 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
212 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
213 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
214
215 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
216 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
217 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
218 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
219 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
220
221 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
222 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
223 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
224 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
225
226 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
227 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
228 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
229 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
230 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
231 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
232 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
233 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
234
235 { 0xFFFFFFFF }
236};
237
238static struct gpu_pt_config_reg DIDTConfig_Polaris11[] = {
239/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
240 * Offset Mask Shift Value Type
241 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
242 */
243 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x0073, GPU_CONFIGREG_DIDT_IND },
244 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00ab, GPU_CONFIGREG_DIDT_IND },
245 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND },
246 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND },
247
248 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x0067, GPU_CONFIGREG_DIDT_IND },
249 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x0084, GPU_CONFIGREG_DIDT_IND },
250 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x0027, GPU_CONFIGREG_DIDT_IND },
251 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND },
252
253 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x00aa, GPU_CONFIGREG_DIDT_IND },
254 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
255 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
256 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
257
258 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
259 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
260
261 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
262 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
263
264 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND },
265 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
266 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND },
267 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
268 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
269 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
270
271 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
272 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
273 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
274 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND },
275 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
276
277 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
278 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND },
279 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND },
280 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
281
282 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
283 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
284 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
285 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
286 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
287 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
288 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
289 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
290
291 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND },
292 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
293 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND },
294 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND },
295
296 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND },
297 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND },
298 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
299 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
300
301 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
302 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
303
304 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
305 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
306
307 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
308 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
309 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
310 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
311 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
312 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
313
314 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
315 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
316 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
317 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
318 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
319
320 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
321 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
322 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
323 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
324
325 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
326 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
327 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
328 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
329 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
330 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
331 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
332 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
333
334 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND },
335 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND },
336 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
337 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
338
339 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND },
340 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
341 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
342 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
343
344 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
345 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
346
347 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
348 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
349
350 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
351 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
352 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND },
353 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
354 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
355 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
356
357 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
358 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
359 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
360 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
361 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
362
363 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
364 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
365 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
366 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
367
368 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
369 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
370 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
371 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
372 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
373 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
374 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
375 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
376 { 0xFFFFFFFF }
377};
378
379
380static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
381{
382
383 uint32_t en = enable ? 1 : 0;
384 int32_t result = 0;
385 uint32_t data;
386
387 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
388 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
389 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
390 data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
391 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
392 DIDTBlock_Info &= ~SQ_Enable_MASK;
393 DIDTBlock_Info |= en << SQ_Enable_SHIFT;
394 }
395
396 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
397 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
398 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
399 data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
401 DIDTBlock_Info &= ~DB_Enable_MASK;
402 DIDTBlock_Info |= en << DB_Enable_SHIFT;
403 }
404
405 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
406 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
407 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
408 data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
409 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
410 DIDTBlock_Info &= ~TD_Enable_MASK;
411 DIDTBlock_Info |= en << TD_Enable_SHIFT;
412 }
413
414 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
415 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
416 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
417 data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
418 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
419 DIDTBlock_Info &= ~TCP_Enable_MASK;
420 DIDTBlock_Info |= en << TCP_Enable_SHIFT;
421 }
422
423 if (enable)
424 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, DIDTBlock_Info);
425
426 return result;
427}
428
429static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
430 struct gpu_pt_config_reg *cac_config_regs)
431{
432 struct gpu_pt_config_reg *config_regs = cac_config_regs;
433 uint32_t cache = 0;
434 uint32_t data = 0;
435
436 PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL);
437
438 while (config_regs->offset != 0xFFFFFFFF) {
439 if (config_regs->type == GPU_CONFIGREG_CACHE)
440 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
441 else {
442 switch (config_regs->type) {
443 case GPU_CONFIGREG_SMC_IND:
444 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
445 break;
446
447 case GPU_CONFIGREG_DIDT_IND:
448 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
449 break;
450
451 case GPU_CONFIGREG_GC_CAC_IND:
452 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
453 break;
454
455 default:
456 data = cgs_read_register(hwmgr->device, config_regs->offset);
457 break;
458 }
459
460 data &= ~config_regs->mask;
461 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
462 data |= cache;
463
464 switch (config_regs->type) {
465 case GPU_CONFIGREG_SMC_IND:
466 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data);
467 break;
468
469 case GPU_CONFIGREG_DIDT_IND:
470 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
471 break;
472
473 case GPU_CONFIGREG_GC_CAC_IND:
474 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
475 break;
476
477 default:
478 cgs_write_register(hwmgr->device, config_regs->offset, data);
479 break;
480 }
481 cache = 0;
482 }
483
484 config_regs++;
485 }
486
487 return 0;
488}
489
490int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
491{
492 int result;
493 uint32_t num_se = 0;
494 uint32_t count, value, value2;
495 struct cgs_system_info sys_info = {0};
496
497 sys_info.size = sizeof(struct cgs_system_info);
498 sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
499 result = cgs_query_system_info(hwmgr->device, &sys_info);
500
501
502 if (result == 0)
503 num_se = sys_info.value;
504
505 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
506 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
507 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
508 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
509
510 /* TO DO Pre DIDT disable clock gating */
511 value = 0;
512 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
513 for (count = 0; count < num_se; count++) {
514 value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
515 | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
516 | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
517 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
518
519 if (hwmgr->chip_id == CHIP_POLARIS10) {
520 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
521 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
522 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
523 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
524 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
525 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
526 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
527 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
528 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
529 }
530 }
531 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
532
533 result = smu7_enable_didt(hwmgr, true);
534 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
535
536 /* TO DO Post DIDT enable clock gating */
537 }
538
539 return 0;
540}
541
542int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
543{
544 int result;
545
546 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
547 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
548 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
549 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
550 /* TO DO Pre DIDT disable clock gating */
551
552 result = smu7_enable_didt(hwmgr, false);
553 PP_ASSERT_WITH_CODE((result == 0), "Post DIDT enable clock gating failed.", return result);
554 /* TO DO Post DIDT enable clock gating */
555 }
556
557 return 0;
558}
559
560int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
561{
562 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
563 int result = 0;
564
565 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
566 PHM_PlatformCaps_CAC)) {
567 int smc_result;
568 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
569 (uint16_t)(PPSMC_MSG_EnableCac));
570 PP_ASSERT_WITH_CODE((0 == smc_result),
571 "Failed to enable CAC in SMC.", result = -1);
572
573 data->cac_enabled = (0 == smc_result) ? true : false;
574 }
575 return result;
576}
577
578int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
579{
580 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
581 int result = 0;
582
583 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
584 PHM_PlatformCaps_CAC) && data->cac_enabled) {
585 int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
586 (uint16_t)(PPSMC_MSG_DisableCac));
587 PP_ASSERT_WITH_CODE((smc_result == 0),
588 "Failed to disable CAC in SMC.", result = -1);
589
590 data->cac_enabled = false;
591 }
592 return result;
593}
594
595int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
596{
597 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
598
599 if (data->power_containment_features &
600 POWERCONTAINMENT_FEATURE_PkgPwrLimit)
601 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
602 PPSMC_MSG_PkgPwrSetLimit, n);
603 return 0;
604}
605
606static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
607{
608 return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
609 PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
610}
611
612int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
613{
614 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
615 struct phm_ppt_v1_information *table_info =
616 (struct phm_ppt_v1_information *)(hwmgr->pptable);
617 int smc_result;
618 int result = 0;
619 struct phm_cac_tdp_table *cac_table;
620
621 data->power_containment_features = 0;
622 if (hwmgr->pp_table_version == PP_TABLE_V1)
623 cac_table = table_info->cac_dtp_table;
624 else
625 cac_table = hwmgr->dyn_state.cac_dtp_table;
626
627 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
628 PHM_PlatformCaps_PowerContainment)) {
629
630 if (data->enable_tdc_limit_feature) {
631 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
632 (uint16_t)(PPSMC_MSG_TDCLimitEnable));
633 PP_ASSERT_WITH_CODE((0 == smc_result),
634 "Failed to enable TDCLimit in SMC.", result = -1;);
635 if (0 == smc_result)
636 data->power_containment_features |=
637 POWERCONTAINMENT_FEATURE_TDCLimit;
638 }
639
640 if (data->enable_pkg_pwr_tracking_feature) {
641 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
642 (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
643 PP_ASSERT_WITH_CODE((0 == smc_result),
644 "Failed to enable PkgPwrTracking in SMC.", result = -1;);
645 if (0 == smc_result) {
646 uint32_t default_limit =
647 (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
648
649 data->power_containment_features |=
650 POWERCONTAINMENT_FEATURE_PkgPwrLimit;
651
652 if (smu7_set_power_limit(hwmgr, default_limit))
653 printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
654 }
655 }
656 }
657 return result;
658}
659
660int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
661{
662 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
663 int result = 0;
664
665 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
666 PHM_PlatformCaps_PowerContainment) &&
667 data->power_containment_features) {
668 int smc_result;
669
670 if (data->power_containment_features &
671 POWERCONTAINMENT_FEATURE_TDCLimit) {
672 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
673 (uint16_t)(PPSMC_MSG_TDCLimitDisable));
674 PP_ASSERT_WITH_CODE((smc_result == 0),
675 "Failed to disable TDCLimit in SMC.",
676 result = smc_result);
677 }
678
679 if (data->power_containment_features &
680 POWERCONTAINMENT_FEATURE_DTE) {
681 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
682 (uint16_t)(PPSMC_MSG_DisableDTE));
683 PP_ASSERT_WITH_CODE((smc_result == 0),
684 "Failed to disable DTE in SMC.",
685 result = smc_result);
686 }
687
688 if (data->power_containment_features &
689 POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
690 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
691 (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
692 PP_ASSERT_WITH_CODE((smc_result == 0),
693 "Failed to disable PkgPwrTracking in SMC.",
694 result = smc_result);
695 }
696 data->power_containment_features = 0;
697 }
698
699 return result;
700}
701
702int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
703{
704 struct phm_ppt_v1_information *table_info =
705 (struct phm_ppt_v1_information *)(hwmgr->pptable);
706 struct phm_cac_tdp_table *cac_table;
707
708 int adjust_percent, target_tdp;
709 int result = 0;
710
711 if (hwmgr->pp_table_version == PP_TABLE_V1)
712 cac_table = table_info->cac_dtp_table;
713 else
714 cac_table = hwmgr->dyn_state.cac_dtp_table;
715 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
716 PHM_PlatformCaps_PowerContainment)) {
717 /* adjustment percentage has already been validated */
718 adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
719 hwmgr->platform_descriptor.TDPAdjustment :
720 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
721 /* SMC requested that target_tdp to be 7 bit fraction in DPM table
722 * but message to be 8 bit fraction for messages
723 */
724 target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
725 result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
726 }
727
728 return result;
729}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h
new file mode 100644
index 000000000000..22f86b6bf1be
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _SMU7_POWERTUNE_H
24#define _SMU7_POWERTUNE_H
25
26#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000
27#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12
28#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000
29#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12
30#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000
31#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
32#define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
33#define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
34#define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
35#define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
36#define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
37#define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
38
39/* PowerContainment Features */
40#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
41#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
42#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
43
44#define ixGC_CAC_CNTL 0x0000
45#define ixDIDT_SQ_STALL_CTRL 0x0004
46#define ixDIDT_SQ_TUNING_CTRL 0x0005
47#define ixDIDT_TD_STALL_CTRL 0x0044
48#define ixDIDT_TD_TUNING_CTRL 0x0045
49#define ixDIDT_TCP_STALL_CTRL 0x0064
50#define ixDIDT_TCP_TUNING_CTRL 0x0065
51
52
53int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr);
54int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr);
55int smu7_enable_power_containment(struct pp_hwmgr *hwmgr);
56int smu7_disable_power_containment(struct pp_hwmgr *hwmgr);
57int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
58int smu7_power_control_set_level(struct pp_hwmgr *hwmgr);
59int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);
60int smu7_disable_didt_config(struct pp_hwmgr *hwmgr);
61#endif /* DGPU_POWERTUNE_H */
62
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
new file mode 100644
index 000000000000..fb6c6f6106d5
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -0,0 +1,577 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <asm/div64.h>
25#include "smu7_thermal.h"
26#include "smu7_hwmgr.h"
27#include "smu7_common.h"
28
29int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
30 struct phm_fan_speed_info *fan_speed_info)
31{
32 if (hwmgr->thermal_controller.fanInfo.bNoFan)
33 return 0;
34
35 fan_speed_info->supports_percent_read = true;
36 fan_speed_info->supports_percent_write = true;
37 fan_speed_info->min_percent = 0;
38 fan_speed_info->max_percent = 100;
39
40 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
41 PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
42 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
43 fan_speed_info->supports_rpm_read = true;
44 fan_speed_info->supports_rpm_write = true;
45 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
46 fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
47 } else {
48 fan_speed_info->min_rpm = 0;
49 fan_speed_info->max_rpm = 0;
50 }
51
52 return 0;
53}
54
55int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
56 uint32_t *speed)
57{
58 uint32_t duty100;
59 uint32_t duty;
60 uint64_t tmp64;
61
62 if (hwmgr->thermal_controller.fanInfo.bNoFan)
63 return 0;
64
65 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
66 CG_FDO_CTRL1, FMAX_DUTY100);
67 duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
68 CG_THERMAL_STATUS, FDO_PWM_DUTY);
69
70 if (duty100 == 0)
71 return -EINVAL;
72
73
74 tmp64 = (uint64_t)duty * 100;
75 do_div(tmp64, duty100);
76 *speed = (uint32_t)tmp64;
77
78 if (*speed > 100)
79 *speed = 100;
80
81 return 0;
82}
83
84int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
85{
86 uint32_t tach_period;
87 uint32_t crystal_clock_freq;
88
89 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
90 (hwmgr->thermal_controller.fanInfo.
91 ucTachometerPulsesPerRevolution == 0))
92 return 0;
93
94 tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
95 CG_TACH_STATUS, TACH_PERIOD);
96
97 if (tach_period == 0)
98 return -EINVAL;
99
100 crystal_clock_freq = smu7_get_xclk(hwmgr);
101
102 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
103
104 return 0;
105}
106
107/**
108* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
109* @param hwmgr the address of the powerplay hardware manager.
110* mode the fan control mode, 0 default, 1 by percent, 5, by RPM
111* @exception Should always succeed.
112*/
113int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
114{
115
116 if (hwmgr->fan_ctrl_is_in_default_mode) {
117 hwmgr->fan_ctrl_default_mode =
118 PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119 CG_FDO_CTRL2, FDO_PWM_MODE);
120 hwmgr->tmin =
121 PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
122 CG_FDO_CTRL2, TMIN);
123 hwmgr->fan_ctrl_is_in_default_mode = false;
124 }
125
126 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
127 CG_FDO_CTRL2, TMIN, 0);
128 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
129 CG_FDO_CTRL2, FDO_PWM_MODE, mode);
130
131 return 0;
132}
133
134/**
135* Reset Fan Speed Control to default mode.
136* @param hwmgr the address of the powerplay hardware manager.
137* @exception Should always succeed.
138*/
139int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
140{
141 if (!hwmgr->fan_ctrl_is_in_default_mode) {
142 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
143 CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
144 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
145 CG_FDO_CTRL2, TMIN, hwmgr->tmin);
146 hwmgr->fan_ctrl_is_in_default_mode = true;
147 }
148
149 return 0;
150}
151
152static int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
153{
154 int result;
155
156 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
157 PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
158 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
159 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
160
161 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_FanSpeedInTableIsRPM))
163 hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
164 hwmgr->thermal_controller.
165 advanceFanControlParameters.usMaxFanRPM);
166 else
167 hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
168 hwmgr->thermal_controller.
169 advanceFanControlParameters.usMaxFanPWM);
170
171 } else {
172 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
173 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
174 }
175
176 if (!result && hwmgr->thermal_controller.
177 advanceFanControlParameters.ucTargetTemperature)
178 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
179 PPSMC_MSG_SetFanTemperatureTarget,
180 hwmgr->thermal_controller.
181 advanceFanControlParameters.ucTargetTemperature);
182
183 return result;
184}
185
186
187int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
188{
189 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
190}
191
192/**
193* Set Fan Speed in percent.
194* @param hwmgr the address of the powerplay hardware manager.
195* @param speed is the percentage value (0% - 100%) to be set.
196* @exception Fails is the 100% setting appears to be 0.
197*/
198int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
199 uint32_t speed)
200{
201 uint32_t duty100;
202 uint32_t duty;
203 uint64_t tmp64;
204
205 if (hwmgr->thermal_controller.fanInfo.bNoFan)
206 return 0;
207
208 if (speed > 100)
209 speed = 100;
210
211 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
212 PHM_PlatformCaps_MicrocodeFanControl))
213 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
214
215 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
216 CG_FDO_CTRL1, FMAX_DUTY100);
217
218 if (duty100 == 0)
219 return -EINVAL;
220
221 tmp64 = (uint64_t)speed * duty100;
222 do_div(tmp64, 100);
223 duty = (uint32_t)tmp64;
224
225 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
226 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
227
228 return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
229}
230
231/**
232* Reset Fan Speed to default.
233* @param hwmgr the address of the powerplay hardware manager.
234* @exception Always succeeds.
235*/
236int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
237{
238 int result;
239
240 if (hwmgr->thermal_controller.fanInfo.bNoFan)
241 return 0;
242
243 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_MicrocodeFanControl)) {
245 result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
246 if (!result)
247 result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
248 } else
249 result = smu7_fan_ctrl_set_default_mode(hwmgr);
250
251 return result;
252}
253
254/**
255* Set Fan Speed in RPM.
256* @param hwmgr the address of the powerplay hardware manager.
257* @param speed is the percentage value (min - max) to be set.
258* @exception Fails is the speed not lie between min and max.
259*/
260int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
261{
262 uint32_t tach_period;
263 uint32_t crystal_clock_freq;
264
265 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
266 (hwmgr->thermal_controller.fanInfo.
267 ucTachometerPulsesPerRevolution == 0) ||
268 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
269 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
270 return 0;
271
272 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
273 PHM_PlatformCaps_MicrocodeFanControl))
274 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
275
276 crystal_clock_freq = smu7_get_xclk(hwmgr);
277
278 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
279
280 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
281 CG_TACH_STATUS, TACH_PERIOD, tach_period);
282
283 return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
284}
285
286/**
287* Reads the remote temperature from the SIslands thermal controller.
288*
289* @param hwmgr The address of the hardware manager.
290*/
291int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr)
292{
293 int temp;
294
295 temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
296 CG_MULT_THERMAL_STATUS, CTF_TEMP);
297
298 /* Bit 9 means the reading is lower than the lowest usable value. */
299 if (temp & 0x200)
300 temp = SMU7_THERMAL_MAXIMUM_TEMP_READING;
301 else
302 temp = temp & 0x1ff;
303
304 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
305
306 return temp;
307}
308
309/**
310* Set the requested temperature range for high and low alert signals
311*
312* @param hwmgr The address of the hardware manager.
313* @param range Temperature range to be programmed for high and low alert signals
314* @exception PP_Result_BadInput if the input data is not valid.
315*/
316static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
317 uint32_t low_temp, uint32_t high_temp)
318{
319 uint32_t low = SMU7_THERMAL_MINIMUM_ALERT_TEMP *
320 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
321 uint32_t high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP *
322 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
323
324 if (low < low_temp)
325 low = low_temp;
326 if (high > high_temp)
327 high = high_temp;
328
329 if (low > high)
330 return -EINVAL;
331
332 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
333 CG_THERMAL_INT, DIG_THERM_INTH,
334 (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
335 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
336 CG_THERMAL_INT, DIG_THERM_INTL,
337 (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
338 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
339 CG_THERMAL_CTRL, DIG_THERM_DPM,
340 (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
341
342 return 0;
343}
344
345/**
346* Programs thermal controller one-time setting registers
347*
348* @param hwmgr The address of the hardware manager.
349*/
350static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
351{
352 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
353 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
354 CG_TACH_CTRL, EDGE_PER_REV,
355 hwmgr->thermal_controller.fanInfo.
356 ucTachometerPulsesPerRevolution - 1);
357
358 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
359 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
360
361 return 0;
362}
363
364/**
365* Enable thermal alerts on the RV770 thermal controller.
366*
367* @param hwmgr The address of the hardware manager.
368*/
369int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
370{
371 uint32_t alert;
372
373 alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
374 CG_THERMAL_INT, THERM_INT_MASK);
375 alert &= ~(SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK);
376 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
377 CG_THERMAL_INT, THERM_INT_MASK, alert);
378
379 /* send message to SMU to enable internal thermal interrupts */
380 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
381}
382
383/**
384* Disable thermal alerts on the RV770 thermal controller.
385* @param hwmgr The address of the hardware manager.
386*/
387int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
388{
389 uint32_t alert;
390
391 alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
392 CG_THERMAL_INT, THERM_INT_MASK);
393 alert |= (SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK);
394 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
395 CG_THERMAL_INT, THERM_INT_MASK, alert);
396
397 /* send message to SMU to disable internal thermal interrupts */
398 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
399}
400
401/**
402* Uninitialize the thermal controller.
403* Currently just disables alerts.
404* @param hwmgr The address of the hardware manager.
405*/
406int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
407{
408 int result = smu7_thermal_disable_alert(hwmgr);
409
410 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
411 smu7_fan_ctrl_set_default_mode(hwmgr);
412
413 return result;
414}
415
416/**
417* Start the fan control on the SMC.
418* @param hwmgr the address of the powerplay hardware manager.
419* @param pInput the pointer to input data
420* @param pOutput the pointer to output data
421* @param pStorage the pointer to temporary storage
422* @param Result the last failure code
423* @return result from set temperature range routine
424*/
425static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
426 void *input, void *output, void *storage, int result)
427{
428/* If the fantable setup has failed we could have disabled
429 * PHM_PlatformCaps_MicrocodeFanControl even after
430 * this function was included in the table.
431 * Make sure that we still think controlling the fan is OK.
432*/
433 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
434 PHM_PlatformCaps_MicrocodeFanControl)) {
435 smu7_fan_ctrl_start_smc_fan_control(hwmgr);
436 smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
437 }
438
439 return 0;
440}
441
442/**
443* Set temperature range for high and low alerts
444* @param hwmgr the address of the powerplay hardware manager.
445* @param pInput the pointer to input data
446* @param pOutput the pointer to output data
447* @param pStorage the pointer to temporary storage
448* @param Result the last failure code
449* @return result from set temperature range routine
450*/
451static int tf_smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
452 void *input, void *output, void *storage, int result)
453{
454 struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
455
456 if (range == NULL)
457 return -EINVAL;
458
459 return smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
460}
461
462/**
463* Programs one-time setting registers
464* @param hwmgr the address of the powerplay hardware manager.
465* @param pInput the pointer to input data
466* @param pOutput the pointer to output data
467* @param pStorage the pointer to temporary storage
468* @param Result the last failure code
469* @return result from initialize thermal controller routine
470*/
471static int tf_smu7_thermal_initialize(struct pp_hwmgr *hwmgr,
472 void *input, void *output, void *storage, int result)
473{
474 return smu7_thermal_initialize(hwmgr);
475}
476
477/**
478* Enable high and low alerts
479* @param hwmgr the address of the powerplay hardware manager.
480* @param pInput the pointer to input data
481* @param pOutput the pointer to output data
482* @param pStorage the pointer to temporary storage
483* @param Result the last failure code
484* @return result from enable alert routine
485*/
486static int tf_smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr,
487 void *input, void *output, void *storage, int result)
488{
489 return smu7_thermal_enable_alert(hwmgr);
490}
491
492/**
493* Disable high and low alerts
494* @param hwmgr the address of the powerplay hardware manager.
495* @param pInput the pointer to input data
496* @param pOutput the pointer to output data
497* @param pStorage the pointer to temporary storage
498* @param Result the last failure code
499* @return result from disable alert routine
500*/
501static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr,
502 void *input, void *output, void *storage, int result)
503{
504 return smu7_thermal_disable_alert(hwmgr);
505}
506
507static const struct phm_master_table_item
508phm_thermal_start_thermal_controller_master_list[] = {
509 {NULL, tf_smu7_thermal_initialize},
510 {NULL, tf_smu7_thermal_set_temperature_range},
511 {NULL, tf_smu7_thermal_enable_alert},
512 {NULL, smum_thermal_avfs_enable},
513/* We should restrict performance levels to low before we halt the SMC.
514 * On the other hand we are still in boot state when we do this
515 * so it would be pointless.
516 * If this assumption changes we have to revisit this table.
517 */
518 {NULL, smum_thermal_setup_fan_table},
519 {NULL, tf_smu7_thermal_start_smc_fan_control},
520 {NULL, NULL}
521};
522
523static const struct phm_master_table_header
524phm_thermal_start_thermal_controller_master = {
525 0,
526 PHM_MasterTableFlag_None,
527 phm_thermal_start_thermal_controller_master_list
528};
529
530static const struct phm_master_table_item
531phm_thermal_set_temperature_range_master_list[] = {
532 {NULL, tf_smu7_thermal_disable_alert},
533 {NULL, tf_smu7_thermal_set_temperature_range},
534 {NULL, tf_smu7_thermal_enable_alert},
535 {NULL, NULL}
536};
537
538static const struct phm_master_table_header
539phm_thermal_set_temperature_range_master = {
540 0,
541 PHM_MasterTableFlag_None,
542 phm_thermal_set_temperature_range_master_list
543};
544
545int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
546{
547 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
548 smu7_fan_ctrl_set_default_mode(hwmgr);
549 return 0;
550}
551
552/**
553* Initializes the thermal controller related functions in the Hardware Manager structure.
554* @param hwmgr The address of the hardware manager.
555* @exception Any error code from the low-level communication.
556*/
557int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
558{
559 int result;
560
561 result = phm_construct_table(hwmgr,
562 &phm_thermal_set_temperature_range_master,
563 &(hwmgr->set_temperature_range));
564
565 if (!result) {
566 result = phm_construct_table(hwmgr,
567 &phm_thermal_start_thermal_controller_master,
568 &(hwmgr->start_thermal_controller));
569 if (result)
570 phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
571 }
572
573 if (!result)
574 hwmgr->fan_ctrl_is_in_default_mode = true;
575 return result;
576}
577
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
new file mode 100644
index 000000000000..6face973be43
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
@@ -0,0 +1,58 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _SMU7_THERMAL_H_
25#define _SMU7_THERMAL_H_
26
27#include "hwmgr.h"
28
29#define SMU7_THERMAL_HIGH_ALERT_MASK 0x1
30#define SMU7_THERMAL_LOW_ALERT_MASK 0x2
31
32#define SMU7_THERMAL_MINIMUM_TEMP_READING -256
33#define SMU7_THERMAL_MAXIMUM_TEMP_READING 255
34
35#define SMU7_THERMAL_MINIMUM_ALERT_TEMP 0
36#define SMU7_THERMAL_MAXIMUM_ALERT_TEMP 255
37
38#define FDO_PWM_MODE_STATIC 1
39#define FDO_PWM_MODE_STATIC_RPM 5
40
41extern int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr);
42extern int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
43extern int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
44extern int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
45extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
46extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
47extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
48extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
49extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr);
50extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
51extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
52extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
53extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
54extern int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr);
55extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr);
56
57#endif
58
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h
new file mode 100644
index 000000000000..65eb630bfea3
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_common.h
@@ -0,0 +1,58 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _PP_COMMON_H
25#define _PP_COMMON_H
26
27#include "smu7_ppsmc.h"
28#include "cgs_common.h"
29
30#include "smu/smu_7_1_3_d.h"
31#include "smu/smu_7_1_3_sh_mask.h"
32
33
34#include "smu74.h"
35#include "smu74_discrete.h"
36
37#include "gmc/gmc_8_1_d.h"
38#include "gmc/gmc_8_1_sh_mask.h"
39
40#include "bif/bif_5_0_d.h"
41#include "bif/bif_5_0_sh_mask.h"
42
43
44#include "bif/bif_5_0_d.h"
45#include "bif/bif_5_0_sh_mask.h"
46
47#include "dce/dce_10_0_d.h"
48#include "dce/dce_10_0_sh_mask.h"
49
50#include "gca/gfx_8_0_d.h"
51#include "gca/gfx_8_0_sh_mask.h"
52
53#include "oss/oss_3_0_d.h"
54#include "oss/oss_3_0_sh_mask.h"
55
56
57#endif
58
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
new file mode 100644
index 000000000000..bce00096d80d
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
@@ -0,0 +1,412 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef DGPU_VI_PP_SMC_H
25#define DGPU_VI_PP_SMC_H
26
27
28#pragma pack(push, 1)
29
30#define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
31
32#define PPSMC_SWSTATE_FLAG_DC 0x01
33#define PPSMC_SWSTATE_FLAG_UVD 0x02
34#define PPSMC_SWSTATE_FLAG_VCE 0x04
35
36#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
39
40#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42#define PPSMC_SYSTEMFLAG_GDDR5 0x04
43
44#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
45
46#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
47#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
48
49#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
50#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
51
52#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
53#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
54
55
56#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
57#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
58#define PPSMC_DPM2FLAGS_OCP 0x04
59
60
61#define PPSMC_DISPLAY_WATERMARK_LOW 0
62#define PPSMC_DISPLAY_WATERMARK_HIGH 1
63
64
65#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
66#define PPSMC_STATEFLAG_POWERBOOST 0x02
67#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
68#define PPSMC_STATEFLAG_POWERSHIFT 0x08
69#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
70#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
71#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
72
73
74#define FDO_MODE_HARDWARE 0
75#define FDO_MODE_PIECE_WISE_LINEAR 1
76
77enum FAN_CONTROL {
78 FAN_CONTROL_FUZZY,
79 FAN_CONTROL_TABLE
80};
81
82
83#define PPSMC_Result_OK ((uint16_t)0x01)
84#define PPSMC_Result_NoMore ((uint16_t)0x02)
85
86#define PPSMC_Result_NotNow ((uint16_t)0x03)
87#define PPSMC_Result_Failed ((uint16_t)0xFF)
88#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
89#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
90
91typedef uint16_t PPSMC_Result;
92
93#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
94
95
96#define PPSMC_MSG_Halt ((uint16_t)0x10)
97#define PPSMC_MSG_Resume ((uint16_t)0x11)
98#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
99#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
100#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
101#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
102#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
103#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
104#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
105#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
106#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
107#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
108#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
109#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
110#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
111#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
112#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
113#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
114#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
115#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
116#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
117#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
118#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
119#define PPSMC_CACHistoryStart ((uint16_t)0x57)
120#define PPSMC_CACHistoryStop ((uint16_t)0x58)
121#define PPSMC_TDPClampingActive ((uint16_t)0x59)
122#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
123#define PPSMC_StartFanControl ((uint16_t)0x5B)
124#define PPSMC_StopFanControl ((uint16_t)0x5C)
125#define PPSMC_NoDisplay ((uint16_t)0x5D)
126#define PPSMC_HasDisplay ((uint16_t)0x5E)
127#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
128#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
129#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
130#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
131#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
132#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
133#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
134#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
135#define PPSMC_OCPActive ((uint16_t)0x6C)
136#define PPSMC_OCPInactive ((uint16_t)0x6D)
137#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
138#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
139#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
140#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
141#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
142#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
143#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
144#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
145#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
146#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
147#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
148#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
149#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
150#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
151#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
152#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
153
154#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
155#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
156#define PPSMC_FlushDataCache ((uint16_t)0x80)
157#define PPSMC_FlushInstrCache ((uint16_t)0x81)
158
159#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
160#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
161
162#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
163
164#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
165#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
166#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
167#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
168
169#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
170#define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A)
171#define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B)
172#define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C)
173
174#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
175
176#define PPSMC_MSG_Test ((uint16_t) 0x100)
177#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
178#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
179#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
180#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
181#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
182#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
183#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
184#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
185#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
186#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
187#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
188#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
189#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
190#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
191#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
192#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
193#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
194#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
195#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
196#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
197#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
198#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
199#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
200#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
201#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
202#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
203#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
204#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
205#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
206#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
207#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
208#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
209#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
210#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
211#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)
212#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
213
214#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
215#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
216#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
217#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
218#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
219#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
220#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
221#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
222#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
223#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
224#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
225#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
226#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
227#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
228#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
229#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
230#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
231#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
232#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
233#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
234#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
235#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
236#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
237#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
238#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
239#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
240#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
241#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
242#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
243#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
244#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
245#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
246#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
247#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
248#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
249#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
250#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
251
252#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e)
253#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f)
254#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150)
255#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151)
256#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152)
257#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153)
258#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154)
259#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155)
260#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156)
261#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157)
262#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158)
263#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159)
264#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a)
265#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b)
266#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c)
267#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
268#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
269#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
270#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
271#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
272#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
273#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
274#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
275#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
276#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
277#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
278#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
279#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
280#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
281#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
282#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c)
283#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d)
284#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e)
285#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f)
286#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170)
287#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171)
288#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
289#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
290#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
291#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
292#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
293#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
294#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
295#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
296#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
297#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
298#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
299#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
300#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
301#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
302#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
303#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
304#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
305#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
306#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
307#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
308#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
309#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
310#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
311#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
312#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
313#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
314#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
315#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
316#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
317#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
318#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
319#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
320#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
321#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
322#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
323#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
324#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
325#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
326#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
327#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
328#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
329#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
330#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
331#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
332#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
333
334#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
335#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
336#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
337#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
338#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
339#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
340#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
341#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
342#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
343
344#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
345#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
346#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
347#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
348#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
349#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
350#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
351
352#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
353#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
354#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
355#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
356#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
357#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
358#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
359#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
360#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
361#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
362#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
363#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
364#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
365#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
366#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
367#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
368#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
369#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
370#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
371#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
372#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
373#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
374#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
375#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
376#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A)
377#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B)
378
379#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C)
380#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275)
381#define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277)
382#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400)
383#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401)
384#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402)
385#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
386#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
387
388#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
389#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
390#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
391
392#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
393#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
394
395#define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306)
396
397#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
398#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
399#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)
400#define PPSMC_MSG_GetData ((uint16_t) 0x801)
401#define PPSMC_MSG_SetData ((uint16_t) 0x802)
402
403typedef uint16_t PPSMC_Msg;
404
405#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
406#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
407#define PPSMC_EVENT_STATUS_DC 0x00000004
408
409#pragma pack(pop)
410
411#endif
412
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 14:24:10 -0400