Merge branches 'clockevents/4.4-fixes' and 'clockevents/4.5-fixes' of http://git.linaro.org/people/daniel.lezcano/linux into timers/urgent

Pull in fixes from Daniel Lezcano: - Fix the vt8500 timer leading to a system lock up when dealing with too small delta (Roman Volkov) - Select the CLKSRC_MMIO when the fsl_ftm_timer is enabled with COMPILE_TEST (Daniel Lezcano) - Prevent to compile timers using the 'iomem' API when the architecture has not HAS_IOMEM set (Richard Weinberger)
author: Thomas Gleixner <tglx@linutronix.de> 2016-01-12 05:01:12 -0500
committer: Thomas Gleixner <tglx@linutronix.de> 2016-01-12 05:01:12 -0500
commit: 1f16f116b01c110db20ab808562c8b8bc3ee3d6e (patch)
tree: 44db563f64cf5f8d62af8f99a61e2b248c44ea3a /drivers/gpu
parent: 03724ac3d48f8f0e3caf1d30fa134f8fd96c94e2 (diff)
parent: f9eccf24615672896dc13251410c3f2f33a14f95 (diff)
98 files changed, 2140 insertions, 1510 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 306f75700bf8..048cfe073dae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -496,6 +496,7 @@ struct amdgpu_bo_va_mapping {
 /* bo virtual addresses in a specific vm */
 struct amdgpu_bo_va {
+        struct mutex                    mutex;
        /* protected by bo being reserved */
        struct list_head                bo_list;
        struct fence                    *last_pt_update;
@@ -538,6 +539,7 @@ struct amdgpu_bo {
        /* Constant after initialization */
        struct amdgpu_device            *adev;
        struct drm_gem_object           gem_base;
+        struct amdgpu_bo                *parent;
        struct ttm_bo_kmap_obj          dma_buf_vmap;
        pid_t                           pid;
@@ -928,8 +930,6 @@ struct amdgpu_vm_id {
 };
 struct amdgpu_vm {
-        struct mutex            mutex;
        struct rb_root          va;
        /* protecting invalidated */
@@ -956,6 +956,8 @@ struct amdgpu_vm {
        struct amdgpu_vm_id     ids[AMDGPU_MAX_RINGS];
        /* for interval tree */
        spinlock_t              it_lock;
+        /* protecting freed */
+        spinlock_t              freed_lock;
 };
 struct amdgpu_vm_manager {
@@ -1262,7 +1264,8 @@ struct amdgpu_cs_parser {
        struct ww_acquire_ctx   ticket;
        /* user fence */
-        struct amdgpu_user_fence uf;
+        struct amdgpu_user_fence        uf;
+        struct amdgpu_bo_list_entry     uf_entry;
 };
 struct amdgpu_job {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3afcf0237c25..25a3e2485cc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -127,6 +127,37 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
        return 0;
 }
+static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
+                                      struct drm_amdgpu_cs_chunk_fence *fence_data)
+{
+        struct drm_gem_object *gobj;
+        uint32_t handle;
+        handle = fence_data->handle;
+        gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,
+                                     fence_data->handle);
+        if (gobj == NULL)
+                return -EINVAL;
+        p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
+        p->uf.offset = fence_data->offset;
+        if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) {
+                drm_gem_object_unreference_unlocked(gobj);
+                return -EINVAL;
+        }
+        p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
+        p->uf_entry.prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
+        p->uf_entry.allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
+        p->uf_entry.priority = 0;
+        p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
+        p->uf_entry.tv.shared = true;
+        drm_gem_object_unreference_unlocked(gobj);
+        return 0;
+}
 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 {
        union drm_amdgpu_cs *cs = data;
@@ -207,26 +238,15 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
                case AMDGPU_CHUNK_ID_FENCE:
                        size = sizeof(struct drm_amdgpu_cs_chunk_fence);
-                        if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
+                        if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
-                                uint32_t handle;
-                                struct drm_gem_object *gobj;
-                                struct drm_amdgpu_cs_chunk_fence *fence_data;
-                                fence_data = (void *)p->chunks[i].kdata;
-                                handle = fence_data->handle;
-                                gobj = drm_gem_object_lookup(p->adev->ddev,
-                                                             p->filp, handle);
-                                if (gobj == NULL) {
-                                        ret = -EINVAL;
-                                        goto free_partial_kdata;
-                                }
-                                p->uf.bo = gem_to_amdgpu_bo(gobj);
-                                p->uf.offset = fence_data->offset;
-                        } else {
                                ret = -EINVAL;
                                goto free_partial_kdata;
                        }
+                        ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata);
+                        if (ret)
+                                goto free_partial_kdata;
                        break;
                case AMDGPU_CHUNK_ID_DEPENDENCIES:
@@ -389,6 +409,9 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
        p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
                                      &p->validated);
+        if (p->uf.bo)
+                list_add(&p->uf_entry.tv.head, &p->validated);
        if (need_mmap_lock)
                down_read(&current->mm->mmap_sem);
@@ -486,8 +509,8 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
                for (i = 0; i < parser->num_ibs; i++)
                        amdgpu_ib_free(parser->adev, &parser->ibs[i]);
        kfree(parser->ibs);
-        if (parser->uf.bo)
+        amdgpu_bo_unref(&parser->uf.bo);
-                drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
+        amdgpu_bo_unref(&parser->uf_entry.robj);
 }
 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
@@ -776,7 +799,7 @@ static int amdgpu_cs_free_job(struct amdgpu_job *job)
                        amdgpu_ib_free(job->adev, &job->ibs[i]);
        kfree(job->ibs);
        if (job->uf.bo)
-                drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base);
+                amdgpu_bo_unref(&job->uf.bo);
        return 0;
 }
@@ -784,8 +807,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 {
        struct amdgpu_device *adev = dev->dev_private;
        union drm_amdgpu_cs *cs = data;
-        struct amdgpu_fpriv *fpriv = filp->driver_priv;
-        struct amdgpu_vm *vm = &fpriv->vm;
        struct amdgpu_cs_parser parser = {};
        bool reserved_buffers = false;
        int i, r;
@@ -803,7 +824,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                r = amdgpu_cs_handle_lockup(adev, r);
                return r;
        }
-        mutex_lock(&vm->mutex);
        r = amdgpu_cs_parser_relocs(&parser);
        if (r == -ENOMEM)
                DRM_ERROR("Not enough memory for command submission!\n");
@@ -888,7 +908,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 out:
        amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
-        mutex_unlock(&vm->mutex);
        r = amdgpu_cs_handle_lockup(adev, r);
        return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index e173a5a02f0d..5580d3420c3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -73,6 +73,8 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
        struct drm_crtc *crtc = &amdgpuCrtc->base;
        unsigned long flags;
        unsigned i;
+        int vpos, hpos, stat, min_udelay;
+        struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
        amdgpu_flip_wait_fence(adev, &work->excl);
        for (i = 0; i < work->shared_count; ++i)
@@ -81,6 +83,41 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
        /* We borrow the event spin lock for protecting flip_status */
        spin_lock_irqsave(&crtc->dev->event_lock, flags);
+        /* If this happens to execute within the "virtually extended" vblank
+         * interval before the start of the real vblank interval then it needs
+         * to delay programming the mmio flip until the real vblank is entered.
+         * This prevents completing a flip too early due to the way we fudge
+         * our vblank counter and vblank timestamps in order to work around the
+         * problem that the hw fires vblank interrupts before actual start of
+         * vblank (when line buffer refilling is done for a frame). It
+         * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for
+         * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts.
+         *
+         * In practice this won't execute very often unless on very fast
+         * machines because the time window for this to happen is very small.
+         */
+        for (;;) {
+                /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
+                 * start in hpos, and to the "fudged earlier" vblank start in
+                 * vpos.
+                 */
+                stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id,
+                                                  GET_DISTANCE_TO_VBLANKSTART,
+                                                  &vpos, &hpos, NULL, NULL,
+                                                  &crtc->hwmode);
+                if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
+                    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
+                    !(vpos >= 0 && hpos <= 0))
+                        break;
+                /* Sleep at least until estimated real start of hw vblank */
+                spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+                min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
+                usleep_range(min_udelay, 2 * min_udelay);
+                spin_lock_irqsave(&crtc->dev->event_lock, flags);
+        };
        /* do the flip (mmio) */
        adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
        /* set the flip status */
@@ -109,7 +146,7 @@ static void amdgpu_unpin_work_func(struct work_struct *__work)
        } else
                DRM_ERROR("failed to reserve buffer after flip\n");
-        drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
+        amdgpu_bo_unref(&work->old_rbo);
        kfree(work->shared);
        kfree(work);
 }
@@ -148,8 +185,8 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
        obj = old_amdgpu_fb->obj;
        /* take a reference to the old object */
-        drm_gem_object_reference(obj);
        work->old_rbo = gem_to_amdgpu_bo(obj);
+        amdgpu_bo_ref(work->old_rbo);
        new_amdgpu_fb = to_amdgpu_framebuffer(fb);
        obj = new_amdgpu_fb->obj;
@@ -222,7 +259,7 @@ pflip_cleanup:
        amdgpu_bo_unreserve(new_rbo);
 cleanup:
-        drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
+        amdgpu_bo_unref(&work->old_rbo);
        fence_put(work->excl);
        for (i = 0; i < work->shared_count; ++i)
                fence_put(work->shared[i]);
@@ -712,6 +749,15 @@ bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 * \param dev Device to query.
 * \param pipe Crtc to query.
 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
+ *              For driver internal use only also supports these flags:
+ *
+ *              USE_REAL_VBLANKSTART to use the real start of vblank instead
+ *              of a fudged earlier start of vblank.
+ *
+ *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
+ *              fudged earlier start of vblank in *vpos and the distance
+ *              to true start of vblank in *hpos.
+ *
 * \param *vpos Location where vertical scanout position should be stored.
 * \param *hpos Location where horizontal scanout position should go.
 * \param *stime Target location for timestamp taken immediately before
@@ -776,10 +822,40 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
                vbl_end = 0;
        }
+        /* Called from driver internal vblank counter query code? */
+        if (flags & GET_DISTANCE_TO_VBLANKSTART) {
+            /* Caller wants distance from real vbl_start in *hpos */
+            *hpos = *vpos - vbl_start;
+        }
+        /* Fudge vblank to start a few scanlines earlier to handle the
+         * problem that vblank irqs fire a few scanlines before start
+         * of vblank. Some driver internal callers need the true vblank
+         * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
+         *
+         * The cause of the "early" vblank irq is that the irq is triggered
+         * by the line buffer logic when the line buffer read position enters
+         * the vblank, whereas our crtc scanout position naturally lags the
+         * line buffer read position.
+         */
+        if (!(flags & USE_REAL_VBLANKSTART))
+                vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
        /* Test scanout position against vblank region. */
        if ((*vpos < vbl_start) && (*vpos >= vbl_end))
                in_vbl = false;
+        /* In vblank? */
+        if (in_vbl)
+            ret |= DRM_SCANOUTPOS_IN_VBLANK;
+        /* Called from driver internal vblank counter query code? */
+        if (flags & GET_DISTANCE_TO_VBLANKSTART) {
+                /* Caller wants distance from fudged earlier vbl_start */
+                *vpos -= vbl_start;
+                return ret;
+        }
        /* Check if inside vblank area and apply corrective offsets:
         * vpos will then be >=0 in video scanout area, but negative
         * within vblank area, counting down the number of lines until
@@ -795,32 +871,6 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
        /* Correct for shifted end of vbl at vbl_end. */
        *vpos = *vpos - vbl_end;
-        /* In vblank? */
-        if (in_vbl)
-                ret |= DRM_SCANOUTPOS_IN_VBLANK;
-        /* Is vpos outside nominal vblank area, but less than
-         * 1/100 of a frame height away from start of vblank?
-         * If so, assume this isn't a massively delayed vblank
-         * interrupt, but a vblank interrupt that fired a few
-         * microseconds before true start of vblank. Compensate
-         * by adding a full frame duration to the final timestamp.
-         * Happens, e.g., on ATI R500, R600.
-         *
-         * We only do this if DRM_CALLED_FROM_VBLIRQ.
-         */
-        if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
-                vbl_start = mode->crtc_vdisplay;
-                vtotal = mode->crtc_vtotal;
-                if (vbl_start - *vpos < vtotal / 100) {
-                        *vpos -= vtotal;
-                        /* Signal this correction as "applied". */
-                        ret |= 0x8;
-                }
-        }
        return ret;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 00c5b580f56c..9c253c535d26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -115,12 +115,9 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
        struct amdgpu_vm *vm = &fpriv->vm;
        struct amdgpu_bo_va *bo_va;
        int r;
-        mutex_lock(&vm->mutex);
        r = amdgpu_bo_reserve(rbo, false);
-        if (r) {
+        if (r)
-                mutex_unlock(&vm->mutex);
                return r;
-        }
        bo_va = amdgpu_vm_bo_find(vm, rbo);
        if (!bo_va) {
@@ -129,7 +126,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
                ++bo_va->ref_count;
        }
        amdgpu_bo_unreserve(rbo);
-        mutex_unlock(&vm->mutex);
        return 0;
 }
@@ -142,10 +138,8 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
        struct amdgpu_vm *vm = &fpriv->vm;
        struct amdgpu_bo_va *bo_va;
        int r;
-        mutex_lock(&vm->mutex);
        r = amdgpu_bo_reserve(rbo, true);
        if (r) {
-                mutex_unlock(&vm->mutex);
                dev_err(adev->dev, "leaking bo va because "
                        "we fail to reserve bo (%d)\n", r);
                return;
@@ -157,7 +151,6 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
                }
        }
        amdgpu_bo_unreserve(rbo);
-        mutex_unlock(&vm->mutex);
 }
 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
@@ -242,8 +235,9 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
            AMDGPU_GEM_USERPTR_REGISTER))
                return -EINVAL;
-        if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
+        if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && (
-                   !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
+             !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
+             !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) {
                /* if we want to write to it we must require anonymous
                   memory and install a MMU notifier */
@@ -483,6 +477,14 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
                if (domain == AMDGPU_GEM_DOMAIN_CPU)
                        goto error_unreserve;
        }
+        list_for_each_entry(entry, &duplicates, head) {
+                domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
+                /* if anything is swapped out don't swap it in here,
+                   just abort and wait for the next CS */
+                if (domain == AMDGPU_GEM_DOMAIN_CPU)
+                        goto error_unreserve;
+        }
        r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
        if (r)
                goto error_unreserve;
@@ -553,7 +555,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        gobj = drm_gem_object_lookup(dev, filp, args->handle);
        if (gobj == NULL)
                return -ENOENT;
-        mutex_lock(&fpriv->vm.mutex);
        rbo = gem_to_amdgpu_bo(gobj);
        INIT_LIST_HEAD(&list);
        INIT_LIST_HEAD(&duplicates);
@@ -568,7 +569,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        }
        r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
        if (r) {
-                mutex_unlock(&fpriv->vm.mutex);
                drm_gem_object_unreference_unlocked(gobj);
                return r;
        }
@@ -577,7 +577,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        if (!bo_va) {
                ttm_eu_backoff_reservation(&ticket, &list);
                drm_gem_object_unreference_unlocked(gobj);
-                mutex_unlock(&fpriv->vm.mutex);
                return -ENOENT;
        }
@@ -602,7 +601,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
        ttm_eu_backoff_reservation(&ticket, &list);
        if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
                amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
-        mutex_unlock(&fpriv->vm.mutex);
        drm_gem_object_unreference_unlocked(gobj);
        return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 1618e2294a16..e23843f4d877 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -611,13 +611,59 @@ void amdgpu_driver_preclose_kms(struct drm_device *dev,
 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 {
        struct amdgpu_device *adev = dev->dev_private;
+        int vpos, hpos, stat;
+        u32 count;
        if (pipe >= adev->mode_info.num_crtc) {
                DRM_ERROR("Invalid crtc %u\n", pipe);
                return -EINVAL;
        }
-        return amdgpu_display_vblank_get_counter(adev, pipe);
+        /* The hw increments its frame counter at start of vsync, not at start
+         * of vblank, as is required by DRM core vblank counter handling.
+         * Cook the hw count here to make it appear to the caller as if it
+         * incremented at start of vblank. We measure distance to start of
+         * vblank in vpos. vpos therefore will be >= 0 between start of vblank
+         * and start of vsync, so vpos >= 0 means to bump the hw frame counter
+         * result by 1 to give the proper appearance to caller.
+         */
+        if (adev->mode_info.crtcs[pipe]) {
+                /* Repeat readout if needed to provide stable result if
+                 * we cross start of vsync during the queries.
+                 */
+                do {
+                        count = amdgpu_display_vblank_get_counter(adev, pipe);
+                        /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
+                         * distance to start of vblank, instead of regular
+                         * vertical scanout pos.
+                         */
+                        stat = amdgpu_get_crtc_scanoutpos(
+                                dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
+                                &vpos, &hpos, NULL, NULL,
+                                &adev->mode_info.crtcs[pipe]->base.hwmode);
+                } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
+                if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
+                    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
+                        DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
+                } else {
+                        DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
+                                      pipe, vpos);
+                        /* Bump counter if we are at >= leading edge of vblank,
+                         * but before vsync where vpos would turn negative and
+                         * the hw counter really increments.
+                         */
+                        if (vpos >= 0)
+                                count++;
+                }
+        } else {
+                /* Fallback to use value as is. */
+                count = amdgpu_display_vblank_get_counter(adev, pipe);
+                DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
+        }
+        return count;
 }
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index b62c1710cab6..064ebb347074 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -407,6 +407,7 @@ struct amdgpu_crtc {
        u32 line_time;
        u32 wm_low;
        u32 wm_high;
+        u32 lb_vblank_lead_lines;
        struct drm_display_mode hw_mode;
 };
@@ -528,6 +529,10 @@ struct amdgpu_framebuffer {
 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
                                ((em) == ATOM_ENCODER_MODE_DP_MST))
+/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
+#define USE_REAL_VBLANKSTART            (1 << 30)
+#define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 void amdgpu_link_encoder_connector(struct drm_device *dev);
 struct drm_connector *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0d524384ff79..c3ce103b6a33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -100,6 +100,7 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
        list_del_init(&bo->list);
        mutex_unlock(&bo->adev->gem.mutex);
        drm_gem_object_release(&bo->gem_base);
+        amdgpu_bo_unref(&bo->parent);
        kfree(bo->metadata);
        kfree(bo);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d4bac5f49939..8a1752ff3d8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -587,9 +587,13 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
        uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
        int r;
-        if (gtt->userptr)
+        if (gtt->userptr) {
-                amdgpu_ttm_tt_pin_userptr(ttm);
+                r = amdgpu_ttm_tt_pin_userptr(ttm);
+                if (r) {
+                        DRM_ERROR("failed to pin userptr\n");
+                        return r;
+                }
+        }
        gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
        if (!ttm->num_pages) {
                WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
@@ -797,11 +801,12 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
        if (mem && mem->mem_type != TTM_PL_SYSTEM)
                flags |= AMDGPU_PTE_VALID;
-        if (mem && mem->mem_type == TTM_PL_TT)
+        if (mem && mem->mem_type == TTM_PL_TT) {
                flags |= AMDGPU_PTE_SYSTEM;
-        if (!ttm || ttm->caching_state == tt_cached)
+                if (ttm->caching_state == tt_cached)
-                flags |= AMDGPU_PTE_SNOOPED;
+                        flags |= AMDGPU_PTE_SNOOPED;
+        }
        if (adev->asic_type >= CHIP_TOPAZ)
                flags |= AMDGPU_PTE_EXECUTABLE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 03f0c3bae516..a745eeeb5d82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -392,7 +392,10 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
        ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
        ib->ptr[ib->length_dw++] = handle;
-        ib->ptr[ib->length_dw++] = 0x00000030; /* len */
+        if ((ring->adev->vce.fw_version >> 24) >= 52)
+                ib->ptr[ib->length_dw++] = 0x00000040; /* len */
+        else
+                ib->ptr[ib->length_dw++] = 0x00000030; /* len */
        ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
        ib->ptr[ib->length_dw++] = 0x00000000;
        ib->ptr[ib->length_dw++] = 0x00000042;
@@ -404,6 +407,12 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
        ib->ptr[ib->length_dw++] = 0x00000100;
        ib->ptr[ib->length_dw++] = 0x0000000c;
        ib->ptr[ib->length_dw++] = 0x00000000;
+        if ((ring->adev->vce.fw_version >> 24) >= 52) {
+                ib->ptr[ib->length_dw++] = 0x00000000;
+                ib->ptr[ib->length_dw++] = 0x00000000;
+                ib->ptr[ib->length_dw++] = 0x00000000;
+                ib->ptr[ib->length_dw++] = 0x00000000;
+        }
        ib->ptr[ib->length_dw++] = 0x00000014; /* len */
        ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 159ce54bbd8d..b53d273eb7a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -885,17 +885,21 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
        struct amdgpu_bo_va_mapping *mapping;
        int r;
+        spin_lock(&vm->freed_lock);
        while (!list_empty(&vm->freed)) {
                mapping = list_first_entry(&vm->freed,
                        struct amdgpu_bo_va_mapping, list);
                list_del(&mapping->list);
+                spin_unlock(&vm->freed_lock);
                r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
                kfree(mapping);
                if (r)
                        return r;
+                spin_lock(&vm->freed_lock);
        }
+        spin_unlock(&vm->freed_lock);
        return 0;
 }
@@ -922,8 +926,9 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
                bo_va = list_first_entry(&vm->invalidated,
                        struct amdgpu_bo_va, vm_status);
                spin_unlock(&vm->status_lock);
+                mutex_lock(&bo_va->mutex);
                r = amdgpu_vm_bo_update(adev, bo_va, NULL);
+                mutex_unlock(&bo_va->mutex);
                if (r)
                        return r;
@@ -967,7 +972,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
        INIT_LIST_HEAD(&bo_va->valids);
        INIT_LIST_HEAD(&bo_va->invalids);
        INIT_LIST_HEAD(&bo_va->vm_status);
+        mutex_init(&bo_va->mutex);
        list_add_tail(&bo_va->bo_list, &bo->va);
        return bo_va;
@@ -1045,7 +1050,9 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
        mapping->offset = offset;
        mapping->flags = flags;
+        mutex_lock(&bo_va->mutex);
        list_add(&mapping->list, &bo_va->invalids);
+        mutex_unlock(&bo_va->mutex);
        spin_lock(&vm->it_lock);
        interval_tree_insert(&mapping->it, &vm->va);
        spin_unlock(&vm->it_lock);
@@ -1076,6 +1083,11 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                if (r)
                        goto error_free;
+                /* Keep a reference to the page table to avoid freeing
+                 * them up in the wrong order.
+                 */
+                pt->parent = amdgpu_bo_ref(vm->page_directory);
                r = amdgpu_vm_clear_bo(adev, pt);
                if (r) {
                        amdgpu_bo_unref(&pt);
@@ -1121,7 +1133,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
        bool valid = true;
        saddr /= AMDGPU_GPU_PAGE_SIZE;
+        mutex_lock(&bo_va->mutex);
        list_for_each_entry(mapping, &bo_va->valids, list) {
                if (mapping->it.start == saddr)
                        break;
@@ -1135,20 +1147,25 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
                                break;
                }
-                if (&mapping->list == &bo_va->invalids)
+                if (&mapping->list == &bo_va->invalids) {
+                        mutex_unlock(&bo_va->mutex);
                        return -ENOENT;
+                }
        }
+        mutex_unlock(&bo_va->mutex);
        list_del(&mapping->list);
        spin_lock(&vm->it_lock);
        interval_tree_remove(&mapping->it, &vm->va);
        spin_unlock(&vm->it_lock);
        trace_amdgpu_vm_bo_unmap(bo_va, mapping);
-        if (valid)
+        if (valid) {
+                spin_lock(&vm->freed_lock);
                list_add(&mapping->list, &vm->freed);
-        else
+                spin_unlock(&vm->freed_lock);
+        } else {
                kfree(mapping);
+        }
        return 0;
 }
@@ -1181,7 +1198,9 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
                interval_tree_remove(&mapping->it, &vm->va);
                spin_unlock(&vm->it_lock);
                trace_amdgpu_vm_bo_unmap(bo_va, mapping);
+                spin_lock(&vm->freed_lock);
                list_add(&mapping->list, &vm->freed);
+                spin_unlock(&vm->freed_lock);
        }
        list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
                list_del(&mapping->list);
@@ -1190,8 +1209,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
                spin_unlock(&vm->it_lock);
                kfree(mapping);
        }
        fence_put(bo_va->last_pt_update);
+        mutex_destroy(&bo_va->mutex);
        kfree(bo_va);
 }
@@ -1236,13 +1255,13 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
                vm->ids[i].id = 0;
                vm->ids[i].flushed_updates = NULL;
        }
-        mutex_init(&vm->mutex);
        vm->va = RB_ROOT;
        spin_lock_init(&vm->status_lock);
        INIT_LIST_HEAD(&vm->invalidated);
        INIT_LIST_HEAD(&vm->cleared);
        INIT_LIST_HEAD(&vm->freed);
        spin_lock_init(&vm->it_lock);
+        spin_lock_init(&vm->freed_lock);
        pd_size = amdgpu_vm_directory_size(adev);
        pd_entries = amdgpu_vm_num_pdes(adev);
@@ -1320,7 +1339,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
                fence_put(vm->ids[i].flushed_updates);
        }
-        mutex_destroy(&vm->mutex);
 }
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index cb0f7747e3dc..4dcc8fba5792 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1250,7 +1250,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
        u32 pixel_period;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
-        u32 tmp, wm_mask;
+        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
                pixel_period = 1000000 / (u32)mode->clock;
@@ -1333,6 +1333,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
                    (adev->mode_info.disp_priority == 2)) {
                        DRM_DEBUG_KMS("force priority to high\n");
                }
+                lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
@@ -1357,6 +1358,8 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
        amdgpu_crtc->line_time = line_time;
        amdgpu_crtc->wm_high = latency_watermark_a;
        amdgpu_crtc->wm_low = latency_watermark_b;
+        /* Save number of lines the linebuffer leads before the scanout */
+        amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
 }
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 5af3721851d6..8f1e51128b33 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1238,7 +1238,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
        u32 pixel_period;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
-        u32 tmp, wm_mask;
+        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
                pixel_period = 1000000 / (u32)mode->clock;
@@ -1321,6 +1321,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
                    (adev->mode_info.disp_priority == 2)) {
                        DRM_DEBUG_KMS("force priority to high\n");
                }
+                lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
@@ -1345,6 +1346,8 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
        amdgpu_crtc->line_time = line_time;
        amdgpu_crtc->wm_high = latency_watermark_a;
        amdgpu_crtc->wm_low = latency_watermark_b;
+        /* Save number of lines the linebuffer leads before the scanout */
+        amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
 }
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 4f7b49a6dc50..42d954dc436d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1193,7 +1193,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
        u32 pixel_period;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
-        u32 tmp, wm_mask;
+        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
        if (amdgpu_crtc->base.enabled && num_heads && mode) {
                pixel_period = 1000000 / (u32)mode->clock;
@@ -1276,6 +1276,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
                    (adev->mode_info.disp_priority == 2)) {
                        DRM_DEBUG_KMS("force priority to high\n");
                }
+                lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
@@ -1302,6 +1303,8 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
        amdgpu_crtc->line_time = line_time;
        amdgpu_crtc->wm_high = latency_watermark_a;
        amdgpu_crtc->wm_low = latency_watermark_b;
+        /* Save number of lines the linebuffer leads before the scanout */
+        amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
 }
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 7427d8cd4c43..ed8abb58a785 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -513,7 +513,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        WREG32(mmVM_L2_CNTL3, tmp);
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
-        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
+        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page.addr >> 12));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index cb0e50ebb528..d39028440814 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -657,7 +657,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        WREG32(mmVM_L2_CNTL4, tmp);
        /* setup context0 */
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
-        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1);
+        WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
        WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
                        (u32)(adev->dummy_page.addr >> 12));
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 6a52db6ad8d7..370c6c9d81c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -40,6 +40,9 @@
 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT     0x04
 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK       0x10
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0         0x8616
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1         0x8617
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2         0x8618
 #define VCE_V3_0_FW_SIZE        (384 * 1024)
 #define VCE_V3_0_STACK_SIZE     (64 * 1024)
@@ -130,9 +133,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
                /* set BUSY flag */
                WREG32_P(mmVCE_STATUS, 1, ~1);
+                if (adev->asic_type >= CHIP_STONEY)
-                WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
+                        WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
-                        ~VCE_VCPU_CNTL__CLK_EN_MASK);
+                else
+                        WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
+                                ~VCE_VCPU_CNTL__CLK_EN_MASK);
                WREG32_P(mmVCE_SOFT_RESET,
                         VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
@@ -391,8 +396,12 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
        WREG32(mmVCE_LMI_SWAP_CNTL, 0);
        WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
        WREG32(mmVCE_LMI_VM_CTRL, 0);
+        if (adev->asic_type >= CHIP_STONEY) {
-        WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
+                WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
+                WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
+                WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
+        } else
+                WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
        offset = AMDGPU_VCE_FIRMWARE_OFFSET;
        size = VCE_V3_0_FW_SIZE;
        WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
@@ -576,6 +585,11 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
                                      struct amdgpu_iv_entry *entry)
 {
        DRM_DEBUG("IH: VCE\n");
+        WREG32_P(mmVCE_SYS_INT_STATUS,
+                VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
+                ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
        switch (entry->src_data) {
        case 0:
                amdgpu_fence_process(&adev->vce.ring[0]);
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index ea30d6ad4c13..3a4820e863ec 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -30,8 +30,7 @@
 #define CREATE_TRACE_POINTS
 #include "gpu_sched_trace.h"
-static struct amd_sched_job *
+static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
-amd_sched_entity_pop_job(struct amd_sched_entity *entity);
 static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
 struct kmem_cache *sched_fence_slab;
@@ -64,36 +63,36 @@ static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
 }
 /**
- * Select next job from a specified run queue with round robin policy.
+ * Select an entity which could provide a job to run
- * Return NULL if nothing available.
+ *
+ * @rq          The run queue to check.
+ *
+ * Try to find a ready entity, returns NULL if none found.
 */
-static struct amd_sched_job *
+static struct amd_sched_entity *
-amd_sched_rq_select_job(struct amd_sched_rq *rq)
+amd_sched_rq_select_entity(struct amd_sched_rq *rq)
 {
        struct amd_sched_entity *entity;
-        struct amd_sched_job *sched_job;
        spin_lock(&rq->lock);
        entity = rq->current_entity;
        if (entity) {
                list_for_each_entry_continue(entity, &rq->entities, list) {
-                        sched_job = amd_sched_entity_pop_job(entity);
+                        if (amd_sched_entity_is_ready(entity)) {
-                        if (sched_job) {
                                rq->current_entity = entity;
                                spin_unlock(&rq->lock);
-                                return sched_job;
+                                return entity;
                        }
                }
        }
        list_for_each_entry(entity, &rq->entities, list) {
-                sched_job = amd_sched_entity_pop_job(entity);
+                if (amd_sched_entity_is_ready(entity)) {
-                if (sched_job) {
                        rq->current_entity = entity;
                        spin_unlock(&rq->lock);
-                        return sched_job;
+                        return entity;
                }
                if (entity == rq->current_entity)
@@ -177,6 +176,24 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
 }
 /**
+ * Check if entity is ready
+ *
+ * @entity      The pointer to a valid scheduler entity
+ *
+ * Return true if entity could provide a job.
+ */
+static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
+{
+        if (kfifo_is_empty(&entity->job_queue))
+                return false;
+        if (ACCESS_ONCE(entity->dependency))
+                return false;
+        return true;
+}
+/**
 * Destroy a context entity
 *
 * @sched       Pointer to scheduler instance
@@ -211,32 +228,53 @@ static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb)
        amd_sched_wakeup(entity->sched);
 }
+static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
+{
+        struct amd_gpu_scheduler *sched = entity->sched;
+        struct fence * fence = entity->dependency;
+        struct amd_sched_fence *s_fence;
+        if (fence->context == entity->fence_context) {
+                /* We can ignore fences from ourself */
+                fence_put(entity->dependency);
+                return false;
+        }
+        s_fence = to_amd_sched_fence(fence);
+        if (s_fence && s_fence->sched == sched) {
+                /* Fence is from the same scheduler */
+                if (test_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &fence->flags)) {
+                        /* Ignore it when it is already scheduled */
+                        fence_put(entity->dependency);
+                        return false;
+                }
+                /* Wait for fence to be scheduled */
+                entity->cb.func = amd_sched_entity_wakeup;
+                list_add_tail(&entity->cb.node, &s_fence->scheduled_cb);
+                return true;
+        }
+        if (!fence_add_callback(entity->dependency, &entity->cb,
+                                amd_sched_entity_wakeup))
+                return true;
+        fence_put(entity->dependency);
+        return false;
+}
 static struct amd_sched_job *
 amd_sched_entity_pop_job(struct amd_sched_entity *entity)
 {
        struct amd_gpu_scheduler *sched = entity->sched;
        struct amd_sched_job *sched_job;
-        if (ACCESS_ONCE(entity->dependency))
-                return NULL;
        if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job)))
                return NULL;
-        while ((entity->dependency = sched->ops->dependency(sched_job))) {
+        while ((entity->dependency = sched->ops->dependency(sched_job)))
+                if (amd_sched_entity_add_dependency_cb(entity))
-                if (entity->dependency->context == entity->fence_context) {
-                        /* We can ignore fences from ourself */
-                        fence_put(entity->dependency);
-                        continue;
-                }
-                if (fence_add_callback(entity->dependency, &entity->cb,
-                                       amd_sched_entity_wakeup))
-                        fence_put(entity->dependency);
-                else
                        return NULL;
-        }
        return sched_job;
 }
@@ -250,6 +288,7 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity)
 */
 static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
 {
+        struct amd_gpu_scheduler *sched = sched_job->sched;
        struct amd_sched_entity *entity = sched_job->s_entity;
        bool added, first = false;
@@ -264,7 +303,7 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
        /* first job wakes up scheduler */
        if (first)
-                amd_sched_wakeup(sched_job->sched);
+                amd_sched_wakeup(sched);
        return added;
 }
@@ -280,9 +319,9 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
 {
        struct amd_sched_entity *entity = sched_job->s_entity;
+        trace_amd_sched_job(sched_job);
        wait_event(entity->sched->job_scheduled,
                   amd_sched_entity_in(sched_job));
-        trace_amd_sched_job(sched_job);
 }
 /**
@@ -304,22 +343,22 @@ static void amd_sched_wakeup(struct amd_gpu_scheduler *sched)
 }
 /**
- * Select next to run
+ * Select next entity to process
 */
-static struct amd_sched_job *
+static struct amd_sched_entity *
-amd_sched_select_job(struct amd_gpu_scheduler *sched)
+amd_sched_select_entity(struct amd_gpu_scheduler *sched)
 {
-        struct amd_sched_job *sched_job;
+        struct amd_sched_entity *entity;
        if (!amd_sched_ready(sched))
                return NULL;
        /* Kernel run queue has higher priority than normal run queue*/
-        sched_job = amd_sched_rq_select_job(&sched->kernel_rq);
+        entity = amd_sched_rq_select_entity(&sched->kernel_rq);
-        if (sched_job == NULL)
+        if (entity == NULL)
-                sched_job = amd_sched_rq_select_job(&sched->sched_rq);
+                entity = amd_sched_rq_select_entity(&sched->sched_rq);
-        return sched_job;
+        return entity;
 }
 static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
@@ -381,13 +420,16 @@ static int amd_sched_main(void *param)
                unsigned long flags;
                wait_event_interruptible(sched->wake_up_worker,
-                        kthread_should_stop() ||
+                        (entity = amd_sched_select_entity(sched)) ||
-                        (sched_job = amd_sched_select_job(sched)));
+                        kthread_should_stop());
+                if (!entity)
+                        continue;
+                sched_job = amd_sched_entity_pop_job(entity);
                if (!sched_job)
                        continue;
-                entity = sched_job->s_entity;
                s_fence = sched_job->s_fence;
                if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
@@ -400,6 +442,7 @@ static int amd_sched_main(void *param)
                atomic_inc(&sched->hw_rq_count);
                fence = sched->ops->run_job(sched_job);
+                amd_sched_fence_scheduled(s_fence);
                if (fence) {
                        r = fence_add_callback(fence, &s_fence->cb,
                                               amd_sched_process_job);
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 939692b14f4b..a0f0ae53aacd 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -27,6 +27,8 @@
 #include <linux/kfifo.h>
 #include <linux/fence.h>
+#define AMD_SCHED_FENCE_SCHEDULED_BIT   FENCE_FLAG_USER_BITS
 struct amd_gpu_scheduler;
 struct amd_sched_rq;
@@ -68,6 +70,7 @@ struct amd_sched_rq {
 struct amd_sched_fence {
        struct fence                    base;
        struct fence_cb                 cb;
+        struct list_head                scheduled_cb;
        struct amd_gpu_scheduler        *sched;
        spinlock_t                      lock;
        void                            *owner;
@@ -134,7 +137,7 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
 struct amd_sched_fence *amd_sched_fence_create(
        struct amd_sched_entity *s_entity, void *owner);
+void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
 void amd_sched_fence_signal(struct amd_sched_fence *fence);
 #endif
diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
index 8d2130b9ff05..87c78eecea64 100644
--- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
+++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
@@ -35,6 +35,8 @@ struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *s_entity
        fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL);
        if (fence == NULL)
                return NULL;
+        INIT_LIST_HEAD(&fence->scheduled_cb);
        fence->owner = owner;
        fence->sched = s_entity->sched;
        spin_lock_init(&fence->lock);
@@ -55,6 +57,17 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence)
                FENCE_TRACE(&fence->base, "was already signaled\n");
 }
+void amd_sched_fence_scheduled(struct amd_sched_fence *s_fence)
+{
+        struct fence_cb *cur, *tmp;
+        set_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &s_fence->base.flags);
+        list_for_each_entry_safe(cur, tmp, &s_fence->scheduled_cb, node) {
+                list_del_init(&cur->node);
+                cur->func(&s_fence->base, cur);
+        }
+}
 static const char *amd_sched_fence_get_driver_name(struct fence *fence)
 {
        return "amd_sched";
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 9362609df38a..7dd6728dd092 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -160,6 +160,11 @@ int drm_setmaster_ioctl(struct drm_device *dev, void *data,
                goto out_unlock;
        }
+        if (!file_priv->allowed_master) {
+                ret = drm_new_set_master(dev, file_priv);
+                goto out_unlock;
+        }
        file_priv->minor->master = drm_master_get(file_priv->master);
        file_priv->is_master = 1;
        if (dev->driver->master_set) {
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index c59ce4d0ef75..6b5625e66119 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -126,6 +126,60 @@ static int drm_cpu_valid(void)
 }
 /**
+ * drm_new_set_master - Allocate a new master object and become master for the
+ * associated master realm.
+ *
+ * @dev: The associated device.
+ * @fpriv: File private identifying the client.
+ *
+ * This function must be called with dev::struct_mutex held.
+ * Returns negative error code on failure. Zero on success.
+ */
+int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv)
+{
+        struct drm_master *old_master;
+        int ret;
+        lockdep_assert_held_once(&dev->master_mutex);
+        /* create a new master */
+        fpriv->minor->master = drm_master_create(fpriv->minor);
+        if (!fpriv->minor->master)
+                return -ENOMEM;
+        /* take another reference for the copy in the local file priv */
+        old_master = fpriv->master;
+        fpriv->master = drm_master_get(fpriv->minor->master);
+        if (dev->driver->master_create) {
+                ret = dev->driver->master_create(dev, fpriv->master);
+                if (ret)
+                        goto out_err;
+        }
+        if (dev->driver->master_set) {
+                ret = dev->driver->master_set(dev, fpriv, true);
+                if (ret)
+                        goto out_err;
+        }
+        fpriv->is_master = 1;
+        fpriv->allowed_master = 1;
+        fpriv->authenticated = 1;
+        if (old_master)
+                drm_master_put(&old_master);
+        return 0;
+out_err:
+        /* drop both references and restore old master on failure */
+        drm_master_put(&fpriv->minor->master);
+        drm_master_put(&fpriv->master);
+        fpriv->master = old_master;
+        return ret;
+}
+/**
 * Called whenever a process opens /dev/drm.
 *
 * \param filp file pointer.
@@ -189,35 +243,9 @@ static int drm_open_helper(struct file *filp, struct drm_minor *minor)
        mutex_lock(&dev->master_mutex);
        if (drm_is_primary_client(priv) && !priv->minor->master) {
                /* create a new master */
-                priv->minor->master = drm_master_create(priv->minor);
+                ret = drm_new_set_master(dev, priv);
-                if (!priv->minor->master) {
+                if (ret)
-                        ret = -ENOMEM;
                        goto out_close;
-                }
-                priv->is_master = 1;
-                /* take another reference for the copy in the local file priv */
-                priv->master = drm_master_get(priv->minor->master);
-                priv->authenticated = 1;
-                if (dev->driver->master_create) {
-                        ret = dev->driver->master_create(dev, priv->master);
-                        if (ret) {
-                                /* drop both references if this fails */
-                                drm_master_put(&priv->minor->master);
-                                drm_master_put(&priv->master);
-                                goto out_close;
-                        }
-                }
-                if (dev->driver->master_set) {
-                        ret = dev->driver->master_set(dev, priv, true);
-                        if (ret) {
-                                /* drop both references if this fails */
-                                drm_master_put(&priv->minor->master);
-                                drm_master_put(&priv->master);
-                                goto out_close;
-                        }
-                }
        } else if (drm_is_primary_client(priv)) {
                /* get a reference to the master */
                priv->master = drm_master_get(priv->minor->master);
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 2151ea551d3b..607f493ae801 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -980,7 +980,8 @@ static void send_vblank_event(struct drm_device *dev,
                struct drm_pending_vblank_event *e,
                unsigned long seq, struct timeval *now)
 {
-        WARN_ON_SMP(!spin_is_locked(&dev->event_lock));
+        assert_spin_locked(&dev->event_lock);
        e->event.sequence = seq;
        e->event.tv_sec = now->tv_sec;
        e->event.tv_usec = now->tv_usec;
@@ -993,6 +994,57 @@ static void send_vblank_event(struct drm_device *dev,
 }
 /**
+ * drm_arm_vblank_event - arm vblank event after pageflip
+ * @dev: DRM device
+ * @pipe: CRTC index
+ * @e: the event to prepare to send
+ *
+ * A lot of drivers need to generate vblank events for the very next vblank
+ * interrupt. For example when the page flip interrupt happens when the page
+ * flip gets armed, but not when it actually executes within the next vblank
+ * period. This helper function implements exactly the required vblank arming
+ * behaviour.
+ *
+ * Caller must hold event lock. Caller must also hold a vblank reference for
+ * the event @e, which will be dropped when the next vblank arrives.
+ *
+ * This is the legacy version of drm_crtc_arm_vblank_event().
+ */
+void drm_arm_vblank_event(struct drm_device *dev, unsigned int pipe,
+                          struct drm_pending_vblank_event *e)
+{
+        assert_spin_locked(&dev->event_lock);
+        e->pipe = pipe;
+        e->event.sequence = drm_vblank_count(dev, pipe);
+        list_add_tail(&e->base.link, &dev->vblank_event_list);
+}
+EXPORT_SYMBOL(drm_arm_vblank_event);
+/**
+ * drm_crtc_arm_vblank_event - arm vblank event after pageflip
+ * @crtc: the source CRTC of the vblank event
+ * @e: the event to send
+ *
+ * A lot of drivers need to generate vblank events for the very next vblank
+ * interrupt. For example when the page flip interrupt happens when the page
+ * flip gets armed, but not when it actually executes within the next vblank
+ * period. This helper function implements exactly the required vblank arming
+ * behaviour.
+ *
+ * Caller must hold event lock. Caller must also hold a vblank reference for
+ * the event @e, which will be dropped when the next vblank arrives.
+ *
+ * This is the native KMS version of drm_arm_vblank_event().
+ */
+void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
+                               struct drm_pending_vblank_event *e)
+{
+        drm_arm_vblank_event(crtc->dev, drm_crtc_index(crtc), e);
+}
+EXPORT_SYMBOL(drm_crtc_arm_vblank_event);
+/**
 * drm_send_vblank_event - helper to send vblank event after pageflip
 * @dev: DRM device
 * @pipe: CRTC index
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index a18164f2f6d2..f8b5fcfa91a2 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -229,7 +229,8 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
                mode_flags |= DRM_MODE_FLAG_3D_MASK;
        list_for_each_entry(mode, &connector->modes, head) {
-                mode->status = drm_mode_validate_basic(mode);
+                if (mode->status == MODE_OK)
+                        mode->status = drm_mode_validate_basic(mode);
                if (mode->status == MODE_OK)
                        mode->status = drm_mode_validate_size(mode, maxX, maxY);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index b3ba27fd9a6b..e69357172ffb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -55,6 +55,9 @@ static int exynos_crtc_atomic_check(struct drm_crtc *crtc,
 {
        struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
+        if (!state->enable)
+                return 0;
        if (exynos_crtc->ops->atomic_check)
                return exynos_crtc->ops->atomic_check(exynos_crtc, state);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bdacd44..8aab974b0564 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2734,6 +2734,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
                return "AUX_C";
        case POWER_DOMAIN_AUX_D:
                return "AUX_D";
+        case POWER_DOMAIN_GMBUS:
+                return "GMBUS";
        case POWER_DOMAIN_INIT:
                return "INIT";
        default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95bb27de774f..f4af19a0d569 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -199,6 +199,7 @@ enum intel_display_power_domain {
        POWER_DOMAIN_AUX_B,
        POWER_DOMAIN_AUX_C,
        POWER_DOMAIN_AUX_D,
+        POWER_DOMAIN_GMBUS,
        POWER_DOMAIN_INIT,
        POWER_DOMAIN_NUM,
@@ -2192,8 +2193,17 @@ struct drm_i915_gem_request {
        struct drm_i915_private *i915;
        struct intel_engine_cs *ring;
-        /** GEM sequence number associated with this request. */
+         /** GEM sequence number associated with the previous request,
-        uint32_t seqno;
+          * when the HWS breadcrumb is equal to this the GPU is processing
+          * this request.
+          */
+        u32 previous_seqno;
+         /** GEM sequence number associated with this request,
+          * when the HWS breadcrumb is equal or greater than this the GPU
+          * has finished processing this request.
+          */
+        u32 seqno;
        /** Position in the ringbuffer of the start of the request */
        u32 head;
@@ -2838,6 +2848,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
                  u32 flags);
+void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
 /*
 * BEWARE: Do not use the function below unless you can _absolutely_
@@ -2909,15 +2920,17 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
        return (int32_t)(seq1 - seq2) >= 0;
 }
+static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
+                                           bool lazy_coherency)
+{
+        u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
+        return i915_seqno_passed(seqno, req->previous_seqno);
+}
 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
                                              bool lazy_coherency)
 {
-        u32 seqno;
+        u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
-        BUG_ON(req == NULL);
-        seqno = req->ring->get_seqno(req->ring, lazy_coherency);
        return i915_seqno_passed(seqno, req->seqno);
 }
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 91bb1fc27420..f56af0aaafde 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1146,23 +1146,74 @@ static bool missed_irq(struct drm_i915_private *dev_priv,
        return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
 }
-static int __i915_spin_request(struct drm_i915_gem_request *req)
+static unsigned long local_clock_us(unsigned *cpu)
+{
+        unsigned long t;
+        /* Cheaply and approximately convert from nanoseconds to microseconds.
+         * The result and subsequent calculations are also defined in the same
+         * approximate microseconds units. The principal source of timing
+         * error here is from the simple truncation.
+         *
+         * Note that local_clock() is only defined wrt to the current CPU;
+         * the comparisons are no longer valid if we switch CPUs. Instead of
+         * blocking preemption for the entire busywait, we can detect the CPU
+         * switch and use that as indicator of system load and a reason to
+         * stop busywaiting, see busywait_stop().
+         */
+        *cpu = get_cpu();
+        t = local_clock() >> 10;
+        put_cpu();
+        return t;
+}
+static bool busywait_stop(unsigned long timeout, unsigned cpu)
+{
+        unsigned this_cpu;
+        if (time_after(local_clock_us(&this_cpu), timeout))
+                return true;
+        return this_cpu != cpu;
+}
+static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
 {
        unsigned long timeout;
+        unsigned cpu;
+        /* When waiting for high frequency requests, e.g. during synchronous
+         * rendering split between the CPU and GPU, the finite amount of time
+         * required to set up the irq and wait upon it limits the response
+         * rate. By busywaiting on the request completion for a short while we
+         * can service the high frequency waits as quick as possible. However,
+         * if it is a slow request, we want to sleep as quickly as possible.
+         * The tradeoff between waiting and sleeping is roughly the time it
+         * takes to sleep on a request, on the order of a microsecond.
+         */
-        if (i915_gem_request_get_ring(req)->irq_refcount)
+        if (req->ring->irq_refcount)
                return -EBUSY;
-        timeout = jiffies + 1;
+        /* Only spin if we know the GPU is processing this request */
+        if (!i915_gem_request_started(req, true))
+                return -EAGAIN;
+        timeout = local_clock_us(&cpu) + 5;
        while (!need_resched()) {
                if (i915_gem_request_completed(req, true))
                        return 0;
-                if (time_after_eq(jiffies, timeout))
+                if (signal_pending_state(state, current))
+                        break;
+                if (busywait_stop(timeout, cpu))
                        break;
                cpu_relax_lowlatency();
        }
        if (i915_gem_request_completed(req, false))
                return 0;
@@ -1197,6 +1248,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
        struct drm_i915_private *dev_priv = dev->dev_private;
        const bool irq_test_in_progress =
                ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
+        int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
        DEFINE_WAIT(wait);
        unsigned long timeout_expire;
        s64 before, now;
@@ -1210,8 +1262,16 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
        if (i915_gem_request_completed(req, true))
                return 0;
-        timeout_expire = timeout ?
+        timeout_expire = 0;
-                jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
+        if (timeout) {
+                if (WARN_ON(*timeout < 0))
+                        return -EINVAL;
+                if (*timeout == 0)
+                        return -ETIME;
+                timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
+        }
        if (INTEL_INFO(dev_priv)->gen >= 6)
                gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
@@ -1221,7 +1281,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
        before = ktime_get_raw_ns();
        /* Optimistic spin for the next jiffie before touching IRQs */
-        ret = __i915_spin_request(req);
+        ret = __i915_spin_request(req, state);
        if (ret == 0)
                goto out;
@@ -1233,8 +1293,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
        for (;;) {
                struct timer_list timer;
-                prepare_to_wait(&ring->irq_queue, &wait,
+                prepare_to_wait(&ring->irq_queue, &wait, state);
-                                interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
                /* We need to check whether any gpu reset happened in between
                 * the caller grabbing the seqno and now ... */
@@ -1252,7 +1311,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
                        break;
                }
-                if (interruptible && signal_pending(current)) {
+                if (signal_pending_state(state, current)) {
                        ret = -ERESTARTSYS;
                        break;
                }
@@ -2546,6 +2605,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
        request->batch_obj = obj;
        request->emitted_jiffies = jiffies;
+        request->previous_seqno = ring->last_submitted_seqno;
        ring->last_submitted_seqno = request->seqno;
        list_add_tail(&request->list, &ring->request_list);
@@ -4072,6 +4132,29 @@ i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
        return false;
 }
+void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
+{
+        struct drm_i915_gem_object *obj = vma->obj;
+        bool mappable, fenceable;
+        u32 fence_size, fence_alignment;
+        fence_size = i915_gem_get_gtt_size(obj->base.dev,
+                                           obj->base.size,
+                                           obj->tiling_mode);
+        fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
+                                                     obj->base.size,
+                                                     obj->tiling_mode,
+                                                     true);
+        fenceable = (vma->node.size == fence_size &&
+                     (vma->node.start & (fence_alignment - 1)) == 0);
+        mappable = (vma->node.start + fence_size <=
+                    to_i915(obj->base.dev)->gtt.mappable_end);
+        obj->map_and_fenceable = mappable && fenceable;
+}
 static int
 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
                       struct i915_address_space *vm,
@@ -4139,25 +4222,7 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
        if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
            (bound ^ vma->bound) & GLOBAL_BIND) {
-                bool mappable, fenceable;
+                __i915_vma_set_map_and_fenceable(vma);
-                u32 fence_size, fence_alignment;
-                fence_size = i915_gem_get_gtt_size(obj->base.dev,
-                                                   obj->base.size,
-                                                   obj->tiling_mode);
-                fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
-                                                             obj->base.size,
-                                                             obj->tiling_mode,
-                                                             true);
-                fenceable = (vma->node.size == fence_size &&
-                             (vma->node.start & (fence_alignment - 1)) == 0);
-                mappable = (vma->node.start + fence_size <=
-                            dev_priv->gtt.mappable_end);
-                obj->map_and_fenceable = mappable && fenceable;
                WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
        }
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 8c688a5f1589..02ceb7a4b481 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -141,8 +141,6 @@ static void i915_gem_context_clean(struct intel_context *ctx)
        if (!ppgtt)
                return;
-        WARN_ON(!list_empty(&ppgtt->base.active_list));
        list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
                                 mm_list) {
                if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 40a10b25956c..f010391b87f5 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -642,11 +642,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                }
                /* check for L-shaped memory aka modified enhanced addressing */
-                if (IS_GEN4(dev)) {
+                if (IS_GEN4(dev) &&
-                        uint32_t ddc2 = I915_READ(DCC2);
+                    !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
+                        swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-                        if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
+                        swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-                                dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
                }
                if (dcc == 0xffffffff) {
@@ -675,16 +674,35 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                 * matching, which was the case for the swizzling required in
                 * the table above, or from the 1-ch value being less than
                 * the minimum size of a rank.
+                 *
+                 * Reports indicate that the swizzling actually
+                 * varies depending upon page placement inside the
+                 * channels, i.e. we see swizzled pages where the
+                 * banks of memory are paired and unswizzled on the
+                 * uneven portion, so leave that as unknown.
                 */
-                if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
+                if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
-                        swizzle_x = I915_BIT_6_SWIZZLE_NONE;
-                        swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-                } else {
                        swizzle_x = I915_BIT_6_SWIZZLE_9_10;
                        swizzle_y = I915_BIT_6_SWIZZLE_9;
                }
        }
+        if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
+            swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
+                /* Userspace likes to explode if it sees unknown swizzling,
+                 * so lie. We will finish the lie when reporting through
+                 * the get-tiling-ioctl by reporting the physical swizzle
+                 * mode as unknown instead.
+                 *
+                 * As we don't strictly know what the swizzling is, it may be
+                 * bit17 dependent, and so we need to also prevent the pages
+                 * from being moved.
+                 */
+                dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
+                swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+        }
        dev_priv->mm.bit_6_swizzle_x = swizzle_x;
        dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 43f35d12b677..86c7500454b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2676,6 +2676,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
                        return ret;
                }
                vma->bound |= GLOBAL_BIND;
+                __i915_vma_set_map_and_fenceable(vma);
                list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
        }
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index cdacf3f5b77a..87e919a06b27 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -687,6 +687,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
                }
                vma->bound |= GLOBAL_BIND;
+                __i915_vma_set_map_and_fenceable(vma);
                list_add_tail(&vma->mm_list, &ggtt->inactive_list);
        }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 71860f8680f9..beb0374a19f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -116,6 +116,7 @@ static void skylake_pfit_enable(struct intel_crtc *crtc);
 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 static void intel_modeset_setup_hw_state(struct drm_device *dev);
+static void intel_pre_disable_primary(struct drm_crtc *crtc);
 typedef struct {
        int     min, max;
@@ -2607,6 +2608,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
        struct drm_i915_gem_object *obj;
        struct drm_plane *primary = intel_crtc->base.primary;
        struct drm_plane_state *plane_state = primary->state;
+        struct drm_crtc_state *crtc_state = intel_crtc->base.state;
+        struct intel_plane *intel_plane = to_intel_plane(primary);
        struct drm_framebuffer *fb;
        if (!plane_config->fb)
@@ -2643,6 +2646,18 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
                }
        }
+        /*
+         * We've failed to reconstruct the BIOS FB.  Current display state
+         * indicates that the primary plane is visible, but has a NULL FB,
+         * which will lead to problems later if we don't fix it up.  The
+         * simplest solution is to just disable the primary plane now and
+         * pretend the BIOS never had it enabled.
+         */
+        to_intel_plane_state(plane_state)->visible = false;
+        crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
+        intel_pre_disable_primary(&intel_crtc->base);
+        intel_plane->disable_plane(primary, &intel_crtc->base);
        return;
 valid_fb:
@@ -5194,11 +5209,31 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
        case PORT_E:
                return POWER_DOMAIN_PORT_DDI_E_2_LANES;
        default:
-                WARN_ON_ONCE(1);
+                MISSING_CASE(port);
                return POWER_DOMAIN_PORT_OTHER;
        }
 }
+static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
+{
+        switch (port) {
+        case PORT_A:
+                return POWER_DOMAIN_AUX_A;
+        case PORT_B:
+                return POWER_DOMAIN_AUX_B;
+        case PORT_C:
+                return POWER_DOMAIN_AUX_C;
+        case PORT_D:
+                return POWER_DOMAIN_AUX_D;
+        case PORT_E:
+                /* FIXME: Check VBT for actual wiring of PORT E */
+                return POWER_DOMAIN_AUX_D;
+        default:
+                MISSING_CASE(port);
+                return POWER_DOMAIN_AUX_A;
+        }
+}
 #define for_each_power_domain(domain, mask)                             \
        for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
                if ((1 << (domain)) & (mask))
@@ -5230,6 +5265,36 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
        }
 }
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
+{
+        struct drm_device *dev = intel_encoder->base.dev;
+        struct intel_digital_port *intel_dig_port;
+        switch (intel_encoder->type) {
+        case INTEL_OUTPUT_UNKNOWN:
+        case INTEL_OUTPUT_HDMI:
+                /*
+                 * Only DDI platforms should ever use these output types.
+                 * We can get here after the HDMI detect code has already set
+                 * the type of the shared encoder. Since we can't be sure
+                 * what's the status of the given connectors, play safe and
+                 * run the DP detection too.
+                 */
+                WARN_ON_ONCE(!HAS_DDI(dev));
+        case INTEL_OUTPUT_DISPLAYPORT:
+        case INTEL_OUTPUT_EDP:
+                intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+                return port_to_aux_power_domain(intel_dig_port->port);
+        case INTEL_OUTPUT_DP_MST:
+                intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
+                return port_to_aux_power_domain(intel_dig_port->port);
+        default:
+                MISSING_CASE(intel_encoder->type);
+                return POWER_DOMAIN_AUX_A;
+        }
+}
 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
@@ -6259,9 +6324,11 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
        if (to_intel_plane_state(crtc->primary->state)->visible) {
                intel_crtc_wait_for_pending_flips(crtc);
                intel_pre_disable_primary(crtc);
+                intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
+                to_intel_plane_state(crtc->primary->state)->visible = false;
        }
-        intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
        dev_priv->display.crtc_disable(crtc);
        intel_crtc->active = false;
        intel_update_watermarks(crtc);
@@ -9858,14 +9925,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
        return true;
 }
-static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
+static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        uint32_t cntl = 0, size = 0;
-        if (base) {
+        if (on) {
                unsigned int width = intel_crtc->base.cursor->state->crtc_w;
                unsigned int height = intel_crtc->base.cursor->state->crtc_h;
                unsigned int stride = roundup_pow_of_two(width) * 4;
@@ -9920,16 +9987,15 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
        }
 }
-static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
+static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
-        uint32_t cntl;
+        uint32_t cntl = 0;
-        cntl = 0;
+        if (on) {
-        if (base) {
                cntl = MCURSOR_GAMMA_ENABLE;
                switch (intel_crtc->base.cursor->state->crtc_w) {
                        case 64:
@@ -9980,18 +10046,17 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        int y = cursor_state->crtc_y;
        u32 base = 0, pos = 0;
-        if (on)
+        base = intel_crtc->cursor_addr;
-                base = intel_crtc->cursor_addr;
        if (x >= intel_crtc->config->pipe_src_w)
-                base = 0;
+                on = false;
        if (y >= intel_crtc->config->pipe_src_h)
-                base = 0;
+                on = false;
        if (x < 0) {
                if (x + cursor_state->crtc_w <= 0)
-                        base = 0;
+                        on = false;
                pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
                x = -x;
@@ -10000,16 +10065,13 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        if (y < 0) {
                if (y + cursor_state->crtc_h <= 0)
-                        base = 0;
+                        on = false;
                pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
                y = -y;
        }
        pos |= y << CURSOR_Y_SHIFT;
-        if (base == 0 && intel_crtc->cursor_base == 0)
-                return;
        I915_WRITE(CURPOS(pipe), pos);
        /* ILK+ do this automagically */
@@ -10020,9 +10082,9 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        }
        if (IS_845G(dev) || IS_I865G(dev))
-                i845_update_cursor(crtc, base);
+                i845_update_cursor(crtc, base, on);
        else
-                i9xx_update_cursor(crtc, base);
+                i9xx_update_cursor(crtc, base, on);
 }
 static bool cursor_size_ok(struct drm_device *dev,
@@ -12460,7 +12522,6 @@ intel_pipe_config_compare(struct drm_device *dev,
        if (INTEL_INFO(dev)->gen < 8) {
                PIPE_CONF_CHECK_M_N(dp_m_n);
-                PIPE_CONF_CHECK_I(has_drrs);
                if (current_config->has_drrs)
                        PIPE_CONF_CHECK_M_N(dp_m2_n2);
        } else
@@ -13667,6 +13728,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
        struct drm_crtc *crtc = crtc_state->base.crtc;
        struct drm_framebuffer *fb = state->base.fb;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+        enum pipe pipe = to_intel_plane(plane)->pipe;
        unsigned stride;
        int ret;
@@ -13700,6 +13762,22 @@ intel_check_cursor_plane(struct drm_plane *plane,
                return -EINVAL;
        }
+        /*
+         * There's something wrong with the cursor on CHV pipe C.
+         * If it straddles the left edge of the screen then
+         * moving it away from the edge or disabling it often
+         * results in a pipe underrun, and often that can lead to
+         * dead pipe (constant underrun reported, and it scans
+         * out just a solid color). To recover from that, the
+         * display power well must be turned off and on again.
+         * Refuse the put the cursor into that compromised position.
+         */
+        if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
+            state->visible && state->base.crtc_x < 0) {
+                DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
+                return -EINVAL;
+        }
        return 0;
 }
@@ -13723,9 +13801,6 @@ intel_commit_cursor_plane(struct drm_plane *plane,
        crtc = crtc ? crtc : plane->crtc;
        intel_crtc = to_intel_crtc(crtc);
-        if (intel_crtc->cursor_bo == obj)
-                goto update;
        if (!obj)
                addr = 0;
        else if (!INTEL_INFO(dev)->cursor_needs_physical)
@@ -13734,9 +13809,7 @@ intel_commit_cursor_plane(struct drm_plane *plane,
                addr = obj->phys_handle->busaddr;
        intel_crtc->cursor_addr = addr;
-        intel_crtc->cursor_bo = obj;
-update:
        if (crtc->state->active)
                intel_crtc_update_cursor(crtc, state->visible);
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 09bdd94ca3ba..78b8ec84d576 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
         * See vlv_power_sequencer_reset() why we need
         * a power domain reference here.
         */
-        power_domain = intel_display_port_power_domain(encoder);
+        power_domain = intel_display_port_aux_power_domain(encoder);
        intel_display_power_get(dev_priv, power_domain);
        mutex_lock(&dev_priv->pps_mutex);
@@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
        mutex_unlock(&dev_priv->pps_mutex);
-        power_domain = intel_display_port_power_domain(encoder);
+        power_domain = intel_display_port_aux_power_domain(encoder);
        intel_display_power_put(dev_priv, power_domain);
 }
@@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
        intel_dp_check_edp(intel_dp);
-        intel_aux_display_runtime_get(dev_priv);
        /* Try to wait for any previous AUX channel activity */
        for (try = 0; try < 3; try++) {
                status = I915_READ_NOTRACE(ch_ctl);
@@ -926,7 +924,6 @@ done:
        ret = recv_bytes;
 out:
        pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-        intel_aux_display_runtime_put(dev_priv);
        if (vdd)
                edp_panel_vdd_off(intel_dp, false);
@@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
        if (edp_have_panel_vdd(intel_dp))
                return need_to_disable;
-        power_domain = intel_display_port_power_domain(intel_encoder);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_get(dev_priv, power_domain);
        DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
@@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
        if ((pp & POWER_TARGET_ON) == 0)
                intel_dp->last_power_cycle = jiffies;
-        power_domain = intel_display_port_power_domain(intel_encoder);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_put(dev_priv, power_domain);
 }
@@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
        wait_panel_off(intel_dp);
        /* We got a reference when we enabled the VDD. */
-        power_domain = intel_display_port_power_domain(intel_encoder);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_put(dev_priv, power_domain);
 }
@@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
        intel_dp->has_audio = false;
 }
-static enum intel_display_power_domain
-intel_dp_power_get(struct intel_dp *dp)
-{
-        struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
-        enum intel_display_power_domain power_domain;
-        power_domain = intel_display_port_power_domain(encoder);
-        intel_display_power_get(to_i915(encoder->base.dev), power_domain);
-        return power_domain;
-}
-static void
-intel_dp_power_put(struct intel_dp *dp,
-                   enum intel_display_power_domain power_domain)
-{
-        struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
-        intel_display_power_put(to_i915(encoder->base.dev), power_domain);
-}
 static enum drm_connector_status
 intel_dp_detect(struct drm_connector *connector, bool force)
 {
@@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector *connector, bool force)
                return connector_status_disconnected;
        }
-        power_domain = intel_dp_power_get(intel_dp);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
+        intel_display_power_get(to_i915(dev), power_domain);
        /* Can't disconnect eDP, but you can close the lid... */
        if (is_edp(intel_dp))
@@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
        }
 out:
-        intel_dp_power_put(intel_dp, power_domain);
+        intel_display_power_put(to_i915(dev), power_domain);
        return status;
 }
@@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
 {
        struct intel_dp *intel_dp = intel_attached_dp(connector);
        struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+        struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
        enum intel_display_power_domain power_domain;
        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
@@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector *connector)
        if (connector->status != connector_status_connected)
                return;
-        power_domain = intel_dp_power_get(intel_dp);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
+        intel_display_power_get(dev_priv, power_domain);
        intel_dp_set_edid(intel_dp);
-        intel_dp_power_put(intel_dp, power_domain);
+        intel_display_power_put(dev_priv, power_domain);
        if (intel_encoder->type != INTEL_OUTPUT_EDP)
                intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
@@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
         * indefinitely.
         */
        DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
-        power_domain = intel_display_port_power_domain(&intel_dig_port->base);
+        power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
        intel_display_power_get(dev_priv, power_domain);
        edp_panel_vdd_schedule_off(intel_dp);
@@ -5153,7 +5133,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
        enum intel_display_power_domain power_domain;
        enum irqreturn ret = IRQ_NONE;
-        if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
+        if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
+            intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
                intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
        if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
@@ -5172,7 +5153,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
                      port_name(intel_dig_port->port),
                      long_hpd ? "long" : "short");
-        power_domain = intel_display_port_power_domain(intel_encoder);
+        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_get(dev_priv, power_domain);
        if (long_hpd) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0598932ce623..0d00f07b7163 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -550,7 +550,6 @@ struct intel_crtc {
        int adjusted_x;
        int adjusted_y;
-        struct drm_i915_gem_object *cursor_bo;
        uint32_t cursor_addr;
        uint32_t cursor_cntl;
        uint32_t cursor_size;
@@ -1169,6 +1168,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
 void hsw_disable_ips(struct intel_crtc *crtc);
 enum intel_display_power_domain
 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
                                 struct intel_crtc_state *pipe_config);
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
@@ -1377,8 +1378,6 @@ void intel_display_power_get(struct drm_i915_private *dev_priv,
                             enum intel_display_power_domain domain);
 void intel_display_power_put(struct drm_i915_private *dev_priv,
                             enum intel_display_power_domain domain);
-void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
-void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9eafa191cee2..64086f2d4e26 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1335,21 +1335,17 @@ intel_hdmi_set_edid(struct drm_connector *connector, bool force)
 {
        struct drm_i915_private *dev_priv = to_i915(connector->dev);
        struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
-        struct intel_encoder *intel_encoder =
-                &hdmi_to_dig_port(intel_hdmi)->base;
-        enum intel_display_power_domain power_domain;
        struct edid *edid = NULL;
        bool connected = false;
-        power_domain = intel_display_port_power_domain(intel_encoder);
+        intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
-        intel_display_power_get(dev_priv, power_domain);
        if (force)
                edid = drm_get_edid(connector,
                                    intel_gmbus_get_adapter(dev_priv,
                                    intel_hdmi->ddc_bus));
-        intel_display_power_put(dev_priv, power_domain);
+        intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
        to_intel_connector(connector)->detect_edid = edid;
        if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
@@ -1378,15 +1374,18 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
        struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
        struct drm_i915_private *dev_priv = to_i915(connector->dev);
        bool live_status = false;
-        unsigned int retry = 3;
+        unsigned int try;
        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
                      connector->base.id, connector->name);
-        while (!live_status && --retry) {
+        intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
+        for (try = 0; !live_status && try < 4; try++) {
+                if (try)
+                        msleep(10);
                live_status = intel_digital_port_connected(dev_priv,
                                hdmi_to_dig_port(intel_hdmi));
-                mdelay(10);
        }
        if (!live_status)
@@ -1402,6 +1401,8 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
        } else
                status = connector_status_disconnected;
+        intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
        return status;
 }
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1369fc41d039..8324654037b6 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -483,7 +483,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
        int i = 0, inc, try = 0;
        int ret = 0;
-        intel_aux_display_runtime_get(dev_priv);
+        intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
        mutex_lock(&dev_priv->gmbus_mutex);
        if (bus->force_bit) {
@@ -595,7 +595,9 @@ timeout:
 out:
        mutex_unlock(&dev_priv->gmbus_mutex);
-        intel_aux_display_runtime_put(dev_priv);
+        intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
        return ret;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 071a76b9ac52..f091ad12d694 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4782,8 +4782,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
        /* 2b: Program RC6 thresholds.*/
        /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
-        if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
+        if (IS_SKYLAKE(dev))
-                                 (INTEL_REVID(dev) <= SKL_REVID_E0)))
                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
        else
                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
@@ -4825,7 +4824,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
         * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
         */
        if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
-            ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+            ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
                I915_WRITE(GEN9_PG_ENABLE, 0);
        else
                I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d89c1d0aa1b7..7e23d65c9b24 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -362,6 +362,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
        BIT(POWER_DOMAIN_AUX_C) |                       \
        BIT(POWER_DOMAIN_AUDIO) |                       \
        BIT(POWER_DOMAIN_VGA) |                         \
+        BIT(POWER_DOMAIN_GMBUS) |                       \
        BIT(POWER_DOMAIN_INIT))
 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
        BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
@@ -1483,6 +1484,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        BIT(POWER_DOMAIN_AUX_B) |                       \
        BIT(POWER_DOMAIN_AUX_C) |                       \
        BIT(POWER_DOMAIN_AUX_D) |                       \
+        BIT(POWER_DOMAIN_GMBUS) |                       \
        BIT(POWER_DOMAIN_INIT))
 #define HSW_DISPLAY_POWER_DOMAINS (                             \
        (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
@@ -1845,6 +1847,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
        i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
                                                     i915.disable_power_well);
+        BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
        mutex_init(&power_domains->lock);
        /*
@@ -2064,36 +2068,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
 }
 /**
- * intel_aux_display_runtime_get - grab an auxiliary power domain reference
- * @dev_priv: i915 device instance
- *
- * This function grabs a power domain reference for the auxiliary power domain
- * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
- * parents are powered up. Therefore users should only grab a reference to the
- * innermost power domain they need.
- *
- * Any power domain reference obtained by this function must have a symmetric
- * call to intel_aux_display_runtime_put() to release the reference again.
- */
-void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
-{
-        intel_runtime_pm_get(dev_priv);
-}
-/**
- * intel_aux_display_runtime_put - release an auxiliary power domain reference
- * @dev_priv: i915 device instance
- *
- * This function drops the auxiliary power domain reference obtained by
- * intel_aux_display_runtime_get() and might power down the corresponding
- * hardware block right away if this is the last reference.
- */
-void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
-{
-        intel_runtime_pm_put(dev_priv);
-}
-/**
 * intel_runtime_pm_get - grab a runtime pm reference
 * @dev_priv: i915 device instance
 *
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index 64f16ea779ef..7b990b4e96d2 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -63,8 +63,7 @@ static void imx_drm_driver_lastclose(struct drm_device *drm)
 #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
        struct imx_drm_device *imxdrm = drm->dev_private;
-        if (imxdrm->fbhelper)
+        drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
-                drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
 #endif
 }
@@ -340,7 +339,7 @@ err_kms:
 * imx_drm_add_crtc - add a new crtc
 */
 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
-                struct imx_drm_crtc **new_crtc,
+                struct imx_drm_crtc **new_crtc, struct drm_plane *primary_plane,
                const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs,
                struct device_node *port)
 {
@@ -379,7 +378,7 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
        drm_crtc_helper_add(crtc,
                        imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
-        drm_crtc_init(drm, crtc,
+        drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
                        imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
        return 0;
diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h
index 28e776d8d9d2..83284b4d4be1 100644
--- a/drivers/gpu/drm/imx/imx-drm.h
+++ b/drivers/gpu/drm/imx/imx-drm.h
@@ -9,6 +9,7 @@ struct drm_display_mode;
 struct drm_encoder;
 struct drm_fbdev_cma;
 struct drm_framebuffer;
+struct drm_plane;
 struct imx_drm_crtc;
 struct platform_device;
@@ -24,7 +25,7 @@ struct imx_drm_crtc_helper_funcs {
 };
 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
-                struct imx_drm_crtc **new_crtc,
+                struct imx_drm_crtc **new_crtc, struct drm_plane *primary_plane,
                const struct imx_drm_crtc_helper_funcs *imx_helper_funcs,
                struct device_node *port);
 int imx_drm_remove_crtc(struct imx_drm_crtc *);
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index e671ad369416..f9597146dc67 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -721,6 +721,7 @@ static const struct of_device_id imx_tve_dt_ids[] = {
        { .compatible = "fsl,imx53-tve", },
        { /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
 static struct platform_driver imx_tve_driver = {
        .probe          = imx_tve_probe,
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 7bc8301fafff..4ab841eebee1 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -212,7 +212,8 @@ static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
        spin_lock_irqsave(&drm->event_lock, flags);
        if (ipu_crtc->page_flip_event)
-                drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
+                drm_crtc_send_vblank_event(&ipu_crtc->base,
+                                           ipu_crtc->page_flip_event);
        ipu_crtc->page_flip_event = NULL;
        imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
        spin_unlock_irqrestore(&drm->event_lock, flags);
@@ -349,7 +350,6 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
        struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
        int dp = -EINVAL;
        int ret;
-        int id;
        ret = ipu_get_resources(ipu_crtc, pdata);
        if (ret) {
@@ -358,18 +358,23 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
                return ret;
        }
+        if (pdata->dp >= 0)
+                dp = IPU_DP_FLOW_SYNC_BG;
+        ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
+                                            DRM_PLANE_TYPE_PRIMARY);
+        if (IS_ERR(ipu_crtc->plane[0])) {
+                ret = PTR_ERR(ipu_crtc->plane[0]);
+                goto err_put_resources;
+        }
        ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
-                        &ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
+                        &ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs,
+                        ipu_crtc->dev->of_node);
        if (ret) {
                dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
                goto err_put_resources;
        }
-        if (pdata->dp >= 0)
-                dp = IPU_DP_FLOW_SYNC_BG;
-        id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
-        ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
-                                            pdata->dma[0], dp, BIT(id), true);
        ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
        if (ret) {
                dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
@@ -379,10 +384,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
        /* If this crtc is using the DP, add an overlay plane */
        if (pdata->dp >= 0 && pdata->dma[1] > 0) {
-                ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
+                ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
-                                                    pdata->dma[1],
+                                                IPU_DP_FLOW_SYNC_FG,
-                                                    IPU_DP_FLOW_SYNC_FG,
+                                                drm_crtc_mask(&ipu_crtc->base),
-                                                    BIT(id), false);
+                                                DRM_PLANE_TYPE_OVERLAY);
                if (IS_ERR(ipu_crtc->plane[1]))
                        ipu_crtc->plane[1] = NULL;
        }
@@ -407,28 +412,6 @@ err_put_resources:
        return ret;
 }
-static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent,
-                                                  int port_id)
-{
-        struct device_node *port;
-        int id, ret;
-        port = of_get_child_by_name(parent, "port");
-        while (port) {
-                ret = of_property_read_u32(port, "reg", &id);
-                if (!ret && id == port_id)
-                        return port;
-                do {
-                        port = of_get_next_child(parent, port);
-                        if (!port)
-                                return NULL;
-                } while (of_node_cmp(port->name, "port"));
-        }
-        return NULL;
-}
 static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
 {
        struct ipu_client_platformdata *pdata = dev->platform_data;
@@ -470,23 +453,11 @@ static const struct component_ops ipu_crtc_ops = {
 static int ipu_drm_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
-        struct ipu_client_platformdata *pdata = dev->platform_data;
        int ret;
        if (!dev->platform_data)
                return -EINVAL;
-        if (!dev->of_node) {
-                /* Associate crtc device with the corresponding DI port node */
-                dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
-                                                      pdata->di + 2);
-                if (!dev->of_node) {
-                        dev_err(dev, "missing port@%d node in %s\n",
-                                pdata->di + 2, dev->parent->of_node->full_name);
-                        return -ENODEV;
-                }
-        }
        ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
        if (ret)
                return ret;
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 575f4c84388f..e2ff410bab74 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -381,7 +381,7 @@ static struct drm_plane_funcs ipu_plane_funcs = {
 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
                                 int dma, int dp, unsigned int possible_crtcs,
-                                 bool priv)
+                                 enum drm_plane_type type)
 {
        struct ipu_plane *ipu_plane;
        int ret;
@@ -399,10 +399,9 @@ struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
        ipu_plane->dma = dma;
        ipu_plane->dp_flow = dp;
-        ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
+        ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
-                             &ipu_plane_funcs, ipu_plane_formats,
+                                       &ipu_plane_funcs, ipu_plane_formats,
-                             ARRAY_SIZE(ipu_plane_formats),
+                                       ARRAY_SIZE(ipu_plane_formats), type);
-                             priv);
        if (ret) {
                DRM_ERROR("failed to initialize plane\n");
                kfree(ipu_plane);
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.h b/drivers/gpu/drm/imx/ipuv3-plane.h
index 9b5eff18f5b8..3a443b413c60 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.h
+++ b/drivers/gpu/drm/imx/ipuv3-plane.h
@@ -34,7 +34,7 @@ struct ipu_plane {
 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
                                 int dma, int dp, unsigned int possible_crtcs,
-                                 bool priv);
+                                 enum drm_plane_type type);
 /* Init IDMAC, DMFC, DP */
 int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index b4deb9cf9d71..2e9b9f1b5cd2 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -54,7 +54,11 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
        if (imxpd->panel && imxpd->panel->funcs &&
            imxpd->panel->funcs->get_modes) {
+                struct drm_display_info *di = &connector->display_info;
                num_modes = imxpd->panel->funcs->get_modes(imxpd->panel);
+                if (!imxpd->bus_format && di->num_bus_formats)
+                        imxpd->bus_format = di->bus_formats[0];
                if (num_modes > 0)
                        return num_modes;
        }
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 8f760002e401..913192c94876 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -159,7 +159,6 @@ struct nvkm_device_func {
 struct nvkm_device_quirk {
        u8 tv_pin_mask;
        u8 tv_gpio;
-        bool War00C800_0;
 };
 struct nvkm_device_chip {
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
index 28bc202f9753..40f845e31272 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
@@ -7,6 +7,7 @@ struct nvkm_instmem {
        const struct nvkm_instmem_func *func;
        struct nvkm_subdev subdev;
+        spinlock_t lock;
        struct list_head list;
        u32 reserved;
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 8b8332e46f24..d5e6938cc6bc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -367,6 +367,7 @@ static int nouveau_rom_call(acpi_handle rom_handle, uint8_t *bios,
                return -ENODEV;
        }
        obj = (union acpi_object *)buffer.pointer;
+        len = min(len, (int)obj->buffer.length);
        memcpy(bios+offset, obj->buffer.pointer, len);
        kfree(buffer.pointer);
        return len;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index db6bc6760545..64c8d932d5f1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -829,7 +829,6 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
        struct drm_device *dev = drm->dev;
        struct nouveau_page_flip_state *s;
        unsigned long flags;
-        int crtcid = -1;
        spin_lock_irqsave(&dev->event_lock, flags);
@@ -841,15 +840,19 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
        s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
        if (s->event) {
-                /* Vblank timestamps/counts are only correct on >= NV-50 */
+                if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
-                if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
+                        drm_arm_vblank_event(dev, s->crtc, s->event);
-                        crtcid = s->crtc;
+                } else {
+                        drm_send_vblank_event(dev, s->crtc, s->event);
-                drm_send_vblank_event(dev, crtcid, s->event);
+                        /* Give up ownership of vblank for page-flipped crtc */
+                        drm_vblank_put(dev, s->crtc);
+                }
+        }
+        else {
+                /* Give up ownership of vblank for page-flipped crtc */
+                drm_vblank_put(dev, s->crtc);
        }
-        /* Give up ownership of vblank for page-flipped crtc */
-        drm_vblank_put(dev, s->crtc);
        list_del(&s->head);
        if (ps)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index 3050042e6c6d..a02813e994ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -39,6 +39,7 @@
 #include <nvif/client.h>
 #include <nvif/device.h>
+#include <nvif/ioctl.h>
 #include <drmP.h>
@@ -65,9 +66,10 @@ struct nouveau_drm_tile {
 };
 enum nouveau_drm_object_route {
-        NVDRM_OBJECT_NVIF = 0,
+        NVDRM_OBJECT_NVIF = NVIF_IOCTL_V0_OWNER_NVIF,
        NVDRM_OBJECT_USIF,
        NVDRM_OBJECT_ABI16,
+        NVDRM_OBJECT_ANY = NVIF_IOCTL_V0_OWNER_ANY,
 };
 enum nouveau_drm_notify_route {
diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c
index 89dc4ce63490..6ae1b3494bcd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_usif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_usif.c
@@ -313,7 +313,10 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc)
        if (nvif_unpack(argv->v0, 0, 0, true)) {
                /* block access to objects not created via this interface */
                owner = argv->v0.owner;
-                argv->v0.owner = NVDRM_OBJECT_USIF;
+                if (argv->v0.object == 0ULL)
+                        argv->v0.owner = NVDRM_OBJECT_ANY; /* except client */
+                else
+                        argv->v0.owner = NVDRM_OBJECT_USIF;
        } else
                goto done;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
index e3c783d0e2ab..62ad0300cfa5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
@@ -259,12 +259,6 @@ nvkm_device_pci_10de_0df4[] = {
 };
 static const struct nvkm_device_pci_vendor
-nvkm_device_pci_10de_0fcd[] = {
-        { 0x17aa, 0x3801, NULL, { .War00C800_0 = true } }, /* Lenovo Y510P */
-        {}
-};
-static const struct nvkm_device_pci_vendor
 nvkm_device_pci_10de_0fd2[] = {
        { 0x1028, 0x0595, "GeForce GT 640M LE" },
        { 0x1028, 0x05b2, "GeForce GT 640M LE" },
@@ -684,7 +678,6 @@ nvkm_device_pci_10de_1189[] = {
 static const struct nvkm_device_pci_vendor
 nvkm_device_pci_10de_1199[] = {
        { 0x1458, 0xd001, "GeForce GTX 760" },
-        { 0x1462, 0x1106, "GeForce GTX 780M", { .War00C800_0 = true } }, /* Medion Erazer X7827 */
        {}
 };
@@ -695,14 +688,6 @@ nvkm_device_pci_10de_11e3[] = {
 };
 static const struct nvkm_device_pci_vendor
-nvkm_device_pci_10de_11fc[] = {
-        { 0x1179, 0x0001, NULL, { .War00C800_0 = true } }, /* Toshiba Tecra W50 */
-        { 0x17aa, 0x2211, NULL, { .War00C800_0 = true } }, /* Lenovo W541 */
-        { 0x17aa, 0x221e, NULL, { .War00C800_0 = true } }, /* Lenovo W541 */
-        {}
-};
-static const struct nvkm_device_pci_vendor
 nvkm_device_pci_10de_1247[] = {
        { 0x1043, 0x212a, "GeForce GT 635M" },
        { 0x1043, 0x212b, "GeForce GT 635M" },
@@ -1356,7 +1341,7 @@ nvkm_device_pci_10de[] = {
        { 0x0fc6, "GeForce GTX 650" },
        { 0x0fc8, "GeForce GT 740" },
        { 0x0fc9, "GeForce GT 730" },
-        { 0x0fcd, "GeForce GT 755M", nvkm_device_pci_10de_0fcd },
+        { 0x0fcd, "GeForce GT 755M" },
        { 0x0fce, "GeForce GT 640M LE" },
        { 0x0fd1, "GeForce GT 650M" },
        { 0x0fd2, "GeForce GT 640M", nvkm_device_pci_10de_0fd2 },
@@ -1490,7 +1475,7 @@ nvkm_device_pci_10de[] = {
        { 0x11e2, "GeForce GTX 765M" },
        { 0x11e3, "GeForce GTX 760M", nvkm_device_pci_10de_11e3 },
        { 0x11fa, "Quadro K4000" },
-        { 0x11fc, "Quadro K2100M", nvkm_device_pci_10de_11fc },
+        { 0x11fc, "Quadro K2100M" },
        { 0x1200, "GeForce GTX 560 Ti" },
        { 0x1201, "GeForce GTX 560" },
        { 0x1203, "GeForce GTX 460 SE v2" },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
index b5b875928aba..74de7a96c22a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
@@ -207,6 +207,8 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info)
                        const u32 b =  beta * gr->ppc_tpc_nr[gpc][ppc];
                        const u32 t = timeslice_mode;
                        const u32 o = PPC_UNIT(gpc, ppc, 0);
+                        if (!(gr->ppc_mask[gpc] & (1 << ppc)))
+                                continue;
                        mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
                        mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
                        bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
index 194afe910d21..7dacb3cc0668 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
@@ -52,10 +52,12 @@ mmio_list_base:
 #endif
 #ifdef INCLUDE_CODE
+#define gpc_addr(reg,addr)                                                    /*
+*/      imm32(reg,addr)                                                       /*
+*/      or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
 #define gpc_wr32(addr,reg)                                                    /*
+*/      gpc_addr($r14,addr)                                                   /*
 */      mov b32 $r15 reg                                                      /*
-*/      imm32($r14, addr)                                                     /*
-*/      or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE                    /*
 */      call(nv_wr32)
 // reports an exception to the host
@@ -161,7 +163,7 @@ init:
 #if NV_PGRAPH_GPCX_UNK__SIZE > 0
        // figure out which, and how many, UNKs are actually present
-        imm32($r14, 0x500c30)
+        gpc_addr($r14, 0x500c30)
        clear b32 $r2
        clear b32 $r3
        clear b32 $r4
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
index 64d07df4b8b1..bb820ff28621 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gf117_grgpc_code[] = {
        0x03f01200,
        0x0002d000,
        0x17f104bd,
-        0x10fe0542,
+        0x10fe0545,
        0x0007f100,
        0x0003f007,
        0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gf117_grgpc_code[] = {
        0x02d00103,
        0xf104bd00,
        0xf00c30e7,
-        0x24bd50e3,
+        0xe5f050e3,
-        0x44bd34bd,
+        0xbd24bd01,
-/* 0x0430: init_unk_loop */
+/* 0x0433: init_unk_loop */
-        0xb06821f4,
+        0xf444bd34,
-        0x0bf400f6,
+        0xf6b06821,
-        0x01f7f00f,
+        0x0f0bf400,
-        0xfd04f2bb,
+        0xbb01f7f0,
-        0x30b6054f,
+        0x4ffd04f2,
-/* 0x0445: init_unk_next */
+        0x0130b605,
-        0x0120b601,
+/* 0x0448: init_unk_next */
-        0xb004e0b6,
+        0xb60120b6,
-        0x1bf40126,
+        0x26b004e0,
-/* 0x0451: init_unk_done */
+        0xe21bf401,
-        0x070380e2,
+/* 0x0454: init_unk_done */
-        0xf1080480,
+        0x80070380,
-        0xf0010027,
+        0x27f10804,
-        0x22cf0223,
+        0x23f00100,
-        0x9534bd00,
+        0x0022cf02,
-        0x07f10825,
+        0x259534bd,
-        0x03f0c000,
+        0x0007f108,
-        0x0005d001,
+        0x0103f0c0,
-        0x07f104bd,
+        0xbd0005d0,
-        0x03f0c100,
+        0x0007f104,
-        0x0005d001,
+        0x0103f0c1,
-        0x0e9804bd,
+        0xbd0005d0,
-        0x010f9800,
+        0x000e9804,
-        0x015021f5,
+        0xf5010f98,
-        0xbb002fbb,
+        0xbb015021,
-        0x0e98003f,
+        0x3fbb002f,
-        0x020f9801,
+        0x010e9800,
-        0x015021f5,
+        0xf5020f98,
-        0xfd050e98,
+        0x98015021,
-        0x2ebb00ef,
+        0xeffd050e,
-        0x003ebb00,
+        0x002ebb00,
-        0x98020e98,
+        0x98003ebb,
-        0x21f5030f,
+        0x0f98020e,
-        0x0e980150,
+        0x5021f503,
-        0x00effd07,
+        0x070e9801,
-        0xbb002ebb,
+        0xbb00effd,
-        0x35b6003e,
+        0x3ebb002e,
-        0x0007f102,
+        0x0235b600,
-        0x0103f0d3,
+        0xd30007f1,
-        0xbd0003d0,
+        0xd00103f0,
-        0x0825b604,
-        0xb60635b6,
-        0x30b60120,
-        0x0824b601,
-        0xb90834b6,
-        0x21f5022f,
-        0x2fbb02d3,
-        0x003fbb00,
-        0x010007f1,
-        0xd00203f0,
        0x04bd0003,
-        0x29f024bd,
+        0xb60825b6,
-        0x0007f11f,
+        0x20b60635,
-        0x0203f008,
+        0x0130b601,
-        0xbd0002d0,
+        0xb60824b6,
-/* 0x0505: main */
+        0x2fb90834,
-        0x0031f404,
+        0xd321f502,
-        0xf00028f4,
+        0x002fbb02,
-        0x21f424d7,
+        0xf1003fbb,
-        0xf401f439,
+        0xf0010007,
-        0xf404e4b0,
+        0x03d00203,
-        0x81fe1e18,
+        0xbd04bd00,
-        0x0627f001,
+        0x1f29f024,
-        0x12fd20bd,
+        0x080007f1,
-        0x01e4b604,
+        0xd00203f0,
-        0xfe051efd,
+        0x04bd0002,
-        0x21f50018,
+/* 0x0508: main */
-        0x0ef405fa,
+        0xf40031f4,
-/* 0x0535: main_not_ctx_xfer */
+        0xd7f00028,
-        0x10ef94d3,
+        0x3921f424,
-        0xf501f5f0,
+        0xb0f401f4,
-        0xf4037e21,
+        0x18f404e4,
-/* 0x0542: ih */
+        0x0181fe1e,
-        0x80f9c60e,
+        0xbd0627f0,
-        0xf90188fe,
+        0x0412fd20,
-        0xf990f980,
+        0xfd01e4b6,
-        0xf9b0f9a0,
+        0x18fe051e,
-        0xf9e0f9d0,
+        0xfd21f500,
-        0xf104bdf0,
+        0xd30ef405,
-        0xf00200a7,
+/* 0x0538: main_not_ctx_xfer */
-        0xaacf00a3,
+        0xf010ef94,
-        0x04abc400,
+        0x21f501f5,
-        0xf02c0bf4,
+        0x0ef4037e,
-        0xe7f124d7,
+/* 0x0545: ih */
-        0xe3f01a00,
+        0xfe80f9c6,
-        0x00eecf00,
+        0x80f90188,
-        0x1900f7f1,
+        0xa0f990f9,
-        0xcf00f3f0,
+        0xd0f9b0f9,
-        0x21f400ff,
+        0xf0f9e0f9,
-        0x01e7f004,
+        0xa7f104bd,
-        0x1d0007f1,
+        0xa3f00200,
-        0xd00003f0,
+        0x00aacf00,
-        0x04bd000e,
+        0xf404abc4,
-/* 0x0590: ih_no_fifo */
+        0xd7f02c0b,
-        0x010007f1,
+        0x00e7f124,
-        0xd00003f0,
+        0x00e3f01a,
-        0x04bd000a,
+        0xf100eecf,
-        0xe0fcf0fc,
+        0xf01900f7,
-        0xb0fcd0fc,
+        0xffcf00f3,
-        0x90fca0fc,
+        0x0421f400,
-        0x88fe80fc,
+        0xf101e7f0,
-        0xf480fc00,
+        0xf01d0007,
-        0x01f80032,
+        0x0ed00003,
-/* 0x05b4: hub_barrier_done */
+/* 0x0593: ih_no_fifo */
-        0x9801f7f0,
+        0xf104bd00,
-        0xfebb040e,
+        0xf0010007,
-        0x02ffb904,
+        0x0ad00003,
-        0x9418e7f1,
+        0xfc04bd00,
-        0xf440e3f0,
+        0xfce0fcf0,
-        0x00f89d21,
+        0xfcb0fcd0,
-/* 0x05cc: ctx_redswitch */
+        0xfc90fca0,
-        0xf120f7f0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x05b7: hub_barrier_done */
+        0xf001f800,
+        0x0e9801f7,
+        0x04febb04,
+        0xf102ffb9,
+        0xf09418e7,
+        0x21f440e3,
+/* 0x05cf: ctx_redswitch */
+        0xf000f89d,
+        0x07f120f7,
+        0x03f08500,
+        0x000fd001,
+        0xe7f004bd,
+/* 0x05e1: ctx_redswitch_delay */
+        0x01e2b608,
+        0xf1fd1bf4,
+        0xf10800f5,
+        0xf10200f5,
        0xf0850007,
        0x0fd00103,
-        0xf004bd00,
+        0xf804bd00,
-/* 0x05de: ctx_redswitch_delay */
+/* 0x05fd: ctx_xfer */
-        0xe2b608e7,
+        0x0007f100,
-        0xfd1bf401,
+        0x0203f081,
-        0x0800f5f1,
+        0xbd000fd0,
-        0x0200f5f1,
+        0x0711f404,
-        0x850007f1,
+        0x05cf21f5,
-        0xd00103f0,
+/* 0x0610: ctx_xfer_not_load */
-        0x04bd000f,
+        0x026a21f5,
-/* 0x05fa: ctx_xfer */
+        0x07f124bd,
-        0x07f100f8,
+        0x03f047fc,
-        0x03f08100,
+        0x0002d002,
-        0x000fd002,
+        0x2cf004bd,
-        0x11f404bd,
+        0x0320b601,
-        0xcc21f507,
+        0x4afc07f1,
-/* 0x060d: ctx_xfer_not_load */
+        0xd00203f0,
-        0x6a21f505,
+        0x04bd0002,
-        0xf124bd02,
-        0xf047fc07,
-        0x02d00203,
-        0xf004bd00,
-        0x20b6012c,
-        0xfc07f103,
-        0x0203f04a,
-        0xbd0002d0,
-        0x01acf004,
-        0xf102a5f0,
-        0xf00000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98000c,
-        0x00e7f001,
-        0x016f21f5,
-        0xf101acf0,
-        0xf04000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98010c,
-        0x060f9802,
-        0x0800e7f1,
-        0x016f21f5,
        0xf001acf0,
-        0xb7f104a5,
+        0xb7f102a5,
-        0xb3f03000,
+        0xb3f00000,
        0x040c9850,
        0xbb0fc4b6,
        0x0c9800bc,
-        0x030d9802,
+        0x010d9800,
-        0xf1080f98,
+        0xf500e7f0,
-        0xf50200e7,
+        0xf0016f21,
-        0xf5016f21,
+        0xb7f101ac,
-        0xf4025e21,
+        0xb3f04000,
-        0x12f40601,
+        0x040c9850,
-/* 0x06a9: ctx_xfer_post */
+        0xbb0fc4b6,
-        0x7f21f507,
+        0x0c9800bc,
-/* 0x06ad: ctx_xfer_done */
+        0x020d9801,
-        0xb421f502,
+        0xf1060f98,
-        0x0000f805,
+        0xf50800e7,
-        0x00000000,
+        0xf0016f21,
+        0xa5f001ac,
+        0x00b7f104,
+        0x50b3f030,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x020c9800,
+        0x98030d98,
+        0xe7f1080f,
+        0x21f50200,
+        0x21f5016f,
+        0x01f4025e,
+        0x0712f406,
+/* 0x06ac: ctx_xfer_post */
+        0x027f21f5,
+/* 0x06b0: ctx_xfer_done */
+        0x05b721f5,
+        0x000000f8,
        0x00000000,
        0x00000000,
        0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
index 2f596433c222..911976d20940 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gk104_grgpc_code[] = {
        0x03f01200,
        0x0002d000,
        0x17f104bd,
-        0x10fe0542,
+        0x10fe0545,
        0x0007f100,
        0x0003f007,
        0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gk104_grgpc_code[] = {
        0x02d00103,
        0xf104bd00,
        0xf00c30e7,
-        0x24bd50e3,
+        0xe5f050e3,
-        0x44bd34bd,
+        0xbd24bd01,
-/* 0x0430: init_unk_loop */
+/* 0x0433: init_unk_loop */
-        0xb06821f4,
+        0xf444bd34,
-        0x0bf400f6,
+        0xf6b06821,
-        0x01f7f00f,
+        0x0f0bf400,
-        0xfd04f2bb,
+        0xbb01f7f0,
-        0x30b6054f,
+        0x4ffd04f2,
-/* 0x0445: init_unk_next */
+        0x0130b605,
-        0x0120b601,
+/* 0x0448: init_unk_next */
-        0xb004e0b6,
+        0xb60120b6,
-        0x1bf40126,
+        0x26b004e0,
-/* 0x0451: init_unk_done */
+        0xe21bf401,
-        0x070380e2,
+/* 0x0454: init_unk_done */
-        0xf1080480,
+        0x80070380,
-        0xf0010027,
+        0x27f10804,
-        0x22cf0223,
+        0x23f00100,
-        0x9534bd00,
+        0x0022cf02,
-        0x07f10825,
+        0x259534bd,
-        0x03f0c000,
+        0x0007f108,
-        0x0005d001,
+        0x0103f0c0,
-        0x07f104bd,
+        0xbd0005d0,
-        0x03f0c100,
+        0x0007f104,
-        0x0005d001,
+        0x0103f0c1,
-        0x0e9804bd,
+        0xbd0005d0,
-        0x010f9800,
+        0x000e9804,
-        0x015021f5,
+        0xf5010f98,
-        0xbb002fbb,
+        0xbb015021,
-        0x0e98003f,
+        0x3fbb002f,
-        0x020f9801,
+        0x010e9800,
-        0x015021f5,
+        0xf5020f98,
-        0xfd050e98,
+        0x98015021,
-        0x2ebb00ef,
+        0xeffd050e,
-        0x003ebb00,
+        0x002ebb00,
-        0x98020e98,
+        0x98003ebb,
-        0x21f5030f,
+        0x0f98020e,
-        0x0e980150,
+        0x5021f503,
-        0x00effd07,
+        0x070e9801,
-        0xbb002ebb,
+        0xbb00effd,
-        0x35b6003e,
+        0x3ebb002e,
-        0x0007f102,
+        0x0235b600,
-        0x0103f0d3,
+        0xd30007f1,
-        0xbd0003d0,
+        0xd00103f0,
-        0x0825b604,
-        0xb60635b6,
-        0x30b60120,
-        0x0824b601,
-        0xb90834b6,
-        0x21f5022f,
-        0x2fbb02d3,
-        0x003fbb00,
-        0x010007f1,
-        0xd00203f0,
        0x04bd0003,
-        0x29f024bd,
+        0xb60825b6,
-        0x0007f11f,
+        0x20b60635,
-        0x0203f008,
+        0x0130b601,
-        0xbd0002d0,
+        0xb60824b6,
-/* 0x0505: main */
+        0x2fb90834,
-        0x0031f404,
+        0xd321f502,
-        0xf00028f4,
+        0x002fbb02,
-        0x21f424d7,
+        0xf1003fbb,
-        0xf401f439,
+        0xf0010007,
-        0xf404e4b0,
+        0x03d00203,
-        0x81fe1e18,
+        0xbd04bd00,
-        0x0627f001,
+        0x1f29f024,
-        0x12fd20bd,
+        0x080007f1,
-        0x01e4b604,
+        0xd00203f0,
-        0xfe051efd,
+        0x04bd0002,
-        0x21f50018,
+/* 0x0508: main */
-        0x0ef405fa,
+        0xf40031f4,
-/* 0x0535: main_not_ctx_xfer */
+        0xd7f00028,
-        0x10ef94d3,
+        0x3921f424,
-        0xf501f5f0,
+        0xb0f401f4,
-        0xf4037e21,
+        0x18f404e4,
-/* 0x0542: ih */
+        0x0181fe1e,
-        0x80f9c60e,
+        0xbd0627f0,
-        0xf90188fe,
+        0x0412fd20,
-        0xf990f980,
+        0xfd01e4b6,
-        0xf9b0f9a0,
+        0x18fe051e,
-        0xf9e0f9d0,
+        0xfd21f500,
-        0xf104bdf0,
+        0xd30ef405,
-        0xf00200a7,
+/* 0x0538: main_not_ctx_xfer */
-        0xaacf00a3,
+        0xf010ef94,
-        0x04abc400,
+        0x21f501f5,
-        0xf02c0bf4,
+        0x0ef4037e,
-        0xe7f124d7,
+/* 0x0545: ih */
-        0xe3f01a00,
+        0xfe80f9c6,
-        0x00eecf00,
+        0x80f90188,
-        0x1900f7f1,
+        0xa0f990f9,
-        0xcf00f3f0,
+        0xd0f9b0f9,
-        0x21f400ff,
+        0xf0f9e0f9,
-        0x01e7f004,
+        0xa7f104bd,
-        0x1d0007f1,
+        0xa3f00200,
-        0xd00003f0,
+        0x00aacf00,
-        0x04bd000e,
+        0xf404abc4,
-/* 0x0590: ih_no_fifo */
+        0xd7f02c0b,
-        0x010007f1,
+        0x00e7f124,
-        0xd00003f0,
+        0x00e3f01a,
-        0x04bd000a,
+        0xf100eecf,
-        0xe0fcf0fc,
+        0xf01900f7,
-        0xb0fcd0fc,
+        0xffcf00f3,
-        0x90fca0fc,
+        0x0421f400,
-        0x88fe80fc,
+        0xf101e7f0,
-        0xf480fc00,
+        0xf01d0007,
-        0x01f80032,
+        0x0ed00003,
-/* 0x05b4: hub_barrier_done */
+/* 0x0593: ih_no_fifo */
-        0x9801f7f0,
+        0xf104bd00,
-        0xfebb040e,
+        0xf0010007,
-        0x02ffb904,
+        0x0ad00003,
-        0x9418e7f1,
+        0xfc04bd00,
-        0xf440e3f0,
+        0xfce0fcf0,
-        0x00f89d21,
+        0xfcb0fcd0,
-/* 0x05cc: ctx_redswitch */
+        0xfc90fca0,
-        0xf120f7f0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x05b7: hub_barrier_done */
+        0xf001f800,
+        0x0e9801f7,
+        0x04febb04,
+        0xf102ffb9,
+        0xf09418e7,
+        0x21f440e3,
+/* 0x05cf: ctx_redswitch */
+        0xf000f89d,
+        0x07f120f7,
+        0x03f08500,
+        0x000fd001,
+        0xe7f004bd,
+/* 0x05e1: ctx_redswitch_delay */
+        0x01e2b608,
+        0xf1fd1bf4,
+        0xf10800f5,
+        0xf10200f5,
        0xf0850007,
        0x0fd00103,
-        0xf004bd00,
+        0xf804bd00,
-/* 0x05de: ctx_redswitch_delay */
+/* 0x05fd: ctx_xfer */
-        0xe2b608e7,
+        0x0007f100,
-        0xfd1bf401,
+        0x0203f081,
-        0x0800f5f1,
+        0xbd000fd0,
-        0x0200f5f1,
+        0x0711f404,
-        0x850007f1,
+        0x05cf21f5,
-        0xd00103f0,
+/* 0x0610: ctx_xfer_not_load */
-        0x04bd000f,
+        0x026a21f5,
-/* 0x05fa: ctx_xfer */
+        0x07f124bd,
-        0x07f100f8,
+        0x03f047fc,
-        0x03f08100,
+        0x0002d002,
-        0x000fd002,
+        0x2cf004bd,
-        0x11f404bd,
+        0x0320b601,
-        0xcc21f507,
+        0x4afc07f1,
-/* 0x060d: ctx_xfer_not_load */
+        0xd00203f0,
-        0x6a21f505,
+        0x04bd0002,
-        0xf124bd02,
-        0xf047fc07,
-        0x02d00203,
-        0xf004bd00,
-        0x20b6012c,
-        0xfc07f103,
-        0x0203f04a,
-        0xbd0002d0,
-        0x01acf004,
-        0xf102a5f0,
-        0xf00000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98000c,
-        0x00e7f001,
-        0x016f21f5,
-        0xf101acf0,
-        0xf04000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98010c,
-        0x060f9802,
-        0x0800e7f1,
-        0x016f21f5,
        0xf001acf0,
-        0xb7f104a5,
+        0xb7f102a5,
-        0xb3f03000,
+        0xb3f00000,
        0x040c9850,
        0xbb0fc4b6,
        0x0c9800bc,
-        0x030d9802,
+        0x010d9800,
-        0xf1080f98,
+        0xf500e7f0,
-        0xf50200e7,
+        0xf0016f21,
-        0xf5016f21,
+        0xb7f101ac,
-        0xf4025e21,
+        0xb3f04000,
-        0x12f40601,
+        0x040c9850,
-/* 0x06a9: ctx_xfer_post */
+        0xbb0fc4b6,
-        0x7f21f507,
+        0x0c9800bc,
-/* 0x06ad: ctx_xfer_done */
+        0x020d9801,
-        0xb421f502,
+        0xf1060f98,
-        0x0000f805,
+        0xf50800e7,
-        0x00000000,
+        0xf0016f21,
+        0xa5f001ac,
+        0x00b7f104,
+        0x50b3f030,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x020c9800,
+        0x98030d98,
+        0xe7f1080f,
+        0x21f50200,
+        0x21f5016f,
+        0x01f4025e,
+        0x0712f406,
+/* 0x06ac: ctx_xfer_post */
+        0x027f21f5,
+/* 0x06b0: ctx_xfer_done */
+        0x05b721f5,
+        0x000000f8,
        0x00000000,
        0x00000000,
        0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
index ee8e54db8fc9..1c6e11b05df2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gk110_grgpc_code[] = {
        0x03f01200,
        0x0002d000,
        0x17f104bd,
-        0x10fe0542,
+        0x10fe0545,
        0x0007f100,
        0x0003f007,
        0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gk110_grgpc_code[] = {
        0x02d00103,
        0xf104bd00,
        0xf00c30e7,
-        0x24bd50e3,
+        0xe5f050e3,
-        0x44bd34bd,
+        0xbd24bd01,
-/* 0x0430: init_unk_loop */
+/* 0x0433: init_unk_loop */
-        0xb06821f4,
+        0xf444bd34,
-        0x0bf400f6,
+        0xf6b06821,
-        0x01f7f00f,
+        0x0f0bf400,
-        0xfd04f2bb,
+        0xbb01f7f0,
-        0x30b6054f,
+        0x4ffd04f2,
-/* 0x0445: init_unk_next */
+        0x0130b605,
-        0x0120b601,
+/* 0x0448: init_unk_next */
-        0xb004e0b6,
+        0xb60120b6,
-        0x1bf40226,
+        0x26b004e0,
-/* 0x0451: init_unk_done */
+        0xe21bf402,
-        0x070380e2,
+/* 0x0454: init_unk_done */
-        0xf1080480,
+        0x80070380,
-        0xf0010027,
+        0x27f10804,
-        0x22cf0223,
+        0x23f00100,
-        0x9534bd00,
+        0x0022cf02,
-        0x07f10825,
+        0x259534bd,
-        0x03f0c000,
+        0x0007f108,
-        0x0005d001,
+        0x0103f0c0,
-        0x07f104bd,
+        0xbd0005d0,
-        0x03f0c100,
+        0x0007f104,
-        0x0005d001,
+        0x0103f0c1,
-        0x0e9804bd,
+        0xbd0005d0,
-        0x010f9800,
+        0x000e9804,
-        0x015021f5,
+        0xf5010f98,
-        0xbb002fbb,
+        0xbb015021,
-        0x0e98003f,
+        0x3fbb002f,
-        0x020f9801,
+        0x010e9800,
-        0x015021f5,
+        0xf5020f98,
-        0xfd050e98,
+        0x98015021,
-        0x2ebb00ef,
+        0xeffd050e,
-        0x003ebb00,
+        0x002ebb00,
-        0x98020e98,
+        0x98003ebb,
-        0x21f5030f,
+        0x0f98020e,
-        0x0e980150,
+        0x5021f503,
-        0x00effd07,
+        0x070e9801,
-        0xbb002ebb,
+        0xbb00effd,
-        0x35b6003e,
+        0x3ebb002e,
-        0x0007f102,
+        0x0235b600,
-        0x0103f0d3,
+        0xd30007f1,
-        0xbd0003d0,
+        0xd00103f0,
-        0x0825b604,
-        0xb60635b6,
-        0x30b60120,
-        0x0824b601,
-        0xb90834b6,
-        0x21f5022f,
-        0x2fbb02d3,
-        0x003fbb00,
-        0x010007f1,
-        0xd00203f0,
        0x04bd0003,
-        0x29f024bd,
+        0xb60825b6,
-        0x0007f11f,
+        0x20b60635,
-        0x0203f030,
+        0x0130b601,
-        0xbd0002d0,
+        0xb60824b6,
-/* 0x0505: main */
+        0x2fb90834,
-        0x0031f404,
+        0xd321f502,
-        0xf00028f4,
+        0x002fbb02,
-        0x21f424d7,
+        0xf1003fbb,
-        0xf401f439,
+        0xf0010007,
-        0xf404e4b0,
+        0x03d00203,
-        0x81fe1e18,
+        0xbd04bd00,
-        0x0627f001,
+        0x1f29f024,
-        0x12fd20bd,
+        0x300007f1,
-        0x01e4b604,
+        0xd00203f0,
-        0xfe051efd,
+        0x04bd0002,
-        0x21f50018,
+/* 0x0508: main */
-        0x0ef405fa,
+        0xf40031f4,
-/* 0x0535: main_not_ctx_xfer */
+        0xd7f00028,
-        0x10ef94d3,
+        0x3921f424,
-        0xf501f5f0,
+        0xb0f401f4,
-        0xf4037e21,
+        0x18f404e4,
-/* 0x0542: ih */
+        0x0181fe1e,
-        0x80f9c60e,
+        0xbd0627f0,
-        0xf90188fe,
+        0x0412fd20,
-        0xf990f980,
+        0xfd01e4b6,
-        0xf9b0f9a0,
+        0x18fe051e,
-        0xf9e0f9d0,
+        0xfd21f500,
-        0xf104bdf0,
+        0xd30ef405,
-        0xf00200a7,
+/* 0x0538: main_not_ctx_xfer */
-        0xaacf00a3,
+        0xf010ef94,
-        0x04abc400,
+        0x21f501f5,
-        0xf02c0bf4,
+        0x0ef4037e,
-        0xe7f124d7,
+/* 0x0545: ih */
-        0xe3f01a00,
+        0xfe80f9c6,
-        0x00eecf00,
+        0x80f90188,
-        0x1900f7f1,
+        0xa0f990f9,
-        0xcf00f3f0,
+        0xd0f9b0f9,
-        0x21f400ff,
+        0xf0f9e0f9,
-        0x01e7f004,
+        0xa7f104bd,
-        0x1d0007f1,
+        0xa3f00200,
-        0xd00003f0,
+        0x00aacf00,
-        0x04bd000e,
+        0xf404abc4,
-/* 0x0590: ih_no_fifo */
+        0xd7f02c0b,
-        0x010007f1,
+        0x00e7f124,
-        0xd00003f0,
+        0x00e3f01a,
-        0x04bd000a,
+        0xf100eecf,
-        0xe0fcf0fc,
+        0xf01900f7,
-        0xb0fcd0fc,
+        0xffcf00f3,
-        0x90fca0fc,
+        0x0421f400,
-        0x88fe80fc,
+        0xf101e7f0,
-        0xf480fc00,
+        0xf01d0007,
-        0x01f80032,
+        0x0ed00003,
-/* 0x05b4: hub_barrier_done */
+/* 0x0593: ih_no_fifo */
-        0x9801f7f0,
+        0xf104bd00,
-        0xfebb040e,
+        0xf0010007,
-        0x02ffb904,
+        0x0ad00003,
-        0x9418e7f1,
+        0xfc04bd00,
-        0xf440e3f0,
+        0xfce0fcf0,
-        0x00f89d21,
+        0xfcb0fcd0,
-/* 0x05cc: ctx_redswitch */
+        0xfc90fca0,
-        0xf120f7f0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x05b7: hub_barrier_done */
+        0xf001f800,
+        0x0e9801f7,
+        0x04febb04,
+        0xf102ffb9,
+        0xf09418e7,
+        0x21f440e3,
+/* 0x05cf: ctx_redswitch */
+        0xf000f89d,
+        0x07f120f7,
+        0x03f08500,
+        0x000fd001,
+        0xe7f004bd,
+/* 0x05e1: ctx_redswitch_delay */
+        0x01e2b608,
+        0xf1fd1bf4,
+        0xf10800f5,
+        0xf10200f5,
        0xf0850007,
        0x0fd00103,
-        0xf004bd00,
+        0xf804bd00,
-/* 0x05de: ctx_redswitch_delay */
+/* 0x05fd: ctx_xfer */
-        0xe2b608e7,
+        0x0007f100,
-        0xfd1bf401,
+        0x0203f081,
-        0x0800f5f1,
+        0xbd000fd0,
-        0x0200f5f1,
+        0x0711f404,
-        0x850007f1,
+        0x05cf21f5,
-        0xd00103f0,
+/* 0x0610: ctx_xfer_not_load */
-        0x04bd000f,
+        0x026a21f5,
-/* 0x05fa: ctx_xfer */
+        0x07f124bd,
-        0x07f100f8,
+        0x03f047fc,
-        0x03f08100,
+        0x0002d002,
-        0x000fd002,
+        0x2cf004bd,
-        0x11f404bd,
+        0x0320b601,
-        0xcc21f507,
+        0x4afc07f1,
-/* 0x060d: ctx_xfer_not_load */
+        0xd00203f0,
-        0x6a21f505,
+        0x04bd0002,
-        0xf124bd02,
-        0xf047fc07,
-        0x02d00203,
-        0xf004bd00,
-        0x20b6012c,
-        0xfc07f103,
-        0x0203f04a,
-        0xbd0002d0,
-        0x01acf004,
-        0xf102a5f0,
-        0xf00000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98000c,
-        0x00e7f001,
-        0x016f21f5,
-        0xf101acf0,
-        0xf04000b7,
-        0x0c9850b3,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98010c,
-        0x060f9802,
-        0x0800e7f1,
-        0x016f21f5,
        0xf001acf0,
-        0xb7f104a5,
+        0xb7f102a5,
-        0xb3f03000,
+        0xb3f00000,
        0x040c9850,
        0xbb0fc4b6,
        0x0c9800bc,
-        0x030d9802,
+        0x010d9800,
-        0xf1080f98,
+        0xf500e7f0,
-        0xf50200e7,
+        0xf0016f21,
-        0xf5016f21,
+        0xb7f101ac,
-        0xf4025e21,
+        0xb3f04000,
-        0x12f40601,
+        0x040c9850,
-/* 0x06a9: ctx_xfer_post */
+        0xbb0fc4b6,
-        0x7f21f507,
+        0x0c9800bc,
-/* 0x06ad: ctx_xfer_done */
+        0x020d9801,
-        0xb421f502,
+        0xf1060f98,
-        0x0000f805,
+        0xf50800e7,
-        0x00000000,
+        0xf0016f21,
+        0xa5f001ac,
+        0x00b7f104,
+        0x50b3f030,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x020c9800,
+        0x98030d98,
+        0xe7f1080f,
+        0x21f50200,
+        0x21f5016f,
+        0x01f4025e,
+        0x0712f406,
+/* 0x06ac: ctx_xfer_post */
+        0x027f21f5,
+/* 0x06b0: ctx_xfer_done */
+        0x05b721f5,
+        0x000000f8,
        0x00000000,
        0x00000000,
        0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
index fbcc342f896f..84af7ec6a78e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
@@ -276,7 +276,7 @@ uint32_t gk208_grgpc_code[] = {
        0x02020014,
        0xf6120040,
        0x04bd0002,
-        0xfe048141,
+        0xfe048441,
        0x00400010,
        0x0000f607,
        0x040204bd,
@@ -295,165 +295,165 @@ uint32_t gk208_grgpc_code[] = {
        0x01c90080,
        0xbd0002f6,
        0x0c308e04,
-        0xbd24bd50,
+        0x01e5f050,
-/* 0x0383: init_unk_loop */
+        0x34bd24bd,
-        0x7e44bd34,
+/* 0x0386: init_unk_loop */
-        0xb0000065,
+        0x657e44bd,
-        0x0bf400f6,
+        0xf6b00000,
-        0xbb010f0e,
+        0x0e0bf400,
-        0x4ffd04f2,
+        0xf2bb010f,
-        0x0130b605,
+        0x054ffd04,
-/* 0x0398: init_unk_next */
+/* 0x039b: init_unk_next */
-        0xb60120b6,
+        0xb60130b6,
-        0x26b004e0,
+        0xe0b60120,
-        0xe21bf401,
+        0x0126b004,
-/* 0x03a4: init_unk_done */
+/* 0x03a7: init_unk_done */
-        0xb50703b5,
+        0xb5e21bf4,
-        0x00820804,
+        0x04b50703,
-        0x22cf0201,
+        0x01008208,
-        0x9534bd00,
+        0x0022cf02,
-        0x00800825,
+        0x259534bd,
-        0x05f601c0,
+        0xc0008008,
-        0x8004bd00,
+        0x0005f601,
-        0xf601c100,
+        0x008004bd,
-        0x04bd0005,
+        0x05f601c1,
-        0x98000e98,
+        0x9804bd00,
-        0x207e010f,
+        0x0f98000e,
-        0x2fbb0001,
+        0x01207e01,
-        0x003fbb00,
+        0x002fbb00,
-        0x98010e98,
+        0x98003fbb,
-        0x207e020f,
+        0x0f98010e,
-        0x0e980001,
+        0x01207e02,
-        0x00effd05,
+        0x050e9800,
-        0xbb002ebb,
+        0xbb00effd,
-        0x0e98003e,
+        0x3ebb002e,
-        0x030f9802,
+        0x020e9800,
-        0x0001207e,
+        0x7e030f98,
-        0xfd070e98,
+        0x98000120,
-        0x2ebb00ef,
+        0xeffd070e,
-        0x003ebb00,
+        0x002ebb00,
-        0x800235b6,
+        0xb6003ebb,
-        0xf601d300,
+        0x00800235,
-        0x04bd0003,
+        0x03f601d3,
-        0xb60825b6,
+        0xb604bd00,
-        0x20b60635,
+        0x35b60825,
-        0x0130b601,
+        0x0120b606,
-        0xb60824b6,
+        0xb60130b6,
-        0x2fb20834,
+        0x34b60824,
-        0x0002687e,
+        0x7e2fb208,
-        0xbb002fbb,
+        0xbb000268,
-        0x0080003f,
+        0x3fbb002f,
-        0x03f60201,
+        0x01008000,
-        0xbd04bd00,
+        0x0003f602,
-        0x1f29f024,
+        0x24bd04bd,
-        0x02300080,
+        0x801f29f0,
-        0xbd0002f6,
+        0xf6023000,
-/* 0x0445: main */
+        0x04bd0002,
-        0x0031f404,
+/* 0x0448: main */
-        0x0d0028f4,
+        0xf40031f4,
-        0x00377e24,
+        0x240d0028,
-        0xf401f400,
+        0x0000377e,
-        0xf404e4b0,
+        0xb0f401f4,
-        0x81fe1d18,
+        0x18f404e4,
-        0xbd060201,
+        0x0181fe1d,
-        0x0412fd20,
+        0x20bd0602,
-        0xfd01e4b6,
+        0xb60412fd,
-        0x18fe051e,
+        0x1efd01e4,
-        0x05187e00,
+        0x0018fe05,
-        0xd40ef400,
+        0x00051b7e,
-/* 0x0474: main_not_ctx_xfer */
+/* 0x0477: main_not_ctx_xfer */
-        0xf010ef94,
+        0x94d40ef4,
-        0xf87e01f5,
+        0xf5f010ef,
-        0x0ef40002,
+        0x02f87e01,
-/* 0x0481: ih */
+        0xc70ef400,
-        0xfe80f9c7,
+/* 0x0484: ih */
-        0x80f90188,
+        0x88fe80f9,
-        0xa0f990f9,
+        0xf980f901,
-        0xd0f9b0f9,
+        0xf9a0f990,
-        0xf0f9e0f9,
+        0xf9d0f9b0,
-        0x004a04bd,
+        0xbdf0f9e0,
-        0x00aacf02,
+        0x02004a04,
-        0xf404abc4,
+        0xc400aacf,
-        0x240d1f0b,
+        0x0bf404ab,
-        0xcf1a004e,
+        0x4e240d1f,
-        0x004f00ee,
+        0xeecf1a00,
-        0x00ffcf19,
+        0x19004f00,
-        0x0000047e,
+        0x7e00ffcf,
-        0x0040010e,
+        0x0e000004,
-        0x000ef61d,
+        0x1d004001,
-/* 0x04be: ih_no_fifo */
+        0xbd000ef6,
-        0x004004bd,
+/* 0x04c1: ih_no_fifo */
-        0x000af601,
+        0x01004004,
-        0xf0fc04bd,
+        0xbd000af6,
-        0xd0fce0fc,
+        0xfcf0fc04,
-        0xa0fcb0fc,
+        0xfcd0fce0,
-        0x80fc90fc,
+        0xfca0fcb0,
-        0xfc0088fe,
+        0xfe80fc90,
-        0x0032f480,
+        0x80fc0088,
-/* 0x04de: hub_barrier_done */
+        0xf80032f4,
-        0x010f01f8,
+/* 0x04e1: hub_barrier_done */
-        0xbb040e98,
+        0x98010f01,
-        0xffb204fe,
+        0xfebb040e,
-        0x4094188e,
+        0x8effb204,
-        0x00008f7e,
+        0x7e409418,
-/* 0x04f2: ctx_redswitch */
+        0xf800008f,
-        0x200f00f8,
+/* 0x04f5: ctx_redswitch */
+        0x80200f00,
+        0xf6018500,
+        0x04bd000f,
+/* 0x0502: ctx_redswitch_delay */
+        0xe2b6080e,
+        0xfd1bf401,
+        0x0800f5f1,
+        0x0200f5f1,
        0x01850080,
        0xbd000ff6,
-/* 0x04ff: ctx_redswitch_delay */
+/* 0x051b: ctx_xfer */
-        0xb6080e04,
+        0x8000f804,
-        0x1bf401e2,
+        0xf6028100,
-        0x00f5f1fd,
+        0x04bd000f,
-        0x00f5f108,
+        0x7e0711f4,
-        0x85008002,
+/* 0x052b: ctx_xfer_not_load */
-        0x000ff601,
+        0x7e0004f5,
-        0x00f804bd,
+        0xbd000216,
-/* 0x0518: ctx_xfer */
+        0x47fc8024,
-        0x02810080,
-        0xbd000ff6,
-        0x0711f404,
-        0x0004f27e,
-/* 0x0528: ctx_xfer_not_load */
-        0x0002167e,
-        0xfc8024bd,
-        0x02f60247,
-        0xf004bd00,
-        0x20b6012c,
-        0x4afc8003,
        0x0002f602,
-        0xacf004bd,
+        0x2cf004bd,
-        0x02a5f001,
+        0x0320b601,
-        0x5000008b,
+        0x024afc80,
-        0xb6040c98,
+        0xbd0002f6,
-        0xbcbb0fc4,
+        0x01acf004,
-        0x000c9800,
+        0x8b02a5f0,
-        0x0e010d98,
+        0x98500000,
-        0x013d7e00,
-        0x01acf000,
-        0x5040008b,
-        0xb6040c98,
-        0xbcbb0fc4,
-        0x010c9800,
-        0x98020d98,
-        0x004e060f,
-        0x013d7e08,
-        0x01acf000,
-        0x8b04a5f0,
-        0x98503000,
        0xc4b6040c,
        0x00bcbb0f,
-        0x98020c98,
+        0x98000c98,
-        0x0f98030d,
+        0x000e010d,
-        0x02004e08,
        0x00013d7e,
-        0x00020a7e,
+        0x8b01acf0,
-        0xf40601f4,
+        0x98504000,
-/* 0x05b2: ctx_xfer_post */
+        0xc4b6040c,
-        0x277e0712,
+        0x00bcbb0f,
-/* 0x05b6: ctx_xfer_done */
+        0x98010c98,
-        0xde7e0002,
+        0x0f98020d,
-        0x00f80004,
+        0x08004e06,
-        0x00000000,
+        0x00013d7e,
+        0xf001acf0,
+        0x008b04a5,
+        0x0c985030,
+        0x0fc4b604,
+        0x9800bcbb,
+        0x0d98020c,
+        0x080f9803,
+        0x7e02004e,
+        0x7e00013d,
+        0xf400020a,
+        0x12f40601,
+/* 0x05b5: ctx_xfer_post */
+        0x02277e07,
+/* 0x05b9: ctx_xfer_done */
+        0x04e17e00,
+        0x0000f800,
        0x00000000,
        0x00000000,
        0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
index 51f5c3c6e966..11bf363a6ae9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
@@ -289,7 +289,7 @@ uint32_t gm107_grgpc_code[] = {
        0x020014fe,
        0x12004002,
        0xbd0002f6,
-        0x05b04104,
+        0x05b34104,
        0x400010fe,
        0x00f60700,
        0x0204bd00,
@@ -308,259 +308,259 @@ uint32_t gm107_grgpc_code[] = {
        0xc900800f,
        0x0002f601,
        0x308e04bd,
-        0x24bd500c,
+        0xe5f0500c,
-        0x44bd34bd,
+        0xbd24bd01,
-/* 0x03b0: init_unk_loop */
+/* 0x03b3: init_unk_loop */
-        0x0000657e,
+        0x7e44bd34,
-        0xf400f6b0,
+        0xb0000065,
-        0x010f0e0b,
+        0x0bf400f6,
-        0xfd04f2bb,
+        0xbb010f0e,
-        0x30b6054f,
+        0x4ffd04f2,
-/* 0x03c5: init_unk_next */
+        0x0130b605,
-        0x0120b601,
+/* 0x03c8: init_unk_next */
-        0xb004e0b6,
+        0xb60120b6,
-        0x1bf40226,
+        0x26b004e0,
-/* 0x03d1: init_unk_done */
+        0xe21bf402,
-        0x0703b5e2,
+/* 0x03d4: init_unk_done */
-        0x820804b5,
+        0xb50703b5,
-        0xcf020100,
+        0x00820804,
-        0x34bd0022,
+        0x22cf0201,
-        0x80082595,
+        0x9534bd00,
-        0xf601c000,
+        0x00800825,
+        0x05f601c0,
+        0x8004bd00,
+        0xf601c100,
        0x04bd0005,
-        0x01c10080,
+        0x98000e98,
-        0xbd0005f6,
+        0x207e010f,
-        0x000e9804,
+        0x2fbb0001,
-        0x7e010f98,
+        0x003fbb00,
-        0xbb000120,
+        0x98010e98,
-        0x3fbb002f,
+        0x207e020f,
-        0x010e9800,
+        0x0e980001,
-        0x7e020f98,
+        0x00effd05,
-        0x98000120,
+        0xbb002ebb,
-        0xeffd050e,
+        0x0e98003e,
-        0x002ebb00,
+        0x030f9802,
-        0x98003ebb,
+        0x0001207e,
-        0x0f98020e,
+        0xfd070e98,
-        0x01207e03,
+        0x2ebb00ef,
-        0x070e9800,
+        0x003ebb00,
-        0xbb00effd,
+        0x800235b6,
-        0x3ebb002e,
+        0xf601d300,
-        0x0235b600,
+        0x04bd0003,
-        0x01d30080,
+        0xb60825b6,
-        0xbd0003f6,
+        0x20b60635,
-        0x0825b604,
+        0x0130b601,
-        0xb60635b6,
+        0xb60824b6,
-        0x30b60120,
+        0x2fb20834,
-        0x0824b601,
+        0x0002687e,
-        0xb20834b6,
+        0xbb002fbb,
-        0x02687e2f,
+        0x3f0f003f,
-        0x002fbb00,
+        0x501d608e,
-        0x0f003fbb,
+        0xb201e5f0,
-        0x8effb23f,
+        0x008f7eff,
-        0xf0501d60,
+        0x8e0c0f00,
-        0x8f7e01e5,
-        0x0c0f0000,
-        0xa88effb2,
-        0xe5f0501d,
-        0x008f7e01,
-        0x03147e00,
-        0xb23f0f00,
-        0x1d608eff,
-        0x01e5f050,
-        0x00008f7e,
-        0xffb2000f,
-        0x501d9c8e,
-        0x7e01e5f0,
-        0x0f00008f,
-        0x03147e01,
-        0x8effb200,
        0xf0501da8,
-        0x8f7e01e5,
+        0xffb201e5,
-        0xff0f0000,
+        0x00008f7e,
-        0x988effb2,
+        0x0003147e,
+        0x608e3f0f,
        0xe5f0501d,
-        0x008f7e01,
+        0x7effb201,
-        0xb2020f00,
+        0x0f00008f,
-        0x1da88eff,
+        0x1d9c8e00,
        0x01e5f050,
-        0x00008f7e,
+        0x8f7effb2,
+        0x010f0000,
        0x0003147e,
-        0x85050498,
+        0x501da88e,
-        0x98504000,
+        0xb201e5f0,
-        0x64b60406,
+        0x008f7eff,
-        0x0056bb0f,
+        0x8eff0f00,
-/* 0x04e0: tpc_strand_init_tpc_loop */
+        0xf0501d98,
-        0x05705eb8,
+        0xffb201e5,
-        0x00657e00,
-        0xbdf6b200,
-/* 0x04ed: tpc_strand_init_idx_loop */
-        0x605eb874,
-        0x7fb20005,
-        0x00008f7e,
-        0x05885eb8,
-        0x082f9500,
-        0x00008f7e,
-        0x058c5eb8,
-        0x082f9500,
        0x00008f7e,
-        0x05905eb8,
+        0xa88e020f,
-        0x00657e00,
-        0x06f5b600,
-        0xb601f0b6,
-        0x2fbb08f4,
-        0x003fbb00,
-        0xb60170b6,
-        0x1bf40162,
-        0x0050b7bf,
-        0x0142b608,
-        0x0fa81bf4,
-        0x8effb23f,
-        0xf0501d60,
-        0x8f7e01e5,
-        0x0d0f0000,
-        0xa88effb2,
        0xe5f0501d,
-        0x008f7e01,
+        0x7effb201,
-        0x03147e00,
+        0x7e00008f,
-        0x01008000,
+        0x98000314,
-        0x0003f602,
+        0x00850504,
-        0x24bd04bd,
+        0x06985040,
-        0x801f29f0,
+        0x0f64b604,
-        0xf6023000,
+/* 0x04e3: tpc_strand_init_tpc_loop */
-        0x04bd0002,
+        0xb80056bb,
-/* 0x0574: main */
+        0x0005705e,
-        0xf40031f4,
+        0x0000657e,
-        0x240d0028,
+        0x74bdf6b2,
-        0x0000377e,
+/* 0x04f0: tpc_strand_init_idx_loop */
-        0xb0f401f4,
+        0x05605eb8,
-        0x18f404e4,
+        0x7e7fb200,
-        0x0181fe1d,
+        0xb800008f,
-        0x20bd0602,
+        0x0005885e,
-        0xb60412fd,
+        0x7e082f95,
-        0x1efd01e4,
+        0xb800008f,
-        0x0018fe05,
+        0x00058c5e,
-        0x0006477e,
+        0x7e082f95,
-/* 0x05a3: main_not_ctx_xfer */
+        0xb800008f,
-        0x94d40ef4,
+        0x0005905e,
-        0xf5f010ef,
+        0x0000657e,
-        0x02f87e01,
+        0xb606f5b6,
-        0xc70ef400,
+        0xf4b601f0,
-/* 0x05b0: ih */
+        0x002fbb08,
-        0x88fe80f9,
+        0xb6003fbb,
-        0xf980f901,
+        0x62b60170,
-        0xf9a0f990,
+        0xbf1bf401,
-        0xf9d0f9b0,
+        0x080050b7,
-        0xbdf0f9e0,
+        0xf40142b6,
-        0x02004a04,
+        0x3f0fa81b,
-        0xc400aacf,
+        0x501d608e,
-        0x0bf404ab,
+        0xb201e5f0,
-        0x4e240d1f,
+        0x008f7eff,
-        0xeecf1a00,
+        0x8e0d0f00,
-        0x19004f00,
+        0xf0501da8,
-        0x7e00ffcf,
+        0xffb201e5,
-        0x0e000004,
+        0x00008f7e,
-        0x1d004001,
+        0x0003147e,
-        0xbd000ef6,
+        0x02010080,
-/* 0x05ed: ih_no_fifo */
+        0xbd0003f6,
-        0x01004004,
+        0xf024bd04,
-        0xbd000af6,
+        0x00801f29,
-        0xfcf0fc04,
+        0x02f60230,
-        0xfcd0fce0,
+/* 0x0577: main */
-        0xfca0fcb0,
+        0xf404bd00,
-        0xfe80fc90,
+        0x28f40031,
-        0x80fc0088,
+        0x7e240d00,
-        0xf80032f4,
+        0xf4000037,
-/* 0x060d: hub_barrier_done */
+        0xe4b0f401,
-        0x98010f01,
+        0x1d18f404,
-        0xfebb040e,
+        0x020181fe,
-        0x8effb204,
+        0xfd20bd06,
-        0x7e409418,
+        0xe4b60412,
-        0xf800008f,
+        0x051efd01,
-/* 0x0621: ctx_redswitch */
+        0x7e0018fe,
-        0x80200f00,
+        0xf400064a,
+/* 0x05a6: main_not_ctx_xfer */
+        0xef94d40e,
+        0x01f5f010,
+        0x0002f87e,
+/* 0x05b3: ih */
+        0xf9c70ef4,
+        0x0188fe80,
+        0x90f980f9,
+        0xb0f9a0f9,
+        0xe0f9d0f9,
+        0x04bdf0f9,
+        0xcf02004a,
+        0xabc400aa,
+        0x1f0bf404,
+        0x004e240d,
+        0x00eecf1a,
+        0xcf19004f,
+        0x047e00ff,
+        0x010e0000,
+        0xf61d0040,
+        0x04bd000e,
+/* 0x05f0: ih_no_fifo */
+        0xf6010040,
+        0x04bd000a,
+        0xe0fcf0fc,
+        0xb0fcd0fc,
+        0x90fca0fc,
+        0x88fe80fc,
+        0xf480fc00,
+        0x01f80032,
+/* 0x0610: hub_barrier_done */
+        0x0e98010f,
+        0x04febb04,
+        0x188effb2,
+        0x8f7e4094,
+        0x00f80000,
+/* 0x0624: ctx_redswitch */
+        0x0080200f,
+        0x0ff60185,
+        0x0e04bd00,
+/* 0x0631: ctx_redswitch_delay */
+        0x01e2b608,
+        0xf1fd1bf4,
+        0xf10800f5,
+        0x800200f5,
        0xf6018500,
        0x04bd000f,
-/* 0x062e: ctx_redswitch_delay */
+/* 0x064a: ctx_xfer */
-        0xe2b6080e,
+        0x008000f8,
-        0xfd1bf401,
+        0x0ff60281,
-        0x0800f5f1,
+        0x8e04bd00,
-        0x0200f5f1,
+        0xf0501dc4,
-        0x01850080,
+        0xffb201e5,
-        0xbd000ff6,
+        0x00008f7e,
-/* 0x0647: ctx_xfer */
+        0x7e0711f4,
-        0x8000f804,
+/* 0x0667: ctx_xfer_not_load */
-        0xf6028100,
+        0x7e000624,
-        0x04bd000f,
+        0xbd000216,
-        0xc48effb2,
+        0x47fc8024,
-        0xe5f0501d,
-        0x008f7e01,
-        0x0711f400,
-        0x0006217e,
-/* 0x0664: ctx_xfer_not_load */
-        0x0002167e,
-        0xfc8024bd,
-        0x02f60247,
-        0xf004bd00,
-        0x20b6012c,
-        0x4afc8003,
        0x0002f602,
-        0x0c0f04bd,
+        0x2cf004bd,
-        0xa88effb2,
+        0x0320b601,
-        0xe5f0501d,
+        0x024afc80,
-        0x008f7e01,
+        0xbd0002f6,
-        0x03147e00,
+        0x8e0c0f04,
-        0xb23f0f00,
+        0xf0501da8,
-        0x1d608eff,
+        0xffb201e5,
-        0x01e5f050,
        0x00008f7e,
-        0xffb2000f,
+        0x0003147e,
-        0x501d9c8e,
+        0x608e3f0f,
-        0x7e01e5f0,
+        0xe5f0501d,
+        0x7effb201,
        0x0f00008f,
-        0x03147e01,
+        0x1d9c8e00,
-        0x01fcf000,
-        0xb203f0b6,
-        0x1da88eff,
        0x01e5f050,
-        0x00008f7e,
+        0x8f7effb2,
-        0xf001acf0,
+        0x010f0000,
-        0x008b02a5,
+        0x0003147e,
-        0x0c985000,
+        0xb601fcf0,
-        0x0fc4b604,
+        0xa88e03f0,
-        0x9800bcbb,
+        0xe5f0501d,
-        0x0d98000c,
+        0x7effb201,
-        0x7e000e01,
+        0xf000008f,
-        0xf000013d,
-        0x008b01ac,
-        0x0c985040,
-        0x0fc4b604,
-        0x9800bcbb,
-        0x0d98010c,
-        0x060f9802,
-        0x7e08004e,
-        0xf000013d,
        0xa5f001ac,
-        0x30008b04,
+        0x00008b02,
        0x040c9850,
        0xbb0fc4b6,
        0x0c9800bc,
-        0x030d9802,
+        0x010d9800,
-        0x4e080f98,
+        0x3d7e000e,
-        0x3d7e0200,
+        0xacf00001,
-        0x0a7e0001,
+        0x40008b01,
-        0x147e0002,
+        0x040c9850,
-        0x01f40003,
+        0xbb0fc4b6,
-        0x1a12f406,
+        0x0c9800bc,
-/* 0x073c: ctx_xfer_post */
+        0x020d9801,
-        0x0002277e,
+        0x4e060f98,
-        0xffb20d0f,
+        0x3d7e0800,
-        0x501da88e,
+        0xacf00001,
-        0x7e01e5f0,
+        0x04a5f001,
-        0x7e00008f,
+        0x5030008b,
-/* 0x0753: ctx_xfer_done */
+        0xb6040c98,
-        0x7e000314,
+        0xbcbb0fc4,
-        0xf800060d,
+        0x020c9800,
-        0x00000000,
+        0x98030d98,
+        0x004e080f,
+        0x013d7e02,
+        0x020a7e00,
+        0x03147e00,
+        0x0601f400,
+/* 0x073f: ctx_xfer_post */
+        0x7e1a12f4,
+        0x0f000227,
+        0x1da88e0d,
+        0x01e5f050,
+        0x8f7effb2,
+        0x147e0000,
+/* 0x0756: ctx_xfer_done */
+        0x107e0003,
+        0x00f80006,
        0x00000000,
        0x00000000,
        0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index dda7a7d224c9..9f5dfc85147a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -143,7 +143,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
 static int
 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
 {
-        struct gf100_gr *gr = (void *)object->engine;
+        struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
        union {
                struct fermi_a_zbc_color_v0 v0;
        } *args = data;
@@ -189,7 +189,7 @@ gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
 static int
 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
 {
-        struct gf100_gr *gr = (void *)object->engine;
+        struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
        union {
                struct fermi_a_zbc_depth_v0 v0;
        } *args = data;
@@ -1530,6 +1530,8 @@ gf100_gr_oneinit(struct nvkm_gr *base)
                gr->ppc_nr[i]  = gr->func->ppc_nr;
                for (j = 0; j < gr->ppc_nr[i]; j++) {
                        u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
+                        if (mask)
+                                gr->ppc_mask[i] |= (1 << j);
                        gr->ppc_tpc_nr[i][j] = hweight8(mask);
                }
        }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
index 4611961b1187..02e78b8d93f6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -97,6 +97,7 @@ struct gf100_gr {
        u8 tpc_nr[GPC_MAX];
        u8 tpc_total;
        u8 ppc_nr[GPC_MAX];
+        u8 ppc_mask[GPC_MAX];
        u8 ppc_tpc_nr[GPC_MAX][4];
        struct nvkm_memory *unk4188b4;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
index 43006db6fd58..80fed7e78dcb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
@@ -83,6 +83,7 @@ nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
                        fan->type = NVBIOS_THERM_FAN_UNK;
                }
+                fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
                fan->min_duty = nvbios_rd08(bios, data + 0x02);
                fan->max_duty = nvbios_rd08(bios, data + 0x03);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
index 895ba74057d4..1d7dd38292b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
@@ -97,7 +97,9 @@ static void *
 nvkm_instobj_dtor(struct nvkm_memory *memory)
 {
        struct nvkm_instobj *iobj = nvkm_instobj(memory);
+        spin_lock(&iobj->imem->lock);
        list_del(&iobj->head);
+        spin_unlock(&iobj->imem->lock);
        nvkm_memory_del(&iobj->parent);
        return iobj;
 }
@@ -190,7 +192,9 @@ nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero,
                nvkm_memory_ctor(&nvkm_instobj_func_slow, &iobj->memory);
                iobj->parent = memory;
                iobj->imem = imem;
+                spin_lock(&iobj->imem->lock);
                list_add_tail(&iobj->head, &imem->list);
+                spin_unlock(&iobj->imem->lock);
                memory = &iobj->memory;
        }
@@ -309,5 +313,6 @@ nvkm_instmem_ctor(const struct nvkm_instmem_func *func,
 {
        nvkm_subdev_ctor(&nvkm_instmem, device, index, 0, &imem->subdev);
        imem->func = func;
+        spin_lock_init(&imem->lock);
        INIT_LIST_HEAD(&imem->list);
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
index d942fa7b9f18..86f9f3b13f71 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
@@ -81,9 +81,7 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
        nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
        nvkm_rd32(device, 0x000200);
-        if ( nvkm_boolopt(device->cfgopt, "War00C800_0",
+        if (nvkm_boolopt(device->cfgopt, "War00C800_0", true)) {
-            device->quirk ? device->quirk->War00C800_0 : false)) {
-                nvkm_info(&pmu->subdev, "hw bug workaround enabled\n");
                switch (device->chipset) {
                case 0xe4:
                        magic(device, 0x04000000);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
index b61509e26ec9..b735173a18ff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
@@ -59,7 +59,7 @@ gk104_volt_set(struct nvkm_volt *base, u32 uv)
        duty = (uv - bios->base) * div / bios->pwm_range;
        nvkm_wr32(device, 0x20340, div);
-        nvkm_wr32(device, 0x20344, 0x8000000 | duty);
+        nvkm_wr32(device, 0x20344, 0x80000000 | duty);
        return 0;
 }
diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c
index b8e4cdec28c3..24f92bea39c7 100644
--- a/drivers/gpu/drm/omapdrm/omap_fbdev.c
+++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c
@@ -112,11 +112,8 @@ static int omap_fbdev_create(struct drm_fb_helper *helper,
        dma_addr_t paddr;
        int ret;
-        /* only doing ARGB32 since this is what is needed to alpha-blend
-         * with video overlays:
-         */
        sizes->surface_bpp = 32;
-        sizes->surface_depth = 32;
+        sizes->surface_depth = 24;
        DBG("create fbdev: %dx%d@%d (%dx%d)", sizes->surface_width,
                        sizes->surface_height, sizes->surface_bpp,
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 248953d2fdb7..f81fb2641097 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4173,11 +4173,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
        control |= ib->length_dw | (vm_id << 24);
        radeon_ring_write(ring, header);
-        radeon_ring_write(ring,
+        radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
-#ifdef __BIG_ENDIAN
-                          (2 << 0) |
-#endif
-                          (ib->gpu_addr & 0xFFFFFFFC));
        radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
        radeon_ring_write(ring, control);
 }
@@ -8472,7 +8468,7 @@ restart_ih:
        if (queue_dp)
                schedule_work(&rdev->dp_work);
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (queue_reset) {
                rdev->needs_reset = true;
                wake_up_all(&rdev->fence_queue);
@@ -9630,6 +9626,9 @@ static void dce8_program_watermarks(struct radeon_device *rdev,
                    (rdev->disp_priority == 2)) {
                        DRM_DEBUG_KMS("force priority to high\n");
                }
+                /* Save number of lines the linebuffer leads before the scanout */
+                radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 7f33767d7ed6..2ad462896896 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2372,6 +2372,9 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
                c.full = dfixed_div(c, a);
                priority_b_mark = dfixed_trunc(c);
                priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
+                /* Save number of lines the linebuffer leads before the scanout */
+                radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
@@ -5344,7 +5347,7 @@ restart_ih:
        if (queue_dp)
                schedule_work(&rdev->dp_work);
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (queue_hdmi)
                schedule_work(&rdev->audio_work);
        if (queue_thermal && rdev->pm.dpm_enabled)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 238b13f045c1..9e7e2bf03b81 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -806,7 +806,7 @@ int r100_irq_process(struct radeon_device *rdev)
                status = r100_irq_ack(rdev);
        }
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (rdev->msi_enabled) {
                switch (rdev->family) {
                case CHIP_RS400:
@@ -3217,6 +3217,9 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        uint32_t pixel_bytes1 = 0;
        uint32_t pixel_bytes2 = 0;
+        /* Guess line buffer size to be 8192 pixels */
+        u32 lb_size = 8192;
        if (!rdev->mode_info.mode_config_initialized)
                return;
@@ -3631,6 +3634,13 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
                          (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
        }
+        /* Save number of lines the linebuffer leads before the scanout */
+        if (mode1)
+            rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
+        if (mode2)
+            rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
 }
 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4ea5b10ff5f4..cc2fdf0be37a 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -4276,7 +4276,7 @@ restart_ih:
                WREG32(IH_RB_RPTR, rptr);
        }
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (queue_hdmi)
                schedule_work(&rdev->audio_work);
        if (queue_thermal && rdev->pm.dpm_enabled)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b6cbd816537e..87db64983ea8 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2414,7 +2414,7 @@ struct radeon_device {
        struct r600_ih ih; /* r6/700 interrupt ring */
        struct radeon_rlc rlc;
        struct radeon_mec mec;
-        struct work_struct hotplug_work;
+        struct delayed_work hotplug_work;
        struct work_struct dp_work;
        struct work_struct audio_work;
        int num_crtc; /* number of crtcs */
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index fe994aac3b04..c77d349c561c 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -54,6 +54,9 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
        /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */
        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50,
                PCI_VENDOR_ID_IBM, 0x0550, 1},
+        /* Intel 82855PM host bridge / RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] needs AGPMode 1 (Thinkpad T40p) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
+                PCI_VENDOR_ID_IBM, 0x054d, 1},
        /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */
        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57,
                PCI_VENDOR_ID_IBM, 0x0530, 1},
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5a2cafb4f1bc..340f3f549f29 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1234,13 +1234,32 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
        if (r < 0)
                return connector_status_disconnected;
+        if (radeon_connector->detected_hpd_without_ddc) {
+                force = true;
+                radeon_connector->detected_hpd_without_ddc = false;
+        }
        if (!force && radeon_check_hpd_status_unchanged(connector)) {
                ret = connector->status;
                goto exit;
        }
-        if (radeon_connector->ddc_bus)
+        if (radeon_connector->ddc_bus) {
                dret = radeon_ddc_probe(radeon_connector, false);
+                /* Sometimes the pins required for the DDC probe on DVI
+                 * connectors don't make contact at the same time that the ones
+                 * for HPD do. If the DDC probe fails even though we had an HPD
+                 * signal, try again later */
+                if (!dret && !force &&
+                    connector->status != connector_status_connected) {
+                        DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
+                        radeon_connector->detected_hpd_without_ddc = true;
+                        schedule_delayed_work(&rdev->hotplug_work,
+                                              msecs_to_jiffies(1000));
+                        goto exit;
+                }
+        }
        if (dret) {
                radeon_connector->detected_by_load = false;
                radeon_connector_free_edid(connector);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a8d9927ed9eb..1eca0acac016 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -322,7 +322,9 @@ void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
         * to complete in this vblank?
         */
        if (update_pending &&
-            (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
+            (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
+                                                               crtc_id,
+                                                               USE_REAL_VBLANKSTART,
                                                               &vpos, &hpos, NULL, NULL,
                                                               &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
            ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
@@ -401,6 +403,8 @@ static void radeon_flip_work_func(struct work_struct *__work)
        struct drm_crtc *crtc = &radeon_crtc->base;
        unsigned long flags;
        int r;
+        int vpos, hpos, stat, min_udelay;
+        struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
        down_read(&rdev->exclusive_lock);
        if (work->fence) {
@@ -437,6 +441,41 @@ static void radeon_flip_work_func(struct work_struct *__work)
        /* set the proper interrupt */
        radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
+        /* If this happens to execute within the "virtually extended" vblank
+         * interval before the start of the real vblank interval then it needs
+         * to delay programming the mmio flip until the real vblank is entered.
+         * This prevents completing a flip too early due to the way we fudge
+         * our vblank counter and vblank timestamps in order to work around the
+         * problem that the hw fires vblank interrupts before actual start of
+         * vblank (when line buffer refilling is done for a frame). It
+         * complements the fudging logic in radeon_get_crtc_scanoutpos() for
+         * timestamping and radeon_get_vblank_counter_kms() for vblank counts.
+         *
+         * In practice this won't execute very often unless on very fast
+         * machines because the time window for this to happen is very small.
+         */
+        for (;;) {
+                /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
+                 * start in hpos, and to the "fudged earlier" vblank start in
+                 * vpos.
+                 */
+                stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id,
+                                                  GET_DISTANCE_TO_VBLANKSTART,
+                                                  &vpos, &hpos, NULL, NULL,
+                                                  &crtc->hwmode);
+                if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
+                    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
+                    !(vpos >= 0 && hpos <= 0))
+                        break;
+                /* Sleep at least until estimated real start of hw vblank */
+                spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+                min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
+                usleep_range(min_udelay, 2 * min_udelay);
+                spin_lock_irqsave(&crtc->dev->event_lock, flags);
+        };
        /* do the flip (mmio) */
        radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
@@ -1768,6 +1807,15 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 * \param dev Device to query.
 * \param crtc Crtc to query.
 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
+ *              For driver internal use only also supports these flags:
+ *
+ *              USE_REAL_VBLANKSTART to use the real start of vblank instead
+ *              of a fudged earlier start of vblank.
+ *
+ *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
+ *              fudged earlier start of vblank in *vpos and the distance
+ *              to true start of vblank in *hpos.
+ *
 * \param *vpos Location where vertical scanout position should be stored.
 * \param *hpos Location where horizontal scanout position should go.
 * \param *stime Target location for timestamp taken immediately before
@@ -1911,10 +1959,40 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
                vbl_end = 0;
        }
+        /* Called from driver internal vblank counter query code? */
+        if (flags & GET_DISTANCE_TO_VBLANKSTART) {
+            /* Caller wants distance from real vbl_start in *hpos */
+            *hpos = *vpos - vbl_start;
+        }
+        /* Fudge vblank to start a few scanlines earlier to handle the
+         * problem that vblank irqs fire a few scanlines before start
+         * of vblank. Some driver internal callers need the true vblank
+         * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
+         *
+         * The cause of the "early" vblank irq is that the irq is triggered
+         * by the line buffer logic when the line buffer read position enters
+         * the vblank, whereas our crtc scanout position naturally lags the
+         * line buffer read position.
+         */
+        if (!(flags & USE_REAL_VBLANKSTART))
+                vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
        /* Test scanout position against vblank region. */
        if ((*vpos < vbl_start) && (*vpos >= vbl_end))
                in_vbl = false;
+        /* In vblank? */
+        if (in_vbl)
+            ret |= DRM_SCANOUTPOS_IN_VBLANK;
+        /* Called from driver internal vblank counter query code? */
+        if (flags & GET_DISTANCE_TO_VBLANKSTART) {
+                /* Caller wants distance from fudged earlier vbl_start */
+                *vpos -= vbl_start;
+                return ret;
+        }
        /* Check if inside vblank area and apply corrective offsets:
         * vpos will then be >=0 in video scanout area, but negative
         * within vblank area, counting down the number of lines until
@@ -1930,31 +2008,5 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
        /* Correct for shifted end of vbl at vbl_end. */
        *vpos = *vpos - vbl_end;
-        /* In vblank? */
-        if (in_vbl)
-                ret |= DRM_SCANOUTPOS_IN_VBLANK;
-        /* Is vpos outside nominal vblank area, but less than
-         * 1/100 of a frame height away from start of vblank?
-         * If so, assume this isn't a massively delayed vblank
-         * interrupt, but a vblank interrupt that fired a few
-         * microseconds before true start of vblank. Compensate
-         * by adding a full frame duration to the final timestamp.
-         * Happens, e.g., on ATI R500, R600.
-         *
-         * We only do this if DRM_CALLED_FROM_VBLIRQ.
-         */
-        if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
-                vbl_start = mode->crtc_vdisplay;
-                vtotal = mode->crtc_vtotal;
-                if (vbl_start - *vpos < vtotal / 100) {
-                        *vpos -= vtotal;
-                        /* Signal this correction as "applied". */
-                        ret |= 0x8;
-                }
-        }
        return ret;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 171d3e43c30c..979f3bf65f2c 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -74,7 +74,7 @@ irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg)
 static void radeon_hotplug_work_func(struct work_struct *work)
 {
        struct radeon_device *rdev = container_of(work, struct radeon_device,
-                                                  hotplug_work);
+                                                  hotplug_work.work);
        struct drm_device *dev = rdev->ddev;
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct drm_connector *connector;
@@ -302,7 +302,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
                }
        }
-        INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
+        INIT_DELAYED_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
        INIT_WORK(&rdev->dp_work, radeon_dp_work_func);
        INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);
@@ -310,7 +310,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
        r = drm_irq_install(rdev->ddev, rdev->ddev->pdev->irq);
        if (r) {
                rdev->irq.installed = false;
-                flush_work(&rdev->hotplug_work);
+                flush_delayed_work(&rdev->hotplug_work);
                return r;
        }
@@ -333,7 +333,7 @@ void radeon_irq_kms_fini(struct radeon_device *rdev)
                rdev->irq.installed = false;
                if (rdev->msi_enabled)
                        pci_disable_msi(rdev->pdev);
-                flush_work(&rdev->hotplug_work);
+                flush_delayed_work(&rdev->hotplug_work);
        }
 }
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 0ec6fcca16d3..d290a8a09036 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -755,6 +755,8 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
 */
 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 {
+        int vpos, hpos, stat;
+        u32 count;
        struct radeon_device *rdev = dev->dev_private;
        if (crtc < 0 || crtc >= rdev->num_crtc) {
@@ -762,7 +764,53 @@ u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
                return -EINVAL;
        }
-        return radeon_get_vblank_counter(rdev, crtc);
+        /* The hw increments its frame counter at start of vsync, not at start
+         * of vblank, as is required by DRM core vblank counter handling.
+         * Cook the hw count here to make it appear to the caller as if it
+         * incremented at start of vblank. We measure distance to start of
+         * vblank in vpos. vpos therefore will be >= 0 between start of vblank
+         * and start of vsync, so vpos >= 0 means to bump the hw frame counter
+         * result by 1 to give the proper appearance to caller.
+         */
+        if (rdev->mode_info.crtcs[crtc]) {
+                /* Repeat readout if needed to provide stable result if
+                 * we cross start of vsync during the queries.
+                 */
+                do {
+                        count = radeon_get_vblank_counter(rdev, crtc);
+                        /* Ask radeon_get_crtc_scanoutpos to return vpos as
+                         * distance to start of vblank, instead of regular
+                         * vertical scanout pos.
+                         */
+                        stat = radeon_get_crtc_scanoutpos(
+                                dev, crtc, GET_DISTANCE_TO_VBLANKSTART,
+                                &vpos, &hpos, NULL, NULL,
+                                &rdev->mode_info.crtcs[crtc]->base.hwmode);
+                } while (count != radeon_get_vblank_counter(rdev, crtc));
+                if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
+                    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
+                        DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
+                }
+                else {
+                        DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
+                                      crtc, vpos);
+                        /* Bump counter if we are at >= leading edge of vblank,
+                         * but before vsync where vpos would turn negative and
+                         * the hw counter really increments.
+                         */
+                        if (vpos >= 0)
+                                count++;
+                }
+        }
+        else {
+            /* Fallback to use value as is. */
+            count = radeon_get_vblank_counter(rdev, crtc);
+            DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
+        }
+        return count;
 }
 /**
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 830e171c3a9e..bba112628b47 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -367,6 +367,7 @@ struct radeon_crtc {
        u32 line_time;
        u32 wm_low;
        u32 wm_high;
+        u32 lb_vblank_lead_lines;
        struct drm_display_mode hw_mode;
        enum radeon_output_csc output_csc;
 };
@@ -553,6 +554,7 @@ struct radeon_connector {
        void *con_priv;
        bool dac_load_detect;
        bool detected_by_load; /* if the connection status was determined by load */
+        bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
        uint16_t connector_object_id;
        struct radeon_hpd hpd;
        struct radeon_router router;
@@ -686,6 +688,9 @@ struct atom_voltage_table
        struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
 };
+/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
+#define USE_REAL_VBLANKSTART            (1 << 30)
+#define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 extern void
 radeon_add_atom_connector(struct drm_device *dev,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index f4f03dcc1530..59abebd6b5dc 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1756,7 +1756,9 @@ static bool radeon_pm_in_vbl(struct radeon_device *rdev)
         */
        for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
                if (rdev->pm.active_crtcs & (1 << crtc)) {
-                        vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0,
+                        vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
+                                                                crtc,
+                                                                USE_REAL_VBLANKSTART,
                                                                &vpos, &hpos, NULL, NULL,
                                                                &rdev->mode_info.crtcs[crtc]->base.hwmode);
                        if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
index 574f62bbd215..7eb1ae758906 100644
--- a/drivers/gpu/drm/radeon/radeon_vce.c
+++ b/drivers/gpu/drm/radeon/radeon_vce.c
@@ -361,31 +361,31 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
        /* stitch together an VCE create msg */
        ib.length_dw = 0;
-        ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
-        ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
-        ib.ptr[ib.length_dw++] = handle;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
-        ib.ptr[ib.length_dw++] = 0x00000030; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000030); /* len */
-        ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x01000001); /* create cmd */
-        ib.ptr[ib.length_dw++] = 0x00000000;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
-        ib.ptr[ib.length_dw++] = 0x00000042;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000042);
-        ib.ptr[ib.length_dw++] = 0x0000000a;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000a);
-        ib.ptr[ib.length_dw++] = 0x00000001;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
-        ib.ptr[ib.length_dw++] = 0x00000080;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000080);
-        ib.ptr[ib.length_dw++] = 0x00000060;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000060);
-        ib.ptr[ib.length_dw++] = 0x00000100;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
-        ib.ptr[ib.length_dw++] = 0x00000100;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
-        ib.ptr[ib.length_dw++] = 0x0000000c;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c);
-        ib.ptr[ib.length_dw++] = 0x00000000;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
-        ib.ptr[ib.length_dw++] = 0x00000014; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
-        ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
-        ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
+        ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
-        ib.ptr[ib.length_dw++] = dummy;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
-        ib.ptr[ib.length_dw++] = 0x00000001;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
        for (i = ib.length_dw; i < ib_size_dw; ++i)
-                ib.ptr[i] = 0x0;
+                ib.ptr[i] = cpu_to_le32(0x0);
        r = radeon_ib_schedule(rdev, &ib, NULL, false);
        if (r) {
@@ -428,21 +428,21 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
        /* stitch together an VCE destroy msg */
        ib.length_dw = 0;
-        ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
-        ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
-        ib.ptr[ib.length_dw++] = handle;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
-        ib.ptr[ib.length_dw++] = 0x00000014; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
-        ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
-        ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
+        ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
-        ib.ptr[ib.length_dw++] = dummy;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
-        ib.ptr[ib.length_dw++] = 0x00000001;
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
-        ib.ptr[ib.length_dw++] = 0x00000008; /* len */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000008); /* len */
-        ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
+        ib.ptr[ib.length_dw++] = cpu_to_le32(0x02000001); /* destroy cmd */
        for (i = ib.length_dw; i < ib_size_dw; ++i)
-                ib.ptr[i] = 0x0;
+                ib.ptr[i] = cpu_to_le32(0x0);
        r = radeon_ib_schedule(rdev, &ib, NULL, false);
        if (r) {
@@ -699,12 +699,12 @@ bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
 {
        uint64_t addr = semaphore->gpu_addr;
-        radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
-        radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
+        radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
-        radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
+        radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
-        radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
+        radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
        if (!emit_wait)
-                radeon_ring_write(ring, VCE_CMD_END);
+                radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
        return true;
 }
@@ -719,10 +719,10 @@ bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
        struct radeon_ring *ring = &rdev->ring[ib->ring];
-        radeon_ring_write(ring, VCE_CMD_IB);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
-        radeon_ring_write(ring, ib->gpu_addr);
+        radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
-        radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
+        radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
-        radeon_ring_write(ring, ib->length_dw);
+        radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
 }
 /**
@@ -738,12 +738,12 @@ void radeon_vce_fence_emit(struct radeon_device *rdev,
        struct radeon_ring *ring = &rdev->ring[fence->ring];
        uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
-        radeon_ring_write(ring, VCE_CMD_FENCE);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));
-        radeon_ring_write(ring, addr);
+        radeon_ring_write(ring, cpu_to_le32(addr));
-        radeon_ring_write(ring, upper_32_bits(addr));
+        radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));
-        radeon_ring_write(ring, fence->seq);
+        radeon_ring_write(ring, cpu_to_le32(fence->seq));
-        radeon_ring_write(ring, VCE_CMD_TRAP);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));
-        radeon_ring_write(ring, VCE_CMD_END);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
 }
 /**
@@ -765,7 +765,7 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
                          ring->idx, r);
                return r;
        }
-        radeon_ring_write(ring, VCE_CMD_END);
+        radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
        radeon_ring_unlock_commit(rdev, ring, false);
        for (i = 0; i < rdev->usec_timeout; i++) {
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 97a904835759..6244f4e44e9a 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -813,7 +813,7 @@ int rs600_irq_process(struct radeon_device *rdev)
                status = rs600_irq_ack(rdev);
        }
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (queue_hdmi)
                schedule_work(&rdev->audio_work);
        if (rdev->msi_enabled) {
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 516ca27cfa12..6bc44c24e837 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -207,6 +207,9 @@ void rs690_line_buffer_adjust(struct radeon_device *rdev,
 {
        u32 tmp;
+        /* Guess line buffer size to be 8192 pixels */
+        u32 lb_size = 8192;
        /*
         * Line Buffer Setup
         * There is a single line buffer shared by both display controllers.
@@ -243,6 +246,13 @@ void rs690_line_buffer_adjust(struct radeon_device *rdev,
                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
        }
        WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
+        /* Save number of lines the linebuffer leads before the scanout */
+        if (mode1)
+                rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
+        if (mode2)
+                rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
 }
 struct rs690_watermark {
diff --git a/drivers/gpu/drm/radeon/rv730_dpm.c b/drivers/gpu/drm/radeon/rv730_dpm.c
index 3f5e1cf138ba..d37ba2cb886e 100644
--- a/drivers/gpu/drm/radeon/rv730_dpm.c
+++ b/drivers/gpu/drm/radeon/rv730_dpm.c
@@ -464,7 +464,7 @@ void rv730_stop_dpm(struct radeon_device *rdev)
        result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
        if (result != PPSMC_Result_OK)
-                DRM_ERROR("Could not force DPM to low\n");
+                DRM_DEBUG("Could not force DPM to low\n");
        WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index b9c770745a7a..e830c8935db0 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -193,7 +193,7 @@ void rv770_stop_dpm(struct radeon_device *rdev)
        result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
        if (result != PPSMC_Result_OK)
-                DRM_ERROR("Could not force DPM to low.\n");
+                DRM_DEBUG("Could not force DPM to low.\n");
        WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
@@ -1418,7 +1418,7 @@ int rv770_resume_smc(struct radeon_device *rdev)
 int rv770_set_sw_state(struct radeon_device *rdev)
 {
        if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
-                return -EINVAL;
+                DRM_DEBUG("rv770_set_sw_state failed\n");
        return 0;
 }
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 07037e32dea3..f878d6962da5 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2376,6 +2376,9 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
                c.full = dfixed_div(c, a);
                priority_b_mark = dfixed_trunc(c);
                priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
+                /* Save number of lines the linebuffer leads before the scanout */
+                radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
        }
        /* select wm A */
@@ -6848,7 +6851,7 @@ restart_ih:
        if (queue_dp)
                schedule_work(&rdev->dp_work);
        if (queue_hotplug)
-                schedule_work(&rdev->hotplug_work);
+                schedule_delayed_work(&rdev->hotplug_work, 0);
        if (queue_thermal && rdev->pm.dpm_enabled)
                schedule_work(&rdev->pm.dpm.thermal.work);
        rdev->ih.rptr = rptr;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
index 8caea0a33dd8..d908321b94ce 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -67,6 +67,7 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
         * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
         */
        vma->vm_flags &= ~VM_PFNMAP;
+        vma->vm_pgoff = 0;
        ret = dma_mmap_attrs(drm->dev, vma, rk_obj->kvaddr, rk_obj->dma_addr,
                             obj->size, &rk_obj->dma_attrs);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e49c44..03c47eeadc81 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -374,6 +374,7 @@ static const struct of_device_id vop_driver_dt_match[] = {
          .data = &rk3288_vop },
        {},
 };
+MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 {
@@ -959,8 +960,8 @@ static int vop_update_plane_event(struct drm_plane *plane,
        val = (dest.y2 - dest.y1 - 1) << 16;
        val |= (dest.x2 - dest.x1 - 1) & 0xffff;
        VOP_WIN_SET(vop, win, dsp_info, val);
-        val = (dsp_sty - 1) << 16;
+        val = dsp_sty << 16;
-        val |= (dsp_stx - 1) & 0xffff;
+        val |= dsp_stx & 0xffff;
        VOP_WIN_SET(vop, win, dsp_st, val);
        VOP_WIN_SET(vop, win, rb_swap, rb_swap);
@@ -1289,7 +1290,7 @@ static void vop_win_state_complete(struct vop_win *vop_win,
        if (state->event) {
                spin_lock_irqsave(&drm->event_lock, flags);
-                drm_send_vblank_event(drm, -1, state->event);
+                drm_crtc_send_vblank_event(crtc, state->event);
                spin_unlock_irqrestore(&drm->event_lock, flags);
        }
@@ -1575,32 +1576,25 @@ static int vop_initial(struct vop *vop)
                return PTR_ERR(vop->dclk);
        }
-        ret = clk_prepare(vop->hclk);
-        if (ret < 0) {
-                dev_err(vop->dev, "failed to prepare hclk\n");
-                return ret;
-        }
        ret = clk_prepare(vop->dclk);
        if (ret < 0) {
                dev_err(vop->dev, "failed to prepare dclk\n");
-                goto err_unprepare_hclk;
+                return ret;
        }
-        ret = clk_prepare(vop->aclk);
+        /* Enable both the hclk and aclk to setup the vop */
+        ret = clk_prepare_enable(vop->hclk);
        if (ret < 0) {
-                dev_err(vop->dev, "failed to prepare aclk\n");
+                dev_err(vop->dev, "failed to prepare/enable hclk\n");
                goto err_unprepare_dclk;
        }
-        /*
+        ret = clk_prepare_enable(vop->aclk);
-         * enable hclk, so that we can config vop register.
-         */
-        ret = clk_enable(vop->hclk);
        if (ret < 0) {
-                dev_err(vop->dev, "failed to prepare aclk\n");
+                dev_err(vop->dev, "failed to prepare/enable aclk\n");
-                goto err_unprepare_aclk;
+                goto err_disable_hclk;
        }
        /*
         * do hclk_reset, reset all vop registers.
         */
@@ -1608,7 +1602,7 @@ static int vop_initial(struct vop *vop)
        if (IS_ERR(ahb_rst)) {
                dev_err(vop->dev, "failed to get ahb reset\n");
                ret = PTR_ERR(ahb_rst);
-                goto err_disable_hclk;
+                goto err_disable_aclk;
        }
        reset_control_assert(ahb_rst);
        usleep_range(10, 20);
@@ -1634,26 +1628,25 @@ static int vop_initial(struct vop *vop)
        if (IS_ERR(vop->dclk_rst)) {
                dev_err(vop->dev, "failed to get dclk reset\n");
                ret = PTR_ERR(vop->dclk_rst);
-                goto err_unprepare_aclk;
+                goto err_disable_aclk;
        }
        reset_control_assert(vop->dclk_rst);
        usleep_range(10, 20);
        reset_control_deassert(vop->dclk_rst);
        clk_disable(vop->hclk);
+        clk_disable(vop->aclk);
        vop->is_enabled = false;
        return 0;
+err_disable_aclk:
+        clk_disable_unprepare(vop->aclk);
 err_disable_hclk:
-        clk_disable(vop->hclk);
+        clk_disable_unprepare(vop->hclk);
-err_unprepare_aclk:
-        clk_unprepare(vop->aclk);
 err_unprepare_dclk:
        clk_unprepare(vop->dclk);
-err_unprepare_hclk:
-        clk_unprepare(vop->hclk);
        return ret;
 }
diff --git a/drivers/gpu/drm/ttm/ttm_lock.c b/drivers/gpu/drm/ttm/ttm_lock.c
index 6a954544727f..f154fb1929bd 100644
--- a/drivers/gpu/drm/ttm/ttm_lock.c
+++ b/drivers/gpu/drm/ttm/ttm_lock.c
@@ -180,7 +180,7 @@ int ttm_write_lock(struct ttm_lock *lock, bool interruptible)
                        spin_unlock(&lock->lock);
                }
        } else
-                wait_event(lock->queue, __ttm_read_lock(lock));
+                wait_event(lock->queue, __ttm_write_lock(lock));
        return ret;
 }
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c
index f545913a56c7..578fe0a9324c 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -412,7 +412,7 @@ static const struct drm_connector_funcs virtio_gpu_connector_funcs = {
        .save = virtio_gpu_conn_save,
        .restore = virtio_gpu_conn_restore,
        .detect = virtio_gpu_conn_detect,
-        .fill_modes = drm_helper_probe_single_connector_modes,
+        .fill_modes = drm_helper_probe_single_connector_modes_nomerge,
        .destroy = virtio_gpu_conn_destroy,
        .reset = drm_atomic_helper_connector_reset,
        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index a09cf8529b9f..c49812b80dd0 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -1233,6 +1233,7 @@ static void vmw_master_drop(struct drm_device *dev,
        vmw_fp->locked_master = drm_master_get(file_priv->master);
        ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
+        vmw_kms_legacy_hotspot_clear(dev_priv);
        if (unlikely((ret != 0))) {
                DRM_ERROR("Unable to lock TTM at VT switch.\n");
                drm_master_put(&vmw_fp->locked_master);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index a8ae9dfb83b7..469cdd520615 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -925,6 +925,7 @@ int vmw_kms_present(struct vmw_private *dev_priv,
                    uint32_t num_clips);
 int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
                                struct drm_file *file_priv);
+void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv);
 int vmw_dumb_create(struct drm_file *file_priv,
                    struct drm_device *dev,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index a8baf5f5e765..b6a0806b06bf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -390,7 +390,7 @@ void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
        else if (ctx_id == SVGA3D_INVALID_ID)
                ret = vmw_local_fifo_reserve(dev_priv, bytes);
        else {
-                WARN_ON("Command buffer has not been allocated.\n");
+                WARN(1, "Command buffer has not been allocated.\n");
                ret = NULL;
        }
        if (IS_ERR_OR_NULL(ret)) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 9fcd7f82995c..9b4bb9e74d73 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -133,13 +133,19 @@ void vmw_cursor_update_position(struct vmw_private *dev_priv,
        vmw_mmio_write(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
 }
-int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
-                           uint32_t handle, uint32_t width, uint32_t height)
+/*
+ * vmw_du_crtc_cursor_set2 - Driver cursor_set2 callback.
+ */
+int vmw_du_crtc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file_priv,
+                            uint32_t handle, uint32_t width, uint32_t height,
+                            int32_t hot_x, int32_t hot_y)
 {
        struct vmw_private *dev_priv = vmw_priv(crtc->dev);
        struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
        struct vmw_surface *surface = NULL;
        struct vmw_dma_buffer *dmabuf = NULL;
+        s32 hotspot_x, hotspot_y;
        int ret;
        /*
@@ -151,6 +157,8 @@ int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
         */
        drm_modeset_unlock_crtc(crtc);
        drm_modeset_lock_all(dev_priv->dev);
+        hotspot_x = hot_x + du->hotspot_x;
+        hotspot_y = hot_y + du->hotspot_y;
        /* A lot of the code assumes this */
        if (handle && (width != 64 || height != 64)) {
@@ -187,31 +195,34 @@ int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
                vmw_dmabuf_unreference(&du->cursor_dmabuf);
        /* setup new image */
+        ret = 0;
        if (surface) {
                /* vmw_user_surface_lookup takes one reference */
                du->cursor_surface = surface;
                du->cursor_surface->snooper.crtc = crtc;
                du->cursor_age = du->cursor_surface->snooper.age;
-                vmw_cursor_update_image(dev_priv, surface->snooper.image,
+                ret = vmw_cursor_update_image(dev_priv, surface->snooper.image,
-                                        64, 64, du->hotspot_x, du->hotspot_y);
+                                              64, 64, hotspot_x, hotspot_y);
        } else if (dmabuf) {
                /* vmw_user_surface_lookup takes one reference */
                du->cursor_dmabuf = dmabuf;
                ret = vmw_cursor_update_dmabuf(dev_priv, dmabuf, width, height,
-                                               du->hotspot_x, du->hotspot_y);
+                                               hotspot_x, hotspot_y);
        } else {
                vmw_cursor_update_position(dev_priv, false, 0, 0);
-                ret = 0;
                goto out;
        }
-        vmw_cursor_update_position(dev_priv, true,
+        if (!ret) {
-                                   du->cursor_x + du->hotspot_x,
+                vmw_cursor_update_position(dev_priv, true,
-                                   du->cursor_y + du->hotspot_y);
+                                           du->cursor_x + hotspot_x,
+                                           du->cursor_y + hotspot_y);
+                du->core_hotspot_x = hot_x;
+                du->core_hotspot_y = hot_y;
+        }
-        ret = 0;
 out:
        drm_modeset_unlock_all(dev_priv->dev);
        drm_modeset_lock_crtc(crtc, crtc->cursor);
@@ -239,8 +250,10 @@ int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
        drm_modeset_lock_all(dev_priv->dev);
        vmw_cursor_update_position(dev_priv, shown,
-                                   du->cursor_x + du->hotspot_x,
+                                   du->cursor_x + du->hotspot_x +
-                                   du->cursor_y + du->hotspot_y);
+                                   du->core_hotspot_x,
+                                   du->cursor_y + du->hotspot_y +
+                                   du->core_hotspot_y);
        drm_modeset_unlock_all(dev_priv->dev);
        drm_modeset_lock_crtc(crtc, crtc->cursor);
@@ -334,6 +347,29 @@ err_unreserve:
        ttm_bo_unreserve(bo);
 }
+/**
+ * vmw_kms_legacy_hotspot_clear - Clear legacy hotspots
+ *
+ * @dev_priv: Pointer to the device private struct.
+ *
+ * Clears all legacy hotspots.
+ */
+void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv)
+{
+        struct drm_device *dev = dev_priv->dev;
+        struct vmw_display_unit *du;
+        struct drm_crtc *crtc;
+        drm_modeset_lock_all(dev);
+        drm_for_each_crtc(crtc, dev) {
+                du = vmw_crtc_to_du(crtc);
+                du->hotspot_x = 0;
+                du->hotspot_y = 0;
+        }
+        drm_modeset_unlock_all(dev);
+}
 void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
 {
        struct drm_device *dev = dev_priv->dev;
@@ -351,7 +387,9 @@ void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
                du->cursor_age = du->cursor_surface->snooper.age;
                vmw_cursor_update_image(dev_priv,
                                        du->cursor_surface->snooper.image,
-                                        64, 64, du->hotspot_x, du->hotspot_y);
+                                        64, 64,
+                                        du->hotspot_x + du->core_hotspot_x,
+                                        du->hotspot_y + du->core_hotspot_y);
        }
        mutex_unlock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
index 782df7ca9794..edd81503516d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
@@ -159,6 +159,8 @@ struct vmw_display_unit {
        int hotspot_x;
        int hotspot_y;
+        s32 core_hotspot_x;
+        s32 core_hotspot_y;
        unsigned unit;
@@ -193,8 +195,9 @@ void vmw_du_crtc_restore(struct drm_crtc *crtc);
 void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
                           u16 *r, u16 *g, u16 *b,
                           uint32_t start, uint32_t size);
-int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
+int vmw_du_crtc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file_priv,
-                           uint32_t handle, uint32_t width, uint32_t height);
+                            uint32_t handle, uint32_t width, uint32_t height,
+                            int32_t hot_x, int32_t hot_y);
 int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y);
 int vmw_du_connector_dpms(struct drm_connector *connector, int mode);
 void vmw_du_connector_save(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index bb63e4d795fa..52caecb4502e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -297,7 +297,7 @@ static int vmw_ldu_crtc_set_config(struct drm_mode_set *set)
 static struct drm_crtc_funcs vmw_legacy_crtc_funcs = {
        .save = vmw_du_crtc_save,
        .restore = vmw_du_crtc_restore,
-        .cursor_set = vmw_du_crtc_cursor_set,
+        .cursor_set2 = vmw_du_crtc_cursor_set2,
        .cursor_move = vmw_du_crtc_cursor_move,
        .gamma_set = vmw_du_crtc_gamma_set,
        .destroy = vmw_ldu_crtc_destroy,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index b96d1ab610c5..13926ff192e3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -533,7 +533,7 @@ out_no_fence:
 static struct drm_crtc_funcs vmw_screen_object_crtc_funcs = {
        .save = vmw_du_crtc_save,
        .restore = vmw_du_crtc_restore,
-        .cursor_set = vmw_du_crtc_cursor_set,
+        .cursor_set2 = vmw_du_crtc_cursor_set2,
        .cursor_move = vmw_du_crtc_cursor_move,
        .gamma_set = vmw_du_crtc_gamma_set,
        .destroy = vmw_sou_crtc_destroy,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index b1fc1c02792d..f823fc3efed7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -1043,7 +1043,7 @@ out_finish:
 static struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
        .save = vmw_du_crtc_save,
        .restore = vmw_du_crtc_restore,
-        .cursor_set = vmw_du_crtc_cursor_set,
+        .cursor_set2 = vmw_du_crtc_cursor_set2,
        .cursor_move = vmw_du_crtc_cursor_move,
        .gamma_set = vmw_du_crtc_gamma_set,
        .destroy = vmw_stdu_crtc_destroy,
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index ba47b30d28fa..f2e13eb8339f 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -28,6 +28,7 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of_device.h>
+#include <linux/of_graph.h>
 #include <drm/drm_fourcc.h>
@@ -993,12 +994,26 @@ static void platform_device_unregister_children(struct platform_device *pdev)
 struct ipu_platform_reg {
        struct ipu_client_platformdata pdata;
        const char *name;
-        int reg_offset;
 };
+/* These must be in the order of the corresponding device tree port nodes */
 static const struct ipu_platform_reg client_reg[] = {
        {
                .pdata = {
+                        .csi = 0,
+                        .dma[0] = IPUV3_CHANNEL_CSI0,
+                        .dma[1] = -EINVAL,
+                },
+                .name = "imx-ipuv3-camera",
+        }, {
+                .pdata = {
+                        .csi = 1,
+                        .dma[0] = IPUV3_CHANNEL_CSI1,
+                        .dma[1] = -EINVAL,
+                },
+                .name = "imx-ipuv3-camera",
+        }, {
+                .pdata = {
                        .di = 0,
                        .dc = 5,
                        .dp = IPU_DP_FLOW_SYNC_BG,
@@ -1015,22 +1030,6 @@ static const struct ipu_platform_reg client_reg[] = {
                        .dma[1] = -EINVAL,
                },
                .name = "imx-ipuv3-crtc",
-        }, {
-                .pdata = {
-                        .csi = 0,
-                        .dma[0] = IPUV3_CHANNEL_CSI0,
-                        .dma[1] = -EINVAL,
-                },
-                .reg_offset = IPU_CM_CSI0_REG_OFS,
-                .name = "imx-ipuv3-camera",
-        }, {
-                .pdata = {
-                        .csi = 1,
-                        .dma[0] = IPUV3_CHANNEL_CSI1,
-                        .dma[1] = -EINVAL,
-                },
-                .reg_offset = IPU_CM_CSI1_REG_OFS,
-                .name = "imx-ipuv3-camera",
        },
 };
@@ -1051,22 +1050,30 @@ static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
        for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
                const struct ipu_platform_reg *reg = &client_reg[i];
                struct platform_device *pdev;
-                struct resource res;
+                pdev = platform_device_alloc(reg->name, id++);
-                if (reg->reg_offset) {
+                if (!pdev) {
-                        memset(&res, 0, sizeof(res));
+                        ret = -ENOMEM;
-                        res.flags = IORESOURCE_MEM;
+                        goto err_register;
-                        res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
+                }
-                        res.end = res.start + PAGE_SIZE - 1;
-                        pdev = platform_device_register_resndata(dev, reg->name,
+                pdev->dev.parent = dev;
-                                id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
-                } else {
+                /* Associate subdevice with the corresponding port node */
-                        pdev = platform_device_register_data(dev, reg->name,
+                pdev->dev.of_node = of_graph_get_port_by_id(dev->of_node, i);
-                                id++, &reg->pdata, sizeof(reg->pdata));
+                if (!pdev->dev.of_node) {
+                        dev_err(dev, "missing port@%d node in %s\n", i,
+                                dev->of_node->full_name);
+                        ret = -ENODEV;
+                        goto err_register;
                }
-                if (IS_ERR(pdev)) {
+                ret = platform_device_add_data(pdev, &reg->pdata,
-                        ret = PTR_ERR(pdev);
+                                               sizeof(reg->pdata));
+                if (!ret)
+                        ret = platform_device_add(pdev);
+                if (ret) {
+                        platform_device_put(pdev);
                        goto err_register;
                }
        }
diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c
index 3166e4bc4eb6..9abcaa53bd25 100644
--- a/drivers/gpu/vga/vgaarb.c
+++ b/drivers/gpu/vga/vgaarb.c
@@ -395,8 +395,10 @@ int vga_get(struct pci_dev *pdev, unsigned int rsrc, int interruptible)
                set_current_state(interruptible ?
                                  TASK_INTERRUPTIBLE :
                                  TASK_UNINTERRUPTIBLE);
-                if (signal_pending(current)) {
+                if (interruptible && signal_pending(current)) {
-                        rc = -EINTR;
+                        __set_current_state(TASK_RUNNING);
+                        remove_wait_queue(&vga_wait_queue, &wait);
+                        rc = -ERESTARTSYS;
                        break;
                }
                schedule();
author	Thomas Gleixner <tglx@linutronix.de>	2016-01-12 05:01:12 -0500
committer	Thomas Gleixner <tglx@linutronix.de>	2016-01-12 05:01:12 -0500
commit	1f16f116b01c110db20ab808562c8b8bc3ee3d6e (patch)
tree	44db563f64cf5f8d62af8f99a61e2b248c44ea3a /drivers/gpu
parent	03724ac3d48f8f0e3caf1d30fa134f8fd96c94e2 (diff)
parent	f9eccf24615672896dc13251410c3f2f33a14f95 (diff)