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authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2011-12-19 16:41:10 -0500
committerDave Airlie <airlied@redhat.com>2011-12-20 05:23:14 -0500
commit5736995b473b8853d5ee048c7dfb9c1d20ebf0ea (patch)
tree95b82546611ca39c8ae383201e9154175ccaf4df /drivers/gpu/drm
parent5c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067 (diff)
gma500: Replace SDVO code with slightly modified version from i915
Our current SDVO implementation is not working properly, so replace it with a modified version of the i915. Further testing and debugging is needed to make sure we can handle the different SDVO setups and wiring. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h19
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_display.c8
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_drv.h41
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_reg.h2
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_sdvo.c3054
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h591
6 files changed, 2742 insertions, 973 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 962c1b605c32..3e63087a6f5f 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -260,6 +260,16 @@ struct psb_intel_opregion {
260 int enabled; 260 int enabled;
261}; 261};
262 262
263struct sdvo_device_mapping {
264 u8 initialized;
265 u8 dvo_port;
266 u8 slave_addr;
267 u8 dvo_wiring;
268 u8 i2c_pin;
269 u8 i2c_speed;
270 u8 ddc_pin;
271};
272
263struct intel_gmbus { 273struct intel_gmbus {
264 struct i2c_adapter adapter; 274 struct i2c_adapter adapter;
265 struct i2c_adapter *force_bit; 275 struct i2c_adapter *force_bit;
@@ -345,6 +355,15 @@ struct drm_psb_private {
345 /* gmbus */ 355 /* gmbus */
346 struct intel_gmbus *gmbus; 356 struct intel_gmbus *gmbus;
347 357
358 /* Used by SDVO */
359 int crt_ddc_pin;
360 /* FIXME: The mappings should be parsed from bios but for now we can
361 pretend there are no mappings available */
362 struct sdvo_device_mapping sdvo_mappings[2];
363 u32 hotplug_supported_mask;
364 struct drm_property *broadcast_rgb_property;
365 struct drm_property *force_audio_property;
366
348 /* 367 /*
349 * LVDS info 368 * LVDS info
350 */ 369 */
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index ddaf3d428f55..49e983508d5c 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -552,6 +552,14 @@ void psb_intel_encoder_commit(struct drm_encoder *encoder)
552 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 552 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
553} 553}
554 554
555void psb_intel_encoder_destroy(struct drm_encoder *encoder)
556{
557 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
558
559 drm_encoder_cleanup(encoder);
560 kfree(intel_encoder);
561}
562
555static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, 563static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
556 struct drm_display_mode *mode, 564 struct drm_display_mode *mode,
557 struct drm_display_mode *adjusted_mode) 565 struct drm_display_mode *adjusted_mode)
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h
index 3d7a2275238b..7c0bbaeba14a 100644
--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
@@ -39,6 +39,25 @@
39#define INTEL_I2C_BUS_DVO 1 39#define INTEL_I2C_BUS_DVO 1
40#define INTEL_I2C_BUS_SDVO 2 40#define INTEL_I2C_BUS_SDVO 2
41 41
42/* Intel Pipe Clone Bit */
43#define INTEL_HDMIB_CLONE_BIT 1
44#define INTEL_HDMIC_CLONE_BIT 2
45#define INTEL_HDMID_CLONE_BIT 3
46#define INTEL_HDMIE_CLONE_BIT 4
47#define INTEL_HDMIF_CLONE_BIT 5
48#define INTEL_SDVO_NON_TV_CLONE_BIT 6
49#define INTEL_SDVO_TV_CLONE_BIT 7
50#define INTEL_SDVO_LVDS_CLONE_BIT 8
51#define INTEL_ANALOG_CLONE_BIT 9
52#define INTEL_TV_CLONE_BIT 10
53#define INTEL_DP_B_CLONE_BIT 11
54#define INTEL_DP_C_CLONE_BIT 12
55#define INTEL_DP_D_CLONE_BIT 13
56#define INTEL_LVDS_CLONE_BIT 14
57#define INTEL_DVO_TMDS_CLONE_BIT 15
58#define INTEL_DVO_LVDS_CLONE_BIT 16
59#define INTEL_EDP_CLONE_BIT 17
60
42/* these are outputs from the chip - integrated only 61/* these are outputs from the chip - integrated only
43 * external chips are via DVO or SDVO output */ 62 * external chips are via DVO or SDVO output */
44#define INTEL_OUTPUT_UNUSED 0 63#define INTEL_OUTPUT_UNUSED 0
@@ -56,6 +75,25 @@
56#define INTEL_DVO_CHIP_TMDS 2 75#define INTEL_DVO_CHIP_TMDS 2
57#define INTEL_DVO_CHIP_TVOUT 4 76#define INTEL_DVO_CHIP_TVOUT 4
58 77
78#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
79#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
80
81static inline void
82psb_intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
83 int multiplier)
84{
85 mode->clock *= multiplier;
86 mode->private_flags |= multiplier;
87}
88
89static inline int
90psb_intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
91{
92 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK)
93 >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
94}
95
96
59/* 97/*
60 * Hold information useally put on the device driver privates here, 98 * Hold information useally put on the device driver privates here,
61 * since it needs to be shared across multiple of devices drivers privates. 99 * since it needs to be shared across multiple of devices drivers privates.
@@ -173,7 +211,7 @@ extern bool psb_intel_ddc_probe(struct i2c_adapter *adapter);
173extern void psb_intel_crtc_init(struct drm_device *dev, int pipe, 211extern void psb_intel_crtc_init(struct drm_device *dev, int pipe,
174 struct psb_intel_mode_device *mode_dev); 212 struct psb_intel_mode_device *mode_dev);
175extern void psb_intel_crt_init(struct drm_device *dev); 213extern void psb_intel_crt_init(struct drm_device *dev);
176extern void psb_intel_sdvo_init(struct drm_device *dev, int output_device); 214extern bool psb_intel_sdvo_init(struct drm_device *dev, int output_device);
177extern void psb_intel_dvo_init(struct drm_device *dev); 215extern void psb_intel_dvo_init(struct drm_device *dev);
178extern void psb_intel_tv_init(struct drm_device *dev); 216extern void psb_intel_tv_init(struct drm_device *dev);
179extern void psb_intel_lvds_init(struct drm_device *dev, 217extern void psb_intel_lvds_init(struct drm_device *dev,
@@ -190,6 +228,7 @@ extern void mid_dsi_init(struct drm_device *dev,
190extern void psb_intel_crtc_load_lut(struct drm_crtc *crtc); 228extern void psb_intel_crtc_load_lut(struct drm_crtc *crtc);
191extern void psb_intel_encoder_prepare(struct drm_encoder *encoder); 229extern void psb_intel_encoder_prepare(struct drm_encoder *encoder);
192extern void psb_intel_encoder_commit(struct drm_encoder *encoder); 230extern void psb_intel_encoder_commit(struct drm_encoder *encoder);
231extern void psb_intel_encoder_destroy(struct drm_encoder *encoder);
193 232
194static inline struct psb_intel_encoder *psb_intel_attached_encoder( 233static inline struct psb_intel_encoder *psb_intel_attached_encoder(
195 struct drm_connector *connector) 234 struct drm_connector *connector)
diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h
index f5c19f55bf6e..fcc0af03d685 100644
--- a/drivers/gpu/drm/gma500/psb_intel_reg.h
+++ b/drivers/gpu/drm/gma500/psb_intel_reg.h
@@ -376,6 +376,8 @@
376#define SDVO_PIPE_B_SELECT (1 << 30) 376#define SDVO_PIPE_B_SELECT (1 << 30)
377#define SDVO_STALL_SELECT (1 << 29) 377#define SDVO_STALL_SELECT (1 << 29)
378#define SDVO_INTERRUPT_ENABLE (1 << 26) 378#define SDVO_INTERRUPT_ENABLE (1 << 26)
379#define SDVO_COLOR_RANGE_16_235 (1 << 8)
380#define SDVO_AUDIO_ENABLE (1 << 6)
379 381
380/** 382/**
381 * 915G/GM SDVO pixel multiplier. 383 * 915G/GM SDVO pixel multiplier.
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index a4bad1af4b7c..20d536618701 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -1,76 +1,245 @@
1/* 1/*
2 * Copyright (c) 2006-2007 Intel Corporation 2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
3 * 5 *
4 * This program is free software; you can redistribute it and/or modify it 6 * Permission is hereby granted, free of charge, to any person obtaining a
5 * under the terms and conditions of the GNU General Public License, 7 * copy of this software and associated documentation files (the "Software"),
6 * version 2, as published by the Free Software Foundation. 8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
7 * 12 *
8 * This program is distributed in the hope it will be useful, but WITHOUT 13 * The above copyright notice and this permission notice (including the next
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * paragraph) shall be included in all copies or substantial portions of the
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * Software.
11 * more details.
12 * 16 *
13 * You should have received a copy of the GNU General Public License along with 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * this program; if not, write to the Free Software Foundation, Inc., 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
16 * 24 *
17 * Authors: 25 * Authors:
18 * Eric Anholt <eric@anholt.net> 26 * Eric Anholt <eric@anholt.net>
19 */ 27 */
20 28#include <linux/module.h>
21#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/slab.h>
22#include <linux/delay.h> 31#include <linux/delay.h>
23/* #include <drm/drm_crtc.h> */ 32#include "drmP.h"
24#include <drm/drmP.h> 33#include "drm.h"
25#include "psb_drv.h" 34#include "drm_crtc.h"
35#include "drm_edid.h"
26#include "psb_intel_drv.h" 36#include "psb_intel_drv.h"
27#include "psb_intel_reg.h" 37#include "gma_drm.h"
38#include "psb_drv.h"
28#include "psb_intel_sdvo_regs.h" 39#include "psb_intel_sdvo_regs.h"
40#include "psb_intel_reg.h"
41
42#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
43#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
44#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
45#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
46
47#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
48 SDVO_TV_MASK)
49
50#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
51#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
52#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
53#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
54
55
56static const char *tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
68struct psb_intel_sdvo {
69 struct psb_intel_encoder base;
70
71 struct i2c_adapter *i2c;
72 u8 slave_addr;
73
74 struct i2c_adapter ddc;
29 75
30struct psb_intel_sdvo_priv { 76 /* Register for the SDVO device: SDVOB or SDVOC */
31 struct psb_intel_i2c_chan *i2c_bus; 77 int sdvo_reg;
32 int slaveaddr;
33 int output_device;
34 78
35 u16 active_outputs; 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
36 81
82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
37 struct psb_intel_sdvo_caps caps; 86 struct psb_intel_sdvo_caps caps;
87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
38 int pixel_clock_min, pixel_clock_max; 89 int pixel_clock_min, pixel_clock_max;
39 90
40 int save_sdvo_mult; 91 /*
41 u16 save_active_outputs; 92 * For multiple function SDVO device,
42 struct psb_intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; 93 * this is for current attached outputs.
43 struct psb_intel_sdvo_dtd save_output_dtd[16]; 94 */
44 u32 save_SDVOX; 95 uint16_t attached_output;
45 u8 in_out_map[4]; 96
97 /**
98 * This is used to select the color range of RBG outputs in HDMI mode.
99 * It is only valid when using TMDS encoding and 8 bit per color mode.
100 */
101 uint32_t color_range;
102
103 /**
104 * This is set if we're going to treat the device as TV-out.
105 *
106 * While we have these nice friendly flags for output types that ought
107 * to decide this for us, the S-Video output on our HDMI+S-Video card
108 * shows up as RGB1 (VGA).
109 */
110 bool is_tv;
111
112 /* This is for current tv format name */
113 int tv_format_index;
114
115 /**
116 * This is set if we treat the device as HDMI, instead of DVI.
117 */
118 bool is_hdmi;
119 bool has_hdmi_monitor;
120 bool has_hdmi_audio;
121
122 /**
123 * This is set if we detect output of sdvo device as LVDS and
124 * have a valid fixed mode to use with the panel.
125 */
126 bool is_lvds;
127
128 /**
129 * This is sdvo fixed pannel mode pointer
130 */
131 struct drm_display_mode *sdvo_lvds_fixed_mode;
46 132
47 u8 by_input_wiring; 133 /* DDC bus used by this SDVO encoder */
48 u32 active_device; 134 uint8_t ddc_bus;
135
136 /* Input timings for adjusted_mode */
137 struct psb_intel_sdvo_dtd input_dtd;
49}; 138};
50 139
140struct psb_intel_sdvo_connector {
141 struct psb_intel_connector base;
142
143 /* Mark the type of connector */
144 uint16_t output_flag;
145
146 int force_audio;
147
148 /* This contains all current supported TV format */
149 u8 tv_format_supported[TV_FORMAT_NUM];
150 int format_supported_num;
151 struct drm_property *tv_format;
152
153 /* add the property for the SDVO-TV */
154 struct drm_property *left;
155 struct drm_property *right;
156 struct drm_property *top;
157 struct drm_property *bottom;
158 struct drm_property *hpos;
159 struct drm_property *vpos;
160 struct drm_property *contrast;
161 struct drm_property *saturation;
162 struct drm_property *hue;
163 struct drm_property *sharpness;
164 struct drm_property *flicker_filter;
165 struct drm_property *flicker_filter_adaptive;
166 struct drm_property *flicker_filter_2d;
167 struct drm_property *tv_chroma_filter;
168 struct drm_property *tv_luma_filter;
169 struct drm_property *dot_crawl;
170
171 /* add the property for the SDVO-TV/LVDS */
172 struct drm_property *brightness;
173
174 /* Add variable to record current setting for the above property */
175 u32 left_margin, right_margin, top_margin, bottom_margin;
176
177 /* this is to get the range of margin.*/
178 u32 max_hscan, max_vscan;
179 u32 max_hpos, cur_hpos;
180 u32 max_vpos, cur_vpos;
181 u32 cur_brightness, max_brightness;
182 u32 cur_contrast, max_contrast;
183 u32 cur_saturation, max_saturation;
184 u32 cur_hue, max_hue;
185 u32 cur_sharpness, max_sharpness;
186 u32 cur_flicker_filter, max_flicker_filter;
187 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
188 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
189 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
190 u32 cur_tv_luma_filter, max_tv_luma_filter;
191 u32 cur_dot_crawl, max_dot_crawl;
192};
193
194static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
195{
196 return container_of(encoder, struct psb_intel_sdvo, base.base);
197}
198
199static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
200{
201 return container_of(psb_intel_attached_encoder(connector),
202 struct psb_intel_sdvo, base);
203}
204
205static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
206{
207 return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base);
208}
209
210static bool
211psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
212static bool
213psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
214 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
215 int type);
216static bool
217psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
218 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
219
51/** 220/**
52 * Writes the SDVOB or SDVOC with the given value, but always writes both 221 * Writes the SDVOB or SDVOC with the given value, but always writes both
53 * SDVOB and SDVOC to work around apparent hardware issues (according to 222 * SDVOB and SDVOC to work around apparent hardware issues (according to
54 * comments in the BIOS). 223 * comments in the BIOS).
55 */ 224 */
56void psb_intel_sdvo_write_sdvox(struct psb_intel_output *psb_intel_output, 225static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
57 u32 val)
58{ 226{
59 struct drm_device *dev = psb_intel_output->base.dev; 227 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
60 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
61 u32 bval = val, cval = val; 228 u32 bval = val, cval = val;
62 int i; 229 int i;
63 230
64 if (sdvo_priv->output_device == SDVOB) 231 if (psb_intel_sdvo->sdvo_reg == SDVOB) {
65 cval = REG_READ(SDVOC); 232 cval = REG_READ(SDVOC);
66 else 233 } else {
67 bval = REG_READ(SDVOB); 234 bval = REG_READ(SDVOB);
235 }
68 /* 236 /*
69 * Write the registers twice for luck. Sometimes, 237 * Write the registers twice for luck. Sometimes,
70 * writing them only once doesn't appear to 'stick'. 238 * writing them only once doesn't appear to 'stick'.
71 * The BIOS does this too. Yay, magic 239 * The BIOS does this too. Yay, magic
72 */ 240 */
73 for (i = 0; i < 2; i++) { 241 for (i = 0; i < 2; i++)
242 {
74 REG_WRITE(SDVOB, bval); 243 REG_WRITE(SDVOB, bval);
75 REG_READ(SDVOB); 244 REG_READ(SDVOB);
76 REG_WRITE(SDVOC, cval); 245 REG_WRITE(SDVOC, cval);
@@ -78,61 +247,28 @@ void psb_intel_sdvo_write_sdvox(struct psb_intel_output *psb_intel_output,
78 } 247 }
79} 248}
80 249
81static bool psb_intel_sdvo_read_byte( 250static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
82 struct psb_intel_output *psb_intel_output,
83 u8 addr, u8 *ch)
84{ 251{
85 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
86 u8 out_buf[2];
87 u8 buf[2];
88 int ret;
89
90 struct i2c_msg msgs[] = { 252 struct i2c_msg msgs[] = {
91 { 253 {
92 .addr = sdvo_priv->i2c_bus->slave_addr, 254 .addr = psb_intel_sdvo->slave_addr,
93 .flags = 0, 255 .flags = 0,
94 .len = 1, 256 .len = 1,
95 .buf = out_buf, 257 .buf = &addr,
96 }, 258 },
97 { 259 {
98 .addr = sdvo_priv->i2c_bus->slave_addr, 260 .addr = psb_intel_sdvo->slave_addr,
99 .flags = I2C_M_RD, 261 .flags = I2C_M_RD,
100 .len = 1, 262 .len = 1,
101 .buf = buf, 263 .buf = ch,
102 } 264 }
103 }; 265 };
266 int ret;
104 267
105 out_buf[0] = addr; 268 if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
106 out_buf[1] = 0;
107
108 ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2);
109 if (ret == 2) {
110 *ch = buf[0];
111 return true; 269 return true;
112 }
113 270
114 return false; 271 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
115}
116
117static bool psb_intel_sdvo_write_byte(
118 struct psb_intel_output *psb_intel_output,
119 int addr, u8 ch)
120{
121 u8 out_buf[2];
122 struct i2c_msg msgs[] = {
123 {
124 .addr = psb_intel_output->i2c_bus->slave_addr,
125 .flags = 0,
126 .len = 2,
127 .buf = out_buf,
128 }
129 };
130
131 out_buf[0] = addr;
132 out_buf[1] = ch;
133
134 if (i2c_transfer(&psb_intel_output->i2c_bus->adapter, msgs, 1) == 1)
135 return true;
136 return false; 272 return false;
137} 273}
138 274
@@ -140,98 +276,147 @@ static bool psb_intel_sdvo_write_byte(
140/** Mapping of command numbers to names, for debug output */ 276/** Mapping of command numbers to names, for debug output */
141static const struct _sdvo_cmd_name { 277static const struct _sdvo_cmd_name {
142 u8 cmd; 278 u8 cmd;
143 char *name; 279 const char *name;
144} sdvo_cmd_names[] = { 280} sdvo_cmd_names[] = {
145SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
146 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
147 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
148 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
149 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
150 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
151 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
152 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
153 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
154 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
155 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
156 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
157 SDVO_CMD_NAME_ENTRY 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
158 (SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
161 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
162 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
170 SDVO_CMD_NAME_ENTRY 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
171 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
172 SDVO_CMD_NAME_ENTRY 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
173 (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
174 SDVO_CMD_NAME_ENTRY 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
175 (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
176 SDVO_CMD_NAME_ENTRY 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
177 (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
178 SDVO_CMD_NAME_ENTRY 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
179 (SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
180 SDVO_CMD_NAME_ENTRY 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
181 (SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
182 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
183 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
184 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
185 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
187 SDVO_CMD_NAME_ENTRY 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
188 (SDVO_CMD_SET_TV_RESOLUTION_SUPPORT), 324
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),}; 325 /* Add the op code for SDVO enhancements */
190 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
191#define SDVO_NAME(dev_priv) \ 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
192 ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
193#define SDVO_PRIV(output) ((struct psb_intel_sdvo_priv *) (output)->dev_priv) 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
194 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
195static void psb_intel_sdvo_write_cmd(struct psb_intel_output *psb_intel_output, 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
196 u8 cmd, 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
197 void *args, 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
198 int args_len) 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
199{ 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
200 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv; 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
370
371 /* HDMI op code */
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
392};
393
394#define IS_SDVOB(reg) (reg == SDVOB)
395#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
396
397static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
398 const void *args, int args_len)
399{
201 int i; 400 int i;
202 401
203 if (0) { 402 DRM_DEBUG_KMS("%s: W: %02X ",
204 printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd); 403 SDVO_NAME(psb_intel_sdvo), cmd);
205 for (i = 0; i < args_len; i++) 404 for (i = 0; i < args_len; i++)
206 printk(KERN_CONT "%02X ", ((u8 *) args)[i]); 405 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
207 for (; i < 8; i++) 406 for (; i < 8; i++)
208 printk(KERN_CONT " "); 407 DRM_LOG_KMS(" ");
209 for (i = 0; 408 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
210 i < 409 if (cmd == sdvo_cmd_names[i].cmd) {
211 sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); 410 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
212 i++) { 411 break;
213 if (cmd == sdvo_cmd_names[i].cmd) {
214 printk(KERN_CONT
215 "(%s)", sdvo_cmd_names[i].name);
216 break;
217 }
218 } 412 }
219 if (i ==
220 sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]))
221 printk(KERN_CONT "(%02X)", cmd);
222 printk(KERN_CONT "\n");
223 } 413 }
224 414 if (i == ARRAY_SIZE(sdvo_cmd_names))
225 for (i = 0; i < args_len; i++) { 415 DRM_LOG_KMS("(%02X)", cmd);
226 psb_intel_sdvo_write_byte(psb_intel_output, 416 DRM_LOG_KMS("\n");
227 SDVO_I2C_ARG_0 - i,
228 ((u8 *) args)[i]);
229 }
230
231 psb_intel_sdvo_write_byte(psb_intel_output, SDVO_I2C_OPCODE, cmd);
232} 417}
233 418
234static const char *const cmd_status_names[] = { 419static const char *cmd_status_names[] = {
235 "Power on", 420 "Power on",
236 "Success", 421 "Success",
237 "Not supported", 422 "Not supported",
@@ -241,52 +426,111 @@ static const char *const cmd_status_names[] = {
241 "Scaling not supported" 426 "Scaling not supported"
242}; 427};
243 428
244static u8 psb_intel_sdvo_read_response( 429static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
245 struct psb_intel_output *psb_intel_output, 430 const void *args, int args_len)
246 void *response, int response_len)
247{ 431{
248 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv; 432 u8 buf[args_len*2 + 2], status;
249 int i; 433 struct i2c_msg msgs[args_len + 3];
434 int i, ret;
435
436 psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
437
438 for (i = 0; i < args_len; i++) {
439 msgs[i].addr = psb_intel_sdvo->slave_addr;
440 msgs[i].flags = 0;
441 msgs[i].len = 2;
442 msgs[i].buf = buf + 2 *i;
443 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
444 buf[2*i + 1] = ((u8*)args)[i];
445 }
446 msgs[i].addr = psb_intel_sdvo->slave_addr;
447 msgs[i].flags = 0;
448 msgs[i].len = 2;
449 msgs[i].buf = buf + 2*i;
450 buf[2*i + 0] = SDVO_I2C_OPCODE;
451 buf[2*i + 1] = cmd;
452
453 /* the following two are to read the response */
454 status = SDVO_I2C_CMD_STATUS;
455 msgs[i+1].addr = psb_intel_sdvo->slave_addr;
456 msgs[i+1].flags = 0;
457 msgs[i+1].len = 1;
458 msgs[i+1].buf = &status;
459
460 msgs[i+2].addr = psb_intel_sdvo->slave_addr;
461 msgs[i+2].flags = I2C_M_RD;
462 msgs[i+2].len = 1;
463 msgs[i+2].buf = &status;
464
465 ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
466 if (ret < 0) {
467 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
468 return false;
469 }
470 if (ret != i+3) {
471 /* failure in I2C transfer */
472 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
473 return false;
474 }
475
476 return true;
477}
478
479static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
480 void *response, int response_len)
481{
482 u8 retry = 5;
250 u8 status; 483 u8 status;
251 u8 retry = 50; 484 int i;
252
253 while (retry--) {
254 /* Read the command response */
255 for (i = 0; i < response_len; i++) {
256 psb_intel_sdvo_read_byte(psb_intel_output,
257 SDVO_I2C_RETURN_0 + i,
258 &((u8 *) response)[i]);
259 }
260 485
261 /* read the return status */ 486 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
262 psb_intel_sdvo_read_byte(psb_intel_output, 487
263 SDVO_I2C_CMD_STATUS, 488 /*
264 &status); 489 * The documentation states that all commands will be
265 490 * processed within 15µs, and that we need only poll
266 if (0) { 491 * the status byte a maximum of 3 times in order for the
267 pr_debug("%s: R: ", SDVO_NAME(sdvo_priv)); 492 * command to be complete.
268 for (i = 0; i < response_len; i++) 493 *
269 printk(KERN_CONT "%02X ", ((u8 *) response)[i]); 494 * Check 5 times in case the hardware failed to read the docs.
270 for (; i < 8; i++) 495 */
271 printk(" "); 496 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
272 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 497 SDVO_I2C_CMD_STATUS,
273 printk(KERN_CONT "(%s)", 498 &status))
274 cmd_status_names[status]); 499 goto log_fail;
275 else 500
276 printk(KERN_CONT "(??? %d)", status); 501 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
277 printk(KERN_CONT "\n"); 502 udelay(15);
278 } 503 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
504 SDVO_I2C_CMD_STATUS,
505 &status))
506 goto log_fail;
507 }
279 508
280 if (status != SDVO_CMD_STATUS_PENDING) 509 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
281 return status; 510 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
511 else
512 DRM_LOG_KMS("(??? %d)", status);
282 513
283 mdelay(50); 514 if (status != SDVO_CMD_STATUS_SUCCESS)
515 goto log_fail;
516
517 /* Read the command response */
518 for (i = 0; i < response_len; i++) {
519 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
520 SDVO_I2C_RETURN_0 + i,
521 &((u8 *)response)[i]))
522 goto log_fail;
523 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
284 } 524 }
525 DRM_LOG_KMS("\n");
526 return true;
285 527
286 return status; 528log_fail:
529 DRM_LOG_KMS("... failed\n");
530 return false;
287} 531}
288 532
289int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 533static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
290{ 534{
291 if (mode->clock >= 100000) 535 if (mode->clock >= 100000)
292 return 1; 536 return 1;
@@ -296,40 +540,38 @@ int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
296 return 4; 540 return 4;
297} 541}
298 542
299/** 543static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
300 * Don't check status code from this as it switches the bus back to the 544 u8 ddc_bus)
301 * SDVO chips which defeats the purpose of doing a bus switch in the first
302 * place.
303 */
304void psb_intel_sdvo_set_control_bus_switch(
305 struct psb_intel_output *psb_intel_output,
306 u8 target)
307{ 545{
308 psb_intel_sdvo_write_cmd(psb_intel_output, 546 /* This must be the immediately preceding write before the i2c xfer */
309 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 547 return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
310 &target, 548 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
311 1); 549 &ddc_bus, 1);
312} 550}
313 551
314static bool psb_intel_sdvo_set_target_input( 552static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
315 struct psb_intel_output *psb_intel_output,
316 bool target_0, bool target_1)
317{ 553{
318 struct psb_intel_sdvo_set_target_input_args targets = { 0 }; 554 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
319 u8 status; 555 return false;
320
321 if (target_0 && target_1)
322 return SDVO_CMD_STATUS_NOTSUPP;
323 556
324 if (target_1) 557 return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
325 targets.target_1 = 1; 558}
326 559
327 psb_intel_sdvo_write_cmd(psb_intel_output, SDVO_CMD_SET_TARGET_INPUT, 560static bool
328 &targets, sizeof(targets)); 561psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
562{
563 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
564 return false;
329 565
330 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0); 566 return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
567}
331 568
332 return status == SDVO_CMD_STATUS_SUCCESS; 569static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
570{
571 struct psb_intel_sdvo_set_target_input_args targets = {0};
572 return psb_intel_sdvo_set_value(psb_intel_sdvo,
573 SDVO_CMD_SET_TARGET_INPUT,
574 &targets, sizeof(targets));
333} 575}
334 576
335/** 577/**
@@ -338,19 +580,13 @@ static bool psb_intel_sdvo_set_target_input(
338 * This function is making an assumption about the layout of the response, 580 * This function is making an assumption about the layout of the response,
339 * which should be checked against the docs. 581 * which should be checked against the docs.
340 */ 582 */
341static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_output 583static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
342 *psb_intel_output, bool *input_1,
343 bool *input_2)
344{ 584{
345 struct psb_intel_sdvo_get_trained_inputs_response response; 585 struct psb_intel_sdvo_get_trained_inputs_response response;
346 u8 status;
347 586
348 psb_intel_sdvo_write_cmd(psb_intel_output, SDVO_CMD_GET_TRAINED_INPUTS, 587 BUILD_BUG_ON(sizeof(response) != 1);
349 NULL, 0); 588 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
350 status = 589 &response, sizeof(response)))
351 psb_intel_sdvo_read_response(psb_intel_output, &response,
352 sizeof(response));
353 if (status != SDVO_CMD_STATUS_SUCCESS)
354 return false; 590 return false;
355 591
356 *input_1 = response.input0_trained; 592 *input_1 = response.input0_trained;
@@ -358,35 +594,18 @@ static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_output
358 return true; 594 return true;
359} 595}
360 596
361static bool psb_intel_sdvo_get_active_outputs(struct psb_intel_output 597static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
362 *psb_intel_output, u16 *outputs) 598 u16 outputs)
363{ 599{
364 u8 status; 600 return psb_intel_sdvo_set_value(psb_intel_sdvo,
365 601 SDVO_CMD_SET_ACTIVE_OUTPUTS,
366 psb_intel_sdvo_write_cmd(psb_intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, 602 &outputs, sizeof(outputs));
367 NULL, 0);
368 status =
369 psb_intel_sdvo_read_response(psb_intel_output, outputs,
370 sizeof(*outputs));
371
372 return status == SDVO_CMD_STATUS_SUCCESS;
373} 603}
374 604
375static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_output 605static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
376 *psb_intel_output, u16 outputs) 606 int mode)
377{ 607{
378 u8 status; 608 u8 state = SDVO_ENCODER_STATE_ON;
379
380 psb_intel_sdvo_write_cmd(psb_intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS,
381 &outputs, sizeof(outputs));
382 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0);
383 return status == SDVO_CMD_STATUS_SUCCESS;
384}
385
386static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_output
387 *psb_intel_output, int mode)
388{
389 u8 status, state = SDVO_ENCODER_STATE_ON;
390 609
391 switch (mode) { 610 switch (mode) {
392 case DRM_MODE_DPMS_ON: 611 case DRM_MODE_DPMS_ON:
@@ -403,260 +622,360 @@ static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_output
403 break; 622 break;
404 } 623 }
405 624
406 psb_intel_sdvo_write_cmd(psb_intel_output, 625 return psb_intel_sdvo_set_value(psb_intel_sdvo,
407 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, 626 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
408 sizeof(state));
409 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0);
410
411 return status == SDVO_CMD_STATUS_SUCCESS;
412} 627}
413 628
414static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_output 629static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
415 *psb_intel_output,
416 int *clock_min, 630 int *clock_min,
417 int *clock_max) 631 int *clock_max)
418{ 632{
419 struct psb_intel_sdvo_pixel_clock_range clocks; 633 struct psb_intel_sdvo_pixel_clock_range clocks;
420 u8 status;
421
422 psb_intel_sdvo_write_cmd(psb_intel_output,
423 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, NULL,
424 0);
425
426 status =
427 psb_intel_sdvo_read_response(psb_intel_output, &clocks,
428 sizeof(clocks));
429 634
430 if (status != SDVO_CMD_STATUS_SUCCESS) 635 BUILD_BUG_ON(sizeof(clocks) != 4);
636 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
637 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
638 &clocks, sizeof(clocks)))
431 return false; 639 return false;
432 640
433 /* Convert the values from units of 10 kHz to kHz. */ 641 /* Convert the values from units of 10 kHz to kHz. */
434 *clock_min = clocks.min * 10; 642 *clock_min = clocks.min * 10;
435 *clock_max = clocks.max * 10; 643 *clock_max = clocks.max * 10;
436
437 return true; 644 return true;
438} 645}
439 646
440static bool psb_intel_sdvo_set_target_output( 647static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
441 struct psb_intel_output *psb_intel_output, 648 u16 outputs)
442 u16 outputs)
443{ 649{
444 u8 status; 650 return psb_intel_sdvo_set_value(psb_intel_sdvo,
445 651 SDVO_CMD_SET_TARGET_OUTPUT,
446 psb_intel_sdvo_write_cmd(psb_intel_output, SDVO_CMD_SET_TARGET_OUTPUT, 652 &outputs, sizeof(outputs));
447 &outputs, sizeof(outputs)); 653}
448 654
449 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0); 655static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
450 return status == SDVO_CMD_STATUS_SUCCESS; 656 struct psb_intel_sdvo_dtd *dtd)
657{
658 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
659 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
451} 660}
452 661
453static bool psb_intel_sdvo_get_timing(struct psb_intel_output *psb_intel_output, 662static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
454 u8 cmd, struct psb_intel_sdvo_dtd *dtd) 663 struct psb_intel_sdvo_dtd *dtd)
455{ 664{
456 u8 status; 665 return psb_intel_sdvo_set_timing(psb_intel_sdvo,
666 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
667}
457 668
458 psb_intel_sdvo_write_cmd(psb_intel_output, cmd, NULL, 0); 669static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
459 status = psb_intel_sdvo_read_response(psb_intel_output, &dtd->part1, 670 struct psb_intel_sdvo_dtd *dtd)
460 sizeof(dtd->part1)); 671{
461 if (status != SDVO_CMD_STATUS_SUCCESS) 672 return psb_intel_sdvo_set_timing(psb_intel_sdvo,
462 return false; 673 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
674}
463 675
464 psb_intel_sdvo_write_cmd(psb_intel_output, cmd + 1, NULL, 0); 676static bool
465 status = psb_intel_sdvo_read_response(psb_intel_output, &dtd->part2, 677psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
466 sizeof(dtd->part2)); 678 uint16_t clock,
467 if (status != SDVO_CMD_STATUS_SUCCESS) 679 uint16_t width,
468 return false; 680 uint16_t height)
681{
682 struct psb_intel_sdvo_preferred_input_timing_args args;
683
684 memset(&args, 0, sizeof(args));
685 args.clock = clock;
686 args.width = width;
687 args.height = height;
688 args.interlace = 0;
689
690 if (psb_intel_sdvo->is_lvds &&
691 (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
692 psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
693 args.scaled = 1;
694
695 return psb_intel_sdvo_set_value(psb_intel_sdvo,
696 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
697 &args, sizeof(args));
698}
469 699
470 return true; 700static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
701 struct psb_intel_sdvo_dtd *dtd)
702{
703 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
704 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
705 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
706 &dtd->part1, sizeof(dtd->part1)) &&
707 psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
708 &dtd->part2, sizeof(dtd->part2));
471} 709}
472 710
473static bool psb_intel_sdvo_get_input_timing( 711static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
474 struct psb_intel_output *psb_intel_output,
475 struct psb_intel_sdvo_dtd *dtd)
476{ 712{
477 return psb_intel_sdvo_get_timing(psb_intel_output, 713 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
478 SDVO_CMD_GET_INPUT_TIMINGS_PART1,
479 dtd);
480} 714}
481 715
482static bool psb_intel_sdvo_set_timing( 716static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
483 struct psb_intel_output *psb_intel_output, 717 const struct drm_display_mode *mode)
484 u8 cmd,
485 struct psb_intel_sdvo_dtd *dtd)
486{ 718{
487 u8 status; 719 uint16_t width, height;
720 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
721 uint16_t h_sync_offset, v_sync_offset;
488 722
489 psb_intel_sdvo_write_cmd(psb_intel_output, cmd, &dtd->part1, 723 width = mode->crtc_hdisplay;
490 sizeof(dtd->part1)); 724 height = mode->crtc_vdisplay;
491 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0);
492 if (status != SDVO_CMD_STATUS_SUCCESS)
493 return false;
494 725
495 psb_intel_sdvo_write_cmd(psb_intel_output, cmd + 1, &dtd->part2, 726 /* do some mode translations */
496 sizeof(dtd->part2)); 727 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
497 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0); 728 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
498 if (status != SDVO_CMD_STATUS_SUCCESS)
499 return false;
500 729
501 return true; 730 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
731 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
732
733 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
734 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
735
736 dtd->part1.clock = mode->clock / 10;
737 dtd->part1.h_active = width & 0xff;
738 dtd->part1.h_blank = h_blank_len & 0xff;
739 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
740 ((h_blank_len >> 8) & 0xf);
741 dtd->part1.v_active = height & 0xff;
742 dtd->part1.v_blank = v_blank_len & 0xff;
743 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
744 ((v_blank_len >> 8) & 0xf);
745
746 dtd->part2.h_sync_off = h_sync_offset & 0xff;
747 dtd->part2.h_sync_width = h_sync_len & 0xff;
748 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
749 (v_sync_len & 0xf);
750 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
751 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
752 ((v_sync_len & 0x30) >> 4);
753
754 dtd->part2.dtd_flags = 0x18;
755 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
756 dtd->part2.dtd_flags |= 0x2;
757 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
758 dtd->part2.dtd_flags |= 0x4;
759
760 dtd->part2.sdvo_flags = 0;
761 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
762 dtd->part2.reserved = 0;
502} 763}
503 764
504static bool psb_intel_sdvo_set_input_timing( 765static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
505 struct psb_intel_output *psb_intel_output, 766 const struct psb_intel_sdvo_dtd *dtd)
506 struct psb_intel_sdvo_dtd *dtd)
507{ 767{
508 return psb_intel_sdvo_set_timing(psb_intel_output, 768 mode->hdisplay = dtd->part1.h_active;
509 SDVO_CMD_SET_INPUT_TIMINGS_PART1, 769 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
510 dtd); 770 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
771 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
772 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
773 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
774 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
775 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
776
777 mode->vdisplay = dtd->part1.v_active;
778 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
779 mode->vsync_start = mode->vdisplay;
780 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
781 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
782 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
783 mode->vsync_end = mode->vsync_start +
784 (dtd->part2.v_sync_off_width & 0xf);
785 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
786 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
787 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
788
789 mode->clock = dtd->part1.clock * 10;
790
791 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
792 if (dtd->part2.dtd_flags & 0x2)
793 mode->flags |= DRM_MODE_FLAG_PHSYNC;
794 if (dtd->part2.dtd_flags & 0x4)
795 mode->flags |= DRM_MODE_FLAG_PVSYNC;
511} 796}
512 797
513static bool psb_intel_sdvo_set_output_timing( 798static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
514 struct psb_intel_output *psb_intel_output,
515 struct psb_intel_sdvo_dtd *dtd)
516{ 799{
517 return psb_intel_sdvo_set_timing(psb_intel_output, 800 struct psb_intel_sdvo_encode encode;
518 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, 801
519 dtd); 802 BUILD_BUG_ON(sizeof(encode) != 2);
803 return psb_intel_sdvo_get_value(psb_intel_sdvo,
804 SDVO_CMD_GET_SUPP_ENCODE,
805 &encode, sizeof(encode));
520} 806}
521 807
522static int psb_intel_sdvo_get_clock_rate_mult(struct psb_intel_output 808static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
523 *psb_intel_output) 809 uint8_t mode)
524{ 810{
525 u8 response, status; 811 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
526 812}
527 psb_intel_sdvo_write_cmd(psb_intel_output,
528 SDVO_CMD_GET_CLOCK_RATE_MULT,
529 NULL,
530 0);
531 813
532 status = psb_intel_sdvo_read_response(psb_intel_output, &response, 1); 814static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
815 uint8_t mode)
816{
817 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
818}
533 819
534 if (status != SDVO_CMD_STATUS_SUCCESS) { 820#if 0
535 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); 821static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
536 return SDVO_CLOCK_RATE_MULT_1X; 822{
537 } else { 823 int i, j;
538 DRM_DEBUG("Current clock rate multiplier: %d\n", response); 824 uint8_t set_buf_index[2];
825 uint8_t av_split;
826 uint8_t buf_size;
827 uint8_t buf[48];
828 uint8_t *pos;
829
830 psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
831
832 for (i = 0; i <= av_split; i++) {
833 set_buf_index[0] = i; set_buf_index[1] = 0;
834 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
835 set_buf_index, 2);
836 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
837 psb_intel_sdvo_read_response(encoder, &buf_size, 1);
838
839 pos = buf;
840 for (j = 0; j <= buf_size; j += 8) {
841 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
842 NULL, 0);
843 psb_intel_sdvo_read_response(encoder, pos, 8);
844 pos += 8;
845 }
539 } 846 }
540
541 return response;
542} 847}
848#endif
543 849
544static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_output 850static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
545 *psb_intel_output, u8 val)
546{ 851{
547 u8 status; 852 DRM_INFO("HDMI is not supported yet");
548 853
549 psb_intel_sdvo_write_cmd(psb_intel_output, 854 return false;
550 SDVO_CMD_SET_CLOCK_RATE_MULT, 855#if 0
551 &val, 856 struct dip_infoframe avi_if = {
552 1); 857 .type = DIP_TYPE_AVI,
858 .ver = DIP_VERSION_AVI,
859 .len = DIP_LEN_AVI,
860 };
861 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
862 uint8_t set_buf_index[2] = { 1, 0 };
863 uint64_t *data = (uint64_t *)&avi_if;
864 unsigned i;
553 865
554 status = psb_intel_sdvo_read_response(psb_intel_output, NULL, 0); 866 intel_dip_infoframe_csum(&avi_if);
555 if (status != SDVO_CMD_STATUS_SUCCESS) 867
868 if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
869 SDVO_CMD_SET_HBUF_INDEX,
870 set_buf_index, 2))
556 return false; 871 return false;
557 872
558 return true; 873 for (i = 0; i < sizeof(avi_if); i += 8) {
874 if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
875 SDVO_CMD_SET_HBUF_DATA,
876 data, 8))
877 return false;
878 data++;
879 }
880
881 return psb_intel_sdvo_set_value(psb_intel_sdvo,
882 SDVO_CMD_SET_HBUF_TXRATE,
883 &tx_rate, 1);
884#endif
559} 885}
560 886
561static bool psb_sdvo_set_current_inoutmap(struct psb_intel_output *output, 887static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
562 u32 in0outputmask,
563 u32 in1outputmask)
564{ 888{
565 u8 byArgs[4]; 889 struct psb_intel_sdvo_tv_format format;
566 u8 status; 890 uint32_t format_map;
567 int i;
568 struct psb_intel_sdvo_priv *sdvo_priv = output->dev_priv;
569
570 /* Make all fields of the args/ret to zero */
571 memset(byArgs, 0, sizeof(byArgs));
572 891
573 /* Fill up the argument values; */ 892 format_map = 1 << psb_intel_sdvo->tv_format_index;
574 byArgs[0] = (u8) (in0outputmask & 0xFF); 893 memset(&format, 0, sizeof(format));
575 byArgs[1] = (u8) ((in0outputmask >> 8) & 0xFF); 894 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
576 byArgs[2] = (u8) (in1outputmask & 0xFF);
577 byArgs[3] = (u8) ((in1outputmask >> 8) & 0xFF);
578 895
896 BUILD_BUG_ON(sizeof(format) != 6);
897 return psb_intel_sdvo_set_value(psb_intel_sdvo,
898 SDVO_CMD_SET_TV_FORMAT,
899 &format, sizeof(format));
900}
579 901
580 /*save inoutmap arg here*/ 902static bool
581 for (i = 0; i < 4; i++) 903psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
582 sdvo_priv->in_out_map[i] = byArgs[0]; 904 struct drm_display_mode *mode)
905{
906 struct psb_intel_sdvo_dtd output_dtd;
583 907
584 psb_intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP, byArgs, 4); 908 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
585 status = psb_intel_sdvo_read_response(output, NULL, 0); 909 psb_intel_sdvo->attached_output))
910 return false;
586 911
587 if (status != SDVO_CMD_STATUS_SUCCESS) 912 psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
913 if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
588 return false; 914 return false;
915
589 return true; 916 return true;
590} 917}
591 918
592 919static bool
593static void psb_intel_sdvo_set_iomap(struct psb_intel_output *output) 920psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
921 struct drm_display_mode *mode,
922 struct drm_display_mode *adjusted_mode)
594{ 923{
595 u32 dwCurrentSDVOIn0 = 0; 924 /* Reset the input timing to the screen. Assume always input 0. */
596 u32 dwCurrentSDVOIn1 = 0; 925 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
597 u32 dwDevMask = 0; 926 return false;
598 927
928 if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
929 mode->clock / 10,
930 mode->hdisplay,
931 mode->vdisplay))
932 return false;
599 933
600 struct psb_intel_sdvo_priv *sdvo_priv = output->dev_priv; 934 if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
935 &psb_intel_sdvo->input_dtd))
936 return false;
601 937
602 /* Please DO NOT change the following code. */ 938 psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
603 /* SDVOB_IN0 or SDVOB_IN1 ==> sdvo_in0 */
604 /* SDVOC_IN0 or SDVOC_IN1 ==> sdvo_in1 */
605 if (sdvo_priv->by_input_wiring & (SDVOB_IN0 | SDVOC_IN0)) {
606 switch (sdvo_priv->active_device) {
607 case SDVO_DEVICE_LVDS:
608 dwDevMask = SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1;
609 break;
610 case SDVO_DEVICE_TMDS:
611 dwDevMask = SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1;
612 break;
613 case SDVO_DEVICE_TV:
614 dwDevMask =
615 SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_SVID0 |
616 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB1 |
617 SDVO_OUTPUT_SVID1 | SDVO_OUTPUT_CVBS1 |
618 SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1;
619 break;
620 case SDVO_DEVICE_CRT:
621 dwDevMask = SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1;
622 break;
623 }
624 dwCurrentSDVOIn0 = (sdvo_priv->active_outputs & dwDevMask);
625 } else if (sdvo_priv->by_input_wiring & (SDVOB_IN1 | SDVOC_IN1)) {
626 switch (sdvo_priv->active_device) {
627 case SDVO_DEVICE_LVDS:
628 dwDevMask = SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1;
629 break;
630 case SDVO_DEVICE_TMDS:
631 dwDevMask = SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1;
632 break;
633 case SDVO_DEVICE_TV:
634 dwDevMask =
635 SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_SVID0 |
636 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB1 |
637 SDVO_OUTPUT_SVID1 | SDVO_OUTPUT_CVBS1 |
638 SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1;
639 break;
640 case SDVO_DEVICE_CRT:
641 dwDevMask = SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1;
642 break;
643 }
644 dwCurrentSDVOIn1 = (sdvo_priv->active_outputs & dwDevMask);
645 }
646 939
647 psb_sdvo_set_current_inoutmap(output, dwCurrentSDVOIn0, 940 drm_mode_set_crtcinfo(adjusted_mode, 0);
648 dwCurrentSDVOIn1); 941 return true;
649} 942}
650 943
651
652static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder, 944static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
653 struct drm_display_mode *mode, 945 struct drm_display_mode *mode,
654 struct drm_display_mode *adjusted_mode) 946 struct drm_display_mode *adjusted_mode)
655{ 947{
656 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO 948 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
657 * device will be told of the multiplier during mode_set. 949 int multiplier;
950
951 /* We need to construct preferred input timings based on our
952 * output timings. To do that, we have to set the output
953 * timings, even though this isn't really the right place in
954 * the sequence to do it. Oh well.
658 */ 955 */
659 adjusted_mode->clock *= psb_intel_sdvo_get_pixel_multiplier(mode); 956 if (psb_intel_sdvo->is_tv) {
957 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
958 return false;
959
960 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
961 mode,
962 adjusted_mode);
963 } else if (psb_intel_sdvo->is_lvds) {
964 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
965 psb_intel_sdvo->sdvo_lvds_fixed_mode))
966 return false;
967
968 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
969 mode,
970 adjusted_mode);
971 }
972
973 /* Make the CRTC code factor in the SDVO pixel multiplier. The
974 * SDVO device will factor out the multiplier during mode_set.
975 */
976 multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
977 psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
978
660 return true; 979 return true;
661} 980}
662 981
@@ -667,96 +986,79 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
667 struct drm_device *dev = encoder->dev; 986 struct drm_device *dev = encoder->dev;
668 struct drm_crtc *crtc = encoder->crtc; 987 struct drm_crtc *crtc = encoder->crtc;
669 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 988 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
670 struct psb_intel_output *psb_intel_output = 989 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
671 enc_to_psb_intel_output(encoder);
672 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
673 u16 width, height;
674 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
675 u16 h_sync_offset, v_sync_offset;
676 u32 sdvox; 990 u32 sdvox;
677 struct psb_intel_sdvo_dtd output_dtd; 991 struct psb_intel_sdvo_in_out_map in_out;
678 int sdvo_pixel_multiply; 992 struct psb_intel_sdvo_dtd input_dtd;
993 int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
994 int rate;
679 995
680 if (!mode) 996 if (!mode)
681 return; 997 return;
682 998
683 psb_intel_sdvo_set_target_output(psb_intel_output, 0); 999 /* First, set the input mapping for the first input to our controlled
684 1000 * output. This is only correct if we're a single-input device, in
685 width = mode->crtc_hdisplay; 1001 * which case the first input is the output from the appropriate SDVO
686 height = mode->crtc_vdisplay; 1002 * channel on the motherboard. In a two-input device, the first input
687 1003 * will be SDVOB and the second SDVOC.
688 /* do some mode translations */ 1004 */
689 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; 1005 in_out.in0 = psb_intel_sdvo->attached_output;
690 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1006 in_out.in1 = 0;
691
692 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
693 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
694 1007
695 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; 1008 psb_intel_sdvo_set_value(psb_intel_sdvo,
696 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; 1009 SDVO_CMD_SET_IN_OUT_MAP,
1010 &in_out, sizeof(in_out));
697 1011
698 output_dtd.part1.clock = mode->clock / 10; 1012 /* Set the output timings to the screen */
699 output_dtd.part1.h_active = width & 0xff; 1013 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
700 output_dtd.part1.h_blank = h_blank_len & 0xff; 1014 psb_intel_sdvo->attached_output))
701 output_dtd.part1.h_high = (((width >> 8) & 0xf) << 4) | 1015 return;
702 ((h_blank_len >> 8) & 0xf);
703 output_dtd.part1.v_active = height & 0xff;
704 output_dtd.part1.v_blank = v_blank_len & 0xff;
705 output_dtd.part1.v_high = (((height >> 8) & 0xf) << 4) |
706 ((v_blank_len >> 8) & 0xf);
707
708 output_dtd.part2.h_sync_off = h_sync_offset;
709 output_dtd.part2.h_sync_width = h_sync_len & 0xff;
710 output_dtd.part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
711 (v_sync_len & 0xf);
712 output_dtd.part2.sync_off_width_high =
713 ((h_sync_offset & 0x300) >> 2) | ((h_sync_len & 0x300) >> 4) |
714 ((v_sync_offset & 0x30) >> 2) | ((v_sync_len & 0x30) >> 4);
715
716 output_dtd.part2.dtd_flags = 0x18;
717 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
718 output_dtd.part2.dtd_flags |= 0x2;
719 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
720 output_dtd.part2.dtd_flags |= 0x4;
721 1016
722 output_dtd.part2.sdvo_flags = 0; 1017 /* We have tried to get input timing in mode_fixup, and filled into
723 output_dtd.part2.v_sync_off_high = v_sync_offset & 0xc0; 1018 * adjusted_mode.
724 output_dtd.part2.reserved = 0; 1019 */
1020 if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
1021 input_dtd = psb_intel_sdvo->input_dtd;
1022 } else {
1023 /* Set the output timing to the screen */
1024 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
1025 psb_intel_sdvo->attached_output))
1026 return;
725 1027
726 /* Set the output timing to the screen */ 1028 psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
727 psb_intel_sdvo_set_target_output(psb_intel_output, 1029 (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
728 sdvo_priv->active_outputs); 1030 }
729 1031
730 /* Set the input timing to the screen. Assume always input 0. */ 1032 /* Set the input timing to the screen. Assume always input 0. */
731 psb_intel_sdvo_set_target_input(psb_intel_output, true, false); 1033 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
1034 return;
732 1035
733 psb_intel_sdvo_set_output_timing(psb_intel_output, &output_dtd); 1036 if (psb_intel_sdvo->has_hdmi_monitor) {
1037 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
1038 psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
1039 SDVO_COLORIMETRY_RGB256);
1040 psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
1041 } else
1042 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
734 1043
735 /* We would like to use i830_sdvo_create_preferred_input_timing() to 1044 if (psb_intel_sdvo->is_tv &&
736 * provide the device with a timing it can support, if it supports that 1045 !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
737 * feature. However, presumably we would need to adjust the CRTC to 1046 return;
738 * output the preferred timing, and we don't support that currently.
739 */
740 psb_intel_sdvo_set_input_timing(psb_intel_output, &output_dtd);
741 1047
742 switch (psb_intel_sdvo_get_pixel_multiplier(mode)) { 1048 (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
743 case 1: 1049
744 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output, 1050 switch (pixel_multiplier) {
745 SDVO_CLOCK_RATE_MULT_1X); 1051 default:
746 break; 1052 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
747 case 2: 1053 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
748 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output, 1054 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
749 SDVO_CLOCK_RATE_MULT_2X);
750 break;
751 case 4:
752 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output,
753 SDVO_CLOCK_RATE_MULT_4X);
754 break;
755 } 1055 }
1056 if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
1057 return;
756 1058
757 /* Set the SDVO control regs. */ 1059 /* Set the SDVO control regs. */
758 sdvox = REG_READ(sdvo_priv->output_device); 1060 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
759 switch (sdvo_priv->output_device) { 1061 switch (psb_intel_sdvo->sdvo_reg) {
760 case SDVOB: 1062 case SDVOB:
761 sdvox &= SDVOB_PRESERVE_MASK; 1063 sdvox &= SDVOB_PRESERVE_MASK;
762 break; 1064 break;
@@ -765,37 +1067,47 @@ static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
765 break; 1067 break;
766 } 1068 }
767 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1069 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1070
768 if (psb_intel_crtc->pipe == 1) 1071 if (psb_intel_crtc->pipe == 1)
769 sdvox |= SDVO_PIPE_B_SELECT; 1072 sdvox |= SDVO_PIPE_B_SELECT;
1073 if (psb_intel_sdvo->has_hdmi_audio)
1074 sdvox |= SDVO_AUDIO_ENABLE;
770 1075
771 sdvo_pixel_multiply = psb_intel_sdvo_get_pixel_multiplier(mode); 1076 /* FIXME: Check if this is needed for PSB
772 1077 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
773 psb_intel_sdvo_write_sdvox(psb_intel_output, sdvox); 1078 */
774 1079
775 psb_intel_sdvo_set_iomap(psb_intel_output); 1080 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
1081 sdvox |= SDVO_STALL_SELECT;
1082 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
776} 1083}
777 1084
778static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1085static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
779{ 1086{
780 struct drm_device *dev = encoder->dev; 1087 struct drm_device *dev = encoder->dev;
781 struct psb_intel_output *psb_intel_output = 1088 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
782 enc_to_psb_intel_output(encoder);
783 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
784 u32 temp; 1089 u32 temp;
785 1090
1091 switch (mode) {
1092 case DRM_MODE_DPMS_ON:
1093 DRM_DEBUG("DPMS_ON");
1094 break;
1095 case DRM_MODE_DPMS_OFF:
1096 DRM_DEBUG("DPMS_OFF");
1097 break;
1098 default:
1099 DRM_DEBUG("DPMS: %d", mode);
1100 }
1101
786 if (mode != DRM_MODE_DPMS_ON) { 1102 if (mode != DRM_MODE_DPMS_ON) {
787 psb_intel_sdvo_set_active_outputs(psb_intel_output, 0); 1103 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
788 if (0) 1104 if (0)
789 psb_intel_sdvo_set_encoder_power_state( 1105 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
790 psb_intel_output,
791 mode);
792 1106
793 if (mode == DRM_MODE_DPMS_OFF) { 1107 if (mode == DRM_MODE_DPMS_OFF) {
794 temp = REG_READ(sdvo_priv->output_device); 1108 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
795 if ((temp & SDVO_ENABLE) != 0) { 1109 if ((temp & SDVO_ENABLE) != 0) {
796 psb_intel_sdvo_write_sdvox(psb_intel_output, 1110 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
797 temp &
798 ~SDVO_ENABLE);
799 } 1111 }
800 } 1112 }
801 } else { 1113 } else {
@@ -803,185 +1115,112 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
803 int i; 1115 int i;
804 u8 status; 1116 u8 status;
805 1117
806 temp = REG_READ(sdvo_priv->output_device); 1118 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
807 if ((temp & SDVO_ENABLE) == 0) 1119 if ((temp & SDVO_ENABLE) == 0)
808 psb_intel_sdvo_write_sdvox(psb_intel_output, 1120 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
809 temp | SDVO_ENABLE);
810 for (i = 0; i < 2; i++) 1121 for (i = 0; i < 2; i++)
811 psb_intel_wait_for_vblank(dev); 1122 psb_intel_wait_for_vblank(dev);
812 1123
813 status = 1124 status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
814 psb_intel_sdvo_get_trained_inputs(psb_intel_output,
815 &input1,
816 &input2);
817
818
819 /* Warn if the device reported failure to sync. 1125 /* Warn if the device reported failure to sync.
820 * A lot of SDVO devices fail to notify of sync, but it's 1126 * A lot of SDVO devices fail to notify of sync, but it's
821 * a given it the status is a success, we succeeded. 1127 * a given it the status is a success, we succeeded.
822 */ 1128 */
823 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1129 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
824 DRM_DEBUG 1130 DRM_DEBUG_KMS("First %s output reported failure to "
825 ("First %s output reported failure to sync\n", 1131 "sync\n", SDVO_NAME(psb_intel_sdvo));
826 SDVO_NAME(sdvo_priv));
827 } 1132 }
828 1133
829 if (0) 1134 if (0)
830 psb_intel_sdvo_set_encoder_power_state( 1135 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
831 psb_intel_output, 1136 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
832 mode);
833 psb_intel_sdvo_set_active_outputs(psb_intel_output,
834 sdvo_priv->active_outputs);
835 } 1137 }
836 return; 1138 return;
837} 1139}
838 1140
839static void psb_intel_sdvo_save(struct drm_connector *connector)
840{
841 struct drm_device *dev = connector->dev;
842 struct psb_intel_output *psb_intel_output =
843 to_psb_intel_output(connector);
844 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
845 /*int o;*/
846
847 sdvo_priv->save_sdvo_mult =
848 psb_intel_sdvo_get_clock_rate_mult(psb_intel_output);
849 psb_intel_sdvo_get_active_outputs(psb_intel_output,
850 &sdvo_priv->save_active_outputs);
851
852 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
853 psb_intel_sdvo_set_target_input(psb_intel_output,
854 true,
855 false);
856 psb_intel_sdvo_get_input_timing(psb_intel_output,
857 &sdvo_priv->save_input_dtd_1);
858 }
859
860 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
861 psb_intel_sdvo_set_target_input(psb_intel_output,
862 false,
863 true);
864 psb_intel_sdvo_get_input_timing(psb_intel_output,
865 &sdvo_priv->save_input_dtd_2);
866 }
867 sdvo_priv->save_SDVOX = REG_READ(sdvo_priv->output_device);
868
869 /*TODO: save the in_out_map state*/
870}
871
872static void psb_intel_sdvo_restore(struct drm_connector *connector)
873{
874 struct drm_device *dev = connector->dev;
875 struct psb_intel_output *psb_intel_output =
876 to_psb_intel_output(connector);
877 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
878 /*int o;*/
879 int i;
880 bool input1, input2;
881 u8 status;
882
883 psb_intel_sdvo_set_active_outputs(psb_intel_output, 0);
884
885 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
886 psb_intel_sdvo_set_target_input(psb_intel_output, true, false);
887 psb_intel_sdvo_set_input_timing(psb_intel_output,
888 &sdvo_priv->save_input_dtd_1);
889 }
890
891 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
892 psb_intel_sdvo_set_target_input(psb_intel_output, false, true);
893 psb_intel_sdvo_set_input_timing(psb_intel_output,
894 &sdvo_priv->save_input_dtd_2);
895 }
896
897 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output,
898 sdvo_priv->save_sdvo_mult);
899
900 REG_WRITE(sdvo_priv->output_device, sdvo_priv->save_SDVOX);
901
902 if (sdvo_priv->save_SDVOX & SDVO_ENABLE) {
903 for (i = 0; i < 2; i++)
904 psb_intel_wait_for_vblank(dev);
905 status =
906 psb_intel_sdvo_get_trained_inputs(psb_intel_output,
907 &input1,
908 &input2);
909 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
910 DRM_DEBUG
911 ("First %s output reported failure to sync\n",
912 SDVO_NAME(sdvo_priv));
913 }
914
915 psb_intel_sdvo_set_active_outputs(psb_intel_output,
916 sdvo_priv->save_active_outputs);
917
918 /*TODO: restore in_out_map*/
919 psb_intel_sdvo_write_cmd(psb_intel_output,
920 SDVO_CMD_SET_IN_OUT_MAP,
921 sdvo_priv->in_out_map,
922 4);
923
924 psb_intel_sdvo_read_response(psb_intel_output, NULL, 0);
925}
926
927static int psb_intel_sdvo_mode_valid(struct drm_connector *connector, 1141static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
928 struct drm_display_mode *mode) 1142 struct drm_display_mode *mode)
929{ 1143{
930 struct psb_intel_output *psb_intel_output = 1144 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
931 to_psb_intel_output(connector);
932 struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
933 1145
934 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1146 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
935 return MODE_NO_DBLESCAN; 1147 return MODE_NO_DBLESCAN;
936 1148
937 if (sdvo_priv->pixel_clock_min > mode->clock) 1149 if (psb_intel_sdvo->pixel_clock_min > mode->clock)
938 return MODE_CLOCK_LOW; 1150 return MODE_CLOCK_LOW;
939 1151
940 if (sdvo_priv->pixel_clock_max < mode->clock) 1152 if (psb_intel_sdvo->pixel_clock_max < mode->clock)
941 return MODE_CLOCK_HIGH; 1153 return MODE_CLOCK_HIGH;
942 1154
1155 if (psb_intel_sdvo->is_lvds) {
1156 if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1157 return MODE_PANEL;
1158
1159 if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1160 return MODE_PANEL;
1161 }
1162
943 return MODE_OK; 1163 return MODE_OK;
944} 1164}
945 1165
946static bool psb_intel_sdvo_get_capabilities( 1166static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
947 struct psb_intel_output *psb_intel_output,
948 struct psb_intel_sdvo_caps *caps)
949{ 1167{
950 u8 status; 1168 BUILD_BUG_ON(sizeof(*caps) != 8);
951 1169 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
952 psb_intel_sdvo_write_cmd(psb_intel_output, 1170 SDVO_CMD_GET_DEVICE_CAPS,
953 SDVO_CMD_GET_DEVICE_CAPS, 1171 caps, sizeof(*caps)))
954 NULL,
955 0);
956 status = psb_intel_sdvo_read_response(psb_intel_output,
957 caps,
958 sizeof(*caps));
959 if (status != SDVO_CMD_STATUS_SUCCESS)
960 return false; 1172 return false;
961 1173
1174 DRM_DEBUG_KMS("SDVO capabilities:\n"
1175 " vendor_id: %d\n"
1176 " device_id: %d\n"
1177 " device_rev_id: %d\n"
1178 " sdvo_version_major: %d\n"
1179 " sdvo_version_minor: %d\n"
1180 " sdvo_inputs_mask: %d\n"
1181 " smooth_scaling: %d\n"
1182 " sharp_scaling: %d\n"
1183 " up_scaling: %d\n"
1184 " down_scaling: %d\n"
1185 " stall_support: %d\n"
1186 " output_flags: %d\n",
1187 caps->vendor_id,
1188 caps->device_id,
1189 caps->device_rev_id,
1190 caps->sdvo_version_major,
1191 caps->sdvo_version_minor,
1192 caps->sdvo_inputs_mask,
1193 caps->smooth_scaling,
1194 caps->sharp_scaling,
1195 caps->up_scaling,
1196 caps->down_scaling,
1197 caps->stall_support,
1198 caps->output_flags);
1199
962 return true; 1200 return true;
963} 1201}
964 1202
965struct drm_connector *psb_intel_sdvo_find(struct drm_device *dev, int sdvoB) 1203/* No use! */
1204#if 0
1205struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
966{ 1206{
967 struct drm_connector *connector = NULL; 1207 struct drm_connector *connector = NULL;
968 struct psb_intel_output *iout = NULL; 1208 struct psb_intel_sdvo *iout = NULL;
969 struct psb_intel_sdvo_priv *sdvo; 1209 struct psb_intel_sdvo *sdvo;
970 1210
971 /* find the sdvo connector */ 1211 /* find the sdvo connector */
972 list_for_each_entry(connector, &dev->mode_config.connector_list, 1212 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
973 head) { 1213 iout = to_psb_intel_sdvo(connector);
974 iout = to_psb_intel_output(connector);
975 1214
976 if (iout->type != INTEL_OUTPUT_SDVO) 1215 if (iout->type != INTEL_OUTPUT_SDVO)
977 continue; 1216 continue;
978 1217
979 sdvo = iout->dev_priv; 1218 sdvo = iout->dev_priv;
980 1219
981 if (sdvo->output_device == SDVOB && sdvoB) 1220 if (sdvo->sdvo_reg == SDVOB && sdvoB)
982 return connector; 1221 return connector;
983 1222
984 if (sdvo->output_device == SDVOC && !sdvoB) 1223 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
985 return connector; 1224 return connector;
986 1225
987 } 1226 }
@@ -993,112 +1232,607 @@ int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
993{ 1232{
994 u8 response[2]; 1233 u8 response[2];
995 u8 status; 1234 u8 status;
996 struct psb_intel_output *psb_intel_output; 1235 struct psb_intel_sdvo *psb_intel_sdvo;
1236 DRM_DEBUG_KMS("\n");
997 1237
998 if (!connector) 1238 if (!connector)
999 return 0; 1239 return 0;
1000 1240
1001 psb_intel_output = to_psb_intel_output(connector); 1241 psb_intel_sdvo = to_psb_intel_sdvo(connector);
1002 1242
1003 psb_intel_sdvo_write_cmd(psb_intel_output, 1243 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1004 SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1244 &response, 2) && response[0];
1005 NULL,
1006 0);
1007 status = psb_intel_sdvo_read_response(psb_intel_output,
1008 &response,
1009 2);
1010
1011 if (response[0] != 0)
1012 return 1;
1013
1014 return 0;
1015} 1245}
1016 1246
1017void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on) 1247void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1018{ 1248{
1019 u8 response[2]; 1249 u8 response[2];
1020 u8 status; 1250 u8 status;
1021 struct psb_intel_output *psb_intel_output = 1251 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
1022 to_psb_intel_output(connector);
1023 1252
1024 psb_intel_sdvo_write_cmd(psb_intel_output, 1253 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1025 SDVO_CMD_GET_ACTIVE_HOT_PLUG, 1254 psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1026 NULL,
1027 0);
1028 psb_intel_sdvo_read_response(psb_intel_output, &response, 2);
1029 1255
1030 if (on) { 1256 if (on) {
1031 psb_intel_sdvo_write_cmd(psb_intel_output, 1257 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1032 SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 1258 status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1033 0); 1259
1034 status = psb_intel_sdvo_read_response(psb_intel_output, 1260 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1035 &response,
1036 2);
1037
1038 psb_intel_sdvo_write_cmd(psb_intel_output,
1039 SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1040 &response, 2);
1041 } else { 1261 } else {
1042 response[0] = 0; 1262 response[0] = 0;
1043 response[1] = 0; 1263 response[1] = 0;
1044 psb_intel_sdvo_write_cmd(psb_intel_output, 1264 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1045 SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1046 &response, 2);
1047 } 1265 }
1048 1266
1049 psb_intel_sdvo_write_cmd(psb_intel_output, 1267 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1050 SDVO_CMD_GET_ACTIVE_HOT_PLUG, 1268 psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1051 NULL,
1052 0);
1053 psb_intel_sdvo_read_response(psb_intel_output, &response, 2);
1054} 1269}
1270#endif
1055 1271
1056static enum drm_connector_status psb_intel_sdvo_detect(struct drm_connector 1272static bool
1057 *connector, bool force) 1273psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
1058{ 1274{
1059 u8 response[2]; 1275 /* Is there more than one type of output? */
1060 u8 status; 1276 int caps = psb_intel_sdvo->caps.output_flags & 0xf;
1061 struct psb_intel_output *psb_intel_output = 1277 return caps & -caps;
1062 to_psb_intel_output(connector); 1278}
1063 1279
1064 psb_intel_sdvo_write_cmd(psb_intel_output, 1280static struct edid *
1065 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1281psb_intel_sdvo_get_edid(struct drm_connector *connector)
1066 NULL, 1282{
1067 0); 1283 struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
1068 status = psb_intel_sdvo_read_response(psb_intel_output, &response, 2); 1284 return drm_get_edid(connector, &sdvo->ddc);
1069 1285}
1070 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]); 1286
1071 if ((response[0] != 0) || (response[1] != 0)) 1287/* Mac mini hack -- use the same DDC as the analog connector */
1072 return connector_status_connected; 1288static struct edid *
1073 else 1289psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
1290{
1291 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1292
1293 return drm_get_edid(connector,
1294 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1295 return NULL;
1296}
1297
1298enum drm_connector_status
1299psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1300{
1301 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1302 enum drm_connector_status status;
1303 struct edid *edid;
1304
1305 edid = psb_intel_sdvo_get_edid(connector);
1306
1307 if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
1308 u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
1309
1310 /*
1311 * Don't use the 1 as the argument of DDC bus switch to get
1312 * the EDID. It is used for SDVO SPD ROM.
1313 */
1314 for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1315 psb_intel_sdvo->ddc_bus = ddc;
1316 edid = psb_intel_sdvo_get_edid(connector);
1317 if (edid)
1318 break;
1319 }
1320 /*
1321 * If we found the EDID on the other bus,
1322 * assume that is the correct DDC bus.
1323 */
1324 if (edid == NULL)
1325 psb_intel_sdvo->ddc_bus = saved_ddc;
1326 }
1327
1328 /*
1329 * When there is no edid and no monitor is connected with VGA
1330 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1331 */
1332 if (edid == NULL)
1333 edid = psb_intel_sdvo_get_analog_edid(connector);
1334
1335 status = connector_status_unknown;
1336 if (edid != NULL) {
1337 /* DDC bus is shared, match EDID to connector type */
1338 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1339 status = connector_status_connected;
1340 if (psb_intel_sdvo->is_hdmi) {
1341 psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1342 psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1343 }
1344 } else
1345 status = connector_status_disconnected;
1346 connector->display_info.raw_edid = NULL;
1347 kfree(edid);
1348 }
1349
1350 if (status == connector_status_connected) {
1351 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1352 if (psb_intel_sdvo_connector->force_audio)
1353 psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
1354 }
1355
1356 return status;
1357}
1358
1359static enum drm_connector_status
1360psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
1361{
1362 uint16_t response;
1363 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1364 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1365 enum drm_connector_status ret;
1366
1367 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
1368 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1369 return connector_status_unknown;
1370
1371 /* add 30ms delay when the output type might be TV */
1372 if (psb_intel_sdvo->caps.output_flags &
1373 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
1374 mdelay(30);
1375
1376 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
1377 return connector_status_unknown;
1378
1379 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1380 response & 0xff, response >> 8,
1381 psb_intel_sdvo_connector->output_flag);
1382
1383 if (response == 0)
1074 return connector_status_disconnected; 1384 return connector_status_disconnected;
1385
1386 psb_intel_sdvo->attached_output = response;
1387
1388 psb_intel_sdvo->has_hdmi_monitor = false;
1389 psb_intel_sdvo->has_hdmi_audio = false;
1390
1391 if ((psb_intel_sdvo_connector->output_flag & response) == 0)
1392 ret = connector_status_disconnected;
1393 else if (IS_TMDS(psb_intel_sdvo_connector))
1394 ret = psb_intel_sdvo_hdmi_sink_detect(connector);
1395 else {
1396 struct edid *edid;
1397
1398 /* if we have an edid check it matches the connection */
1399 edid = psb_intel_sdvo_get_edid(connector);
1400 if (edid == NULL)
1401 edid = psb_intel_sdvo_get_analog_edid(connector);
1402 if (edid != NULL) {
1403 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1404 ret = connector_status_disconnected;
1405 else
1406 ret = connector_status_connected;
1407 connector->display_info.raw_edid = NULL;
1408 kfree(edid);
1409 } else
1410 ret = connector_status_connected;
1411 }
1412
1413 /* May update encoder flag for like clock for SDVO TV, etc.*/
1414 if (ret == connector_status_connected) {
1415 psb_intel_sdvo->is_tv = false;
1416 psb_intel_sdvo->is_lvds = false;
1417 psb_intel_sdvo->base.needs_tv_clock = false;
1418
1419 if (response & SDVO_TV_MASK) {
1420 psb_intel_sdvo->is_tv = true;
1421 psb_intel_sdvo->base.needs_tv_clock = true;
1422 }
1423 if (response & SDVO_LVDS_MASK)
1424 psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1425 }
1426
1427 return ret;
1075} 1428}
1076 1429
1077static int psb_intel_sdvo_get_modes(struct drm_connector *connector) 1430static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1078{ 1431{
1079 struct psb_intel_output *psb_intel_output = 1432 struct edid *edid;
1080 to_psb_intel_output(connector);
1081 1433
1082 /* set the bus switch and get the modes */ 1434 /* set the bus switch and get the modes */
1083 psb_intel_sdvo_set_control_bus_switch(psb_intel_output, 1435 edid = psb_intel_sdvo_get_edid(connector);
1084 SDVO_CONTROL_BUS_DDC2);
1085 psb_intel_ddc_get_modes(psb_intel_output);
1086 1436
1087 if (list_empty(&connector->probed_modes)) 1437 /*
1088 return 0; 1438 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1089 return 1; 1439 * link between analog and digital outputs. So, if the regular SDVO
1440 * DDC fails, check to see if the analog output is disconnected, in
1441 * which case we'll look there for the digital DDC data.
1442 */
1443 if (edid == NULL)
1444 edid = psb_intel_sdvo_get_analog_edid(connector);
1445
1446 if (edid != NULL) {
1447 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1448 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1449 bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
1450
1451 if (connector_is_digital == monitor_is_digital) {
1452 drm_mode_connector_update_edid_property(connector, edid);
1453 drm_add_edid_modes(connector, edid);
1454 }
1455
1456 connector->display_info.raw_edid = NULL;
1457 kfree(edid);
1458 }
1459}
1460
1461/*
1462 * Set of SDVO TV modes.
1463 * Note! This is in reply order (see loop in get_tv_modes).
1464 * XXX: all 60Hz refresh?
1465 */
1466static const struct drm_display_mode sdvo_tv_modes[] = {
1467 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1468 416, 0, 200, 201, 232, 233, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1470 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1471 416, 0, 240, 241, 272, 273, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1473 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1474 496, 0, 300, 301, 332, 333, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1476 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1477 736, 0, 350, 351, 382, 383, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1479 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1480 736, 0, 400, 401, 432, 433, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1482 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1483 736, 0, 480, 481, 512, 513, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1485 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1486 800, 0, 480, 481, 512, 513, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1488 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1489 800, 0, 576, 577, 608, 609, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1491 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1492 816, 0, 350, 351, 382, 383, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1494 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1495 816, 0, 400, 401, 432, 433, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1497 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1498 816, 0, 480, 481, 512, 513, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1500 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1501 816, 0, 540, 541, 572, 573, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1503 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1504 816, 0, 576, 577, 608, 609, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1506 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1507 864, 0, 576, 577, 608, 609, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1509 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1510 896, 0, 600, 601, 632, 633, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1512 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1513 928, 0, 624, 625, 656, 657, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1515 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1516 1016, 0, 766, 767, 798, 799, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1518 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1519 1120, 0, 768, 769, 800, 801, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1521 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1522 1376, 0, 1024, 1025, 1056, 1057, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1524};
1525
1526static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
1527{
1528 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1529 struct psb_intel_sdvo_sdtv_resolution_request tv_res;
1530 uint32_t reply = 0, format_map = 0;
1531 int i;
1532
1533 /* Read the list of supported input resolutions for the selected TV
1534 * format.
1535 */
1536 format_map = 1 << psb_intel_sdvo->tv_format_index;
1537 memcpy(&tv_res, &format_map,
1538 min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
1539
1540 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
1541 return;
1542
1543 BUILD_BUG_ON(sizeof(tv_res) != 3);
1544 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
1545 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1546 &tv_res, sizeof(tv_res)))
1547 return;
1548 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
1549 return;
1550
1551 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1552 if (reply & (1 << i)) {
1553 struct drm_display_mode *nmode;
1554 nmode = drm_mode_duplicate(connector->dev,
1555 &sdvo_tv_modes[i]);
1556 if (nmode)
1557 drm_mode_probed_add(connector, nmode);
1558 }
1559}
1560
1561static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1562{
1563 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1564 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1565 struct drm_display_mode *newmode;
1566
1567 /*
1568 * Attempt to get the mode list from DDC.
1569 * Assume that the preferred modes are
1570 * arranged in priority order.
1571 */
1572 psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
1573 if (list_empty(&connector->probed_modes) == false)
1574 goto end;
1575
1576 /* Fetch modes from VBT */
1577 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1578 newmode = drm_mode_duplicate(connector->dev,
1579 dev_priv->sdvo_lvds_vbt_mode);
1580 if (newmode != NULL) {
1581 /* Guarantee the mode is preferred */
1582 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1583 DRM_MODE_TYPE_DRIVER);
1584 drm_mode_probed_add(connector, newmode);
1585 }
1586 }
1587
1588end:
1589 list_for_each_entry(newmode, &connector->probed_modes, head) {
1590 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1591 psb_intel_sdvo->sdvo_lvds_fixed_mode =
1592 drm_mode_duplicate(connector->dev, newmode);
1593
1594 drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
1595 0);
1596
1597 psb_intel_sdvo->is_lvds = true;
1598 break;
1599 }
1600 }
1601
1602}
1603
1604static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
1605{
1606 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1607
1608 if (IS_TV(psb_intel_sdvo_connector))
1609 psb_intel_sdvo_get_tv_modes(connector);
1610 else if (IS_LVDS(psb_intel_sdvo_connector))
1611 psb_intel_sdvo_get_lvds_modes(connector);
1612 else
1613 psb_intel_sdvo_get_ddc_modes(connector);
1614
1615 return !list_empty(&connector->probed_modes);
1616}
1617
1618static void
1619psb_intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1620{
1621 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1622 struct drm_device *dev = connector->dev;
1623
1624 if (psb_intel_sdvo_connector->left)
1625 drm_property_destroy(dev, psb_intel_sdvo_connector->left);
1626 if (psb_intel_sdvo_connector->right)
1627 drm_property_destroy(dev, psb_intel_sdvo_connector->right);
1628 if (psb_intel_sdvo_connector->top)
1629 drm_property_destroy(dev, psb_intel_sdvo_connector->top);
1630 if (psb_intel_sdvo_connector->bottom)
1631 drm_property_destroy(dev, psb_intel_sdvo_connector->bottom);
1632 if (psb_intel_sdvo_connector->hpos)
1633 drm_property_destroy(dev, psb_intel_sdvo_connector->hpos);
1634 if (psb_intel_sdvo_connector->vpos)
1635 drm_property_destroy(dev, psb_intel_sdvo_connector->vpos);
1636 if (psb_intel_sdvo_connector->saturation)
1637 drm_property_destroy(dev, psb_intel_sdvo_connector->saturation);
1638 if (psb_intel_sdvo_connector->contrast)
1639 drm_property_destroy(dev, psb_intel_sdvo_connector->contrast);
1640 if (psb_intel_sdvo_connector->hue)
1641 drm_property_destroy(dev, psb_intel_sdvo_connector->hue);
1642 if (psb_intel_sdvo_connector->sharpness)
1643 drm_property_destroy(dev, psb_intel_sdvo_connector->sharpness);
1644 if (psb_intel_sdvo_connector->flicker_filter)
1645 drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter);
1646 if (psb_intel_sdvo_connector->flicker_filter_2d)
1647 drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_2d);
1648 if (psb_intel_sdvo_connector->flicker_filter_adaptive)
1649 drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_adaptive);
1650 if (psb_intel_sdvo_connector->tv_luma_filter)
1651 drm_property_destroy(dev, psb_intel_sdvo_connector->tv_luma_filter);
1652 if (psb_intel_sdvo_connector->tv_chroma_filter)
1653 drm_property_destroy(dev, psb_intel_sdvo_connector->tv_chroma_filter);
1654 if (psb_intel_sdvo_connector->dot_crawl)
1655 drm_property_destroy(dev, psb_intel_sdvo_connector->dot_crawl);
1656 if (psb_intel_sdvo_connector->brightness)
1657 drm_property_destroy(dev, psb_intel_sdvo_connector->brightness);
1090} 1658}
1091 1659
1092static void psb_intel_sdvo_destroy(struct drm_connector *connector) 1660static void psb_intel_sdvo_destroy(struct drm_connector *connector)
1093{ 1661{
1094 struct psb_intel_output *psb_intel_output = 1662 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1095 to_psb_intel_output(connector); 1663
1664 if (psb_intel_sdvo_connector->tv_format)
1665 drm_property_destroy(connector->dev,
1666 psb_intel_sdvo_connector->tv_format);
1096 1667
1097 if (psb_intel_output->i2c_bus) 1668 psb_intel_sdvo_destroy_enhance_property(connector);
1098 psb_intel_i2c_destroy(psb_intel_output->i2c_bus);
1099 drm_sysfs_connector_remove(connector); 1669 drm_sysfs_connector_remove(connector);
1100 drm_connector_cleanup(connector); 1670 drm_connector_cleanup(connector);
1101 kfree(psb_intel_output); 1671 kfree(connector);
1672}
1673
1674static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1675{
1676 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1677 struct edid *edid;
1678 bool has_audio = false;
1679
1680 if (!psb_intel_sdvo->is_hdmi)
1681 return false;
1682
1683 edid = psb_intel_sdvo_get_edid(connector);
1684 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1685 has_audio = drm_detect_monitor_audio(edid);
1686
1687 return has_audio;
1688}
1689
1690static int
1691psb_intel_sdvo_set_property(struct drm_connector *connector,
1692 struct drm_property *property,
1693 uint64_t val)
1694{
1695 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1696 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1697 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1698 uint16_t temp_value;
1699 uint8_t cmd;
1700 int ret;
1701
1702 ret = drm_connector_property_set_value(connector, property, val);
1703 if (ret)
1704 return ret;
1705
1706 if (property == dev_priv->force_audio_property) {
1707 int i = val;
1708 bool has_audio;
1709
1710 if (i == psb_intel_sdvo_connector->force_audio)
1711 return 0;
1712
1713 psb_intel_sdvo_connector->force_audio = i;
1714
1715 if (i == 0)
1716 has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
1717 else
1718 has_audio = i > 0;
1719
1720 if (has_audio == psb_intel_sdvo->has_hdmi_audio)
1721 return 0;
1722
1723 psb_intel_sdvo->has_hdmi_audio = has_audio;
1724 goto done;
1725 }
1726
1727 if (property == dev_priv->broadcast_rgb_property) {
1728 if (val == !!psb_intel_sdvo->color_range)
1729 return 0;
1730
1731 psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
1732 goto done;
1733 }
1734
1735#define CHECK_PROPERTY(name, NAME) \
1736 if (psb_intel_sdvo_connector->name == property) { \
1737 if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
1738 if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1739 cmd = SDVO_CMD_SET_##NAME; \
1740 psb_intel_sdvo_connector->cur_##name = temp_value; \
1741 goto set_value; \
1742 }
1743
1744 if (property == psb_intel_sdvo_connector->tv_format) {
1745 if (val >= TV_FORMAT_NUM)
1746 return -EINVAL;
1747
1748 if (psb_intel_sdvo->tv_format_index ==
1749 psb_intel_sdvo_connector->tv_format_supported[val])
1750 return 0;
1751
1752 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
1753 goto done;
1754 } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
1755 temp_value = val;
1756 if (psb_intel_sdvo_connector->left == property) {
1757 drm_connector_property_set_value(connector,
1758 psb_intel_sdvo_connector->right, val);
1759 if (psb_intel_sdvo_connector->left_margin == temp_value)
1760 return 0;
1761
1762 psb_intel_sdvo_connector->left_margin = temp_value;
1763 psb_intel_sdvo_connector->right_margin = temp_value;
1764 temp_value = psb_intel_sdvo_connector->max_hscan -
1765 psb_intel_sdvo_connector->left_margin;
1766 cmd = SDVO_CMD_SET_OVERSCAN_H;
1767 goto set_value;
1768 } else if (psb_intel_sdvo_connector->right == property) {
1769 drm_connector_property_set_value(connector,
1770 psb_intel_sdvo_connector->left, val);
1771 if (psb_intel_sdvo_connector->right_margin == temp_value)
1772 return 0;
1773
1774 psb_intel_sdvo_connector->left_margin = temp_value;
1775 psb_intel_sdvo_connector->right_margin = temp_value;
1776 temp_value = psb_intel_sdvo_connector->max_hscan -
1777 psb_intel_sdvo_connector->left_margin;
1778 cmd = SDVO_CMD_SET_OVERSCAN_H;
1779 goto set_value;
1780 } else if (psb_intel_sdvo_connector->top == property) {
1781 drm_connector_property_set_value(connector,
1782 psb_intel_sdvo_connector->bottom, val);
1783 if (psb_intel_sdvo_connector->top_margin == temp_value)
1784 return 0;
1785
1786 psb_intel_sdvo_connector->top_margin = temp_value;
1787 psb_intel_sdvo_connector->bottom_margin = temp_value;
1788 temp_value = psb_intel_sdvo_connector->max_vscan -
1789 psb_intel_sdvo_connector->top_margin;
1790 cmd = SDVO_CMD_SET_OVERSCAN_V;
1791 goto set_value;
1792 } else if (psb_intel_sdvo_connector->bottom == property) {
1793 drm_connector_property_set_value(connector,
1794 psb_intel_sdvo_connector->top, val);
1795 if (psb_intel_sdvo_connector->bottom_margin == temp_value)
1796 return 0;
1797
1798 psb_intel_sdvo_connector->top_margin = temp_value;
1799 psb_intel_sdvo_connector->bottom_margin = temp_value;
1800 temp_value = psb_intel_sdvo_connector->max_vscan -
1801 psb_intel_sdvo_connector->top_margin;
1802 cmd = SDVO_CMD_SET_OVERSCAN_V;
1803 goto set_value;
1804 }
1805 CHECK_PROPERTY(hpos, HPOS)
1806 CHECK_PROPERTY(vpos, VPOS)
1807 CHECK_PROPERTY(saturation, SATURATION)
1808 CHECK_PROPERTY(contrast, CONTRAST)
1809 CHECK_PROPERTY(hue, HUE)
1810 CHECK_PROPERTY(brightness, BRIGHTNESS)
1811 CHECK_PROPERTY(sharpness, SHARPNESS)
1812 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1813 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1814 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1815 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1816 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1817 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
1818 }
1819
1820 return -EINVAL; /* unknown property */
1821
1822set_value:
1823 if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
1824 return -EIO;
1825
1826
1827done:
1828 if (psb_intel_sdvo->base.base.crtc) {
1829 struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
1830 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1831 crtc->y, crtc->fb);
1832 }
1833
1834 return 0;
1835#undef CHECK_PROPERTY
1102} 1836}
1103 1837
1104static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = { 1838static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
@@ -1111,183 +1845,765 @@ static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
1111 1845
1112static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = { 1846static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
1113 .dpms = drm_helper_connector_dpms, 1847 .dpms = drm_helper_connector_dpms,
1114 .save = psb_intel_sdvo_save,
1115 .restore = psb_intel_sdvo_restore,
1116 .detect = psb_intel_sdvo_detect, 1848 .detect = psb_intel_sdvo_detect,
1117 .fill_modes = drm_helper_probe_single_connector_modes, 1849 .fill_modes = drm_helper_probe_single_connector_modes,
1850 .set_property = psb_intel_sdvo_set_property,
1118 .destroy = psb_intel_sdvo_destroy, 1851 .destroy = psb_intel_sdvo_destroy,
1119}; 1852};
1120 1853
1121static const struct drm_connector_helper_funcs 1854static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
1122 psb_intel_sdvo_connector_helper_funcs = {
1123 .get_modes = psb_intel_sdvo_get_modes, 1855 .get_modes = psb_intel_sdvo_get_modes,
1124 .mode_valid = psb_intel_sdvo_mode_valid, 1856 .mode_valid = psb_intel_sdvo_mode_valid,
1125 .best_encoder = psb_intel_best_encoder, 1857 .best_encoder = psb_intel_best_encoder,
1126}; 1858};
1127 1859
1128void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1860static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1129{ 1861{
1130 drm_encoder_cleanup(encoder); 1862 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
1863
1864 if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
1865 drm_mode_destroy(encoder->dev,
1866 psb_intel_sdvo->sdvo_lvds_fixed_mode);
1867
1868 i2c_del_adapter(&psb_intel_sdvo->ddc);
1869 psb_intel_encoder_destroy(encoder);
1131} 1870}
1132 1871
1133static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = { 1872static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
1134 .destroy = psb_intel_sdvo_enc_destroy, 1873 .destroy = psb_intel_sdvo_enc_destroy,
1135}; 1874};
1136 1875
1137 1876static void
1138void psb_intel_sdvo_init(struct drm_device *dev, int output_device) 1877psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
1139{ 1878{
1140 struct drm_connector *connector; 1879 uint16_t mask = 0;
1141 struct psb_intel_output *psb_intel_output; 1880 unsigned int num_bits;
1142 struct psb_intel_sdvo_priv *sdvo_priv;
1143 struct psb_intel_i2c_chan *i2cbus = NULL;
1144 int connector_type;
1145 u8 ch[0x40];
1146 int i;
1147 int encoder_type, output_id;
1148 1881
1149 psb_intel_output = 1882 /* Make a mask of outputs less than or equal to our own priority in the
1150 kcalloc(sizeof(struct psb_intel_output) + 1883 * list.
1151 sizeof(struct psb_intel_sdvo_priv), 1, GFP_KERNEL); 1884 */
1152 if (!psb_intel_output) 1885 switch (sdvo->controlled_output) {
1153 return; 1886 case SDVO_OUTPUT_LVDS1:
1887 mask |= SDVO_OUTPUT_LVDS1;
1888 case SDVO_OUTPUT_LVDS0:
1889 mask |= SDVO_OUTPUT_LVDS0;
1890 case SDVO_OUTPUT_TMDS1:
1891 mask |= SDVO_OUTPUT_TMDS1;
1892 case SDVO_OUTPUT_TMDS0:
1893 mask |= SDVO_OUTPUT_TMDS0;
1894 case SDVO_OUTPUT_RGB1:
1895 mask |= SDVO_OUTPUT_RGB1;
1896 case SDVO_OUTPUT_RGB0:
1897 mask |= SDVO_OUTPUT_RGB0;
1898 break;
1899 }
1154 1900
1155 connector = &psb_intel_output->base; 1901 /* Count bits to find what number we are in the priority list. */
1902 mask &= sdvo->caps.output_flags;
1903 num_bits = hweight16(mask);
1904 /* If more than 3 outputs, default to DDC bus 3 for now. */
1905 if (num_bits > 3)
1906 num_bits = 3;
1156 1907
1157 drm_connector_init(dev, connector, &psb_intel_sdvo_connector_funcs, 1908 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1158 DRM_MODE_CONNECTOR_Unknown); 1909 sdvo->ddc_bus = 1 << num_bits;
1159 drm_connector_helper_add(connector, 1910}
1160 &psb_intel_sdvo_connector_helper_funcs);
1161 sdvo_priv = (struct psb_intel_sdvo_priv *) (psb_intel_output + 1);
1162 psb_intel_output->type = INTEL_OUTPUT_SDVO;
1163 1911
1164 connector->interlace_allowed = 0; 1912/**
1165 connector->doublescan_allowed = 0; 1913 * Choose the appropriate DDC bus for control bus switch command for this
1914 * SDVO output based on the controlled output.
1915 *
1916 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1917 * outputs, then LVDS outputs.
1918 */
1919static void
1920psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
1921 struct psb_intel_sdvo *sdvo, u32 reg)
1922{
1923 struct sdvo_device_mapping *mapping;
1166 1924
1167 /* setup the DDC bus. */ 1925 if (IS_SDVOB(reg))
1168 if (output_device == SDVOB) 1926 mapping = &(dev_priv->sdvo_mappings[0]);
1169 i2cbus =
1170 psb_intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1171 else 1927 else
1172 i2cbus = 1928 mapping = &(dev_priv->sdvo_mappings[1]);
1173 psb_intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); 1929
1930 if (mapping->initialized)
1931 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1932 else
1933 psb_intel_sdvo_guess_ddc_bus(sdvo);
1934}
1935
1936static void
1937psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
1938 struct psb_intel_sdvo *sdvo, u32 reg)
1939{
1940 struct sdvo_device_mapping *mapping;
1941 u8 pin, speed;
1942
1943 if (IS_SDVOB(reg))
1944 mapping = &dev_priv->sdvo_mappings[0];
1945 else
1946 mapping = &dev_priv->sdvo_mappings[1];
1947
1948 pin = GMBUS_PORT_DPB;
1949 speed = GMBUS_RATE_1MHZ >> 8;
1950 if (mapping->initialized) {
1951 pin = mapping->i2c_pin;
1952 speed = mapping->i2c_speed;
1953 }
1174 1954
1175 if (!i2cbus) 1955 if (pin < GMBUS_NUM_PORTS) {
1176 goto err_connector; 1956 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1957 gma_intel_gmbus_set_speed(sdvo->i2c, speed);
1958 gma_intel_gmbus_force_bit(sdvo->i2c, true);
1959 } else
1960 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
1961}
1177 1962
1178 sdvo_priv->i2c_bus = i2cbus; 1963static bool
1964psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
1965{
1966 return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
1967}
1968
1969static u8
1970psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
1971{
1972 struct drm_psb_private *dev_priv = dev->dev_private;
1973 struct sdvo_device_mapping *my_mapping, *other_mapping;
1179 1974
1180 if (output_device == SDVOB) { 1975 if (IS_SDVOB(sdvo_reg)) {
1181 output_id = 1; 1976 my_mapping = &dev_priv->sdvo_mappings[0];
1182 sdvo_priv->by_input_wiring = SDVOB_IN0; 1977 other_mapping = &dev_priv->sdvo_mappings[1];
1183 sdvo_priv->i2c_bus->slave_addr = 0x38;
1184 } else { 1978 } else {
1185 output_id = 2; 1979 my_mapping = &dev_priv->sdvo_mappings[1];
1186 sdvo_priv->i2c_bus->slave_addr = 0x39; 1980 other_mapping = &dev_priv->sdvo_mappings[0];
1187 } 1981 }
1188 1982
1189 sdvo_priv->output_device = output_device; 1983 /* If the BIOS described our SDVO device, take advantage of it. */
1190 psb_intel_output->i2c_bus = i2cbus; 1984 if (my_mapping->slave_addr)
1191 psb_intel_output->dev_priv = sdvo_priv; 1985 return my_mapping->slave_addr;
1192 1986
1987 /* If the BIOS only described a different SDVO device, use the
1988 * address that it isn't using.
1989 */
1990 if (other_mapping->slave_addr) {
1991 if (other_mapping->slave_addr == 0x70)
1992 return 0x72;
1993 else
1994 return 0x70;
1995 }
1996
1997 /* No SDVO device info is found for another DVO port,
1998 * so use mapping assumption we had before BIOS parsing.
1999 */
2000 if (IS_SDVOB(sdvo_reg))
2001 return 0x70;
2002 else
2003 return 0x72;
2004}
2005
2006static void
2007psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
2008 struct psb_intel_sdvo *encoder)
2009{
2010 drm_connector_init(encoder->base.base.dev,
2011 &connector->base.base,
2012 &psb_intel_sdvo_connector_funcs,
2013 connector->base.base.connector_type);
2014
2015 drm_connector_helper_add(&connector->base.base,
2016 &psb_intel_sdvo_connector_helper_funcs);
2017
2018 connector->base.base.interlace_allowed = 0;
2019 connector->base.base.doublescan_allowed = 0;
2020 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2021
2022 psb_intel_connector_attach_encoder(&connector->base, &encoder->base);
2023 drm_sysfs_connector_add(&connector->base.base);
2024}
2025
2026static void
2027psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
2028{
2029 /* FIXME: We don't support HDMI at the moment
2030 struct drm_device *dev = connector->base.base.dev;
2031
2032 intel_attach_force_audio_property(&connector->base.base);
2033 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2034 intel_attach_broadcast_rgb_property(&connector->base.base);
2035 */
2036}
2037
2038static bool
2039psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2040{
2041 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2042 struct drm_connector *connector;
2043 struct psb_intel_connector *intel_connector;
2044 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2045
2046 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2047 if (!psb_intel_sdvo_connector)
2048 return false;
2049
2050 if (device == 0) {
2051 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2052 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2053 } else if (device == 1) {
2054 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2055 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2056 }
2057
2058 intel_connector = &psb_intel_sdvo_connector->base;
2059 connector = &intel_connector->base;
2060 // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2061 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2062 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2063
2064 if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
2065 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2066 psb_intel_sdvo->is_hdmi = true;
2067 }
2068 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2069 (1 << INTEL_ANALOG_CLONE_BIT));
2070
2071 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2072 if (psb_intel_sdvo->is_hdmi)
2073 psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
2074
2075 return true;
2076}
2077
2078static bool
2079psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
2080{
2081 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2082 struct drm_connector *connector;
2083 struct psb_intel_connector *intel_connector;
2084 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2085
2086 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2087 if (!psb_intel_sdvo_connector)
2088 return false;
2089
2090 intel_connector = &psb_intel_sdvo_connector->base;
2091 connector = &intel_connector->base;
2092 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2093 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2094
2095 psb_intel_sdvo->controlled_output |= type;
2096 psb_intel_sdvo_connector->output_flag = type;
2097
2098 psb_intel_sdvo->is_tv = true;
2099 psb_intel_sdvo->base.needs_tv_clock = true;
2100 psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2101
2102 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2103
2104 if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
2105 goto err;
2106
2107 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
2108 goto err;
2109
2110 return true;
2111
2112err:
2113 psb_intel_sdvo_destroy(connector);
2114 return false;
2115}
2116
2117static bool
2118psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2119{
2120 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2121 struct drm_connector *connector;
2122 struct psb_intel_connector *intel_connector;
2123 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2124
2125 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2126 if (!psb_intel_sdvo_connector)
2127 return false;
2128
2129 intel_connector = &psb_intel_sdvo_connector->base;
2130 connector = &intel_connector->base;
2131 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2132 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2133 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2134
2135 if (device == 0) {
2136 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2137 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2138 } else if (device == 1) {
2139 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2140 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2141 }
2142
2143 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2144 (1 << INTEL_ANALOG_CLONE_BIT));
2145
2146 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
2147 psb_intel_sdvo);
2148 return true;
2149}
2150
2151static bool
2152psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2153{
2154 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2155 struct drm_connector *connector;
2156 struct psb_intel_connector *intel_connector;
2157 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2158
2159 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2160 if (!psb_intel_sdvo_connector)
2161 return false;
2162
2163 intel_connector = &psb_intel_sdvo_connector->base;
2164 connector = &intel_connector->base;
2165 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2166 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2167
2168 if (device == 0) {
2169 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2170 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2171 } else if (device == 1) {
2172 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2173 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2174 }
2175
2176 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2177 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
2178
2179 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2180 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
2181 goto err;
2182
2183 return true;
2184
2185err:
2186 psb_intel_sdvo_destroy(connector);
2187 return false;
2188}
2189
2190static bool
2191psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
2192{
2193 psb_intel_sdvo->is_tv = false;
2194 psb_intel_sdvo->base.needs_tv_clock = false;
2195 psb_intel_sdvo->is_lvds = false;
2196
2197 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2198
2199 if (flags & SDVO_OUTPUT_TMDS0)
2200 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
2201 return false;
2202
2203 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2204 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
2205 return false;
2206
2207 /* TV has no XXX1 function block */
2208 if (flags & SDVO_OUTPUT_SVID0)
2209 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
2210 return false;
2211
2212 if (flags & SDVO_OUTPUT_CVBS0)
2213 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
2214 return false;
2215
2216 if (flags & SDVO_OUTPUT_RGB0)
2217 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
2218 return false;
2219
2220 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2221 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
2222 return false;
2223
2224 if (flags & SDVO_OUTPUT_LVDS0)
2225 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
2226 return false;
2227
2228 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2229 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
2230 return false;
2231
2232 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2233 unsigned char bytes[2];
2234
2235 psb_intel_sdvo->controlled_output = 0;
2236 memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
2237 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2238 SDVO_NAME(psb_intel_sdvo),
2239 bytes[0], bytes[1]);
2240 return false;
2241 }
2242 psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
2243
2244 return true;
2245}
2246
2247static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
2248 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2249 int type)
2250{
2251 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2252 struct psb_intel_sdvo_tv_format format;
2253 uint32_t format_map, i;
2254
2255 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
2256 return false;
2257
2258 BUILD_BUG_ON(sizeof(format) != 6);
2259 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2260 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2261 &format, sizeof(format)))
2262 return false;
2263
2264 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2265
2266 if (format_map == 0)
2267 return false;
2268
2269 psb_intel_sdvo_connector->format_supported_num = 0;
2270 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2271 if (format_map & (1 << i))
2272 psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
2273
2274
2275 psb_intel_sdvo_connector->tv_format =
2276 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2277 "mode", psb_intel_sdvo_connector->format_supported_num);
2278 if (!psb_intel_sdvo_connector->tv_format)
2279 return false;
2280
2281 for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
2282 drm_property_add_enum(
2283 psb_intel_sdvo_connector->tv_format, i,
2284 i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
2285
2286 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
2287 drm_connector_attach_property(&psb_intel_sdvo_connector->base.base,
2288 psb_intel_sdvo_connector->tv_format, 0);
2289 return true;
2290
2291}
2292
2293#define ENHANCEMENT(name, NAME) do { \
2294 if (enhancements.name) { \
2295 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2296 !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2297 return false; \
2298 psb_intel_sdvo_connector->max_##name = data_value[0]; \
2299 psb_intel_sdvo_connector->cur_##name = response; \
2300 psb_intel_sdvo_connector->name = \
2301 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2302 if (!psb_intel_sdvo_connector->name) return false; \
2303 psb_intel_sdvo_connector->name->values[0] = 0; \
2304 psb_intel_sdvo_connector->name->values[1] = data_value[0]; \
2305 drm_connector_attach_property(connector, \
2306 psb_intel_sdvo_connector->name, \
2307 psb_intel_sdvo_connector->cur_##name); \
2308 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2309 data_value[0], data_value[1], response); \
2310 } \
2311} while(0)
2312
2313static bool
2314psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
2315 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2316 struct psb_intel_sdvo_enhancements_reply enhancements)
2317{
2318 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2319 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
2320 uint16_t response, data_value[2];
2321
2322 /* when horizontal overscan is supported, Add the left/right property */
2323 if (enhancements.overscan_h) {
2324 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2325 SDVO_CMD_GET_MAX_OVERSCAN_H,
2326 &data_value, 4))
2327 return false;
2328
2329 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2330 SDVO_CMD_GET_OVERSCAN_H,
2331 &response, 2))
2332 return false;
2333
2334 psb_intel_sdvo_connector->max_hscan = data_value[0];
2335 psb_intel_sdvo_connector->left_margin = data_value[0] - response;
2336 psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
2337 psb_intel_sdvo_connector->left =
2338 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2339 "left_margin", 2);
2340 if (!psb_intel_sdvo_connector->left)
2341 return false;
2342
2343 psb_intel_sdvo_connector->left->values[0] = 0;
2344 psb_intel_sdvo_connector->left->values[1] = data_value[0];
2345 drm_connector_attach_property(connector,
2346 psb_intel_sdvo_connector->left,
2347 psb_intel_sdvo_connector->left_margin);
2348
2349 psb_intel_sdvo_connector->right =
2350 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2351 "right_margin", 2);
2352 if (!psb_intel_sdvo_connector->right)
2353 return false;
2354
2355 psb_intel_sdvo_connector->right->values[0] = 0;
2356 psb_intel_sdvo_connector->right->values[1] = data_value[0];
2357 drm_connector_attach_property(connector,
2358 psb_intel_sdvo_connector->right,
2359 psb_intel_sdvo_connector->right_margin);
2360 DRM_DEBUG_KMS("h_overscan: max %d, "
2361 "default %d, current %d\n",
2362 data_value[0], data_value[1], response);
2363 }
2364
2365 if (enhancements.overscan_v) {
2366 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2367 SDVO_CMD_GET_MAX_OVERSCAN_V,
2368 &data_value, 4))
2369 return false;
2370
2371 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2372 SDVO_CMD_GET_OVERSCAN_V,
2373 &response, 2))
2374 return false;
2375
2376 psb_intel_sdvo_connector->max_vscan = data_value[0];
2377 psb_intel_sdvo_connector->top_margin = data_value[0] - response;
2378 psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
2379 psb_intel_sdvo_connector->top =
2380 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2381 "top_margin", 2);
2382 if (!psb_intel_sdvo_connector->top)
2383 return false;
2384
2385 psb_intel_sdvo_connector->top->values[0] = 0;
2386 psb_intel_sdvo_connector->top->values[1] = data_value[0];
2387 drm_connector_attach_property(connector,
2388 psb_intel_sdvo_connector->top,
2389 psb_intel_sdvo_connector->top_margin);
2390
2391 psb_intel_sdvo_connector->bottom =
2392 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2393 "bottom_margin", 2);
2394 if (!psb_intel_sdvo_connector->bottom)
2395 return false;
2396
2397 psb_intel_sdvo_connector->bottom->values[0] = 0;
2398 psb_intel_sdvo_connector->bottom->values[1] = data_value[0];
2399 drm_connector_attach_property(connector,
2400 psb_intel_sdvo_connector->bottom,
2401 psb_intel_sdvo_connector->bottom_margin);
2402 DRM_DEBUG_KMS("v_overscan: max %d, "
2403 "default %d, current %d\n",
2404 data_value[0], data_value[1], response);
2405 }
2406
2407 ENHANCEMENT(hpos, HPOS);
2408 ENHANCEMENT(vpos, VPOS);
2409 ENHANCEMENT(saturation, SATURATION);
2410 ENHANCEMENT(contrast, CONTRAST);
2411 ENHANCEMENT(hue, HUE);
2412 ENHANCEMENT(sharpness, SHARPNESS);
2413 ENHANCEMENT(brightness, BRIGHTNESS);
2414 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2415 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2416 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2417 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2418 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2419
2420 if (enhancements.dot_crawl) {
2421 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2422 return false;
2423
2424 psb_intel_sdvo_connector->max_dot_crawl = 1;
2425 psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2426 psb_intel_sdvo_connector->dot_crawl =
2427 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2428 if (!psb_intel_sdvo_connector->dot_crawl)
2429 return false;
2430
2431 psb_intel_sdvo_connector->dot_crawl->values[0] = 0;
2432 psb_intel_sdvo_connector->dot_crawl->values[1] = 1;
2433 drm_connector_attach_property(connector,
2434 psb_intel_sdvo_connector->dot_crawl,
2435 psb_intel_sdvo_connector->cur_dot_crawl);
2436 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2437 }
2438
2439 return true;
2440}
2441
2442static bool
2443psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
2444 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2445 struct psb_intel_sdvo_enhancements_reply enhancements)
2446{
2447 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2448 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
2449 uint16_t response, data_value[2];
2450
2451 ENHANCEMENT(brightness, BRIGHTNESS);
2452
2453 return true;
2454}
2455#undef ENHANCEMENT
2456
2457static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
2458 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
2459{
2460 union {
2461 struct psb_intel_sdvo_enhancements_reply reply;
2462 uint16_t response;
2463 } enhancements;
2464
2465 BUILD_BUG_ON(sizeof(enhancements) != 2);
2466
2467 enhancements.response = 0;
2468 psb_intel_sdvo_get_value(psb_intel_sdvo,
2469 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2470 &enhancements, sizeof(enhancements));
2471 if (enhancements.response == 0) {
2472 DRM_DEBUG_KMS("No enhancement is supported\n");
2473 return true;
2474 }
2475
2476 if (IS_TV(psb_intel_sdvo_connector))
2477 return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
2478 else if(IS_LVDS(psb_intel_sdvo_connector))
2479 return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
2480 else
2481 return true;
2482}
2483
2484static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2485 struct i2c_msg *msgs,
2486 int num)
2487{
2488 struct psb_intel_sdvo *sdvo = adapter->algo_data;
2489
2490 if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2491 return -EIO;
2492
2493 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2494}
2495
2496static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2497{
2498 struct psb_intel_sdvo *sdvo = adapter->algo_data;
2499 return sdvo->i2c->algo->functionality(sdvo->i2c);
2500}
2501
2502static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
2503 .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
2504 .functionality = psb_intel_sdvo_ddc_proxy_func
2505};
2506
2507static bool
2508psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
2509 struct drm_device *dev)
2510{
2511 sdvo->ddc.owner = THIS_MODULE;
2512 sdvo->ddc.class = I2C_CLASS_DDC;
2513 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2514 sdvo->ddc.dev.parent = &dev->pdev->dev;
2515 sdvo->ddc.algo_data = sdvo;
2516 sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
2517
2518 return i2c_add_adapter(&sdvo->ddc) == 0;
2519}
2520
2521bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2522{
2523 struct drm_psb_private *dev_priv = dev->dev_private;
2524 struct psb_intel_encoder *psb_intel_encoder;
2525 struct psb_intel_sdvo *psb_intel_sdvo;
2526 int i;
2527
2528 psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
2529 if (!psb_intel_sdvo)
2530 return false;
2531
2532 psb_intel_sdvo->sdvo_reg = sdvo_reg;
2533 psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2534 psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
2535 if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
2536 kfree(psb_intel_sdvo);
2537 return false;
2538 }
2539
2540 /* encoder type will be decided later */
2541 psb_intel_encoder = &psb_intel_sdvo->base;
2542 psb_intel_encoder->type = INTEL_OUTPUT_SDVO;
2543 drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
1193 2544
1194 /* Read the regs to test if we can talk to the device */ 2545 /* Read the regs to test if we can talk to the device */
1195 for (i = 0; i < 0x40; i++) { 2546 for (i = 0; i < 0x40; i++) {
1196 if (!psb_intel_sdvo_read_byte(psb_intel_output, i, &ch[i])) { 2547 u8 byte;
1197 dev_dbg(dev->dev, "No SDVO device found on SDVO%c\n", 2548
1198 output_device == SDVOB ? 'B' : 'C'); 2549 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
1199 goto err_i2c; 2550 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2551 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2552 goto err;
1200 } 2553 }
1201 } 2554 }
1202 2555
1203 psb_intel_sdvo_get_capabilities(psb_intel_output, &sdvo_priv->caps); 2556 if (IS_SDVOB(sdvo_reg))
1204 2557 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
1205 memset(&sdvo_priv->active_outputs, 0, 2558 else
1206 sizeof(sdvo_priv->active_outputs)); 2559 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
1207
1208 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1209 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0) {
1210 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB0;
1211 sdvo_priv->active_device = SDVO_DEVICE_CRT;
1212 connector->display_info.subpixel_order =
1213 SubPixelHorizontalRGB;
1214 encoder_type = DRM_MODE_ENCODER_DAC;
1215 connector_type = DRM_MODE_CONNECTOR_VGA;
1216 } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1) {
1217 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB1;
1218 sdvo_priv->active_outputs = SDVO_DEVICE_CRT;
1219 connector->display_info.subpixel_order =
1220 SubPixelHorizontalRGB;
1221 encoder_type = DRM_MODE_ENCODER_DAC;
1222 connector_type = DRM_MODE_CONNECTOR_VGA;
1223 } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0) {
1224 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS0;
1225 sdvo_priv->active_device = SDVO_DEVICE_TMDS;
1226 connector->display_info.subpixel_order =
1227 SubPixelHorizontalRGB;
1228 encoder_type = DRM_MODE_ENCODER_TMDS;
1229 connector_type = DRM_MODE_CONNECTOR_DVID;
1230 } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS1) {
1231 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS1;
1232 sdvo_priv->active_device = SDVO_DEVICE_TMDS;
1233 connector->display_info.subpixel_order =
1234 SubPixelHorizontalRGB;
1235 encoder_type = DRM_MODE_ENCODER_TMDS;
1236 connector_type = DRM_MODE_CONNECTOR_DVID;
1237 } else {
1238 unsigned char bytes[2];
1239 2560
1240 memcpy(bytes, &sdvo_priv->caps.output_flags, 2); 2561 drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs);
1241 dev_dbg(dev->dev, "%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1242 SDVO_NAME(sdvo_priv), bytes[0], bytes[1]);
1243 goto err_i2c;
1244 }
1245 2562
1246 drm_encoder_init(dev, &psb_intel_output->enc, &psb_intel_sdvo_enc_funcs, 2563 /* In default case sdvo lvds is false */
1247 encoder_type); 2564 if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
1248 drm_encoder_helper_add(&psb_intel_output->enc, 2565 goto err;
1249 &psb_intel_sdvo_helper_funcs);
1250 connector->connector_type = connector_type;
1251 2566
1252 drm_mode_connector_attach_encoder(&psb_intel_output->base, 2567 if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
1253 &psb_intel_output->enc); 2568 psb_intel_sdvo->caps.output_flags) != true) {
1254 drm_sysfs_connector_add(connector); 2569 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2570 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2571 goto err;
2572 }
1255 2573
1256 /* Set the input timing to the screen. Assume always input 0. */ 2574 psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
1257 psb_intel_sdvo_set_target_input(psb_intel_output, true, false);
1258
1259 psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_output,
1260 &sdvo_priv->pixel_clock_min,
1261 &sdvo_priv->
1262 pixel_clock_max);
1263
1264
1265 dev_dbg(dev->dev, "%s device VID/DID: %02X:%02X.%02X, "
1266 "clock range %dMHz - %dMHz, "
1267 "input 1: %c, input 2: %c, "
1268 "output 1: %c, output 2: %c\n",
1269 SDVO_NAME(sdvo_priv),
1270 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1271 sdvo_priv->caps.device_rev_id,
1272 sdvo_priv->pixel_clock_min / 1000,
1273 sdvo_priv->pixel_clock_max / 1000,
1274 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1275 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1276 /* check currently supported outputs */
1277 sdvo_priv->caps.output_flags &
1278 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1279 sdvo_priv->caps.output_flags &
1280 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1281
1282 psb_intel_output->ddc_bus = i2cbus;
1283 2575
1284 return; 2576 /* Set the input timing to the screen. Assume always input 0. */
2577 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
2578 goto err;
2579
2580 if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
2581 &psb_intel_sdvo->pixel_clock_min,
2582 &psb_intel_sdvo->pixel_clock_max))
2583 goto err;
2584
2585 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2586 "clock range %dMHz - %dMHz, "
2587 "input 1: %c, input 2: %c, "
2588 "output 1: %c, output 2: %c\n",
2589 SDVO_NAME(psb_intel_sdvo),
2590 psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
2591 psb_intel_sdvo->caps.device_rev_id,
2592 psb_intel_sdvo->pixel_clock_min / 1000,
2593 psb_intel_sdvo->pixel_clock_max / 1000,
2594 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2595 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2596 /* check currently supported outputs */
2597 psb_intel_sdvo->caps.output_flags &
2598 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2599 psb_intel_sdvo->caps.output_flags &
2600 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2601 return true;
1285 2602
1286err_i2c: 2603err:
1287 psb_intel_i2c_destroy(psb_intel_output->i2c_bus); 2604 drm_encoder_cleanup(&psb_intel_encoder->base);
1288err_connector: 2605 i2c_del_adapter(&psb_intel_sdvo->ddc);
1289 drm_connector_cleanup(connector); 2606 kfree(psb_intel_sdvo);
1290 kfree(psb_intel_output);
1291 2607
1292 return; 2608 return false;
1293} 2609}
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
index 96862ea65aba..600e79744d68 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
@@ -1,25 +1,33 @@
1/* 1/*
2 * SDVO command definitions and structures. 2 * Copyright ? 2006-2007 Intel Corporation
3 * 3 *
4 * Copyright (c) 2008, Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
5 * 10 *
6 * This program is free software; you can redistribute it and/or modify it 11 * The above copyright notice and this permission notice (including the next
7 * under the terms and conditions of the GNU General Public License, 12 * paragraph) shall be included in all copies or substantial portions of the
8 * version 2, as published by the Free Software Foundation. 13 * Software.
9 * 14 *
10 * This program is distributed in the hope it will be useful, but WITHOUT 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
13 * more details. 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
14 * 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
15 * You should have received a copy of the GNU General Public License along with 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
16 * this program; if not, write to the Free Software Foundation, Inc., 21 * DEALINGS IN THE SOFTWARE.
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * 22 *
19 * Authors: 23 * Authors:
20 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
21 */ 25 */
22 26
27/**
28 * @file SDVO command definitions and structures.
29 */
30
23#define SDVO_OUTPUT_FIRST (0) 31#define SDVO_OUTPUT_FIRST (0)
24#define SDVO_OUTPUT_TMDS0 (1 << 0) 32#define SDVO_OUTPUT_TMDS0 (1 << 0)
25#define SDVO_OUTPUT_RGB0 (1 << 1) 33#define SDVO_OUTPUT_RGB0 (1 << 1)
@@ -38,62 +46,64 @@
38#define SDVO_OUTPUT_LAST (14) 46#define SDVO_OUTPUT_LAST (14)
39 47
40struct psb_intel_sdvo_caps { 48struct psb_intel_sdvo_caps {
41 u8 vendor_id; 49 u8 vendor_id;
42 u8 device_id; 50 u8 device_id;
43 u8 device_rev_id; 51 u8 device_rev_id;
44 u8 sdvo_version_major; 52 u8 sdvo_version_major;
45 u8 sdvo_version_minor; 53 u8 sdvo_version_minor;
46 unsigned int sdvo_inputs_mask:2; 54 unsigned int sdvo_inputs_mask:2;
47 unsigned int smooth_scaling:1; 55 unsigned int smooth_scaling:1;
48 unsigned int sharp_scaling:1; 56 unsigned int sharp_scaling:1;
49 unsigned int up_scaling:1; 57 unsigned int up_scaling:1;
50 unsigned int down_scaling:1; 58 unsigned int down_scaling:1;
51 unsigned int stall_support:1; 59 unsigned int stall_support:1;
52 unsigned int pad:1; 60 unsigned int pad:1;
53 u16 output_flags; 61 u16 output_flags;
54} __packed; 62} __attribute__((packed));
55 63
56/** This matches the EDID DTD structure, more or less */ 64/** This matches the EDID DTD structure, more or less */
57struct psb_intel_sdvo_dtd { 65struct psb_intel_sdvo_dtd {
58 struct { 66 struct {
59 u16 clock; /**< pixel clock, in 10kHz units */ 67 u16 clock; /**< pixel clock, in 10kHz units */
60 u8 h_active; /**< lower 8 bits (pixels) */ 68 u8 h_active; /**< lower 8 bits (pixels) */
61 u8 h_blank; /**< lower 8 bits (pixels) */ 69 u8 h_blank; /**< lower 8 bits (pixels) */
62 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 70 u8 h_high; /**< upper 4 bits each h_active, h_blank */
63 u8 v_active; /**< lower 8 bits (lines) */ 71 u8 v_active; /**< lower 8 bits (lines) */
64 u8 v_blank; /**< lower 8 bits (lines) */ 72 u8 v_blank; /**< lower 8 bits (lines) */
65 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 73 u8 v_high; /**< upper 4 bits each v_active, v_blank */
66 } part1; 74 } part1;
67 75
68 struct { 76 struct {
69 u8 h_sync_off; 77 u8 h_sync_off; /**< lower 8 bits, from hblank start */
70 /**< lower 8 bits, from hblank start */ 78 u8 h_sync_width; /**< lower 8 bits (pixels) */
71 u8 h_sync_width;/**< lower 8 bits (pixels) */
72 /** lower 4 bits each vsync offset, vsync width */ 79 /** lower 4 bits each vsync offset, vsync width */
73 u8 v_sync_off_width; 80 u8 v_sync_off_width;
74 /** 81 /**
75 * 2 high bits of hsync offset, 2 high bits of hsync width, 82 * 2 high bits of hsync offset, 2 high bits of hsync width,
76 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 83 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
77 */ 84 */
78 u8 sync_off_width_high; 85 u8 sync_off_width_high;
79 u8 dtd_flags; 86 u8 dtd_flags;
80 u8 sdvo_flags; 87 u8 sdvo_flags;
81 /** bits 6-7 of vsync offset at bits 6-7 */ 88 /** bits 6-7 of vsync offset at bits 6-7 */
82 u8 v_sync_off_high; 89 u8 v_sync_off_high;
83 u8 reserved; 90 u8 reserved;
84 } part2; 91 } part2;
85} __packed; 92} __attribute__((packed));
86 93
87struct psb_intel_sdvo_pixel_clock_range { 94struct psb_intel_sdvo_pixel_clock_range {
88 u16 min; /**< pixel clock, in 10kHz units */ 95 u16 min; /**< pixel clock, in 10kHz units */
89 u16 max; /**< pixel clock, in 10kHz units */ 96 u16 max; /**< pixel clock, in 10kHz units */
90} __packed; 97} __attribute__((packed));
91 98
92struct psb_intel_sdvo_preferred_input_timing_args { 99struct psb_intel_sdvo_preferred_input_timing_args {
93 u16 clock; 100 u16 clock;
94 u16 width; 101 u16 width;
95 u16 height; 102 u16 height;
96} __packed; 103 u8 interlace:1;
104 u8 scaled:1;
105 u8 pad:6;
106} __attribute__((packed));
97 107
98/* I2C registers for SDVO */ 108/* I2C registers for SDVO */
99#define SDVO_I2C_ARG_0 0x07 109#define SDVO_I2C_ARG_0 0x07
@@ -129,7 +139,7 @@ struct psb_intel_sdvo_preferred_input_timing_args {
129 139
130#define SDVO_CMD_RESET 0x01 140#define SDVO_CMD_RESET 0x01
131 141
132/** Returns a struct psb_intel_sdvo_caps */ 142/** Returns a struct intel_sdvo_caps */
133#define SDVO_CMD_GET_DEVICE_CAPS 0x02 143#define SDVO_CMD_GET_DEVICE_CAPS 0x02
134 144
135#define SDVO_CMD_GET_FIRMWARE_REV 0x86 145#define SDVO_CMD_GET_FIRMWARE_REV 0x86
@@ -144,19 +154,18 @@ struct psb_intel_sdvo_preferred_input_timing_args {
144 */ 154 */
145#define SDVO_CMD_GET_TRAINED_INPUTS 0x03 155#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
146struct psb_intel_sdvo_get_trained_inputs_response { 156struct psb_intel_sdvo_get_trained_inputs_response {
147 unsigned int input0_trained:1; 157 unsigned int input0_trained:1;
148 unsigned int input1_trained:1; 158 unsigned int input1_trained:1;
149 unsigned int pad:6; 159 unsigned int pad:6;
150} __packed; 160} __attribute__((packed));
151 161
152/** Returns a struct psb_intel_sdvo_output_flags of active outputs. */ 162/** Returns a struct intel_sdvo_output_flags of active outputs. */
153#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 163#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
154 164
155/** 165/**
156 * Sets the current set of active outputs. 166 * Sets the current set of active outputs.
157 * 167 *
158 * Takes a struct psb_intel_sdvo_output_flags. 168 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
159 * Must be preceded by a SET_IN_OUT_MAP
160 * on multi-output devices. 169 * on multi-output devices.
161 */ 170 */
162#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 171#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
@@ -164,9 +173,12 @@ struct psb_intel_sdvo_get_trained_inputs_response {
164/** 173/**
165 * Returns the current mapping of SDVO inputs to outputs on the device. 174 * Returns the current mapping of SDVO inputs to outputs on the device.
166 * 175 *
167 * Returns two struct psb_intel_sdvo_output_flags structures. 176 * Returns two struct intel_sdvo_output_flags structures.
168 */ 177 */
169#define SDVO_CMD_GET_IN_OUT_MAP 0x06 178#define SDVO_CMD_GET_IN_OUT_MAP 0x06
179struct psb_intel_sdvo_in_out_map {
180 u16 in0, in1;
181};
170 182
171/** 183/**
172 * Sets the current mapping of SDVO inputs to outputs on the device. 184 * Sets the current mapping of SDVO inputs to outputs on the device.
@@ -176,32 +188,33 @@ struct psb_intel_sdvo_get_trained_inputs_response {
176#define SDVO_CMD_SET_IN_OUT_MAP 0x07 188#define SDVO_CMD_SET_IN_OUT_MAP 0x07
177 189
178/** 190/**
179 * Returns a struct psb_intel_sdvo_output_flags of attached displays. 191 * Returns a struct intel_sdvo_output_flags of attached displays.
180 */ 192 */
181#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 193#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
182 194
183/** 195/**
184 * Returns a struct psb_intel_sdvo_ouptut_flags of displays supporting hot plugging. 196 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
185 */ 197 */
186#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 198#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
187 199
188/** 200/**
189 * Takes a struct psb_intel_sdvo_output_flags. 201 * Takes a struct intel_sdvo_output_flags.
190 */ 202 */
191#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 203#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
192 204
193/** 205/**
194 * Returns a struct psb_intel_sdvo_output_flags of displays with hot plug 206 * Returns a struct intel_sdvo_output_flags of displays with hot plug
195 * interrupts enabled. 207 * interrupts enabled.
196 */ 208 */
197#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 209#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
198 210
199#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 211#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
200struct psb_intel_sdvo_get_interrupt_event_source_response { 212struct intel_sdvo_get_interrupt_event_source_response {
201 u16 interrupt_status; 213 u16 interrupt_status;
202 unsigned int ambient_light_interrupt:1; 214 unsigned int ambient_light_interrupt:1;
203 unsigned int pad:7; 215 unsigned int hdmi_audio_encrypt_change:1;
204} __packed; 216 unsigned int pad:6;
217} __attribute__((packed));
205 218
206/** 219/**
207 * Selects which input is affected by future input commands. 220 * Selects which input is affected by future input commands.
@@ -212,12 +225,12 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
212 */ 225 */
213#define SDVO_CMD_SET_TARGET_INPUT 0x10 226#define SDVO_CMD_SET_TARGET_INPUT 0x10
214struct psb_intel_sdvo_set_target_input_args { 227struct psb_intel_sdvo_set_target_input_args {
215 unsigned int target_1:1; 228 unsigned int target_1:1;
216 unsigned int pad:7; 229 unsigned int pad:7;
217} __packed; 230} __attribute__((packed));
218 231
219/** 232/**
220 * Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by 233 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
221 * future output commands. 234 * future output commands.
222 * 235 *
223 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 236 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
@@ -282,9 +295,9 @@ struct psb_intel_sdvo_set_target_input_args {
282#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 295#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
283#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 296#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
284 297
285/** Returns a struct psb_intel_sdvo_pixel_clock_range */ 298/** Returns a struct intel_sdvo_pixel_clock_range */
286#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 299#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
287/** Returns a struct psb_intel_sdvo_pixel_clock_range */ 300/** Returns a struct intel_sdvo_pixel_clock_range */
288#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 301#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
289 302
290/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 303/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
@@ -299,40 +312,412 @@ struct psb_intel_sdvo_set_target_input_args {
299# define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 312# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
300 313
301#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
315/** 6 bytes of bit flags for TV formats shared by all TV format functions */
316struct psb_intel_sdvo_tv_format {
317 unsigned int ntsc_m:1;
318 unsigned int ntsc_j:1;
319 unsigned int ntsc_443:1;
320 unsigned int pal_b:1;
321 unsigned int pal_d:1;
322 unsigned int pal_g:1;
323 unsigned int pal_h:1;
324 unsigned int pal_i:1;
325
326 unsigned int pal_m:1;
327 unsigned int pal_n:1;
328 unsigned int pal_nc:1;
329 unsigned int pal_60:1;
330 unsigned int secam_b:1;
331 unsigned int secam_d:1;
332 unsigned int secam_g:1;
333 unsigned int secam_k:1;
334
335 unsigned int secam_k1:1;
336 unsigned int secam_l:1;
337 unsigned int secam_60:1;
338 unsigned int hdtv_std_smpte_240m_1080i_59:1;
339 unsigned int hdtv_std_smpte_240m_1080i_60:1;
340 unsigned int hdtv_std_smpte_260m_1080i_59:1;
341 unsigned int hdtv_std_smpte_260m_1080i_60:1;
342 unsigned int hdtv_std_smpte_274m_1080i_50:1;
343
344 unsigned int hdtv_std_smpte_274m_1080i_59:1;
345 unsigned int hdtv_std_smpte_274m_1080i_60:1;
346 unsigned int hdtv_std_smpte_274m_1080p_23:1;
347 unsigned int hdtv_std_smpte_274m_1080p_24:1;
348 unsigned int hdtv_std_smpte_274m_1080p_25:1;
349 unsigned int hdtv_std_smpte_274m_1080p_29:1;
350 unsigned int hdtv_std_smpte_274m_1080p_30:1;
351 unsigned int hdtv_std_smpte_274m_1080p_50:1;
352
353 unsigned int hdtv_std_smpte_274m_1080p_59:1;
354 unsigned int hdtv_std_smpte_274m_1080p_60:1;
355 unsigned int hdtv_std_smpte_295m_1080i_50:1;
356 unsigned int hdtv_std_smpte_295m_1080p_50:1;
357 unsigned int hdtv_std_smpte_296m_720p_59:1;
358 unsigned int hdtv_std_smpte_296m_720p_60:1;
359 unsigned int hdtv_std_smpte_296m_720p_50:1;
360 unsigned int hdtv_std_smpte_293m_480p_59:1;
361
362 unsigned int hdtv_std_smpte_170m_480i_59:1;
363 unsigned int hdtv_std_iturbt601_576i_50:1;
364 unsigned int hdtv_std_iturbt601_576p_50:1;
365 unsigned int hdtv_std_eia_7702a_480i_60:1;
366 unsigned int hdtv_std_eia_7702a_480p_60:1;
367 unsigned int pad:3;
368} __attribute__((packed));
302 369
303#define SDVO_CMD_GET_TV_FORMAT 0x28 370#define SDVO_CMD_GET_TV_FORMAT 0x28
304 371
305#define SDVO_CMD_SET_TV_FORMAT 0x29 372#define SDVO_CMD_SET_TV_FORMAT 0x29
306 373
374/** Returns the resolutiosn that can be used with the given TV format */
375#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
376struct psb_intel_sdvo_sdtv_resolution_request {
377 unsigned int ntsc_m:1;
378 unsigned int ntsc_j:1;
379 unsigned int ntsc_443:1;
380 unsigned int pal_b:1;
381 unsigned int pal_d:1;
382 unsigned int pal_g:1;
383 unsigned int pal_h:1;
384 unsigned int pal_i:1;
385
386 unsigned int pal_m:1;
387 unsigned int pal_n:1;
388 unsigned int pal_nc:1;
389 unsigned int pal_60:1;
390 unsigned int secam_b:1;
391 unsigned int secam_d:1;
392 unsigned int secam_g:1;
393 unsigned int secam_k:1;
394
395 unsigned int secam_k1:1;
396 unsigned int secam_l:1;
397 unsigned int secam_60:1;
398 unsigned int pad:5;
399} __attribute__((packed));
400
401struct psb_intel_sdvo_sdtv_resolution_reply {
402 unsigned int res_320x200:1;
403 unsigned int res_320x240:1;
404 unsigned int res_400x300:1;
405 unsigned int res_640x350:1;
406 unsigned int res_640x400:1;
407 unsigned int res_640x480:1;
408 unsigned int res_704x480:1;
409 unsigned int res_704x576:1;
410
411 unsigned int res_720x350:1;
412 unsigned int res_720x400:1;
413 unsigned int res_720x480:1;
414 unsigned int res_720x540:1;
415 unsigned int res_720x576:1;
416 unsigned int res_768x576:1;
417 unsigned int res_800x600:1;
418 unsigned int res_832x624:1;
419
420 unsigned int res_920x766:1;
421 unsigned int res_1024x768:1;
422 unsigned int res_1280x1024:1;
423 unsigned int pad:5;
424} __attribute__((packed));
425
426/* Get supported resolution with squire pixel aspect ratio that can be
427 scaled for the requested HDTV format */
428#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
429
430struct psb_intel_sdvo_hdtv_resolution_request {
431 unsigned int hdtv_std_smpte_240m_1080i_59:1;
432 unsigned int hdtv_std_smpte_240m_1080i_60:1;
433 unsigned int hdtv_std_smpte_260m_1080i_59:1;
434 unsigned int hdtv_std_smpte_260m_1080i_60:1;
435 unsigned int hdtv_std_smpte_274m_1080i_50:1;
436 unsigned int hdtv_std_smpte_274m_1080i_59:1;
437 unsigned int hdtv_std_smpte_274m_1080i_60:1;
438 unsigned int hdtv_std_smpte_274m_1080p_23:1;
439
440 unsigned int hdtv_std_smpte_274m_1080p_24:1;
441 unsigned int hdtv_std_smpte_274m_1080p_25:1;
442 unsigned int hdtv_std_smpte_274m_1080p_29:1;
443 unsigned int hdtv_std_smpte_274m_1080p_30:1;
444 unsigned int hdtv_std_smpte_274m_1080p_50:1;
445 unsigned int hdtv_std_smpte_274m_1080p_59:1;
446 unsigned int hdtv_std_smpte_274m_1080p_60:1;
447 unsigned int hdtv_std_smpte_295m_1080i_50:1;
448
449 unsigned int hdtv_std_smpte_295m_1080p_50:1;
450 unsigned int hdtv_std_smpte_296m_720p_59:1;
451 unsigned int hdtv_std_smpte_296m_720p_60:1;
452 unsigned int hdtv_std_smpte_296m_720p_50:1;
453 unsigned int hdtv_std_smpte_293m_480p_59:1;
454 unsigned int hdtv_std_smpte_170m_480i_59:1;
455 unsigned int hdtv_std_iturbt601_576i_50:1;
456 unsigned int hdtv_std_iturbt601_576p_50:1;
457
458 unsigned int hdtv_std_eia_7702a_480i_60:1;
459 unsigned int hdtv_std_eia_7702a_480p_60:1;
460 unsigned int pad:6;
461} __attribute__((packed));
462
463struct psb_intel_sdvo_hdtv_resolution_reply {
464 unsigned int res_640x480:1;
465 unsigned int res_800x600:1;
466 unsigned int res_1024x768:1;
467 unsigned int res_1280x960:1;
468 unsigned int res_1400x1050:1;
469 unsigned int res_1600x1200:1;
470 unsigned int res_1920x1440:1;
471 unsigned int res_2048x1536:1;
472
473 unsigned int res_2560x1920:1;
474 unsigned int res_3200x2400:1;
475 unsigned int res_3840x2880:1;
476 unsigned int pad1:5;
477
478 unsigned int res_848x480:1;
479 unsigned int res_1064x600:1;
480 unsigned int res_1280x720:1;
481 unsigned int res_1360x768:1;
482 unsigned int res_1704x960:1;
483 unsigned int res_1864x1050:1;
484 unsigned int res_1920x1080:1;
485 unsigned int res_2128x1200:1;
486
487 unsigned int res_2560x1400:1;
488 unsigned int res_2728x1536:1;
489 unsigned int res_3408x1920:1;
490 unsigned int res_4264x2400:1;
491 unsigned int res_5120x2880:1;
492 unsigned int pad2:3;
493
494 unsigned int res_768x480:1;
495 unsigned int res_960x600:1;
496 unsigned int res_1152x720:1;
497 unsigned int res_1124x768:1;
498 unsigned int res_1536x960:1;
499 unsigned int res_1680x1050:1;
500 unsigned int res_1728x1080:1;
501 unsigned int res_1920x1200:1;
502
503 unsigned int res_2304x1440:1;
504 unsigned int res_2456x1536:1;
505 unsigned int res_3072x1920:1;
506 unsigned int res_3840x2400:1;
507 unsigned int res_4608x2880:1;
508 unsigned int pad3:3;
509
510 unsigned int res_1280x1024:1;
511 unsigned int pad4:7;
512
513 unsigned int res_1280x768:1;
514 unsigned int pad5:7;
515} __attribute__((packed));
516
517/* Get supported power state returns info for encoder and monitor, rely on
518 last SetTargetInput and SetTargetOutput calls */
307#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 519#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
520/* Get power state returns info for encoder and monitor, rely on last
521 SetTargetInput and SetTargetOutput calls */
522#define SDVO_CMD_GET_POWER_STATE 0x2b
308#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 523#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
309#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 524#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
310# define SDVO_ENCODER_STATE_ON (1 << 0) 525# define SDVO_ENCODER_STATE_ON (1 << 0)
311# define SDVO_ENCODER_STATE_STANDBY (1 << 1) 526# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
312# define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 527# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
313# define SDVO_ENCODER_STATE_OFF (1 << 3) 528# define SDVO_ENCODER_STATE_OFF (1 << 3)
314 529# define SDVO_MONITOR_STATE_ON (1 << 4)
315#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93 530# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
531# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
532# define SDVO_MONITOR_STATE_OFF (1 << 7)
533
534#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
535#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
536#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
537/**
538 * The panel power sequencing parameters are in units of milliseconds.
539 * The high fields are bits 8:9 of the 10-bit values.
540 */
541struct psb_sdvo_panel_power_sequencing {
542 u8 t0;
543 u8 t1;
544 u8 t2;
545 u8 t3;
546 u8 t4;
547
548 unsigned int t0_high:2;
549 unsigned int t1_high:2;
550 unsigned int t2_high:2;
551 unsigned int t3_high:2;
552
553 unsigned int t4_high:2;
554 unsigned int pad:6;
555} __attribute__((packed));
556
557#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
558struct sdvo_max_backlight_reply {
559 u8 max_value;
560 u8 default_value;
561} __attribute__((packed));
562
563#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
564#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
565
566#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
567struct sdvo_get_ambient_light_reply {
568 u16 trip_low;
569 u16 trip_high;
570 u16 value;
571} __attribute__((packed));
572#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
573struct sdvo_set_ambient_light_reply {
574 u16 trip_low;
575 u16 trip_high;
576 unsigned int enable:1;
577 unsigned int pad:7;
578} __attribute__((packed));
579
580/* Set display power state */
581#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
582# define SDVO_DISPLAY_STATE_ON (1 << 0)
583# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
584# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
585# define SDVO_DISPLAY_STATE_OFF (1 << 3)
586
587#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
588struct psb_intel_sdvo_enhancements_reply {
589 unsigned int flicker_filter:1;
590 unsigned int flicker_filter_adaptive:1;
591 unsigned int flicker_filter_2d:1;
592 unsigned int saturation:1;
593 unsigned int hue:1;
594 unsigned int brightness:1;
595 unsigned int contrast:1;
596 unsigned int overscan_h:1;
597
598 unsigned int overscan_v:1;
599 unsigned int hpos:1;
600 unsigned int vpos:1;
601 unsigned int sharpness:1;
602 unsigned int dot_crawl:1;
603 unsigned int dither:1;
604 unsigned int tv_chroma_filter:1;
605 unsigned int tv_luma_filter:1;
606} __attribute__((packed));
607
608/* Picture enhancement limits below are dependent on the current TV format,
609 * and thus need to be queried and set after it.
610 */
611#define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
612#define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
613#define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
614#define SDVO_CMD_GET_MAX_SATURATION 0x55
615#define SDVO_CMD_GET_MAX_HUE 0x58
616#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
617#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
618#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
619#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
620#define SDVO_CMD_GET_MAX_HPOS 0x67
621#define SDVO_CMD_GET_MAX_VPOS 0x6a
622#define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
623#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
624#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
625struct psb_intel_sdvo_enhancement_limits_reply {
626 u16 max_value;
627 u16 default_value;
628} __attribute__((packed));
629
630#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
631#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
632# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
633# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
634# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
635# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
636# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
637# define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
638
639#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
640#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
641#define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
642#define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
643#define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
644#define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
645#define SDVO_CMD_GET_SATURATION 0x56
646#define SDVO_CMD_SET_SATURATION 0x57
647#define SDVO_CMD_GET_HUE 0x59
648#define SDVO_CMD_SET_HUE 0x5a
649#define SDVO_CMD_GET_BRIGHTNESS 0x5c
650#define SDVO_CMD_SET_BRIGHTNESS 0x5d
651#define SDVO_CMD_GET_CONTRAST 0x5f
652#define SDVO_CMD_SET_CONTRAST 0x60
653#define SDVO_CMD_GET_OVERSCAN_H 0x62
654#define SDVO_CMD_SET_OVERSCAN_H 0x63
655#define SDVO_CMD_GET_OVERSCAN_V 0x65
656#define SDVO_CMD_SET_OVERSCAN_V 0x66
657#define SDVO_CMD_GET_HPOS 0x68
658#define SDVO_CMD_SET_HPOS 0x69
659#define SDVO_CMD_GET_VPOS 0x6b
660#define SDVO_CMD_SET_VPOS 0x6c
661#define SDVO_CMD_GET_SHARPNESS 0x6e
662#define SDVO_CMD_SET_SHARPNESS 0x6f
663#define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
664#define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
665#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
666#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
667struct psb_intel_sdvo_enhancements_arg {
668 u16 value;
669}__attribute__((packed));
670
671#define SDVO_CMD_GET_DOT_CRAWL 0x70
672#define SDVO_CMD_SET_DOT_CRAWL 0x71
673# define SDVO_DOT_CRAWL_ON (1 << 0)
674# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
675
676#define SDVO_CMD_GET_DITHER 0x72
677#define SDVO_CMD_SET_DITHER 0x73
678# define SDVO_DITHER_ON (1 << 0)
679# define SDVO_DITHER_DEFAULT_ON (1 << 1)
316 680
317#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 681#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
318# define SDVO_CONTROL_BUS_PROM 0x0 682# define SDVO_CONTROL_BUS_PROM (1 << 0)
319# define SDVO_CONTROL_BUS_DDC1 0x1 683# define SDVO_CONTROL_BUS_DDC1 (1 << 1)
320# define SDVO_CONTROL_BUS_DDC2 0x2 684# define SDVO_CONTROL_BUS_DDC2 (1 << 2)
321# define SDVO_CONTROL_BUS_DDC3 0x3 685# define SDVO_CONTROL_BUS_DDC3 (1 << 3)
322 686
323/* SDVO Bus & SDVO Inputs wiring details*/ 687/* HDMI op codes */
324/* Bit 0: Is SDVOB connected to In0 (1 = yes, 0 = no*/ 688#define SDVO_CMD_GET_SUPP_ENCODE 0x9d
325/* Bit 1: Is SDVOB connected to In1 (1 = yes, 0 = no*/ 689#define SDVO_CMD_GET_ENCODE 0x9e
326/* Bit 2: Is SDVOC connected to In0 (1 = yes, 0 = no*/ 690#define SDVO_CMD_SET_ENCODE 0x9f
327/* Bit 3: Is SDVOC connected to In1 (1 = yes, 0 = no*/ 691 #define SDVO_ENCODE_DVI 0x0
328#define SDVOB_IN0 0x01 692 #define SDVO_ENCODE_HDMI 0x1
329#define SDVOB_IN1 0x02 693#define SDVO_CMD_SET_PIXEL_REPLI 0x8b
330#define SDVOC_IN0 0x04 694#define SDVO_CMD_GET_PIXEL_REPLI 0x8c
331#define SDVOC_IN1 0x08 695#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
332 696#define SDVO_CMD_SET_COLORIMETRY 0x8e
333#define SDVO_DEVICE_NONE 0x00 697 #define SDVO_COLORIMETRY_RGB256 0x0
334#define SDVO_DEVICE_CRT 0x01 698 #define SDVO_COLORIMETRY_RGB220 0x1
335#define SDVO_DEVICE_TV 0x02 699 #define SDVO_COLORIMETRY_YCrCb422 0x3
336#define SDVO_DEVICE_LVDS 0x04 700 #define SDVO_COLORIMETRY_YCrCb444 0x4
337#define SDVO_DEVICE_TMDS 0x08 701#define SDVO_CMD_GET_COLORIMETRY 0x8f
338 702#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
703#define SDVO_CMD_SET_AUDIO_STAT 0x91
704#define SDVO_CMD_GET_AUDIO_STAT 0x92
705#define SDVO_CMD_SET_HBUF_INDEX 0x93
706#define SDVO_CMD_GET_HBUF_INDEX 0x94
707#define SDVO_CMD_GET_HBUF_INFO 0x95
708#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
709#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
710#define SDVO_CMD_SET_HBUF_DATA 0x98
711#define SDVO_CMD_GET_HBUF_DATA 0x99
712#define SDVO_CMD_SET_HBUF_TXRATE 0x9a
713#define SDVO_CMD_GET_HBUF_TXRATE 0x9b
714 #define SDVO_HBUF_TX_DISABLED (0 << 6)
715 #define SDVO_HBUF_TX_ONCE (2 << 6)
716 #define SDVO_HBUF_TX_VSYNC (3 << 6)
717#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
718#define SDVO_NEED_TO_STALL (1 << 7)
719
720struct psb_intel_sdvo_encode {
721 u8 dvi_rev;
722 u8 hdmi_rev;
723} __attribute__ ((packed));
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 15:03:04 -0500