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Diffstat (limited to 'drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h591
1 files changed, 488 insertions, 103 deletions
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
index 96862ea65aba..600e79744d68 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
@@ -1,25 +1,33 @@
1/* 1/*
2 * SDVO command definitions and structures. 2 * Copyright ? 2006-2007 Intel Corporation
3 * 3 *
4 * Copyright (c) 2008, Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
5 * 10 *
6 * This program is free software; you can redistribute it and/or modify it 11 * The above copyright notice and this permission notice (including the next
7 * under the terms and conditions of the GNU General Public License, 12 * paragraph) shall be included in all copies or substantial portions of the
8 * version 2, as published by the Free Software Foundation. 13 * Software.
9 * 14 *
10 * This program is distributed in the hope it will be useful, but WITHOUT 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
13 * more details. 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
14 * 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
15 * You should have received a copy of the GNU General Public License along with 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
16 * this program; if not, write to the Free Software Foundation, Inc., 21 * DEALINGS IN THE SOFTWARE.
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * 22 *
19 * Authors: 23 * Authors:
20 * Eric Anholt <eric@anholt.net> 24 * Eric Anholt <eric@anholt.net>
21 */ 25 */
22 26
27/**
28 * @file SDVO command definitions and structures.
29 */
30
23#define SDVO_OUTPUT_FIRST (0) 31#define SDVO_OUTPUT_FIRST (0)
24#define SDVO_OUTPUT_TMDS0 (1 << 0) 32#define SDVO_OUTPUT_TMDS0 (1 << 0)
25#define SDVO_OUTPUT_RGB0 (1 << 1) 33#define SDVO_OUTPUT_RGB0 (1 << 1)
@@ -38,62 +46,64 @@
38#define SDVO_OUTPUT_LAST (14) 46#define SDVO_OUTPUT_LAST (14)
39 47
40struct psb_intel_sdvo_caps { 48struct psb_intel_sdvo_caps {
41 u8 vendor_id; 49 u8 vendor_id;
42 u8 device_id; 50 u8 device_id;
43 u8 device_rev_id; 51 u8 device_rev_id;
44 u8 sdvo_version_major; 52 u8 sdvo_version_major;
45 u8 sdvo_version_minor; 53 u8 sdvo_version_minor;
46 unsigned int sdvo_inputs_mask:2; 54 unsigned int sdvo_inputs_mask:2;
47 unsigned int smooth_scaling:1; 55 unsigned int smooth_scaling:1;
48 unsigned int sharp_scaling:1; 56 unsigned int sharp_scaling:1;
49 unsigned int up_scaling:1; 57 unsigned int up_scaling:1;
50 unsigned int down_scaling:1; 58 unsigned int down_scaling:1;
51 unsigned int stall_support:1; 59 unsigned int stall_support:1;
52 unsigned int pad:1; 60 unsigned int pad:1;
53 u16 output_flags; 61 u16 output_flags;
54} __packed; 62} __attribute__((packed));
55 63
56/** This matches the EDID DTD structure, more or less */ 64/** This matches the EDID DTD structure, more or less */
57struct psb_intel_sdvo_dtd { 65struct psb_intel_sdvo_dtd {
58 struct { 66 struct {
59 u16 clock; /**< pixel clock, in 10kHz units */ 67 u16 clock; /**< pixel clock, in 10kHz units */
60 u8 h_active; /**< lower 8 bits (pixels) */ 68 u8 h_active; /**< lower 8 bits (pixels) */
61 u8 h_blank; /**< lower 8 bits (pixels) */ 69 u8 h_blank; /**< lower 8 bits (pixels) */
62 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 70 u8 h_high; /**< upper 4 bits each h_active, h_blank */
63 u8 v_active; /**< lower 8 bits (lines) */ 71 u8 v_active; /**< lower 8 bits (lines) */
64 u8 v_blank; /**< lower 8 bits (lines) */ 72 u8 v_blank; /**< lower 8 bits (lines) */
65 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 73 u8 v_high; /**< upper 4 bits each v_active, v_blank */
66 } part1; 74 } part1;
67 75
68 struct { 76 struct {
69 u8 h_sync_off; 77 u8 h_sync_off; /**< lower 8 bits, from hblank start */
70 /**< lower 8 bits, from hblank start */ 78 u8 h_sync_width; /**< lower 8 bits (pixels) */
71 u8 h_sync_width;/**< lower 8 bits (pixels) */
72 /** lower 4 bits each vsync offset, vsync width */ 79 /** lower 4 bits each vsync offset, vsync width */
73 u8 v_sync_off_width; 80 u8 v_sync_off_width;
74 /** 81 /**
75 * 2 high bits of hsync offset, 2 high bits of hsync width, 82 * 2 high bits of hsync offset, 2 high bits of hsync width,
76 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 83 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
77 */ 84 */
78 u8 sync_off_width_high; 85 u8 sync_off_width_high;
79 u8 dtd_flags; 86 u8 dtd_flags;
80 u8 sdvo_flags; 87 u8 sdvo_flags;
81 /** bits 6-7 of vsync offset at bits 6-7 */ 88 /** bits 6-7 of vsync offset at bits 6-7 */
82 u8 v_sync_off_high; 89 u8 v_sync_off_high;
83 u8 reserved; 90 u8 reserved;
84 } part2; 91 } part2;
85} __packed; 92} __attribute__((packed));
86 93
87struct psb_intel_sdvo_pixel_clock_range { 94struct psb_intel_sdvo_pixel_clock_range {
88 u16 min; /**< pixel clock, in 10kHz units */ 95 u16 min; /**< pixel clock, in 10kHz units */
89 u16 max; /**< pixel clock, in 10kHz units */ 96 u16 max; /**< pixel clock, in 10kHz units */
90} __packed; 97} __attribute__((packed));
91 98
92struct psb_intel_sdvo_preferred_input_timing_args { 99struct psb_intel_sdvo_preferred_input_timing_args {
93 u16 clock; 100 u16 clock;
94 u16 width; 101 u16 width;
95 u16 height; 102 u16 height;
96} __packed; 103 u8 interlace:1;
104 u8 scaled:1;
105 u8 pad:6;
106} __attribute__((packed));
97 107
98/* I2C registers for SDVO */ 108/* I2C registers for SDVO */
99#define SDVO_I2C_ARG_0 0x07 109#define SDVO_I2C_ARG_0 0x07
@@ -129,7 +139,7 @@ struct psb_intel_sdvo_preferred_input_timing_args {
129 139
130#define SDVO_CMD_RESET 0x01 140#define SDVO_CMD_RESET 0x01
131 141
132/** Returns a struct psb_intel_sdvo_caps */ 142/** Returns a struct intel_sdvo_caps */
133#define SDVO_CMD_GET_DEVICE_CAPS 0x02 143#define SDVO_CMD_GET_DEVICE_CAPS 0x02
134 144
135#define SDVO_CMD_GET_FIRMWARE_REV 0x86 145#define SDVO_CMD_GET_FIRMWARE_REV 0x86
@@ -144,19 +154,18 @@ struct psb_intel_sdvo_preferred_input_timing_args {
144 */ 154 */
145#define SDVO_CMD_GET_TRAINED_INPUTS 0x03 155#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
146struct psb_intel_sdvo_get_trained_inputs_response { 156struct psb_intel_sdvo_get_trained_inputs_response {
147 unsigned int input0_trained:1; 157 unsigned int input0_trained:1;
148 unsigned int input1_trained:1; 158 unsigned int input1_trained:1;
149 unsigned int pad:6; 159 unsigned int pad:6;
150} __packed; 160} __attribute__((packed));
151 161
152/** Returns a struct psb_intel_sdvo_output_flags of active outputs. */ 162/** Returns a struct intel_sdvo_output_flags of active outputs. */
153#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 163#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
154 164
155/** 165/**
156 * Sets the current set of active outputs. 166 * Sets the current set of active outputs.
157 * 167 *
158 * Takes a struct psb_intel_sdvo_output_flags. 168 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
159 * Must be preceded by a SET_IN_OUT_MAP
160 * on multi-output devices. 169 * on multi-output devices.
161 */ 170 */
162#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 171#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
@@ -164,9 +173,12 @@ struct psb_intel_sdvo_get_trained_inputs_response {
164/** 173/**
165 * Returns the current mapping of SDVO inputs to outputs on the device. 174 * Returns the current mapping of SDVO inputs to outputs on the device.
166 * 175 *
167 * Returns two struct psb_intel_sdvo_output_flags structures. 176 * Returns two struct intel_sdvo_output_flags structures.
168 */ 177 */
169#define SDVO_CMD_GET_IN_OUT_MAP 0x06 178#define SDVO_CMD_GET_IN_OUT_MAP 0x06
179struct psb_intel_sdvo_in_out_map {
180 u16 in0, in1;
181};
170 182
171/** 183/**
172 * Sets the current mapping of SDVO inputs to outputs on the device. 184 * Sets the current mapping of SDVO inputs to outputs on the device.
@@ -176,32 +188,33 @@ struct psb_intel_sdvo_get_trained_inputs_response {
176#define SDVO_CMD_SET_IN_OUT_MAP 0x07 188#define SDVO_CMD_SET_IN_OUT_MAP 0x07
177 189
178/** 190/**
179 * Returns a struct psb_intel_sdvo_output_flags of attached displays. 191 * Returns a struct intel_sdvo_output_flags of attached displays.
180 */ 192 */
181#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 193#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
182 194
183/** 195/**
184 * Returns a struct psb_intel_sdvo_ouptut_flags of displays supporting hot plugging. 196 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
185 */ 197 */
186#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 198#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
187 199
188/** 200/**
189 * Takes a struct psb_intel_sdvo_output_flags. 201 * Takes a struct intel_sdvo_output_flags.
190 */ 202 */
191#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 203#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
192 204
193/** 205/**
194 * Returns a struct psb_intel_sdvo_output_flags of displays with hot plug 206 * Returns a struct intel_sdvo_output_flags of displays with hot plug
195 * interrupts enabled. 207 * interrupts enabled.
196 */ 208 */
197#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 209#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
198 210
199#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 211#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
200struct psb_intel_sdvo_get_interrupt_event_source_response { 212struct intel_sdvo_get_interrupt_event_source_response {
201 u16 interrupt_status; 213 u16 interrupt_status;
202 unsigned int ambient_light_interrupt:1; 214 unsigned int ambient_light_interrupt:1;
203 unsigned int pad:7; 215 unsigned int hdmi_audio_encrypt_change:1;
204} __packed; 216 unsigned int pad:6;
217} __attribute__((packed));
205 218
206/** 219/**
207 * Selects which input is affected by future input commands. 220 * Selects which input is affected by future input commands.
@@ -212,12 +225,12 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
212 */ 225 */
213#define SDVO_CMD_SET_TARGET_INPUT 0x10 226#define SDVO_CMD_SET_TARGET_INPUT 0x10
214struct psb_intel_sdvo_set_target_input_args { 227struct psb_intel_sdvo_set_target_input_args {
215 unsigned int target_1:1; 228 unsigned int target_1:1;
216 unsigned int pad:7; 229 unsigned int pad:7;
217} __packed; 230} __attribute__((packed));
218 231
219/** 232/**
220 * Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by 233 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
221 * future output commands. 234 * future output commands.
222 * 235 *
223 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 236 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
@@ -282,9 +295,9 @@ struct psb_intel_sdvo_set_target_input_args {
282#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 295#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
283#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 296#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
284 297
285/** Returns a struct psb_intel_sdvo_pixel_clock_range */ 298/** Returns a struct intel_sdvo_pixel_clock_range */
286#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 299#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
287/** Returns a struct psb_intel_sdvo_pixel_clock_range */ 300/** Returns a struct intel_sdvo_pixel_clock_range */
288#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 301#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
289 302
290/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 303/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
@@ -299,40 +312,412 @@ struct psb_intel_sdvo_set_target_input_args {
299# define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 312# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
300 313
301#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
315/** 6 bytes of bit flags for TV formats shared by all TV format functions */
316struct psb_intel_sdvo_tv_format {
317 unsigned int ntsc_m:1;
318 unsigned int ntsc_j:1;
319 unsigned int ntsc_443:1;
320 unsigned int pal_b:1;
321 unsigned int pal_d:1;
322 unsigned int pal_g:1;
323 unsigned int pal_h:1;
324 unsigned int pal_i:1;
325
326 unsigned int pal_m:1;
327 unsigned int pal_n:1;
328 unsigned int pal_nc:1;
329 unsigned int pal_60:1;
330 unsigned int secam_b:1;
331 unsigned int secam_d:1;
332 unsigned int secam_g:1;
333 unsigned int secam_k:1;
334
335 unsigned int secam_k1:1;
336 unsigned int secam_l:1;
337 unsigned int secam_60:1;
338 unsigned int hdtv_std_smpte_240m_1080i_59:1;
339 unsigned int hdtv_std_smpte_240m_1080i_60:1;
340 unsigned int hdtv_std_smpte_260m_1080i_59:1;
341 unsigned int hdtv_std_smpte_260m_1080i_60:1;
342 unsigned int hdtv_std_smpte_274m_1080i_50:1;
343
344 unsigned int hdtv_std_smpte_274m_1080i_59:1;
345 unsigned int hdtv_std_smpte_274m_1080i_60:1;
346 unsigned int hdtv_std_smpte_274m_1080p_23:1;
347 unsigned int hdtv_std_smpte_274m_1080p_24:1;
348 unsigned int hdtv_std_smpte_274m_1080p_25:1;
349 unsigned int hdtv_std_smpte_274m_1080p_29:1;
350 unsigned int hdtv_std_smpte_274m_1080p_30:1;
351 unsigned int hdtv_std_smpte_274m_1080p_50:1;
352
353 unsigned int hdtv_std_smpte_274m_1080p_59:1;
354 unsigned int hdtv_std_smpte_274m_1080p_60:1;
355 unsigned int hdtv_std_smpte_295m_1080i_50:1;
356 unsigned int hdtv_std_smpte_295m_1080p_50:1;
357 unsigned int hdtv_std_smpte_296m_720p_59:1;
358 unsigned int hdtv_std_smpte_296m_720p_60:1;
359 unsigned int hdtv_std_smpte_296m_720p_50:1;
360 unsigned int hdtv_std_smpte_293m_480p_59:1;
361
362 unsigned int hdtv_std_smpte_170m_480i_59:1;
363 unsigned int hdtv_std_iturbt601_576i_50:1;
364 unsigned int hdtv_std_iturbt601_576p_50:1;
365 unsigned int hdtv_std_eia_7702a_480i_60:1;
366 unsigned int hdtv_std_eia_7702a_480p_60:1;
367 unsigned int pad:3;
368} __attribute__((packed));
302 369
303#define SDVO_CMD_GET_TV_FORMAT 0x28 370#define SDVO_CMD_GET_TV_FORMAT 0x28
304 371
305#define SDVO_CMD_SET_TV_FORMAT 0x29 372#define SDVO_CMD_SET_TV_FORMAT 0x29
306 373
374/** Returns the resolutiosn that can be used with the given TV format */
375#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
376struct psb_intel_sdvo_sdtv_resolution_request {
377 unsigned int ntsc_m:1;
378 unsigned int ntsc_j:1;
379 unsigned int ntsc_443:1;
380 unsigned int pal_b:1;
381 unsigned int pal_d:1;
382 unsigned int pal_g:1;
383 unsigned int pal_h:1;
384 unsigned int pal_i:1;
385
386 unsigned int pal_m:1;
387 unsigned int pal_n:1;
388 unsigned int pal_nc:1;
389 unsigned int pal_60:1;
390 unsigned int secam_b:1;
391 unsigned int secam_d:1;
392 unsigned int secam_g:1;
393 unsigned int secam_k:1;
394
395 unsigned int secam_k1:1;
396 unsigned int secam_l:1;
397 unsigned int secam_60:1;
398 unsigned int pad:5;
399} __attribute__((packed));
400
401struct psb_intel_sdvo_sdtv_resolution_reply {
402 unsigned int res_320x200:1;
403 unsigned int res_320x240:1;
404 unsigned int res_400x300:1;
405 unsigned int res_640x350:1;
406 unsigned int res_640x400:1;
407 unsigned int res_640x480:1;
408 unsigned int res_704x480:1;
409 unsigned int res_704x576:1;
410
411 unsigned int res_720x350:1;
412 unsigned int res_720x400:1;
413 unsigned int res_720x480:1;
414 unsigned int res_720x540:1;
415 unsigned int res_720x576:1;
416 unsigned int res_768x576:1;
417 unsigned int res_800x600:1;
418 unsigned int res_832x624:1;
419
420 unsigned int res_920x766:1;
421 unsigned int res_1024x768:1;
422 unsigned int res_1280x1024:1;
423 unsigned int pad:5;
424} __attribute__((packed));
425
426/* Get supported resolution with squire pixel aspect ratio that can be
427 scaled for the requested HDTV format */
428#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
429
430struct psb_intel_sdvo_hdtv_resolution_request {
431 unsigned int hdtv_std_smpte_240m_1080i_59:1;
432 unsigned int hdtv_std_smpte_240m_1080i_60:1;
433 unsigned int hdtv_std_smpte_260m_1080i_59:1;
434 unsigned int hdtv_std_smpte_260m_1080i_60:1;
435 unsigned int hdtv_std_smpte_274m_1080i_50:1;
436 unsigned int hdtv_std_smpte_274m_1080i_59:1;
437 unsigned int hdtv_std_smpte_274m_1080i_60:1;
438 unsigned int hdtv_std_smpte_274m_1080p_23:1;
439
440 unsigned int hdtv_std_smpte_274m_1080p_24:1;
441 unsigned int hdtv_std_smpte_274m_1080p_25:1;
442 unsigned int hdtv_std_smpte_274m_1080p_29:1;
443 unsigned int hdtv_std_smpte_274m_1080p_30:1;
444 unsigned int hdtv_std_smpte_274m_1080p_50:1;
445 unsigned int hdtv_std_smpte_274m_1080p_59:1;
446 unsigned int hdtv_std_smpte_274m_1080p_60:1;
447 unsigned int hdtv_std_smpte_295m_1080i_50:1;
448
449 unsigned int hdtv_std_smpte_295m_1080p_50:1;
450 unsigned int hdtv_std_smpte_296m_720p_59:1;
451 unsigned int hdtv_std_smpte_296m_720p_60:1;
452 unsigned int hdtv_std_smpte_296m_720p_50:1;
453 unsigned int hdtv_std_smpte_293m_480p_59:1;
454 unsigned int hdtv_std_smpte_170m_480i_59:1;
455 unsigned int hdtv_std_iturbt601_576i_50:1;
456 unsigned int hdtv_std_iturbt601_576p_50:1;
457
458 unsigned int hdtv_std_eia_7702a_480i_60:1;
459 unsigned int hdtv_std_eia_7702a_480p_60:1;
460 unsigned int pad:6;
461} __attribute__((packed));
462
463struct psb_intel_sdvo_hdtv_resolution_reply {
464 unsigned int res_640x480:1;
465 unsigned int res_800x600:1;
466 unsigned int res_1024x768:1;
467 unsigned int res_1280x960:1;
468 unsigned int res_1400x1050:1;
469 unsigned int res_1600x1200:1;
470 unsigned int res_1920x1440:1;
471 unsigned int res_2048x1536:1;
472
473 unsigned int res_2560x1920:1;
474 unsigned int res_3200x2400:1;
475 unsigned int res_3840x2880:1;
476 unsigned int pad1:5;
477
478 unsigned int res_848x480:1;
479 unsigned int res_1064x600:1;
480 unsigned int res_1280x720:1;
481 unsigned int res_1360x768:1;
482 unsigned int res_1704x960:1;
483 unsigned int res_1864x1050:1;
484 unsigned int res_1920x1080:1;
485 unsigned int res_2128x1200:1;
486
487 unsigned int res_2560x1400:1;
488 unsigned int res_2728x1536:1;
489 unsigned int res_3408x1920:1;
490 unsigned int res_4264x2400:1;
491 unsigned int res_5120x2880:1;
492 unsigned int pad2:3;
493
494 unsigned int res_768x480:1;
495 unsigned int res_960x600:1;
496 unsigned int res_1152x720:1;
497 unsigned int res_1124x768:1;
498 unsigned int res_1536x960:1;
499 unsigned int res_1680x1050:1;
500 unsigned int res_1728x1080:1;
501 unsigned int res_1920x1200:1;
502
503 unsigned int res_2304x1440:1;
504 unsigned int res_2456x1536:1;
505 unsigned int res_3072x1920:1;
506 unsigned int res_3840x2400:1;
507 unsigned int res_4608x2880:1;
508 unsigned int pad3:3;
509
510 unsigned int res_1280x1024:1;
511 unsigned int pad4:7;
512
513 unsigned int res_1280x768:1;
514 unsigned int pad5:7;
515} __attribute__((packed));
516
517/* Get supported power state returns info for encoder and monitor, rely on
518 last SetTargetInput and SetTargetOutput calls */
307#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 519#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
520/* Get power state returns info for encoder and monitor, rely on last
521 SetTargetInput and SetTargetOutput calls */
522#define SDVO_CMD_GET_POWER_STATE 0x2b
308#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 523#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
309#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 524#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
310# define SDVO_ENCODER_STATE_ON (1 << 0) 525# define SDVO_ENCODER_STATE_ON (1 << 0)
311# define SDVO_ENCODER_STATE_STANDBY (1 << 1) 526# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
312# define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 527# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
313# define SDVO_ENCODER_STATE_OFF (1 << 3) 528# define SDVO_ENCODER_STATE_OFF (1 << 3)
314 529# define SDVO_MONITOR_STATE_ON (1 << 4)
315#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93 530# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
531# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
532# define SDVO_MONITOR_STATE_OFF (1 << 7)
533
534#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
535#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
536#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
537/**
538 * The panel power sequencing parameters are in units of milliseconds.
539 * The high fields are bits 8:9 of the 10-bit values.
540 */
541struct psb_sdvo_panel_power_sequencing {
542 u8 t0;
543 u8 t1;
544 u8 t2;
545 u8 t3;
546 u8 t4;
547
548 unsigned int t0_high:2;
549 unsigned int t1_high:2;
550 unsigned int t2_high:2;
551 unsigned int t3_high:2;
552
553 unsigned int t4_high:2;
554 unsigned int pad:6;
555} __attribute__((packed));
556
557#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
558struct sdvo_max_backlight_reply {
559 u8 max_value;
560 u8 default_value;
561} __attribute__((packed));
562
563#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
564#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
565
566#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
567struct sdvo_get_ambient_light_reply {
568 u16 trip_low;
569 u16 trip_high;
570 u16 value;
571} __attribute__((packed));
572#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
573struct sdvo_set_ambient_light_reply {
574 u16 trip_low;
575 u16 trip_high;
576 unsigned int enable:1;
577 unsigned int pad:7;
578} __attribute__((packed));
579
580/* Set display power state */
581#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
582# define SDVO_DISPLAY_STATE_ON (1 << 0)
583# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
584# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
585# define SDVO_DISPLAY_STATE_OFF (1 << 3)
586
587#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
588struct psb_intel_sdvo_enhancements_reply {
589 unsigned int flicker_filter:1;
590 unsigned int flicker_filter_adaptive:1;
591 unsigned int flicker_filter_2d:1;
592 unsigned int saturation:1;
593 unsigned int hue:1;
594 unsigned int brightness:1;
595 unsigned int contrast:1;
596 unsigned int overscan_h:1;
597
598 unsigned int overscan_v:1;
599 unsigned int hpos:1;
600 unsigned int vpos:1;
601 unsigned int sharpness:1;
602 unsigned int dot_crawl:1;
603 unsigned int dither:1;
604 unsigned int tv_chroma_filter:1;
605 unsigned int tv_luma_filter:1;
606} __attribute__((packed));
607
608/* Picture enhancement limits below are dependent on the current TV format,
609 * and thus need to be queried and set after it.
610 */
611#define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
612#define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
613#define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
614#define SDVO_CMD_GET_MAX_SATURATION 0x55
615#define SDVO_CMD_GET_MAX_HUE 0x58
616#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
617#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
618#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
619#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
620#define SDVO_CMD_GET_MAX_HPOS 0x67
621#define SDVO_CMD_GET_MAX_VPOS 0x6a
622#define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
623#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
624#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
625struct psb_intel_sdvo_enhancement_limits_reply {
626 u16 max_value;
627 u16 default_value;
628} __attribute__((packed));
629
630#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
631#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
632# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
633# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
634# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
635# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
636# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
637# define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
638
639#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
640#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
641#define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
642#define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
643#define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
644#define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
645#define SDVO_CMD_GET_SATURATION 0x56
646#define SDVO_CMD_SET_SATURATION 0x57
647#define SDVO_CMD_GET_HUE 0x59
648#define SDVO_CMD_SET_HUE 0x5a
649#define SDVO_CMD_GET_BRIGHTNESS 0x5c
650#define SDVO_CMD_SET_BRIGHTNESS 0x5d
651#define SDVO_CMD_GET_CONTRAST 0x5f
652#define SDVO_CMD_SET_CONTRAST 0x60
653#define SDVO_CMD_GET_OVERSCAN_H 0x62
654#define SDVO_CMD_SET_OVERSCAN_H 0x63
655#define SDVO_CMD_GET_OVERSCAN_V 0x65
656#define SDVO_CMD_SET_OVERSCAN_V 0x66
657#define SDVO_CMD_GET_HPOS 0x68
658#define SDVO_CMD_SET_HPOS 0x69
659#define SDVO_CMD_GET_VPOS 0x6b
660#define SDVO_CMD_SET_VPOS 0x6c
661#define SDVO_CMD_GET_SHARPNESS 0x6e
662#define SDVO_CMD_SET_SHARPNESS 0x6f
663#define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
664#define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
665#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
666#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
667struct psb_intel_sdvo_enhancements_arg {
668 u16 value;
669}__attribute__((packed));
670
671#define SDVO_CMD_GET_DOT_CRAWL 0x70
672#define SDVO_CMD_SET_DOT_CRAWL 0x71
673# define SDVO_DOT_CRAWL_ON (1 << 0)
674# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
675
676#define SDVO_CMD_GET_DITHER 0x72
677#define SDVO_CMD_SET_DITHER 0x73
678# define SDVO_DITHER_ON (1 << 0)
679# define SDVO_DITHER_DEFAULT_ON (1 << 1)
316 680
317#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 681#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
318# define SDVO_CONTROL_BUS_PROM 0x0 682# define SDVO_CONTROL_BUS_PROM (1 << 0)
319# define SDVO_CONTROL_BUS_DDC1 0x1 683# define SDVO_CONTROL_BUS_DDC1 (1 << 1)
320# define SDVO_CONTROL_BUS_DDC2 0x2 684# define SDVO_CONTROL_BUS_DDC2 (1 << 2)
321# define SDVO_CONTROL_BUS_DDC3 0x3 685# define SDVO_CONTROL_BUS_DDC3 (1 << 3)
322 686
323/* SDVO Bus & SDVO Inputs wiring details*/ 687/* HDMI op codes */
324/* Bit 0: Is SDVOB connected to In0 (1 = yes, 0 = no*/ 688#define SDVO_CMD_GET_SUPP_ENCODE 0x9d
325/* Bit 1: Is SDVOB connected to In1 (1 = yes, 0 = no*/ 689#define SDVO_CMD_GET_ENCODE 0x9e
326/* Bit 2: Is SDVOC connected to In0 (1 = yes, 0 = no*/ 690#define SDVO_CMD_SET_ENCODE 0x9f
327/* Bit 3: Is SDVOC connected to In1 (1 = yes, 0 = no*/ 691 #define SDVO_ENCODE_DVI 0x0
328#define SDVOB_IN0 0x01 692 #define SDVO_ENCODE_HDMI 0x1
329#define SDVOB_IN1 0x02 693#define SDVO_CMD_SET_PIXEL_REPLI 0x8b
330#define SDVOC_IN0 0x04 694#define SDVO_CMD_GET_PIXEL_REPLI 0x8c
331#define SDVOC_IN1 0x08 695#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
332 696#define SDVO_CMD_SET_COLORIMETRY 0x8e
333#define SDVO_DEVICE_NONE 0x00 697 #define SDVO_COLORIMETRY_RGB256 0x0
334#define SDVO_DEVICE_CRT 0x01 698 #define SDVO_COLORIMETRY_RGB220 0x1
335#define SDVO_DEVICE_TV 0x02 699 #define SDVO_COLORIMETRY_YCrCb422 0x3
336#define SDVO_DEVICE_LVDS 0x04 700 #define SDVO_COLORIMETRY_YCrCb444 0x4
337#define SDVO_DEVICE_TMDS 0x08 701#define SDVO_CMD_GET_COLORIMETRY 0x8f
338 702#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
703#define SDVO_CMD_SET_AUDIO_STAT 0x91
704#define SDVO_CMD_GET_AUDIO_STAT 0x92
705#define SDVO_CMD_SET_HBUF_INDEX 0x93
706#define SDVO_CMD_GET_HBUF_INDEX 0x94
707#define SDVO_CMD_GET_HBUF_INFO 0x95
708#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
709#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
710#define SDVO_CMD_SET_HBUF_DATA 0x98
711#define SDVO_CMD_GET_HBUF_DATA 0x99
712#define SDVO_CMD_SET_HBUF_TXRATE 0x9a
713#define SDVO_CMD_GET_HBUF_TXRATE 0x9b
714 #define SDVO_HBUF_TX_DISABLED (0 << 6)
715 #define SDVO_HBUF_TX_ONCE (2 << 6)
716 #define SDVO_HBUF_TX_VSYNC (3 << 6)
717#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
718#define SDVO_NEED_TO_STALL (1 << 7)
719
720struct psb_intel_sdvo_encode {
721 u8 dvi_rev;
722 u8 hdmi_rev;
723} __attribute__ ((packed));
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 19:04:36 -0500